GS8320E18/32/36AGT-400/375/333/250/200/150
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
400 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.03 8/2013 1/23 © 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JRoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS8320E18/32/36 AGT is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, th e
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in eit her li near or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipe line Reads
The function of the Data Output register can be controlled by
the user via the FT mo de pin (Pi n 14). Hol ding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Outpu t Register. Holdi ng FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8320E18/32/36AGT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their output s just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8320E18/32/36AGT operates on a 3.3 V or 2.5 V
power supply. All input are 3.3 V and 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 3.3 V and 2.5 V
compatible.
Parameter Synopsis
-400 -375 -333 -250 -200 -150 Unit
Pipeline
3-1-1-1
tKQ
tCycle 2.5
2.5 2.5
2.66 2.5
3.3 2.5
4.0 3.0
5.0 3.8
6.7 ns
ns
Curr (x18)
Curr (x32/x36) 395
475 390
455 355
415 280
335 240
280 205
230 mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle 4.0
4.0 4.2
4.2 4.5
4.5 5.5
5.5 6.5
6.5 7.5
7.5 ns
ns
Curr (x18)
Curr (x32/x36) 290
335 275
320 260
305 235
270 200
240 190
220 mA
mA