Spartan-IIE: Detailed Functional Description - Xilinx, Inc.

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 1

Preliminary Product Specification 1-800-255-7778

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Architectural Description

Spartan-IIE Arra y

The Spartan-IIE user-programmable gate array, shown in

Figure 1, is composed of five major configurab le elements:

• IOBs provide the interface between the package pins

and the internal logic

• CLBs provide the functional elements for constructing

most logic

• Dedicated block RAM mem orie s of 4096 bits each

• Clock DLLs for clock-distribution delay compens ation

and clock doma in control

• Versatile multi-level interconnect structure

As can be seen in Figure 1, the CLBs for m the cen tral logic

structure with easy acce ss to all suppor t an d ro uting stru c-

tures. The IOBs are located around all the logic and mem-

ory elements for easy and quick routing of signals on and off

the chip.

Values stored in static memory cells control all the config-

urable logic elements and interconnect resources. These

values load into the memory cells on power-up, and can

reload if necessary to change the function of the device.

Each of these elements will be discussed in detail in the fol -

lowing sections.

Input/Output Block

The Spartan-IIE IOB, as seen in Figure 2, features inputs

and outputs that support a wide v ariety of I/O signaling stan-

dard s. These high-speed inputs and outputs are cap able of

supporting various state of the art memory and bus inter-

faces. Table 1 lists seve ral of the standards which a re sup-

ported along with the required reference, output and

ter m inat ion voltages needed to meet the standard.

The three IOB registers function either as edge-triggered

D-type flip-flops or as level-sensit ive latches. Each IOB has

a clock signal (CLK) shared by the three registers and inde-

pendent Clock Enable (CE) signals for each regist er.

0Spartan-IIE 1.8V FPGA Family:

Functional Description

DS077-2 (v1.0) November 15, 2001 00Preliminary Product Speci fication

Figure 1: Basi c Spar tan -IIE Family FPGA Block Diagram

DLL

K RA

K RAM

K RA

DS077

10220

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

2www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

In addition to the CLK and CE control signals, the three reg-

isters share a S et/Reset (SR). For each register, this signal

can be independently configured as a synchronous Set, a

synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear .

A feature not shown in the bl ock di agram, but co ntrolled by

the software, is polarity control. The input and output buff ers

and all of the IOB control signals have in dependent polarity

controls.

Optional pull-up and pull-down resistors and an optional

weak-keeper circuit are attached to each p ad. Prior to con-

figuration all outputs not involved i n conf iguration are f orced

into their high-impedance state. The pull -do wn resistors and

the weak-keeper circuits are inactiv e, but inputs ma y option-

ally be pulled up.The activation of pull-up resistors prior to

configu ration is c ont rolled on a global bas i s by the c onfigu-

ration mode pins. If the pull-up resistors are not activated,

all the pins will float. Consequently, external pull-up or

pull-down resistors must be provided on pins required to be

at a well-defined logic level prior to confi guration.

All pads are protected against damage from electrostatic

discharge (ESD) and from over- v oltage transients.

All Spartan-IIE IOBs support IEEE 1149.1-compatible

boundary sca n testing.

Figure 2: Spartan-IIE Input/Output Block (IOB)

Package Pin

Package

Package Pin

SR Q

Programmable

Bias and

ESD Network

CCO

I/O

I/O, V

REF

Internal

Reference

To Next I/O

To Other

External V

REF

Inputs

of Bank

Notes:

1. For some I/O standards.

Programmable

Input Buffer

Programmable

Output Buffer

Programmable

Delay

CC(1)

OCE

ICE

CLK

TCE

DS077-2_01_051501

TFF

OFF

IFF

Table 1: Standards Supported by I/O (Typical Values)

I/O Sta ndard

Input

Ref.

Volt.

(VREF)

Input

Volt.

(VCCO)

Output

Source

Volt.

(VCCO)

Board

Term.

Volt.

(VTT)

LVTTL (2-24 mA) N/A 3.3 3.3 N/A

LVCMOS2 N/A 2.5 2.5 N/A

LVCMOS18 N/A 1.8 1.8 N/A

PCI (3V,

33 MHz/66 MHz) N/A 3.3 3.3 N/A

GTL 0.8 N/A N/A 1.2

GTL+ 1.0 N/A N/A 1.5

HSTL Class I 0.75 N/A 1.5 0.75

HSTL Class III 0.9 N/A 1.5 1.5

HSTL Class IV 0.9 N/A 1.5 1.5

SSTL3 Class I and II 1.5 N/A 3.3 1.5

SSTL2 Class I and II 1.25 N/A 2.5 1.25

CTT 1.5 N/A 3.3 1.5

AGP 1.32 N/A 3.3 N/A

LVDS, Bus LVDS N/A N/A 2.5 N/A

LVPECL N/A N/A 3.3 N/A

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

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Preliminary Product Specification 1-800-255-7778

Input Pa t h

A buffer in the Spartan-IIE IOB input path routes the input

signal either directly to internal logic or throug h a n o ptional

input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is ze ro.

Each input buffer can be confi gured to conform to any of the

low-voltage signaling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, VREF. The n eed to supply VREF imposes

constraints on which st andards ca n used in cl ose proximity

to each other. See I/ O Ba nkin g.

There are optional pull-up and pull-down resistors a t each

input for us e after configuration.

Output Pa t h

The output path includ es a 3-state output bu ffer that dri ves

the output signal onto the pad. The output signal can be

routed to the buff er di rectly from the internal logic or through

an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

Each output driver can be individually programmed for a

wide range of low-vo ltage s ignaling sta ndards. Each outp ut

buffer can source up to 24 m A and s ink u p t o 48 mA . Drive

strength and slew rat e cont rols minimize bus transient s.

In most signaling standards, the output high voltage

depends on an externall y supplied VCCO voltage. The need

to supply VCCO imposes constraints on which standards

can be used in close pro ximity to each other . See I/O Bank-

ing.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way helps eliminate bus chatter.

Because the weak-keeper circuit uses the IOB input buffer

to monitor the input level, an appropriate VREF voltage must

be provided if the signaling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

I/O B a nking

Some of the I/O standards described above require VCCO

and/or VREF voltages. These voltages are externally con-

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be comb ined within a given bank.

Eight I/O banks result from separating each edge of the

FP GA into two banks (see Figure 3). Each bank has multi-

ple VCCO pins which must be connected to the same volt-

age. Voltage requirements are determined by the output

standards in use.

In the TQ144 and PQ208 packages, the eight banks have

VCCO connected together. Thus, only one VCCO level is

allowed in these packages, although different VREF values

are allowed in each of the eight banks.

Within a bank, output standards may be mixed only if they

use the same VCCO. Compatible standards are shown in

Table 2. G TL a nd GTL+ appear under all voltages bec ause

their open-drain outputs do not depend on VCCO.

Some input standards require a user-supplied threshold

voltage, VREF

. In this case, certain user-I/O pins are auto-

matically configured as inputs for the VREF voltage. About

one in six of the I/O pins in the bank assum e this role.

VREF pins within a bank are interconnected internally and

consequently only one VREF voltage can be used within

each bank. All VREF pins in the bank, howev er , must be con-

nected to the exter nal voltage sourc e for correct operation.

In a bank, inputs requiring VREF can be mixed with those

that do not but only one VREF voltage may be used within a

Figure 3: Spartan-IIE I/O Banks

Table 2: Compatible Output Standards

VCCO Compatible Standards

3.3V PCI, LVTTL , SST L3 I, SSTL3 II, CTT, A G P,

LV PEC L, GTL, GTL+

2.5V SSTL2 I, SSTL2 II, LVCMO S2, LVDS, Bus

LV D S, GTL, GTL+

1.8V LV CMO S 18, GTL, GTL+

1.5V HSTL I, HSTL III, HSTL IV, GTL, G TL+

DS077-2_02_051501

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Spartan-IIE

Device

Bank 7Bank 6

Bank 2Bank 3

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

4www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

bank. The VCCO and VREF pins f or each bank appear in the

device pinout tables.

Within a giv en pack age , the number of VREF and VCCO pins

can vary depending on the size of de vice. In larger devices,

more I/O pins convert to VREF pins. Since these are always

a superset of the VREF pins used for smaller devices, it is

possible to design a PCB that per mits migra tio n to a larger

device . Al l VREF pins for t he largest device anticipated must

be connected to the VREF voltage, and not used for I/O.

Configurable Logic Block

The basic building block of the S partan-IIE C LB is the logic

cell (LC). An LC includes a 4-input function generator, carry

logic, and storage element. The output from the function

generator in each LC drives the CLB output or the D input of

the flip-flop . Each Spartan-IIE CLB contains four LCs, orga-

nized in two similar slices; a single slice is shown in

Figure 4.

In additi on to the four basic LCs, the Spar tan-IIE CLB c on-

tains logic that combines function generators to provide

funct ions of five or six input s.

Look-Up Tables

Spartan-IIE function generators are implemented as 4-input

look-up tabl es (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RAM.

The Spartan-IIE LUT can also provide a 16-bit shift register

that is ideal for capturing high-speed or burst-mode data.

This mode can also be used to store data in applications

such as Digital Signal Processing.

Storage Elements

Storage elements in the Spartan-IIE slice can be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inputs can be driven either by function

generators within the slice or directly from slice inputs,

bypassing the function generators.

Table 3: I/O Banking

Package TQ144

PQ208 FT256

FG456

VCCO Banks Interc onnect ed as 1 8 independent

VREF Ba nks 8 independent 8 independent

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

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Preliminary Product Specification 1-800-255-7778

In addition to Clock and Clock Enable signals, each slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the co nfiguration . BY forces it in to the opposite

state. Alternatively, these signals may be configured to

operate asynchronously.

All control signals are independently invertible, and are

shared by t he two flip-flops within the slice.

Addition al Logic

The F5 multiplexer in each slice combines the function gen-

erator outputs (Figure 5). This combination provides either

a function generator that can implement any 5-input func-

tion, a 4:1 multiplexer, or selected functions of up to nine

inputs.

Similarly, the F6 multiple xer combines the outputs of all four

function gene rators in the CLB by selecting one of the two

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Figure 4: Spartan-IIE CLB Slice (two identical slices in each CLB)

Look-Up

Table D

Look-Up

Table D

SXQ

CLK

CIN

F5IN

COUT

Carry

and

Control

Logic

Carry

and

Control

Logic

DS001_04_091400

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

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1-800-255-7778 Preliminary Product Specification

Each CLB has four direct feedthrough paths, one per LC.

These paths provide e xtr a data input lines or additional local

routing that does not consume logic resources.

Arithmetic Logic

Dedicated carry logic pro vides f ast arithmetic carry capabil-

ity f or high-speed arithmetic functions. The Spartan-IIE CLB

supports two separate carry chains, one per slice. The

height of the carr y chains is two b its per CLB.

The arithmetic logic includes an XOR gate that allows a

1-bit full adder to be implement ed wi thin an LC. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementations.

The dedicated carry path can also be used to cascade func-

tion generators for implem enting wide logic functions.

BUFTs

Each Spartan-IIE CLB contains two 3-state driv ers (BUFTs)

that can driv e on-chip busses . The IOBs on the left and right

sides can also drive the on-chip busses. See Dedicated

Routing, page 8. Eac h Spart an-IIE B UFT h as an indepen-

dent 3-state control pin and an independent input pin. The

3-state control pin is an active-Low enable (T). When all

BUFTs on a net are disabled, the net is High. There is no

need to instantiate a pull-up unless desired for simulation

purposes. Simultaneously driving BUFTs onto the same net

will not cau se contention. If driven both High and Low, the

net will be Low.

Block RAM

Spartan-IIE FPGAs incorporate several large block RAM

memories. These complement the distributed RAM

Look -Up Tables (LUTs) that p rovide shallow memory s truc -

tures implemented in CLBs.

Block RAM memory blocks are organized in columns. All

Spartan-IIE devices contain two such columns, one along

each ver tical edge. These c olum ns extend the full heigh t of

the chip. Each memory block is four CLBs high, and conse-

quently, a Spartan-IIE de vice 16 CLBs high will contain four

mem ory blocks per column, and a total of eight blo cks.

Each block RAM cell, as illustrated in Figure 6, i s a fully syn-

chrono us d ual-por ted 4096-bit RAM with independent con-

trol signals for e ach port. The data widths of the two ports

can be configured independently, providing built-in

bus-width conversion.

Figure 5: F5 and F6 Mul t i ple xers

LUT

DS077-2_05-111501

LUT

MUXF5

MUXF6

LUT

Slice

CLB

LUT

MUXF5

Table 4: Spar tan -IIE Block RAM Amounts

Spartan-IIE

Device # of Blocks Total Block RAM

Bits

XC2S50E 8 32K

XC2S100E 10 40K

XC2S150E 12 48K

XC2S200E 14 56K

XC2S300E 16 64K

Figure 6: Dual-Port Block RAM

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADD[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

DS001_05_060100

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 7

Preliminary Product Specification 1-800-255-7778

Table 5 shows the depth and width aspect ratios for the

block RAM.

The Spartan-IIE block RAM also includes dedicated routing

to provide an efficient interface with both CLBs and other

block RAMs.

Programmable Ro uting

It is the longest delay path that limits the speed of any

design. Consequently, the Spartan-IIE routing architecture

and its place-and-route software were defined jointly to min-

imize long-path delays and yield the best system perfor-

mance.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

The software automatically uses the best available routing

based on user timing requirements. The details are pro-

vided here for reference.

Local Routing

The local routing resources, as shown in Figure 7, p rovide

the following three t ypes of connections:

•Interconnections am ong the LUTs, flip-flops, and

General Routing Matrix (GRM ), describ ed below.

•Internal CLB feed back paths that prov id e high-speed

connections to LUTs within the same CLB, chai ning

them together with minimal routing delay

•Direct paths that provide high-speed co nnect ions

between horizontally adjacent CLB s, eli minating the

delay of the GRM

General Purpose Routing

Most Spartan-IIE signals are routed on the general purpose

routing, and consequently, the majority of interconnect

resources a re associated wi th this level of the routing hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the rows

and columns of CLBs. The general-purpose routing

resources are listed below.

•Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the sw itch matri x through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general pur po se routing.

•24 single-leng th lines route GRM signals to adjacent

GR Ms in each of the four directions.

•96 buffered He x lines route GRM signals to other

GRMs six bloc ks away in each one of the four

directions. Organized in a staggered pattern, Hex li nes

may be driven only at their endpoints. Hex- l ine signals

can be acces sed either at the endpoints or at the

midp oint (three blocks from the source). One third of

the Hex lines are bidirectional, while the remaining

ones are unidirectional.

•12 Longline s are buffered, bidirectiona l wires that

distr ibute signals across the devi ce quickly an d

efficiently. Vertical Longlines span the full height of the

device, and hor izontal ones span the full wid th of the

device.

I/O Routing

Spartan-IIE devices have additional routing resources

around their periphery that form an interface between the

CLB array and the I OBs. This add itional routing, called t he

VersaRing™ routing, facilitates pin-swapping and pin-lock-

ing, such that logic redesigns can adapt to existing PCB lay-

outs. Time-to-market is reduced, since PCBs and other

system components can be manufactured while the logic

de si g n is st ill in p r og r es s.

Table 5: Block RAM Port Aspe ct Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

Figure 7: Spartan-IIE Local Ro uting

DS001_06_032300

CLB

GRM

Adjacent

GRM To Adjacent

GRM

Direct

Connection

To Adjacent

CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

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1-800-255-7778 Preliminary Product Specification

Dedic ated Routing

Some classes of signal require dedicated routing resources

to maximize performance. In the Spartan-IIE architecture,

dedicated routing resources are provided for two classes of

signal.

•Horizontal routing resources are provided f or on-chip

3-state busses. Four partitionable bus lin es are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.

Global Routing

Global Routing resources distribute clocks and other sig-

nals with very high fanout throughout the device. Spar-

tan-IIE devices includ e two tiers of global routing resources

referred to as primary and secondary global routing

resources.

•The primary global routing resources are f our

dedicated global nets with dedicated input pins that are

designed to distribute high-fanout clock signals with

minimal skew. Each global clock n et can drive all CLB,

IOB, and blo ck RAM clock pins. The prim ary global

nets may only be dr iven by global buffers. There are

four global buffers, one for each global net.

•The seconda ry global routing resources consist of 2 4

backbone lines, 12 across the top of the chip and 12

across the bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These secondary resources

are more flexib le than the primary resources since they

are not restricted to routing only to clock pins.

Clock Distribution

The Spartan-IIE f amily provi des high-speed, low-sk ew cloc k

distribution through the primary global routing resources

described above. A typical cloc k distrib ution net is shown in

Figure 9.

F our global buff ers are provided, two at the top center of the

device and two at the bottom center. These drive the four

primary glo bal nets that in tur n drive any clock p in.

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selec ted either from these p ads or from signals in the gen-

eral purpose routing.

Delay-Locked Loop (DLL)

Associated with each global clock input buff er is a fully digi-

tal Delay-Locked Loop (DLL) that can eliminate skew

between the clock input pad and internal clock-input pins

throughout the device. Each DLL can drive two global clock

networks . The DLL m onitors the input clo ck an d the dis tr ib-

uted clock, and automatically adjusts a clock delay element

(Figure 10). Additional delay is introduced such that clock

edges reach internal flip-flops exactly one cloc k period after

they arrive at the inp ut. T his closed-loop sy stem effec tively

eliminates clock-distribution delay by ensuring that clock

Figure 8: BUF T Connection s to Dedicated Horizontal Bus Lines

CLB CLB CLB CLB

3-State

Lines

DS001_07_090600

Figure 9: Global Clock Distrib ution Network

Global Clock

Spine

Global Clock

Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1 GCLKBUF0

GCLKPAD0

Global

Clock Rows

DS001_08_060100

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Preliminary Product Specification 1-800-255-7778

edges arrive at i ntern al flip-flops in synchronism with clock

edges arriving at the input.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

can doubl e the cloc k, or divide the clock by 1.5, 2, 2.5, 3, 4,

5, 8, or 16. The phase-shifted output have optional

duty-cycle correction (Figure 11).

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to deskew a board l ev el cloc k among multiple Spar-

tan-II E d ev i c e s.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA star ting up after configuration, the

DLL c an de lay the completion of the configu ration process

until after it has achieved lock .

Boundary Scan

Spartan-IIE devices support all the mandatory bound-

ary-scan instructions specified in the IEEE standard 1149.1.

A Test Access Port (TAP) and registers are provided that

implement the EXTEST, SAMPLE/PRELOAD, and BYPASS

instructions. The TAP also supports two USERCODE

instructions and internal scan chains.

The TAP uses dedicated package pins that always ope rate

using L VTTL. For TDO to operate using L VTTL, the VCCO for

Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail

between ground and VCCO. The boundary-scan input pins

(TDI, TMS, TCK) do not have a VCCO requirement and oper-

ate with either 2.5V or 3.3V input signalling levels.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including unbonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the b idirectional test capabi lity af ter configu ration facilitates

the testing of ex t er nal interconnec t ions.

Table 6 lists the boundary-scan instructions supported in

Spartan-IIE FPGAs. Internal signals can be captured during

EXTEST by connecting them to unbonded or unused IOBs.

They may also be connected to the unused outputs of IOBs

defin ed as unidirectional input pins. This technique partially

compens ates for the abs ence of INTEST support.

F igure 10: Delay-Locked Loop Block Diagram

Figure 11: DLL Output Characteristics

Clock

Distribution

Network

Variable

Delay Line CLKOUT

Control

CLKFB

CLKIN

x132_01_091799

x132_07_092599

CLKIN

CLK2X

CLK0

CLK90

CLK180

CLK270

CLKDV

CLKDV_DIVIDE=2

DUTY_CYCLE_CORRECTION=FALSE

CLK0

CLK90

CLK180

CLK270

DUTY_CYCLE_CORRECTION=TRUE

0 90 180 270 0 90 180 270

Table 6: Boundary-Scan Instructions

Boundary-Scan

Command Binar y

Code[4:0] Description

EXTEST 00000 Enables boundary-scan

EXTEST operation

SAMPLE 00001 Enables boundary-scan

SAM PL E operation

USR1 00010 Access user-defined

USR2 00011 Access user-defined

CFG_OUT 00100 Access the

configuration bus for

Readback

CFG_IN 00101 Access the

configuration bus for

Configuration

INTEST 00111 Enables boundary-scan

INTES T operation

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1-800-255-7778 Preliminary Product Specification

The public boundary-scan instructions are availab l e prior to

configuration. After configuration, the public instructions

remain av ailable t ogether with an y USERCODE instructions

installed during the configuration. While the SAMPLE and

BYPASS instructions are a vailabl e during configuration, it is

recommended that boundary-scan operations not be per-

formed during this transitional period.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FP GA, and also to read back th e configuration data.

To f acilitate internal scan chains, the User Register prov ides

three outputs (Reset, Upda te, and Shift) that represent the

corresponding states in the boundary-scan internal state

machine.

Figure 12 is a diagram of the Spartan-IIE family boundary

scan logic. It includes three bits of Data Register per IOB,

the IEEE 1149.1 Test Access Port controller, and the

Instruc tion Register with decodes.

USRCODE 01000 E na bles sh ifting out

USER cod e

IDCODE 01001 Enables shifting out of

ID Code

HIZ 01010 Disables output pins

while enabling the

Bypass Register

JSTART 01100 Clock the start-up

sequen ce when

StartupClk is TCK

BYPASS 1 1111 Enables BYPA SS

RESERVED All other

codes Xilinx reserved

instructions

Table 6: Boun dar y-Scan Instru ctions (Continued)

Boundary-Scan

Command Binary

Code[4:0] Description

Figure 12: Spartan-IIE Family Boundary Scan Logic

D Q

IOB

Bypass

IOB IOB

TDO

TDI

IOB IOB IOB

D Q

IOB

D Q

0DQ

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE CLOCK DATA

DATAOUT UPDATE EXTEST

DS001_09_032300

Instruction Register

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 11

Preliminary Product Specification 1-800-255-7778

Bit Seque nce

The bit sequence within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register , while the output-only pins contributes

all three b its.

From a cavity-up view of the chip (as shown in the FPGA

Editor), starting in the upper right chip corner, the boundary

scan data-register bits are ordered as shown in Figure 13.

BSDL (Boundary Scan Description Language) files for

Spar tan-I IE fami ly devices are available on the Xilin x web-

site, in the File Download area.

Development System

Spartan-IIE FPGAs are suppor ted by the Xilinx ISE Foun-

dation and Alliance CAE tools. The basic methodology for

Spartan-IIE design consists of three interrelated

steps: design entry, implementation, and verification.

Industry-standard tools are used for design entry and simu-

lation, while Xilinx pro vides proprietary architecture-specific

tools for implementation.

The Xilinx development system is integrated under the

Xilinx Project Navigator software, providing designers with a

common user interface regardless of their choice of entry

and verification tools. The software simplifies the selection

of implementation options with pull-down m enus and on-line

help.

Application programs ranging from schematic capture to

placement and routing can be accessed through the soft-

ware. The program command sequence is generated prior

to execution, and stored for do cu men tation.

Several advanced software features facilitate Spartan-IIE

design. CORE Generator™ functions, for example, include

macros with relative location constraints to guide their

placement. They help ensure optimal implementation of

common func tions.

For HDL design entry, the Xilinx FPGA development system

provides interfaces to several synthesis design environ-

ments.

A standard interface-file specification, Electronic Design

Interchange Form at (EDIF), simpl ifies file trans fe rs into a nd

out of the development system.

Spartan-IIE FPGAs are supported by a unified library of

standard functions. This library contains over 400 primitiv es

and macros, ranging from 2-input AND gates to 16-bit accu-

mulators, and includes arithmetic functions, comparators,

counters , data registers, decoders, encoders, I/O functions,

latches, Boolean functions, multiple xers, shift registers, and

barrel shifters.

The design environment supports hierarchical design entry,

with high-level designs that comprise major functional

blocks, while lower-level designs define the logic in these

blocks. These hierarchical design elements are automati-

cally combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used fo r each portion of the design.

Design Implementation

The p lace-and-route tools automatically provide the imple-

mentation flow described in this section. The partitioner

takes the EDIF netlist for the design and maps the logic into

the architectural resources of the FPGA (CLBs and IOBs,

for e xample). The placer then determines the best locations

for these blocks based on their interconnections and the

desired performance. Finally, the router interconnects the

blocks.

The algorithms support fully automatic implementation of

most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User p art itioning, placement , and rou ting inform ation

is optionally spec i fied duri ng t he design -e ntry pro cess. The

implementation of highly structured designs can benefit

greatly from basic floorplanning.

The implementation software incorporates timing-driven

placement and routing. Designers specify timing require-

ments along entire paths during design entry. The timing

path analysis routines then recogn ize these user-specified

requirem ents and acc om mod ate them.

Timing requirements are entered in a for m directly relating

to the syste m requirements, such as the targeted clock fre-

quenc y, or the maximum allowa ble delay between two reg-

isters. In this way, the overall performance of the system

along entire signal paths is automatically tailored to

user-generated specifications. Specific timing information

for individual nets is unnecessary.

Design Verification

In addition to conv entional software sim ulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

Figure 13: Boundary Scan Bit Sequence

Bit 0 ( TDO end)

Bit 1

Bit 2

TDO.T

TDO.O

Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

MODE.I

Bottom-edge IOBs (Left to Right)

Right-edge IOBs (Bottom to Top)

BSCANT.UPD

(TDI end)

DS001_10_032300

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

12 www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

devices are infini tely re programmable, d esigns c an be veri-

fied in real tim e without the need for extensive sets o f soft-

ware simulation vectors.

The de v elo pment syst em supports both so ftware simul ation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing informat ion from t he

design database, and back-annotates this information into

the netlist for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

static timing analyzer.

For in-circuit debugging, Xilinx offers a download and read-

back cabl e, which connects the FPGA in the ta rg et syste m

to a PC or workstation. After downloading the design into

the FPGA, the des igner can singl e-step the logic, readback

the contents of the flip-flops, and so observe the internal

logic state. Simple modifications can be downloaded into

the system in a matte r of m inutes.

Configuration

Configuration is the process by which the bitstream of a

design, as generated by the Xilinx development softw are, i s

loaded into the inter nal configura tion memory of the FPGA .

Spartan-IIE de vices support both serial configuration, using

the master/slave serial and JTAG modes, as well as

byte -wide configuration employing the S lave Parallel mode.

Configuration File

Spartan-IIE devices are configured by sequentially loading

frames of data that have been conca ten ated into a configu-

ration file. Table 7 shows how much nonvolatile storage

space is needed for Spartan-IIE de vices.

It is important to note that, while a PROM is commonly used

to store configuration data before loading them into the

FPGA, it is by no means required. Any of a number of diff er-

ent kinds of under populated nonvolatile storage already

av ailable either on or off the board (f or example, hard drives ,

FLASH cards, and so on) can be used. For more informa-

tion on configuration without a PROM, refer to XAPP098,

The Low-Cost, Effi cient Serial Configuration of Spartan

FPGAs.

Modes

Spartan-IIE devices support the following four configuration

modes:

•Slave Serial mode

•Master Serial mode

•Slave Paral lel mode

•Boundary-scan mode

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 8.

Configuration through the boundary-scan port is always

available, inde penden t of th e mod e select ion. Se lecting t he

boundary-scan mode simply turns off the other modes. The

three mo de pi ns have internal pul l-up resi stors, and default

to a logic High if left unconnec ted.

Table 7: Spartan-IIE Configuration File Size

Device Configuration File Size (Bits)

XC2S50E 630,048

XC2S100E 863,840

XC2S150E 1,134,496

XC2S200E 1,442,016

XC2S300E 1,875,648

Table 8: Confi gura tion Mo de s

Co nf ig urat io n Mode Preconfiguration

Pull-ups M0 M1 M2 CCLK

Direction Data Width S er ial DOUT

Master Serial mode No 0 0 0 Out 1 Yes

Yes 0 0 1

Slave Parallel mode

(SelectMAP) Yes 0 1 0 In 8 No

No 0 1 1

Boundary-Scan mode Yes 1 0 0 N/A 1 No

No 1 0 1

Slave Serial mode Yes 1 1 0 In 1 Yes

No 1 1 1

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 13

Preliminary Product Specification 1-800-255-7778

Signals

There are two kinds of pins that are used to configure

Spartan-IIE devices: Dedicated pins perform only specific

configuration-related f unct ions; t he other pi ns can serve as

general purpose I/Os once user operation has begun.

The dedicated pins c omprise the mode pins (M2, M 1, M0),

the configuration clock pin (CCLK), the P ROGRAM pin, the

DONE pin and the boundary-scan pins (TDI, TDO, TMS,

TCK). Depending on the selected configuration mode,

CCLK ma y be an output generated by the FPGA, or may be

generated ex ternally, and provided to the FPGA as an input.

Note that some configuration pins can act as outputs. For

correct operation, these pins require a VCCO of 3.3V to driv e

an LVTTL signal or 2.5V to driv e an LVCMOS signal. All the

rele vant pins fall in banks 2 or 3.

For a more d etailed description than that give n below, see

DS077-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables

and XAPP176, Spartan-II FPGA Series Configuration

and Readback.

The Process

The sequenc e of steps nec essar y to configure S par tan-IIE

devices are shown in Figure 14. The overall flow can be

divided into three different phases.

•Initiating configuration

•Configuration memor y clear

•Loading data frames

•Start-up

The memory clearing and start-up phases are the same for

all configuration modes; however, the steps for the loading

of data frames are different. Thus, the details f or data frame

loading are d escr ibed se parately in th e sec tions devoted to

each mode.

Init iating Conf igura ti on

There are two diff erent w ays to i nitiate the configuration pro-

cess: applying power to the device or asserting the PRO-

GRAM input.

Configuration on power-up occurs aut om atically unless i t is

delayed by the user, as described in a separate section

below. The waveform for configuration on power-up is

shown in DS077-3, Spartan-IIE 1.8V FPGA F amily, DC and

Switching Characteristics. Before configuration can begin,

VCCO Bank 2 must be greater than 1.0V. Furthermore, all

VCCINT power pins must be connected to a 1.8V supply. For

more information on delaying configuration, see Clearing

Configurat i on Memor y, page 14.

Once in user operation, the device can be re-configured

simply by pulling the PROGRAM pin Low. The device

ackno wledges the beginning of the configuration process by

driving DONE Low , then enters the memory-clearing phase. Figure 14: Configuration Flow Di a gra m

FPGA Drives

INIT Low

Abort Start-up

User Holding

INIT

Low?

User Holding

PROGRAM

Low?

FPGA

Drives INIT

and DONE Low

Load

Configuration

Data Frames

User Operation

Configuration

at Power-up

DS001_11_111501

CRC

Correct?

Yes

FPGA

Samples

Mode Pins

Delay

Configuration

Delay

Configuration

Clear

Configuration

Memory

User Pulls

PROGRAM

Low

Start-up Sequence

FPGA Drives DONE High,

Activates I/Os,

Releases GSR net

Yes

Configuration During

User Operation

CCO

AND

CCINT

High?

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

14 www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

Clearing Configuration Memory

The de vice indicates that clearing the configuration memory

is in progress by driving INIT Low.

Delaying Configuration

At this time, the user can delay configuration by holding

either PROGRAM or INIT Low, which c auses the device to

remain in the memory clearing phase. Note that the bidirec-

tional INIT line is driving a Low logic level during memory

clearing. Thus, to avoid contention, use an open-drain driver

to ke e p I N IT Low.

With no delay in f orce, the de vice indicates that the memory

is completely clear by driving INIT High. The FPGA samples

its mode pins on this Low-to-High tra nsition.

Loading Configuration Data

Once INIT is High, the user can begin loading configuration

data frames into t he device. The de tails of lo ading t he con-

figuration data are discussed in the sections treating the

configuration modes individually. The sequence of opera-

tions necessary to load configuration data using the serial

modes is shown in Figure 16. Loading data using the Slave

Parallel mode is shown in Fig ure 19, page 18.

CRC Error Checking

After the loading of configuration data, a CRC value embed-

ded in the configuration fil e i s checked against a CRC value

calculated within the FPGA. If the CRC values do not

match, the FPGA dr ives INIT L ow to indicate that an error

has occurred and configuration is aborted.

To reconfigure the device, the PROGRAM pin should be

asserted to reset the configuration logic. Recycling power

also resets the FPGA for configuration. See Clearing Con-

figur atio n Memory.

Start-up

The star t -up seq uence oversees the transition of the FPGA

from the configuration state to full user operation. A match

of CRC v alues, indicating a successful loading of t he config-

uration data, initiates the sequence.

During star t -up, the device perform s four operations:

1. The assertion of DONE. The failure of DONE to go High

may indicate the unsuccessful loading of configuration

data.

2. The release of the Global Three State (GTS). This

activates all the I/Os.

3. The release of the Global Set Reset (GSR). This allows

all flip-fl ops to change state.

4. The assertion of Global Write Enabl e (GWE). This

allows all RAMs and flip-flops to change state.

By default, these operations are synchronized to CCLK.

The entire start-up sequence lasts eight cycles, called

C0-C7, af ter which t he l oaded design is fully f unctional. The

four operations can be selected to switch on any CCLK

cycle C1-C6 through settings in the Xilinx

Development Software. The default timing for start-up is

shown in the top half of Figure 15; heavy lines show default

settings.

The default Start-up sequence is tha t one CCLK cycle aft er

DONE goes High, the global 3-state signal (GTS) is

released. This pe rmits device out puts to t urn on as neces-

sary.

One CCLK cycle later , the Global Set/Reset (GSR) and Glo-

bal Wri te E nable (G WE) s igna ls are rele as ed. This pe rmits

the internal storage elements to begin changing state in

response to the logic and the user clock.

The bottom half of Figure 15 shows another commonly

used version of the start-up timing known as

Sync-to-DONE. This version makes the GTS, GSR, and

GWE events conditional upon the DONE pin going High.

This timing is important f or a daisy chain of multiple FPGAs

in serial mode, since it ensures that all FPGAs go through

start-up together , after all their DONE pins hav e gone High.

Sync-to-DO NE timing is selected by setting the GTS, GSR,

and GWE cycles to a value of DONE in the configuration

options. This causes these signals to transition one clock

cycle after DONE externally transitio ns High.

The sequence can also be paused at any stage until lock

has been achieved on any or all DLLs.

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 15

Preliminary Product Specification 1-800-255-7778

Serial Modes

There are two serial configuration modes. In Master Serial

mode, the FPGA controls the configuration process by driv-

ing CCLK as an output. In Slave Serial mode, the FPGA

passively receiv es CCLK as an input from an external agent

(e.g., a microprocessor, CPLD, or second FPGA in master

mode) that is controlling the configuration process. In both

modes, the FPGA is configured by loading one bit per CCLK

cycle. The MSB of each configuration data byte is always

written to the DIN pin first.

See Figure 16 for the sequence for loading data into the

Spartan-IIE FPGA serially. This is an expansion of the

"Load Configuration Data Frames" block in Figure 14,

page 13.

Slave Serial M ode

In Slave Seri al m ode, the FPGA’s CCLK pin is driven by an

external source, allowing the FPGA to be configured from

other logic devices such as microprocessors or in a

daisy -cha in configuratio n. Figure 17 shows con nections for

a Master Serial FPGA configuring a Slave Serial FPGA

from a PROM. A Spartan-IIE device in slave serial mode

shou ld be connecte d as shown for the thi rd device from the

left. S lave Serial mod e is selecte d by a <11x> on th e mo de

pins (M0, M1, M2). The weak pull-ups on the mode pins

make sla ve serial the default mode if the pins are left uncon-

nected.

The serial bitstream must be setup at the DIN input pin a

short time before each rising edge of an externally gener-

ated CCLK.

Timing for Slave Serial mode is shown in DS077-3,

Spar t an-IIE 1.8V FPGA Family: DC and Switc hing Charac-

teristics.

Daisy Chain

Multiple FPGAs in Slave Serial mode can be daisy-chained

for configuration from a single source. After an FPGA is

configured, data for the ne xt device is sent to the DOUT pin.

Data on the DOUT pin changes on the rising edge of CCLK.

Note that DOUT changes on the falling edge of CCLK for

some Xilinx families but mixed daisy chains are allowed.

Configuration must be delayed until INIT pins of all

daisy-chained FPGAs are High. For more information, see

Start-up, page 14.

Figure 15: Start-Up Waveforms

Start-up CLK

Default Cycles

Sync to DONE

01234567

DONE High

234567

Phase

Start-up CLK

Phase

DONE

GTS

GSR

GWE

DS001_13_090600

DONE

GTS

GSR

GWE

Figure 16: Loa d in g S e ri al M ode Co nfi gura tio n D at a

Yes

End of

Configuration

Data File?

After INIT

Goes High

User Load One

Configuration

Bit on Next

CCLK Rising Edge

To CRC Check

DS001_14_032300

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

16 www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

Mas t er Seri al M o de

In Master Serial mode, the CCLK output of the FPGA drives

a Xilinx P ROM wh ich feeds a serial s tream of c onf igu ration

data to the FPGA’s DIN input. Figure 17 shows a Master

Serial FPGA configuring a Slave Serial FPGA from a

PROM. A Spartan-IIE device in Mas ter Se rial m ode sh ould

be connected as shown f or the de vice on the left side . Mas-

ter Serial mode is selected by a <00x> on the mode pins

(M 0 , M1, M2). The PROM RESET pin i s d r iven by INIT, and

the CE input is driven by DONE. For more information on

serial P ROMs, see the S part an Ser ial P ROM data sheet at

www.xilinx.com/partinfo/ds078.pdf.

The interface is identical to the slave serial mode except

that an o scillator internal to the FPGA is used to ge nera te

the configuration clock (CCLK). Any of a number of diff erent

frequencies rangin g fro m 4 to 60 M Hz can be set using the

ConfigRate option in the Xilinx development software.

When selecting a CCLK frequency, ensure that the serial

PROM and any daisy-chained FPGAs are fast enough to

support the cloc k rat e. On power-up , while the first 60 b yt es

of the configuration data are being loaded, the CCLK fre-

quency is alway s 2.5 MHz . This frequency is used until the

ConfigRate bits, part of the configuration file, have been

loaded into the FPGA, at which point the frequency

changes to the selecte d Co nfigRat e. Unless a different fre-

quency is specified in the design, the defa ult Con figRate is

4MHz.

The FPGA accepts one bit of configuration data on each ris-

ing CCLK e dge. Af ter the FPGA h as been loaded, the data

for the next device in a daisy-chain is presented on the

DOUT pin after the rising CCLK edge. The timing f or Master

Ser ial mode i s shown in DS077-3, Spartan-IIE, 1.8V FPGA

Family: DC and Switching Characteristics.

Slave Parallel Mode (SelectMAP)

The Slave Parallel mode, also know as SelectMAP, is the

fastest configuration option. Byte-wide data is written into

the FPGA. A BUSY flag is prov ided for c ontrolling the flow of

data at a clock freque nc y above 5 0 MHz .

Figure 18, page 17 shows the connections for two

Spartan-IIE devices using the Slave Parallel mode. Slave

P arallel mode is selected by a <011> on the mode pins (M0,

M1, M2).

The agent controlling configuration is not sho wn. Typically, a

processor, a microcontroller, or CPLD controls the Slave

Parallel interface. The controllin g a gent provides byte-wide

configuration data, CCLK, a Chip Select (CS) signal and a

Write signal (WRITE). If BUSY is asserted (High) by the

FP GA , the data must be held until BUS Y goe s Low.

After configuration, the pins of the Slave Parallel port

(D0-D7) can be used as additional user I/O. Alternatively,

the port may be retained to permit high-speed 8-bit read-

back. Then data can be read by de-asserting WRITE. If

retention is selected, prohibit the D0-D7 pins from being

used as user I/O. See Readback, page 18.

Notes:

1. If t he Driv eDone configuration opti on is not acti ve for any of the FPGAs, pull up DONE with a 3.3K Ω resistor.

Figure 17: Master/Slave Serial Configuration Circuit Diagram

Spartan-IIE

(Master Serial) Xilinx

PROM

PROGRAM

M0 M1

DOUT

CCLK CLK

3.3V

DATA

CE CEO

RESET/OE

DIN

INIT

DONE

PROGRAM

3.3 K

DS077-2_04_102201

GND GND

VCC

3.3V

VCCO

VCCINT

1.8V3.3V 3.3V 1.8V

Spartan-IIE

(Slave)

DONE INIT

PROGRAM

CCLK

DIN DOUT

M0 M1

GND

VCCO

VCCINT

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 17

Preliminary Product Specification 1-800-255-7778

Multiple Spartan-IIE FPGAs can be configured using the

Slave Parallel mode, and be made to start-up simulta-

neously. To co nfigure multiple devices in this way, wire the

individual CCLK, Data, WRITE, and BUSY pins of all the

devices in parallel. The indi vidual devices are loaded sepa-

rately by asserting the CS pin of each device in turn and

writing the appropr iate data. Syn c-to-DONE s tar t-up timing

is used to ensure that the start-up sequence does not begin

until all the FPGAs have been loaded. See Start-up,

page 14.

Write

When using the Slave Parallel Mode, write op erations send

packets of byte-wide configuration data into the FPGA.

F i gur e 19, p age 18 shows a flo wchart of the write sequence

used to load data into the Spartan-IIE FPGA. This is an

ex pansion of the "Load Configuration Data Fr ames" block in

Figure 1 4, page 13.

The timing for Slave Parallel mode is shown in DS077-3,

Spartan-IIE, 1.8V FPGA F am ily: DC and Switching Charac-

teristics.

For the present example, the user holds WRITE and CS

Low throughout the sequence of write operations. Note that

when CS is asserted on successive CCLKs, WRITE must

remain either asse rt ed or de-ass er ted. Ot herwise an ab ort

will be initiated, as in the next section.

1. Dr ive data on to D0-D7. Note th at to avoid contention ,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

mo re than on e device’s CS should be assert ed.

2. On the rising edge of CCLK: If BUSY is Low , the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance will instead

occur on the first clock after BUSY goes Low, and the

data must be held until this happens.

3. Re peat steps 1 and 2 until all the data has been sent.

4. De-assert CS and WRITE.

Figure 18: S lave Pa ral lel Configuration Circuit Diagram

M1 M2

D0:D7

CCLK

WRITE

BUSY

PROGRAM

DONE INIT

CCLK

DATA[7:0]

WRITE

BUSY

CS(0)

Spartan-IIE

DONE

INIT

PROGRAM

M1 M2

D0:D7

CCLK

WRITE

BUSY

PROGRAM

DONE INIT

CS(1)

Spartan-IIE

DS077-2_06_051501

2.5V 2.5V

GND GND

Spartan - IIE 1.8V FPGA Family: F unctional Descri ption

18 www.xilinx.com DS077-2 (v1 .0) November 15, 2001

1-800-255-7778 Preliminary Product Specification

If CCLK is slower than F CCNH, the F PG A will never asser t

BUSY. In this case, the above handshake is unnecessary,

and data can simply be entered into the FPGA every CCLK

cycle.

A configuration packet does not have to be written in one

continuous stretch, rather it can be split into many write

sequences. Each seque nce would involve asser t ion of CS.

In applications where multip le cloc k cycles may be required

to access the configuration data before each byte can be

loaded i nto the Slave Para llel interface, a new byte of da ta

ma y not be ready for each consecutive CCLK edge. In such

a case the CS signal may be de-asserted until the ne xt byte

is valid on D0-D7. While CS is High, the Slav e P arallel inter-

face does not expect any data an d ignores all CCLK transi-

tions. However, to avoid aborting configuration, WRITE

must continue to be asserted while CS is asserted.

Abort

To abort configuration during a write sequence, de-assert

WRITE while holding CS Low. The abort operation is initi-

ated at the rising edge of CCLK. The device will remain

BUSY until the aborted operation is complete. After aborting

configuration, data is assumed to be unaligned to word

boundaries and the FPGA requires a new synchronization

word prior to accepting any new packets.

Boundary-Scan Configuration Mode

In the boundary-scan mode, no nondedicated pins are

required, configuration being done entirely through the

IEEE 1149.1 Test Access Port (TAP ).

Configuration through the TAP uses the special CFG_IN

instruction. This instruction allows data input on TDI to be

converted into data packets for the internal configuration

bus.

The following steps are required to configure the FPGA

through the boundary-scan port.

1. Load the CFG_I N instr uc tion into the b oundary- scan

instruction register (IR)

2. Enter the Shift-DR (SD R) state

3. Shift a standard configuration bitstream into TDI

4. Retur n to Run-Test-Idle (RTI)

5. Lo ad the JSTART instruction into IR

6. Enter the SDR state

7. Clock TCK (if selec ted) through the star tup se quence

(the length is programmable)

8. Retu rn to RTI

Configuration and readback via the TAP is always av ailab le.

The boundary-scan mode simply loc ks out the other modes.

The boundary-scan mode is selected by a <10x> on the

mode pin s (M0, M1, M2).

Readback

The con figuration data s tored in t he Spar tan-IIE configura-

tion memory can be read back for verification. Along with

the configuration data it is possible to read back the con-

tents of all flip-flops/latches, LUT RAMs, and block RAMs.

This capability is used for real-time debugging.

For more detailed information see XAPP176, Spartan-II

FP GA Family Configuration and Readback.

F igure 19: L oad ing Config uratio n Data for the Slave

Parallel Mode

Yes

FPGA

Driving BUSY

High?

After INIT

Goes High

Load One

Configuration

Byte on Next

CCLK Rising Edge

To CRC Check

DS001_19_032300

End of

Configuration

Data File?

Yes

User Drives

WRITE and CS

Low

User Drives

WRITE and CS

High

Spartan - IIE 1.8V FPGA Family: Functiona l Descrip tion

DS077-2 (v1.0) No vember 15, 2001 www.xilinx.com 19

Preliminary Product Specification 1-800-255-7778

Revision History

The Spartan-IIE Family Data Sheet

DS001-1, Spart an- I IE 1 .8V FP GA Fa mily: Introduction and Ordering Information (M odule 1)

DS001-2, Spart an- I IE 1 .8V FPGA Fa m ily: Function al D escrip t io n (Module 2)

DS001-3, Spart an- I IE 1 .8V FP GA Fa mily: DC and Switching Characteristics (Modu le 3)

DS001-4, Spart an- I IE 1 .8V FP GA Fa mily: Pinout Tables (Module 4)

Version No. Date Description

1.0 11/15 /01 Initial X ilinx releas e .