TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 6-A Output D-CAP+TM Mode Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination Check for Samples: TPS53317 FEATURES DESCRIPTION * The TPS53317 is a FET-integrated tracking synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at 1/2 VDDQ with both sink and source capability. The TPS53317 employs D-CAP+TM mode operation that provides ease of use, low external component count and fast transient response. It can also be used for other POL regulation applications requiring up to 6 A. In addition, the TPS53317 still utilizes pulse-widthmodulation (PWM) for output voltage regulation when sinking current. The switchers are turned on in pulses to sink the negative inductor current to the input side. 1 2 * * * * * * * * * * * * * * TI proprietary Integrated MOSFET and Packaging Technology Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current External Tracking Minimum External Components Count 1-V to 6-V Conversion Voltage D-CAP+TM Mode Architecture Supports All MLCC Output Capacitors and SP/POSCAP Selectable SKIP Mode or Forced CCM Optimized Efficiency at Light and Heavy Loads Selectable 600-kHz or 1-MHz Switching Frequency Selectable Overcurrent Limit (OCL) Overvoltage, Over-Temperature and Hiccup Undervoltage Protection Hiccup Undervoltage Protection Adjustable Output Voltage from 0.6 V to 2 V 3.5 mm x 4 mm, 20-Pin QFN Package The TPS53317 features two switching frequency settings (600 kHz and 1 MHz), synchronous operation in skip mode, integrated droop support, external tracking support, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, EN/Input UVLO protection, and both output ceramic and SP/POS/AL capacitor support. It supports supply and conversion voltages up to 6.0 V, and output voltages adjustable from 0.6 V to 2.0 V. It also provides external tracking support. The TPS53317 is available in the 3.5 mm by 4 mm, 20-pin QFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from -40C to 85C. APPLICATIONS * * * Memory Termination Regulator for DDR, DDR2, DDR3 and DDR3L VTT Termination Low-Voltage Applications for 1-V to 6-V Input Rails DDR VDDQ IN VIN TPS53317 BST EN SW COMP VREF PGOOD VOUT PGOOD PGND VOUT REFIN MODE 5VIN V5IN GND PowerPAD UDG-11105 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PACKAGE (2) ORDERING NUMBER PINS OUTPUT SUPPLY MINIMUM QUANTITY -40C to 85C Plastic QFN (RGB) TPS53317RGBR 20 Tape and reel 3000 TPS53317RGBT 20 Mini reel 250 (1) (2) ECO PLAN Green (RoHS and no Pb/Br) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. THERMAL INFORMATION TPS53317 THERMAL METRIC (1) RGB UNITS 20 PINS Junction-to-ambient thermal resistance (2) JA 35.5 (3) JCtop Junction-to-case (top) thermal resistance JB Junction-to-board thermal resistance (4) 12.4 JT Junction-to-top characterization parameter (5) 0.5 JB Junction-to-board characterization parameter (6) JCbot (1) (2) (3) (4) (5) (6) (7) 2 Junction-to-case (bottom) thermal resistance 39.6 (7) C/W 12.5 3.7 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN UNIT MAX VIN, V5IN, BST (with respect to SW) -0.3 7.0 BST -0.3 14.0 SW -2 7 EN -0.3 7 MODE, REFIN -0.3 3.6 -1 3.6 COMP, VREF -0.3 3.6 PGOOD -0.3 7.0 PGND -0.3 0.3 Junction temperature TJ -40 150 Storage temperature Tstg -55 150 C 300 C Input voltage range VOUT Output voltage range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) V V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VALUE MIN VIN, EN, BST (with respect fo SW) Input voltage range Output voltage range -0.1 TYP MAX 6.5 V5IN 4.5 6.5 BST -0.1 13.5 SW -1.0 6.5 VOUT, MODE, REFIN -0.1 3.5 COMP, VREF -0.1 3.5 PGOOD -0.1 6.5 PGND -0.1 0.1 -40 85 Operating temperature range, TA Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 UNIT V V C 3 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO IVINSD VIN shutdown current EN = 'LO' V5VIN 5VIN supply voltage V5IN voltage range I5VIN 5VIN supply current EN ='HI', V5IN supply current I5VINSD 5VIN shutdown current EN = `LO', V5IN shutdown current VV5UVLO V5IN UVLO Ramp up; EN = 'HI' VV5UVHYS V5IN UVLO hysteresis Falling hysteresis VVREFUVLO REF UVLO (1) Rising edge of VREF, EN = 'HI' VVREFUVHYS REF UVLO hysteresis (1) VPOR5VFILT Reset 4.5 4.20 0.02 5 5.0 6.5 1.1 2 mA 0.2 7.0 A 4.37 4.50 440 OVP latch is reset by V5IN falling below the reset threshold 1.5 A V V mV 1.8 V 100 mV 2.3 3.1 V VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER VOUTTOL VOUT accuracy VREFIN = 1 V, No droop -1% 0% 1% IVREF = 0 A 1.98 2.00 2.02 IVREF = 50 A 1.975 2.000 2.025 VVREF VREF IREFSNK VREF sink current GM Transconductance VCM Common mode input voltage range (1) 0 2 V VDM Differential mode input voltage 0 80 mV ICOMPSNK COMP pin maximum sinking current VCOMP = 2 V, (VREFIN - VOUT) = 80 mV ICOMPSRC COMP pin maximum sourcing current VCOMP = 2 V VOFFSET Input offset voltage TA = 25C RDSCH Output voltage discharge resistance f-3dbVL -3dB Frequency (1) VVREF = 2.05 V 2.5 V mA 1.00 mS 80 A -80 A 0 mV 42 4.5 6.0 7.5 MHz 43 53 57 mV/A CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING Gain from the current of the low-side FET to PWM comparator when PWM = "OFF" ACSINT Internal current sense gain IOCL Positive overcurrent limit (valley) 7.6 IOCL(neg) Negative overcurrent limit (valley) -9.3 VZXOFF Zero crossing comp internal offset 0 A A mV PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN VPGDLL PGOOD deassert to lower (PGOOD Low) VPGHYSHL PGOOD high hysteresis VPGDLH PGOOD de-assert to higher (PGOOD Low) VPGHYSHH PGOOD high hysteresis VINMINPG Minimum VIN voltage for valid PGOOD Measured at the VIN pin with a 2-mA sink current on PGOOD pin VOVP OVP threshold Measured at the VOUT pin wrt/ VREFIN UVP threshold Measured at the VOUT pin wrt/ VREFIN, device latches OFF, begins soft-stop VUVP (1) THSD Thermal shutdown THSD(hys) Thermal Shutdown hysteresis (1) (1) 4 Measured at the VOUT pin wrt/ VREFIN 84% 8% Measured at the VOUT pin wrt/ VREFIN 116% -8% Latch off controller, attempt soft-stop. Controller re-starts after temperature has dropped 0.9 1.3 1.5 117% 120% 123% 65% 68% 71% V 145 C 10 C Ensured by design, not production tested. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT DRIVERS: BOOT STRAP SWITCH RDSONBST Internal BST switch on-resistance IBST = 10 mA, TA = 25C 10 IBSTLK Internal BST switch leakage current VBST = 14 V, VSW = 7 V 1 A TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz 210 VVIN = 5 V, VVOUT = 1.05 V, fSW = 600 kHz 310 Minimum OFF time VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz, DRVL on, SW = PGND, VVOUT < VREFIN 270 ns tINT(SS) Soft-start time From EN = HI to VOUT =95%, default setting 1.6 ms tINT(SSDLY) Internal soft-start delay time From EN = HI to VOUT ramp starts 260 s tPGDDLY PGOOD startup delay time External tracking 8 ms tPGDPDLYH PGOOD high propagation delay time 50 mV over drive, rising edge tPGDPDLYL PGOOD low propagation delay time 50 mV over drive, falling edge 10 s tOVPDLY OVP delay time Time from the VOUT pin out of +20% of REFIN to OVP fault 10 s Time from EN_INT going high to undervoltage fault is ready 2 External tracking from VOUT ramp starts 8 tONESHOTC PWM one-shot tMIN(off) (2) tUVDLYEN Undervoltage fault enable delay tUVPDLY UVP delay time 0.8 Time from the VOUT pin out of -30% of REFIN to UVP fault 1 ns 1.2 ms ms 256 s LOGIC PINS: I/O VOLTAGE AND CURRENT VPGDPD PGOOD pull-down voltage PGOOD low impedance, ISINK = 4 mA, VV5IN = 4.5 V IPGDLKG PGOOD leakage current PGOOD high impedance, forced to 5.5 V VENH EN logic high EN, VCCP logic VENL EN logic low EN, VCCP logic IEN EN input current VMODETH MODE threshold voltage (3) IMODE MODE current (2) (3) -1 0 0.3 V 1 A 2 V 0.5 V 1 A Threshold 1 80 130 180 Threshold 2 200 250 300 Threshold 3 370 420 470 Threshold 4 1.765 1.800 1.850 15 mV V A Ensured by design, not production tested. See Table 2 for descriptions of MODE parameters. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 5 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com PGOOD MODE EN 20 19 18 17 BST 5VIN TPS53317 RGB PACKAGE (Top View) SW PGND 3 13 SW VIN 4 SW VIN 5 12 Exposed Thermal Pad 11 6 7 8 9 10 VOUT 14 REFIN 2 COMP PGND VREF 1 GND PGND 16 15 SW SW Table 1. PIN FUNCTIONS PIN NO. NAME I/O DESCRIPTION 16 BST I Power supply for internal high-side gate driver. Connect a 0.1-F bootstrap capacitor between this pin and the SW pin. 8 COMP O Connect series R-C filter between this pin and VREF for loop compensation. 17 EN I Enable of the SMPS (3.3-V logic compatible). 6 GND - Signal ground. 18 MODE I Allows selection of switching frequencies light-load modes. (See Table 2) PGND I Power ground. Source terminal of the rectifying low-side power FET. Positive input for current sensing. 19 PGOOD O Power good output. Connect pull-up resistor. 9 REFIN 1 2 3 Target output voltageinput pin. Apply voltage between 0.6 V to 2.0 V. 11 12 13 SW I/O Switching node output. Connect to the external inductor. Also serve as current-sensing negative input. V5IN I 5-V power supply for analog circuits and gate drive. VIN I Power supply input pin. Drain terminal of the switching high-side power FET. 14 15 20 4 5 6 10 VOUT I Output voltage monitor input pin. 7 VREF O 2.0-V reference output. Connect a 0.22-F ceramic capacitor to GND. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 BLOCK DIAGRAM TPS53317 VREFIN -30% VREFIN + 16% + UV 19 PGOOD + Delay + + OV VREFIN - 16% GND VREFIN +20% COMP REFIN 8 VS Amplifier UVP OVP + + 9 Ramp Comp VREF On-Time Selection 18 MODE 16 BST + SS DAC EN 17 Control Logic * On/Off Time * Minimum On /Off * SKIP/ODA/FPWM * OCL/OVP/UVP * DIsharge 15 ?A PWM 7 DRVH 4 VIN 5 VIN VBG VOUT 10 Current Sense Amplifier + 11 SW 8R 12 SW + tON OneShot OC PGND R XCON 13 SW 14 SW GND SW Current Sense 15 SW 18 V5IN ZC DRVL + ZC Threshold Modulation GND 6 1 PGND 2 PGND 3 PGND Discharge Pad PGND UDG-11106 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 7 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com EN 5VIN 2.2 ?F 100 k? PGOOD 20 19 18 V5IN PGOOD MODE 10 ?F 10 ?F 17 16 EN BST 0.1?? F 1 PGND SW 15 2 PGND SW 14 3 PGND 4 VIN SW 12 5 VIN SW 11 0.25 ?H VOUT = 0.75 V 10 ?F 0.1?? F SW 13 TPS53317 47 ?F 47 ?F 47 ?F DDR VDDQ IN (1.5 V) GND VREF 6 7 COMP REFIN VOUT 8 9 10 33 pF 100 k? VDDQ 1?? F 100 k? 1.5 nF 6.8 k? UDG-11107 Figure 1. Typical DDR Memory Termination Regulator Circuit (Non-droop Configuration) EN 5VIN 2.2 ?F 100 k? PGOOD 20 19 18 V5IN PGOOD MODE 10 ?F 10 ?F 17 16 EN BST 0.1?? F 1 PGND SW 15 2 PGND SW 14 3 PGND 4 VIN SW 12 5 VIN SW 11 0.25 ?H VOUT = 0.75 V 10 ?F 0.1?? F SW 13 TPS53317 47 ?F 47 ?F 47 ?F DDR VDDQ (1.5 V) GND 6 VREF COMP REFIN VOUT 7 8 9 10 1?? F 100 k? 6.8 k? 60 k? UDG-11108 Figure 2. Application Using Droop Configuration 8 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 APPLICATION INFORMATION Functional Overview The TPS53317 is a D-CAP+TM mode adaptive on-time converter. Integrated high-side and low-side FET supports a maximum of 6-A DC output current. The converter automatically runs in discontinuous conduction mode (DCM) to optimize light-load efficiency. Multiple switching frequencies are provided to enable optimization of the power chain for the cost, size and efficiency requirements of the design (see Table 2). In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS53317, the cycle begins when the current feedback reaches an error voltage level which is the amplified difference between the reference voltage and the feedback voltage. PWM Operation Referring to Figure 3, in steady state, continuous conduction mode, the converter operates in the following way. Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCS) is higher than the error amplifier output (VCOMP). VCS falls until it hits VCOMP, which contains a component of the output ripple voltage. VCS is not directly accessible by measuring signals on pins of TPS53317. The PWM comparator senses where the two waveforms cross and triggers the on-time generator. Current Feedback Voltage (V) VCS VCOMP VREF tON t Time (ms) UDG-10187 Figure 3. D-CAP+TM Mode Basic Waveforms The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side FET on-time. The TPS53317 also provides a single-ended differential voltage (VOUT) feedback to increase the system accuracy and reduce the dependence of circuit performance on layout. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 9 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com PWM Frequency and Adaptive on Time Control In general, the on-time (at the SW node) can be estimated by Equation 1. V 1 tON = OUT VIN fSW where * fSW is the frequency selected by the connection of the MODE pin (1) The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value. Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in Table 2. Non-Droop Configuration The TPS53317 can be configured as a non-droop solution. The benefit of a non-droop approach is that load regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is recommended. For the Intel system agent application, non-droop is recommended as the standard configuration. The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the phase delay at unity gain cross over frequency of the converter. The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the value of the capacitor (CC) can be calculated by knowing where the zero location is desired. Figure 4 shows the basic implementation of the non-droop mode using the TPS53317. GMV = 1 mS VREFIN RC CC + + - RDS(on) LOUT + + GMC= 1 mS PWM Comparator Driver ROUT RLOAD COUT 8 kW + - ESR VREF UDG-11168 Figure 4. Non-Droop Mode Basic Implementation 10 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 Figure 5 shows shows the load regulation using non-droop configuration. Figure 6 shows the transient response of TPS53317 using non-droop configuration, where COUT = 3 x 47 F. The applied step load is from 0 A to 2 A. 0.85 0.83 Output Voltage (V) 0.81 0.79 0.77 0.75 0.73 0.71 0.69 0.67 0.65 Non-Droop Configuration 1 2 3 4 Output Current (A) 5 6 Figure 5. Load Regulation for 1.5-V Input and 0.75V Output (Non-Droop Configuration) Figure 6. Non-Droop Configuration Transient Response CH 2: VOUT (20 mV/div) CH 4: ILOAD (1 A/div) CH 3: SW (1 V/div) Droop Configuration The terminology for droop is the same as load line or voltage positioning as defined in the Intel CPU VCORE specification. Based on the actual tolerance requirement of the application, load-line set points can be defined to maximize either cost savings (by reducing output capacitors) or power reduction benefits. Accurate droop voltage response is provided by the finite gain of the droop amplifier. The equation for droop voltage is shown in Equation 2. I(L) A VDROOP = CSINT RDROOP GM where * * * * * low-side on-resistence is used as the current sensing element ACSINT is a constant, which nominally is 53 mV/A. I(L) is the DC current of the inductor, or the load current RDROOP is the value of resistor from the COMP pin to the VREF pin GM is the transconductance of the droop amplifier with nominal value of 1 mS Equation 3 can be used to easily derive RDROOP for any load line slope/droop design target. V A CSINT A CSINT \ RDROOP = RLOAD _ LINE = DROOP = I(L) RDROOP GM RLOAD _ LINE GM Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 (2) (3) 11 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com Figure 7 shows the basic implementation of the droop mode using the TPS53317. GMV = 1 mS VREFIN RDROOP + + - RDS(on) LOUT + + GMC= 1 mS PWM Comparator Driver ROUT RLOAD COUT 8 kW + - ESR VREF UDG-11167 Figure 7. DROOP Mode Basic Implementation The droop (voltage positioning) method was originally recommended to reduce the number of external output capacitors required. The effective transient voltage range is increased because of the active voltage positioning (see Figure 8). Load insertion ILOAD Load release Droop VOUT setpoint at 0 A Maximum transient voltage = (5%-1%) x 2 = 8% x VOUT VOUT setpoint at 6 A NonDroop Maximum overshoot voltage =(5%-1%) x 1 = 4% x VOUT VOUT setpoint at 0 A Maximum undershoot voltage =(5%-1%) x 1 = 4% x VOUT UDG-11080 Figure 8. DROOP vs Non-DROOP in Transient Voltage Window In applications where the DC and the AC tolerances are not separated, which means there is not a strict DC tolerance requirement, the droop method can be used. 12 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 Table 2. Mode Definitions MODE MODE RESISTANCE (k) LIGHT-LOAD POWER SAVING MODE SWITCHING FREQUENCY (fSW) OVERCURRENT LIMIT (OCL) VALLEY (A) 1 0 600 kHz 6 2 12 600 kHz 4 3 22 1 MHz 4 4 33 1 MHz 6 5 47 600 kHz 6 6 68 600 kHz 4 1 MHz 4 1 MHz 6 7 100 8 OPEN SKIP PWM Figure 9 shows the load regulation of the 1.5-V rail using an RDROOP value of 6.8 k. Figure 10 shows the transient response of the TPS53317 using droop configuration and COUT = 3 x 47 F. The applied step load is from 0 A to 2 A. 0.85 0.83 Output Voltage (V) 0.81 0.79 0.77 0.75 0.73 0.71 0.69 0.67 0.65 Droop Configuration 0 1 2 3 4 Output Current (A) 5 6 Figure 9. Load Regulation for 1.5-V Input and 0.75V Output (Droop Configuration) Figure 10. Droop Configuration Transient Response CH 2: VOUT (20 mV/div) CH 4: ILOAD (1 A/div) CH 3: SW (1 V/div) Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 13 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com Light-Load Power Saving Features The TPS53317 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range. The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as well. TPS53317 also provides a special light-load power saving feature, called ripple reduction. Essentially, it reduces the on-time in SKIP mode to effectively reduce the output voltage ripple associated with using an all MLCC capacitor output power stage design. Power Sequences Non-Tracking Startup The TPS53317 can be configured for non-tracking application. When non-tracking is configured, output voltage is regulated to the REFIN voltage which taps off the voltage dividers from the 2VREF. Either the EN pin or the V5IN pin can be used to start up the device. The TPS53317 uses internal voltage servo DAC to provide a precise 1.6ms soft-start time during soft-start initialization. (See Figure 11) Tracking Startup TPS53317 can also be configured for tracking application. When tracking configuration is desired, output voltage is also regulated to the REFIN voltage which comes from external power source. In order for TPS53317 to differentiate between a non-tracking configuration or a tracking configuration, there is a minimum delay time of 260 s required between the time when the EN pin or the 5VIN pin is validated to the time when the REFIN pin voltage can be applied, in order for the TPS53317 to track properly (see Figure 12). The valid REFIN voltage range is between 0.6 V to 2 V. Protection Features The TPS53317 offers many features to protect the converter power chain as well as the system electronics. 5-V Undervoltage Protection (UVLO) The TPS53317 continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The converter starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is reached, the converter transitions the phase node into a off function. And the converter remains in the off state until the device is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does not have a UVLO function. Power Good Signals The TPS53317 has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage condition on V5IN or any other fault is detected. Output Overvoltage Protection (OVP) In addition to the power good function described above, the TPS53317 has additional OVP and UVP thresholds and protection circuits. An OVP condition is detected when the output voltage is approximately 120% x VREFIN. In this case, the converter de-asserts the PGOOD signals and performs the overvoltage protection function. During OVP, the lowside FET is always on before triggering a negative overcurrent. When a negative OC is also tripped, the low-side FET is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. When the VOUT pin voltage drops below 400 mV, the low-side FET is turned off (non-latch) until the VOUT pin voltage exceeds 400 mV again. 14 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 Output Undervoltage Protection (UVP) Output undervoltage protection works in conjunction with the current protection described in the Overcurrent Protection and Overcurrent Limit sections. If the output voltage drops below 70% of VREFIN, after approximately a 250 s delay, the device stops switching and enters hiccup mode. After a hiccup waiting time, a re-start is attempted. If the fault condition is not cleared, hiccup mode operation may continue indefinitely. Overcurrent Protection Both positive and negative overcurrent protection are provided in the TPS53317: * Overcurrent Limit (OCL) * Negative OCL (level same as positive OCL) Overcurrent Limit If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The TPS53317 uses a valley current limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The minimum valley OCL is 6 A or 4 A (depending on mode selection) over process and temperature. During the overcurrent protection event, the output voltage likely droops until the UVP limit is reached. Then, the converter de-asserts the PGOOD pin, and then enters hiccup mode after an 250-s delay. The converter remains in hiccup mode until the fault is cleared.. 1 IOCL(dc ) = IOCL(valley ) + IP-P 2 (4) Negative OCL The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter continues to act in a valley mode, the absolute value of the negative OCL set point is typically -6.5 A or -4.5 A (depending on mode selection) . Thermal Protection Thermal Shutdown The TPS53317 has an internal temperature sensor. When the temperature reaches a nominal 145C, the device shuts down until the temperature cools by approximately 10C. Then the converter restarts. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 15 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com Startup Timing Diagrams Figure 11. Non-Tracking Start-Up Figure 12. Tracking Start-Up 16 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 TPS53317 www.ti.com SLUSAK4B - JUNE 2011 - REVISED MAY 2012 95 0.760 90 0.758 85 0.756 Output Voltage (V) Efficiency (%) TYPICAL CHARACTERISTICS 80 75 70 65 Skip Mode, fSW = 600 kHz Skip Mode, fSW =1 MHz PWM Mode, fSW = 600 kHz PWM Mode, fSW = 1 MHz 60 55 50 0 1 2 3 4 Output Current (A) 5 0.754 0.752 0.750 0.748 0.746 Skip Mode, fSW = 600 kHz Skip Mode, fSW =1 MHz PWM Mode, fSW = 600 kHz PWM Mode, fSW = 1 MHz 0.744 0.742 6 0.740 0 1 G001 Figure 13. Efficiency vs Output Current (1.5-V Input and 0.75-V Output) 2 3 4 Output Current (A) 5 6 G001 Figure 14. Output Voltage vs Output Current (1.5-V Input and 0.75-V Output) LAYOUT CONSIDERATIONS Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout. * Connect PGND pins (or at least one of the pins) to the thermal PAD underneath the device. Also connect GND pin to the thermal PAD underneath the device. Use four vias to connect the thermal pad to internal ground planes. * Place VIN, V5IN and VREF decoupling capacitors as close to the device as possible. * Use wide traces for the VIN, VOUT, PGND and SW pins. These nodes carry high current and also serve as heat sinks. * Place feedback and compensation components as close to the device as possible. * Place COMP analog signal away from noisy signals (SW, BST). Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 17 TPS53317 SLUSAK4B - JUNE 2011 - REVISED MAY 2012 www.ti.com Changes from Original (JUNE 2011) to Revision A Page * Changed from "SKIP and Forced CCM" to "SKIP or Forced CCM" in FEATURES ............................................................. 1 * Changed from "600-kHz and 1-MHz Switching" to "600-kHz or 1-MHz Switching" in FEATURES ..................................... 1 * Added clarity to Simplified Application drawing .................................................................................................................... 1 * Changed from "fSW = 600 kHz" to " fSW = 1 MHz" for tON(min) in EC table ............................................................................. 5 * Added clarity to BLOCK DIAGRAM ...................................................................................................................................... 7 Changes from Revision A (JULY 2011) to Revision B Page * Changed device title ............................................................................................................................................................. 1 * Added Memory Termination bullet in APPLICATIONS ......................................................................................................... 1 * Added clarity to DESCRIPTION ........................................................................................................................................... 1 * Changed title of Figure 1 ...................................................................................................................................................... 8 18 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS53317 PACKAGE OPTION ADDENDUM www.ti.com 25-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS53317RGBR ACTIVE VQFN RGB 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS53317RGBT ACTIVE VQFN RGB 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53317RGBR VQFN RGB 20 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 TPS53317RGBR VQFN RGB 20 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 TPS53317RGBT VQFN RGB 20 250 180.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 TPS53317RGBT VQFN RGB 20 250 180.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53317RGBR VQFN RGB 20 3000 367.0 367.0 35.0 TPS53317RGBR VQFN RGB 20 3000 367.0 367.0 35.0 TPS53317RGBT VQFN RGB 20 250 210.0 185.0 35.0 TPS53317RGBT VQFN RGB 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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