ATMEGA644PA-MU - Atmel - searchdatasheet.com

Features

•High-performance, low-power 8-bit Atmel® AVR® Microcontroller

•Advanced RISC architecture

– 131 powerful Instructions – most single-clock cycle execution

– 32 × 8 general purpose working registers

– Fully static operation

– Up to 20MIPS throughput at 20MHz

– On-chip 2-cycle multiplier

•High endurance non-volatile memory segments

– 16/32/64/128KBytes of In-System Self-programmable Flash program memory

– 512/1K/2K/4KBytes EEPROM

– 1/2/4/16KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C (1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

•Atmel QTouch® library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

•JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1×, 10× or 200×

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

•I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

•Operating Voltages

– 1.8 - 5.5V

•Speed Grades

– 0 - 4MHz @ 1.8 - 5.5V

– 0 - 10MHz @ 2.7 - 5.5V

– 0 - 20MHz @ 4.5 - 5.5V

•Power Consumption at 1MHz, 1.8V, 25°C

– Active: 0.4mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32kHz RTC)

Note: 1. See ”Data retention” on page 9 for details.

8-bit Atmel

Microcontroller

with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164A

ATmega164PA

ATmega324A

ATmega324PA

ATmega644A

ATmega644PA

ATmega1284

ATmega1284P

Summary

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

1. Pin configurations

1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P

Figure 1-1. Pinout.

Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on

the board to ensure good mechanical stability.

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/ICP3/MOSI) PB5

(PCINT14/OC3A/MISO) PB6

(PCINT15/OC3B/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0/T3) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

PC3 (TMS/PCINT19)

PC2 (TCK/PCINT18)

PC1 (SDA/PCINT17)

PC0 (SCL/PCINT16)

PD7 (OC2A/PCINT31)

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

(PCINT13/ICP3/MOSI) PB5

(PCINT14/OC3A/MISO) PB6

(PCINT15/OC3B/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0/T3) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

(PCINT31/OC2A) PD7

VCC

GND

(PCINT16/SCL) PC0

(PCINT17/SDA) PC1

(PCINT18/TCK) PC2

(PCINT19/TMS) PC3

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

TQFP/QFN/MLF

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

1.2 Pinout - DRQFN for Atmel ATmega164A/164PA/324A/324PA

Figure 1-2. DRQFN - pinout.

Table 1-1. DRQFN - pinout.

A1 PB5 A7 PD3 A13 PC4 A19 PA 3

B1 PB6 B6 PD4 B11 PC5 B16 PA 2

A2 PB7 A8 PD5 A14 PC6 A20 PA 1

B2 RESET B7 PD6 B12 PC7 B17 PA 0

A3 VCC A9 PD7 A15 AVCC A21 VCC

B3 GND B8 VCC B13 GND B18 GND

A4 XTAL2 A10 GND A16 AREF A22 PB0

B4 XTAL1 B9 PC0 B14 PA7 B19 PB1

A5 PD0 A11 PC1 A17 PA 6 A23 PB2

B5 PD1 B10 PC2 B15 PA 5 B20 PB3

A6 PD2 A12 PC3 A18 PA 4 A24 PB4

Top view Bottom view

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A12

B10

A11

A10

A24

B20

A23

B19

A22

B18

A21

B17

A20

B16

A19

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A10

A11

B10

A12

A19

B16

A20

B17

A21

B18

A22

B19

A23

B20

A24

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

1.3 Pinout - VFBGA for Atmel ATmega164A/164PA/324A/324PA

Figure 1-3. VFBGA - pinout.

Table 1-2. BGA - pinout.

1234567

AGND PB4 PB2 GND VCC PA2 GND

BPB6 PB5 PB3 PB0 PA0 PA3 PA5

CVCC RESET PB7 PB1 PA1 PA6 AREF

DGND XTAL2 PD0 GND PA4 PA7 GND

EXTAL1 PD1 PD5 PD7 PC5 PC7 AVCC

FPD2 PD3 PD6 PC0 PC2 PC4 PC6

GGND PD4 VCC GND PC1 PC3 GND

1234567

7654321

Top view Bottom view

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

2. Overview

The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS

8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful

instructions in a single clock cycle, the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approach-

ing 1 MIPS per MHz allowing the system designer to optimize power consumption versus

processing speed.

2.1 Block diagram

Figure 2-1. Block diagram.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

CPU

GND

VCC

RESET

Power

Supervision

POR / BOD &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

XTAL1

XTAL2

PORT A (8)

PORT D (8)

PD7..0

PORT C (8)

PC5..0

TWI

SPI

EEPROM

JTAG/OCD

16bit T/C 1

8bit T/C 2

8bit T/C 0

SRAMFLASH

USART 0

Internal

Bandgap reference

Analog

Comparator

A/D

Converter

PA7..0

PORT B (8)

PB7..0

USART 1

TOSC1/PC6TOSC2/PC7

16bit T/C 1

16bit T/C 3

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following

features:

16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities,

512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general

purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with com-

pare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit

ADC with optional differential input stage with programmable gain, programmable Watchdog

Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,

also used for accessing the On-chip Debug system and programming and six software select-

able power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode

saves the register contents but freezes the Oscillator, disabling all other chip functions until the

next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to

run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC

Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and

ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Reso-

nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up

combined with low power consumption. In Extended Standby mode, both the main Oscillator

and the Asynchronous Timer continue to run.

Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels

functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers

robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key

Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcon-

troller that provides a highly flexible and cost effective solution to many embedded control

applications.

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of

program and system development tools including: C compilers, macro assemblers, program

debugger/simulators, in-circuit emulators, and evaluation kits.

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA,

ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P

2.3 Pin Descriptions

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

2.3.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source current if

the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Port A also serves the functions of various special features of the Atmel

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80.

2.3.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 82.

2.3.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A,

ATmega644PA, ATmega1284 and ATmega1284P.

Device Flash EEPROM RAM Units

ATmega164A 16K 512 1K

bytes

ATmega164PA 16K 512 1K

ATmega324A 32K 1K 2K

ATmega324PA 32K 1K 2K

ATmega644A 64K 2K 4K

ATmega644PA 64K 2K 4K

ATmega1284 128K 4K 16K

ATmega1284P 128K 4K 16K

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the Atmel

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85.

2.3.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88.

2.3.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in ”” on page 336.

Shorter pulses are not guaranteed to generate a reset.

2.3.8 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.9 XTAL2

Output from the inverting Oscillator amplifier.

2.3.10 AVCC

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-

nally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected

to VCC through a low-pass filter.

2.3.11 AREF

This is the analog reference pin for the Analog-to-digital Converter.

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for

download on http://www.atmel.com/avr.

4. About code examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

The code examples assume that the part specific header file is included before compilation. For

I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-

tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and

"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

Note: 1.

5. Data retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

6. Capacitive touch sensing

The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces

on most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and

QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library

for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-

nels and sensors, and then calling the touch sensing API’s to retrieve the channel information

and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the

Atmel QTouch Library User Guide - also available for download from the Atmel website.

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

7. Register summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - -

(0xFE) Reserved - - - - - - - -

(0xFD) Reserved - - - - - - - -

(0xFC) Reserved - - - - - - - -

(0xFB) Reserved - - - - - - -

(0xFA) Reserved - - - - - - - -

(0xF9) Reserved - - - - - - -

(0xF8) Reserved - - - - - - - -

(0xF7) Reserved - - - - - - - -

(0xF6) Reserved - - - - - - - -

(0xF5) Reserved - - - - - - -

(0xF4) Reserved - - - - - - - -

(0xF3) Reserved - - - - - - - -

(0xF2) Reserved - - - - - - - -

(0xF1) Reserved - - - - - - -

(0xF0) Reserved - - - - - - - -

(0xEF) Reserved - - - - - - -

(0xEE) Reserved - - - - - - - -

(0xED) Reserved - - - - - - - -

(0xEC) Reserved - - - - - - - -

(0xEB) Reserved - - - - - - -

(0xEA) Reserved - - - - - - - -

(0xE9) Reserved - - - - - - - -

(0xE8) Reserved - - - - - - - -

(0xE7) Reserved - - - - - - -

(0xE6) Reserved - - - - - - - -

(0xE5) Reserved - - - - - - - -

(0xE4) Reserved - - - - - - - -

(0xE3) Reserved - - - - - - -

(0xE2) Reserved - - - - - - - -

(0xE1) Reserved - - - - - - -

(0xE0) Reserved - - - - - - -

(0xDF) Reserved - - - - - - - -

(0xDE) Reserved - - - - - - - -

(0xDD) Reserved - - - - - - - -

(0xDC) Reserved - - - - - - -

(0xDB) Reserved - - - - - - - -

(0xDA) Reserved - - - - - - - -

(0xD9) Reserved - - - - - - - -

(0xD8) Reserved - - - - - - - -

(0xD7) Reserved - - - - - - - -

(0xD6) Reserved - - - - - - - -

(0xD5) Reserved - - - - - - - -

(0xD4) Reserved - - - - - - - -

(0xD3) Reserved - - - - - - - -

(0xD2) Reserved - - - - - - - -

(0xD1) Reserved - - - - - - - -

(0xD0) Reserved - - - - - - - -

(0xCF) Reserved - - - - - - - -

(0xCE) UDR1 USART1 I/O Data Register 192

(0xCD) UBRR1H - - - - USART1 Baud Rate Register High Byte 196/209

(0xCC) UBRR1L USART1 Baud Rate Register Low Byte 196/209

(0xCB) Reserved - - - - - - - -

(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11/UDORD0(5) UCSZ10/UCPHA0(5) UCPOL1 194/208

(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 193/207

(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 192/207

(0xC7) Reserved - - - - - - - -

(0xC6) UDR0 USART0 I/O Data Register 192

(0xC5) UBRR0H - - - - USART0 Baud Rate Register High Byte 196/209

(0xC4) UBRR0L USART0 Baud Rate Register Low Byte 196/209

(0xC3) Reserved - - - - - - - -

(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01/UDORD0(5) UCSZ00/UCPHA0(5) UCPOL0 194/208

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 193/207

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 192/207

(0xBF) Reserved - - - - - - - -

(0xBE) Reserved - - - - - - - -

(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 -238

(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN -TWIE235

(0xBB) TWDR 2-wire Serial Interface Data Register 237

(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 238

(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 237

(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 235

(0xB7) Reserved - - - - - - - -

(0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 161

(0xB5) Reserved - - - - - - - -

(0xB4) OCR2B Timer/Counter2 Output Compare Register B 160

(0xB3) OCR2A Timer/Counter2 Output Compare Register A 160

(0xB2) TCNT2 Timer/Counter2 (8 Bit) 160

(0xB1) TCCR2B FOC2A FOC2B -- WGM22 CS22 CS21 CS20 159

(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 --WGM21WGM20156

(0xAF) Reserved - - - - - - - -

(0xAE) Reserved - - - - - - - -

(0xAD) Reserved - - - - - - - -

(0xAC) Reserved - - - - - - - -

(0xAB) Reserved - - - - - - - -

(0xAA) Reserved - - - - - - - -

(0xA9) Reserved - - - - - - - -

(0xA8) Reserved - - - - - - - -

(0xA7) Reserved - - - - - - - -

(0xA6) Reserved - - - - - - - -

(0xA5) Reserved - - - - - - - -

(0xA4) Reserved - - - - - - - -

(0xA3) Reserved - - - - - - - -

(0xA2) Reserved - - - - - - - -

(0xA1) Reserved - - - - - - - -

(0xA0) Reserved - - - - - - - -

(0x9F) Reserved - - - - - - - -

(0x9E) Reserved - - - - - - - -

(0x9D) Reserved - - - - - - - -

(0x9C) Reserved - - - - - - - -

(0x9B) OCR3BH Timer/Counter3 - Output Compare Register B High Byte 137

(0x9A) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte 137

(0x99) OCR3AH Timer/Counter3 - Output Compare Register A High Byte 136

(0x98) OCR3AL Timer/Counter3 - Output Compare Register A Low Byte 136

(0x97) ICR3H Timer/Counter3 - Input Capture Register High Byte 137

(0x96) ICR3L Timer/Counter3 - Input Capture Register Low Byte 137

(0x95) TCNT3H Timer/Counter3 - Counter Register High Byte 136

(0x94) TCNT3L Timer/Counter3 - Counter Register Low Byte 136

(0x93) Reserved - - - - - - - -

(0x92) TCCR3C FOC3A FOC3B - - - - - - 135

(0x91) TCCR3B ICNC3 ICES3 - WGM33 WGM32 CS32 CS31 CS30 134

(0x90) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 --WGM31WGM30132

(0x8F) Reserved - - - - - - - -

(0x8E) Reserved - - - - - - - -

(0x8D) Reserved - - - - - - - -

(0x8C) Reserved - - - - - - - -

(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 137

(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 137

(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 136

(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 136

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 137

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 137

(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 136

(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 136

(0x83) Reserved - - - - - - - -

(0x82) TCCR1C FOC1A FOC1B - - - - - - 135

(0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 134

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 --WGM11WGM10132

(0x7F) DIDR1 - - - - - -AIN1DAIN0D242

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 262

(0x7D) Reserved - - - - - - - -

(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 258

(0x7B) ADCSRB -ACME - - - ADTS2 ADTS1 ADTS0 241

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 260

(0x79) ADCH ADC Data Register High byte 261

(0x78) ADCL ADC Data Register Low byte 261

(0x77) Reserved - - - - - - - -

(0x76) Reserved - - - - - - - -

(0x75) Reserved - - - - - - - -

(0x74) Reserved - - - - - - - -

(0x73) PCMSK3 PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 70

(0x72) Reserved - - - - - - - -

(0x71) TIMSK3 --ICIE3 -- OCIE3B OCIE3A TOIE3 139

(0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 162

(0x6F) TIMSK1 --ICIE1 -- OCIE1B OCIE1A TOIE1 138

(0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0 109

(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 70

(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 70

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 71

(0x6A) Reserved - - - - - - - -

(0x69) EICRA -- ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 67

(0x68) PCICR - - - - PCIE3 PCIE2 PCIE1 PCIE0 69

(0x67) Reserved - - - - - - - -

(0x66) OSCCAL Oscillator Calibration Register 40

(0x65) Reserved - - - - - - - -

(0x64) PRR PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI PRUSART0 PRADC 48

(0x63) Reserved - - - - - - - -

(0x62) Reserved - - - - - - - -

(0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 40

(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 59

0x3F (0x5F) SREG I T H S V N Z C 11

0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 12

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12

0x3C (0x5C) Reserved - - - - - - - -

0x3B (0x5B) Reserved - - - - - - - -

0x3A (0x5A) Reserved - - - - - - - -

0x39 (0x59) Reserved - - - - - - - -

0x38 (0x58) Reserved - - - - - - - -

0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 295

0x36 (0x56) Reserved - - - - - - - -

0x35 (0x55) MCUCR JTD BODS(6) BODSE(6) PUD -- IVSEL IVCE 91/278

0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 58/278

0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 47

0x32 (0x52) Reserved - - - - - - - -

0x31 (0x51) OCDR On-Chip Debug Register 268

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 260

0x2F (0x4F) Reserved - - - - - - - -

0x2E (0x4E) SPDR SPI 0 Data Register 173

0x2D (0x4D) SPSR SPIF0 WCOL0 - - - - -SPI2X0172

0x2C (0x4C) SPCR SPIE0 SPE0 DORD0 MSTR0 CPOL0 CPHA0 SPR01 SPR00 171

0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 29

0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 29

0x29 (0x49) Reserved - - - - - - - -

0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 108

0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 108

0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 108

0x25 (0x45) TCCR0B FOC0A FOC0B -- WGM02 CS02 CS01 CS00 107

0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 --WGM01WGM00108

0x23 (0x43) GTCCR TSM - - - - - PSRASY PSRSYNC 163

0x22 (0x42) EEARH - - - - EEPROM Address Register High Byte 24

0x21 (0x41) EEARL EEPROM Address Register Low Byte 24

0x20 (0x40) EEDR EEPROM Data Register 24

0x1F (0x3F) EECR -- EEPM1 EEPM0 EERIE EEMPE EEPE EERE 24

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 29

0x1D (0x3D) EIMSK - - - - - INT2 INT1 INT0 68

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-

ters as data space using LD and ST instructions, $20 must be added to these addresses.

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units

than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O

space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

5. USART in SPI Master Mode.

6. Only available in the ATmega164PA/324PA/644PA/1284P.

0x1C (0x3C) EIFR - - - - - INTF2 INTF1 INTF0 68

0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 69

0x1A (0x3A) Reserved - - - - - - - -

0x19 (0x39) Reserved - - - - - - - -

0x18 (0x38) TIFR3 --ICF3 --OCF3B OCF3ATOV3140

0x17 (0x37) TIFR2 - - - - -OCF2B OCF2ATOV2162

0x16 (0x36) TIFR1 --ICF1 --OCF1B OCF1ATOV1139

0x15 (0x35) TIFR0 - - - - -OCF0B OCF0ATOV0109

0x14 (0x34) Reserved - - - - - - - -

0x13 (0x33) Reserved - - - - - - - -

0x12 (0x32) Reserved - - - - - - - -

0x11 (0x31) Reserved - - - - - - - -

0x10 (0x30) Reserved - - - - - - - -

0x0F (0x2F) Reserved - - - - - - - -

0x0E (0x2E) Reserved - - - - - - - -

0x0D (0x2D) Reserved - - - - - - - -

0x0C (0x2C) Reserved - - - - - - - -

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 92

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 92

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 92

0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 92

0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 92

0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 92

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 91

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 91

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 91

0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 91

0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 91

0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 91

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8272DS–AVR–05/12

ATmega164A/PA/324A/PA/644A/PA/1284/P

8. Instruction set summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 4

ICALL Indirect Call to (Z) PC ← ZNone4

CALL k Direct Subroutine Call PC ← kNone5

RET Subroutine Return PC ← STACK None 5

RETI Interrupt Return PC ← STACK I 5

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2