 
  
FEATURES APPLICATIONS
DESCRIPTION
Successive Approximation Register Clock
Comparator CS
CDAC
Buffer
REF
CAP
R1IN
40 k
9.9 k
Internal
+2.5 V Ref
6 k
Parallel
and
Serial
Data
Out
&
Control
BUSYBUSY
DATACLK
TAG
20 k
39.8 k
R2IN
EXT/IN
R/C
SB/BTC
BYTE
REFD
Parallel
Data
PWRD
SDATA
ADS8507
SLAS381 DECEMBER 2006
16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITHINTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
Industrial Process Control40-kHz Min Sampling Rate
Test Equipment4-V, 5-V, and ±10-V Input Ranges
Medical Equipment89.9-dB SINAD with 10-kHz Input
Data Acquisition Systems±1.5 LSB Max INL
Digital Signal Processing+1.5/–1 LSB Max DNL, 16-Bit No Missing
InstrumentationCodes
±5-mV BPZ, ±0.4 PPM/°C BPZ DriftSPI Compatible Serial Output With
The ADS8507 is a complete low power, single 5-VDaisy-Chain (TAG) Feature
supply, 16-bit sampling analog-to-digital (A/D)Single 5-V Analog Supply
converter. It contains a complete 16-bitPin-Compatible With ADS7807 and 12-Bit
capacitor-based, successive approximation register(SAR) A/D converter with sample and hold, clock,ADS7806/8506
reference, and data interface. The converter can beUses Internal or External 2.5-V Reference
configured for a variety of input ranges including ±10Low Power Dissipation
V, 4 V, and 5 V. For most input ranges, the input 24 mW Typ, 30 mW Max at 40 KSPS
voltage can swing to 25 V or –25 V without damageto the converter.50-µW Max Power Down Mode
A SPI compatible serial interface allows data to be28-Pin SO Package
synchronized to an internal or external clock. A fullFull Parallel Interface
parallel interface with BYTE select is also provided to2's Comp or BTC Output Code
allow the maximum system design flexibility. TheADS8507 is specified at 40 kHz sampling rate overthe industrial -40 °C to 85 °C temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.QSPI, SPI are trademarks of Motorola.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
ADS8507
SLAS381 DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
NO MINIMUM SPECIFICATIONRELATIVE PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT MISSING SINAD TEMPERATUREACCURACY LEAD DESIGNATOR NUMBER MEDIA, QTYCODE (dB) RANGE(LSB)
ADS8507IBDW Tube, 20ADS8507IB ±1.5 16 87 -40 °C to 85 °C SO-28 DW
ADS8507IBDWR Tape and Reel, 1000
ADS8507IDW Tube, 20ADS8507I ±3 15 83 -40 °C to 85 °C SO-28 DW
ADS8507IDWR Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
R1
IN
±25 VAnalog inputs R2
IN
±25 VREF +V
ANA
+ 0.3 V to AGND2 - 0.3 VDGND, AGND2 ±0.3 VV
ANA
6 VGround voltage differences
V
DIG
to V
ANA
0.3 VV
DIG
6 VDigital inputs -0.3 V to +V
DIG
+ 0.3 VMaximum junction temperature 165 °CStorage temperature range –65 °C to 150 °CInternal power dissipation 700 mWLead temperature (soldering, 1.6 mm from case 10 seconds) 260 °C
(1) All voltage values are with respect to network ground terminal.
At T
A
= -40°C to 85°C, f
S
= 40 kHz, V
DIG
= V
ANA
= 5 V, and using internal reference and fixed resistors, (see Figure 43 )unless otherwise specified.
ADS8507I ADS8507IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
Resolution 16 16 Bits
ANALOG INPUT
-10 10 -10 10
Voltage ranges See Table 1 0 5 0 5 V
0 4 0 4
Impedance
Capacitance 45 45 pF
THROUGHPUT SPEED
Conversion time 20 20 µs
Complete cycle Acquire and convert 25 25
Throughput rate 40 40 kHz
DC ACCURACY
INL Integral linearity error -3 3 -1.5 1.5 LSB
(1)
(1) LSB means Least Significant Bit. One LSB for the ±10 V input range is 305 µV.
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ADS8507
SLAS381 DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)At T
A
= -40°C to 85°C, f
S
= 40 kHz, V
DIG
= V
ANA
= 5 V, and using internal reference and fixed resistors, (see Figure 43 )unless otherwise specified.
ADS8507I ADS8507IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
DNL Differential linearity error -2 3 -1 1.5 LSB
No missing codes 15 16 Bits
Transition noise
(2)
0.8 0.8 LSB
Gain Error ±0.2 ±0.1 %
Full scale error
(3) (4)
-0.5 0.5 -0.25 0.25 %
Full scale error drift ±7 ±5 ppm/ °C
Full scale error
(3) (4)
Ext. 2.5-V Ref -0.5 0.5 -0.25 0.25 %
Full scale error drift Ext. 2.5-V Ref ±0.5 ±0.5 ppm/ °C
Bipolar zero error
(3)
±10 V Range -10 10 -5 5 mV
Bipolar zero error drift ±10 V Range ±0.5 ±0.5 ppm/ °C
Unipolar zero error
(5)
0 V to 5 V, 0 V to 4 V Ranges -3 3 -3 3 mV
Unipolar zero error drift 0 V to 5 V, 0 V to 4 V Ranges ±0.5 ±0.5 ppm/ °C
Recovery time to rated accuracy from
2.2- µF Capacitor to CAP 1 1 mspower down
(6)
Power supply sensitivity
+4.75 V < V
S
< +5.25 V ±8 ±8 LSB(V
DIG
= V
ANA
= V
S
)
AC ACCURACY
SFDR Spurious-free dynamic range f
IN
= 1 kHz, ±10 V 90 100 96 102 dB
(7)
THD Total harmonic distortion f
IN
= 1 kHz, ±10 V -100 -90 -100 -96 dB
f
IN
= 1 kHz, ±10 V 83 88 87 89.9SINAD Signal-to-(noise+distortion) dB-60 dB Input 30 32
SNR Signal-to-noise 83 88 87 89.9 dB
Usable bandwidth
(8)
f
IN
= 1 kHz, ±10 V 130 130 kHz
Full-power bandwidth (-3 dB) 600 600 kHz
SAMPLING DYNAMICS
Aperture delay 40 40 ns
Aperture jitter 20 20 ps
Transient response FS Step 5 5 µs
Overvoltage recovery
(9)
750 750 ns
REFERENCE
Internal reference voltage No load 2.48 2.5 2.52 2.48 2.5 2.52 V
Internal reference source current (must
1 1 µAuse external buffer)
Internal reference drift 8 8 ppm/ °C
External reference voltage range for
2.3 2.5 2.7 2.3 2.5 2.7 Vspecified linearity
External reference current drain Ext. 2.5-V Ref 100 100 µA
DIGITAL INPUTS
V
IL
Low-level input voltage -0.3 +0.8 -0.3 +0.8 V
V
IH
High-level input voltage 2.0 V
D
+0.3 V 2.0 V
D
+0.3 V V
I
IL
Low-level input current V
IL
= 0 V ±10 ±10 µA
(2) Typical rms noise at worst case transitions.(3) As measured with fixed resistors, see Figure 43 . Adjustable to zero with external potentiometer.(4) Full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided bythe transition voltage (not divided by the full-scale range) and includes the effect of offset error.(5) As measured with fixed resistors, see Figure 43 . Adjustable to zero with external potentiometer.(6) This is the time delay after the ADS8507 is brought out of Power-Down mode until all internal settling occurs and the analog input isacquired to rated accuracy. A Convert command after this delay will yield accurate results.(7) All specifications in dB are referred to a full-scale input.(8) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB.(9) Recovers to specified performance after 2 x FS input overvoltage.
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DEVICE INFORMATION
VDIG
VANA
BUSY
CS
R/C
BYTE
TAG
SDATA
DATACLK
D0
D1
D2
R1IN
AGND1
CAP
REF
AGND2
D7
D6
D5
D4
D3
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8507
R2IN
SB/BTC
EXT/INT
REFD
PWRD
ADS8507
SLAS381 DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)At T
A
= -40°C to 85°C, f
S
= 40 kHz, V
DIG
= V
ANA
= 5 V, and using internal reference and fixed resistors, (see Figure 43 )unless otherwise specified.
ADS8507I ADS8507IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
I
IH
High-level input current V
IH
= 5 V ±10 ±10 µA
DIGITAL OUTPUTS
Data format - Parallel 16-bits in 2-bytes
Data coding - Serial binary 2scomplement or straight binary
V
OL
Low-level output voltage I
SINK
= 1.6 mA 0.4 0.4 V
V
OH
High-level output voltage I
SOURCE
= 500 µA 4 4 V
High-Z state,Leakage Current ±5 ±5 µAV
OUT
= 0 V to V
DIG
Output capacitance High-Z state 15 15 pF
DIGITAL TIMING
Bus access time R
L
= 3.3 k , C
L
= 50 pF 83 83 ns
Bus relinquish time R
L
= 3.3 k , C
L
= 10 pF 83 83 ns
POWER SUPPLIES
V
DIG
Digital voltage Must be V
ANA
4.75 5 5.25 4.75 5 5.25 V
V
ANA
Analog voltage 4.75 5 5.25 4.75 5 5.25 V
I
DIG
Digital current 0.6 0.6 mA
I
ANA
Analog current 4.2 4.2 mA
V
ANA
= V
DIG
= 5 V,
24 30 24 30 mWf
S
= 40 kHzPower dissipation
REFD High 20 20 mW
PWRD and REFD High 50 50 µW
TEMPERATURE RANGE
Specified performance -40 85 -40 85 °C
Derated performance -55 125 -55 125 °C
Storage temperature -65 150 -65 150 °C
SO Thermal resistance ( Θ
JA
) 46 46 °C/W
4
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ADS8507
SLAS381 DECEMBER 2006
DEVICE INFORMATION (continued)Terminal Functions
TERMINAL
DIGITAL
DESCRIPTIONI/ONO. NAME
1 R1
IN
Analog Input.2 AGND1 Analog sense ground. Used internally as ground reference point. Minimal current flow3 R2
IN
Analog Input.4 CAP Reference buffer output. 2.2-µF Tantalum capacitor to ground.5 REF Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external systemreference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.6 AGND2 Analog ground7 SB/ BTC I Selects straight binary or binary 2s complement for output data format. if high, data is output in astraight binary format. If low, data is output in a binary 2's complement format.8 EXT/ INT I Selects external/Internal data clock for transmitting data. If high, data is output synchronized tothe clock input on DATACLK. If low, a convert command initiates the transmission of the datafrom the previous conversion, along with 16-clock pulses output on DATACLK.9 D7 O Data bit 7 if BYTE is high. Data bit 15 (MSB) if BYTE is low. Hi-Z when CS is high and/or R/ C islow. Leave unconnected when using serial output.10 D6 O Data bit 6 if BYTE is high. Data bit 14 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.11 D5 O Data bit 5 if BYTE is high. Data bit 13 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.12 D4 O Data bit 4 if BYTE is high. Data bit 12 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.13 D3 O Data bit 3 if BYTE is high. Data bit 11 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.14 DGND Digital ground15 D2 O Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.16 D1 O Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. Hi-Z when CS is high and/or R/ C is low.17 D0 O Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. Hi-Z when CS is high and/or R/ C islow.18 DATACLK I/O Either an input or an output depending on the EXT/ INT level. Output data is synchronized to thisclock. If EXT/ INT is low, DATACLK transmits 16 pulses after each conversion, and then remainslow between conversions.19 SDATA O Serial data output. Data is synchronized to DATACLK, with the format determined by the level ofSB/ BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input onTAG as long as CS is low and R/ C is high. If EXT/ INT is low, data is valid on both the rising andfalling edges of DATACLK, and between conversions SDATA stays at the level of the TAG inputwhen the conversion was started.20 TAG I Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is outputon DATA with a delay that is dependent on the external clock mode.21 BYTE I Selects 8 most significant bits (low) or 8 least significant bits (high) on parallel output pins.22 R/ C I Read/convert input. With CS low, a falling edge on R/ C puts the internal sample-and-hold intothe hold state and starts a conversion. When EXT/ INT is low, this also initiates the transmissionof the data results from the previous conversion.23 CS I Internally ORed with R/ C. If R/ C is low, a falling edge on CS initiates a new conversion. IfEXT/ INT is low, this same falling edge will start the transmission of serial data results from theprevious conversion.24 BUSY O At the start of a conversion, BUSY goes low and stays low until the conversion is completed andthe digital outputs have been updated.25 PWRD I Power down input. If high, conversions are inhibited and power consumption is significantlyreduced. Results from the previous conversion are maintained in the output shift register.26 REFD I REFD High shuts down the internal reference. External reference will be required forconversions.27 V
ANA
Analog Supply. Nominally +5 V. Decouple with 0.1-µF ceramic and 10-µF tantalum capacitors.28 V
DIG
Digital Supply. Nominally +5 V. Connect directly to pin 27. Must be V
ANA
.
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TYPICAL CHARACTERISTICS
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
-40 -25 -10 5 20 35 50 65 80 95 110 125
InternalReference-V
T -Free-AirTemperature-ºC
A
4
4.5
5
5.5
6
-40 -25 -10 5 20 35 50 65 80 95 110 125
T -Free-AirTemperature-ºC
A
PowerSupplyCurrent-mA
4
4.5
5
5.5
6
10 20 30 40
SamplingFrequency-kHz
PowerSupplyCurrent-mA
-2
-1
0
1
2
3
BipolarOffsetError-mV
-45 -30 -15 0 15 30 45 60 75 90 105 120
T -Free-AirTemperature-ºC
A
20VBipolarRange
-0.2
-0.15
-0.1
-0.05
0
BipolarNegativeFull-ScaleError-%FSR
T -Free-AirTemperature-ºC
A
-45 -30 -15 0 15 30 45 60 75 90 105 120
20VBipolarRange
ADS8507
SLAS381 DECEMBER 2006
Table 1. Input Range Connections (see Figure 42 and Figure 43 )
ANALOG INPUT
CONNECT R1
IN
VIA 200 TO CONNECT R2
IN
VIA 100 TO IMPEDANCERANGE
±10 V V
IN
CAP 45.7 k 0 V to 5 V AGND V
IN
20.0 k 0 V to 4 V V
IN
V
IN
21.4 k
POWER SUPPLY CURRENT INTERNAL REFERENCE POWER SUPPLY CURRENTvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SAMPLING FREQUENCY
Figure 1. Figure 2. Figure 3.
BIPOLAR POSITIVE FULL-SCALE BIPOLAR NEGATIVE FULL-SCALEBIPOLAR OFFSET ERROR ERROR ERRORvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 4. Figure 5. Figure 6.
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-2
-1
0
1
2
3
UnipolarOffsetError-mV
T -Free-AirTemperature-ºC
A
-45 -30 -15 0 15 30 45 60 75 90 105 120
UnipolarRange
-0.2
-0.1
0
0.1
0.2
UnipolarFull-ScaleError-%FSR
T -Free-AirTemperature-ºC
A
-45 -30 -15 0 15 30 45 60 75 90 105 120
UnipolarRange,
4VInputRange
-0.4
-0.3
-0.2
-0.1
0
UnipolarFull-ScaleError-%FSR
T -Free-AirTemperature-ºC
A
-45 -30 -15 0 15 30 45 60 75 90 105 120
UnipolarRange,
5VInputRange
-110
-105
-100
-95
-90
-85
-80
THD-TotalHarmonicDistortion-dB
-50 -25 025 50 75 100 125
T -Free-AirTemperature-ºC
A
f =10kHz,0dB
i
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12 14 16 18 20
f-Frequency-kHz
SINAD-SignaltoNoiseRatioandDistortion-dB
-20dB
-60dB
0dB
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
SINAD-SignaltoNoiseRatioandDistortion-dB
f =10kHz
s
f =20kHz
s
f =30kHz
s
f =40kHz
s
f =10kHz,0dB;f =10kHzto40kHz
i s
T -Free-AirTemperature-°C
A
ADS8507
SLAS381 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
UNIPOLAR OFFSET ERROR UNIPOLAR FULL-SCALE ERROR UNIPOLAR FULL-SCALE ERRORvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 7. Figure 8. Figure 9.
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION SIGNAL TO NOISE RATIOvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 10. Figure 11. Figure 12.
SIGNAL TO NOISE AND SIGNAL TO NOISE AND SIGNAL TO NOISE ANDDISTORTION DISTORTION DISTORTIONvs vs vsFREE-AIR TEMPERATURE FREQUENCY FREE-AIR TEMPERATURE
Figure 13. Figure 14. Figure 15.
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60
70
80
90
100
0 1 10 100 1000
f-Frequency-kHz
SINAD-Signal-to-NoiseandDistortion-dB
f =0dB
i
60
70
80
90
100
0 1 10 100 1000
f-Frequency-kHz
SNR-Signal-to-NoiseRatio-dB
f = 0 dB
i
80
85
90
95
100
105
110
0 1 2 3 4 5 6 7 8 9 10
SFDR-SpuriousFreeDynamicRange-dB
ESR- W
f =10kHz,0dB
i
0 1 2 3 4 5 6 7 8 9 10
ESR- W
-110
-105
-100
-95
-90
-85
-80
THD-TotalHarmonicDistortion-dB
f =10kHz,0dB
i
-80
-70
-60
-50
-40
-30
-20
10 100 1000 1k 10k 100k
Power-SupplyRippleFrequency-Hz
OutputRejection-dB
ADS8507
SLAS381 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE ANDSIGNAL-TO-NOISE RATIO DISTORTION SPURIOUS FREE DYNAMIC RANGEvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 16. Figure 17. Figure 18.
TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTIONvs vs vsFREQUENCY EQUIVALENT SERIES RESISTOR EQUIVALENT SERIES RESISTOR
Figure 19. Figure 20. Figure 21.
SIGNAL TO NOISE RATIO AND OUTPUT REJECTIONSIGNAL TO NOISE RATIO DISTORTION vsvs vs POWER-SUPPLY RIPPLEEQUIVALENT SERIES RESISTOR EQUIVALENT SERIES RESISTOR FREQUENCY
Figure 22. Figure 23. Figure 24.
8
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17.5
17.6
17.7
17.8
17.9
18
18.1
-50 -25 0 25 50 75 100 125
T -Free-AirTemperature-°C
A
t -ConversionTime- s
CONVERT m
-1.5
-1
-0.5
0
0.5
1
1.5
INL -Bits
08192 16384 24576 32768 40960 49152 57344 65535
Code
INL
-1
-0.5
0
0.5
1
1.5
0 8192 16384 24576 32768 40960 49152 57344
Code
DNL -Bits
65535
DNL
ADS8507
SLAS381 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
CONVERSION TIMEvsFREE-AIR TEMPERATURE
Figure 25.
Figure 26.
Figure 27.
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-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5 10 15 20
f-Frequency-kHz
Amplitude-dB
FFT
8192PointFFT;f =10kHz,0dB
I
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5 10 15 20
f-Frequency-kHz
Amplitude-dB
FFT
8192PointFFT;f =20kHz,0dB
I
0 5 10 15 20
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
f-Frequency-kHz
Amplitude-dB
8192PointFFT;f =1kHz,0dB
i
FFT
BASIC OPERATION
PARALLEL OUTPUT
ADS8507
SLAS381 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 28.
Figure 29.
Figure 30.
Figure 31 shows a basic circuit to operate the ADS8507 with a ±10 V input range and parallel output. TakingR/ C (pin 22) LOW for a minimum of 40 ns (12 µs max) will initiate a conversion. BUSY (pin 24) will go LOW and
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8507
+5 V
++
Convert Pulse
40 ns Min
200
0.1 µF10 µF
100
+
2.2 µF
66.5 k
+5 V
Parallel Output
B11B12B13B14B15
(MSB)
Pin 21
LOW B3B4B5B6B7Pin 21
HIGH
NC(1)
B8B9B10
B0
(LSB)
B1B2
BUSY
R/C
BYTE
± 10 V
2.2 µF
SERIAL OUTPUT
ADS8507
SLAS381 DECEMBER 2006
BASIC OPERATION (continued)stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, theeight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the eight least significant bits(LSBs) will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY goingHIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing theremaining byte to be read. All convert commands will be ignored while BUSY is LOW.
The ADS8507 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convertcommands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistorscompensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer tothe Calibration section).
Figure 31. Basic ±10-V Operation, Both Parallel and Serial Output
Figure 32 shows a basic circuit to operate the ADS8507 with a ±10 V input range and serial output. Taking R/ C(pin 22) LOW for 40 ns (12 µs max) will initiate a conversion and output valid data from the previous conversionon SDATA (pin 19) synchronized to 16 clock pulses output on DATACLK (pin 18). BUSY (pin 24) will go LOWand stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output inBTC format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGHcan be used to latch the data. All convert commands will be ignored while BUSY is LOW.
The ADS8507 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convertcommands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistorscompensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to theCalibration section).
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8507
+5 V
++
Convert Pulse
40 ns Min
200
0.1 µF10 µF
100
+
2.2 µF
66.5 k
Serial Output
NC(1)
BUSY
R/C
SDATA
± 10 V
+ 5 V
22 µF+
NC(1)
NC(1)
NC(1)
NC(1)
NC(1) NC(1)
NC(1)
DATACLK
STARTING A CONVERSION
ADS8507
SLAS381 DECEMBER 2006
BASIC OPERATION (continued)
Figure 32. Basic ±10-V Operation With Serial Output
The combination of CS (pin 23) and R/ C (pin 22) low for a minimum of 40 ns puts the sample-and-hold of theADS8507 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion Niscompleted and the internal output register has been updated. All new convert commands during BUSY low areignored. CS and/or R/ C must go high before BUSY goes high, or a new conversion is initiated without sufficienttime to acquire a new signal.
The ADS8507 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convertcommands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,R/ C, and BUSY states, and Figure 33 ,Figure 34 ,Figure 35 ,Figure 36 ,Figure 37 ,Figure 38 , and Figure 39 fortiming diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/ INT Tied High)
CS R/ C BUSY OPERATION
1 X X None. Data bus is in Hi-Z state.0 1 Initiates conversion N. Data bus remains in Hi-Z state.01 Initiates conversion N. Databus enters Hi-Z state.0 1 Conversion Ncompleted. Valid data from conversion Non the databus.1 1 Enables databus with valid data from conversion N.1 0 Enables databus with valid data from conversion N–1
(1)
. Conversion Nin progress.00 Enables databus with valid data from conversion N–1
(1)
. Conversion Nin progress.0 0 New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/ Cmust be HIGH when BUSY goes HIGH.X X 0 New convert commands ignored. Conversion Nin progress.
(1) See Figure 33 and Figure 34 for constraints on data valid from conversion N–1.
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READING DATA
ADS8507
SLAS381 DECEMBER 2006
CS and R/ C are internally ORed and level triggered. It is not a requirement which input goes low first wheninitiating a conversion. If, however, it is critical that CS or R/ C initiates conversion N, be sure the less criticalinput is low at least t
su2
10 ns prior to the initiating input. If EXT/ INT (pin 8) is low when initiating conversion N,serial data from conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See InternalData Clock in the Reading Data section.
To reduce the number of control pins, CS can be tied low using R/ C to control the read and convert modes. Thishas no effect when using the internal data clock in the serial output mode. The parallel output and the serialoutput (only when using an external data clock), however, is affected whenever R/ C goes high and the externalclock is active. Refer to the Reading Data section. In the internal clock mode data is clocked out every convertcycle regardless of the states of CS and R/ C. The conversion result is available as soon as BUSY returns tohigh therefore, data always represents the conversion previously completed even when it is read during aconversion.
The ADS8507 outputs serial or parallel data in straight binary (SB) or binary 2's complement data output format.If SB/ BTC (pin 7) is high, the output is in SB format, and if low, the output is in BTC format. Refer to Table 4 forideal output codes. The first conversion immediately following a power-up does not produce a valid conversionresult.
The parallel output can be read without affecting the internal output registers; however, reading the data throughthe serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read onthe parallel port prior to reading the same data on the serial port, but data cannot be read through the serial portprior to reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output
(1)
CS R/ C BUSY EXT/ INT DATACLK OPERATION
0 1 0 Output Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.01 0 Output Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.0 1 1 Input Initiates conversion N. Internal clock still runs conversion process.01 1 Initiates conversion N. Internal clock still runs conversion process.1 1 1 Input Conversion Ncompleted. Valid data from conversion Nclocked out on SDATAsynchronized to external data clock.1 0 1 Input Valid data from conversion N–1 output on SDATA synchronized to external data clock.Conversion Nin progress.00 1 Input Valid data from conversion N–1 output on SDATA synchronized to external data clock.Conversion Nin progress.0 0 X Input New conversion initiated without acquisition of a new signal. Data will be invalid. CSand/or R/ C must be HIGH when BUSY goes HIGH.X X 0 X X New convert commands ignored. Conversion Nin progress..
(1) See Figure 37 ,Figure 38 , and Figure 39 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION ANALOG INPUT BINARY 2's COMPLEMENT
STRAIGHT BINARY (SB/ BTC HIGH)(SB/ BTC LOW)
Full-scale range ±10 0 V to 5 V 0 V to 4 V HEXBINARY CODE BINARY CODE HEX CODECODELeast significant bit (LSB) 305 µV 76 µV 61 µV
+Full-Scale (FS - 1LSB) 9.999695 V 4.999924 V 3.999939 V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF
Midscale 0 V 2.5 V 2 V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000
One LSB Below Midscale 305 µV 2.499924 V 1.999939 V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF
-Full-Scale -10 V 0 V 0 V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000
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PARALLEL OUTPUT
PARALLEL OUTPUT (After a Conversion)
R/C
BUSY
MODE
Parallel
Data Bus
BYTE
t1
t3t4
t1
t3
t6t7
t5t6
t8
t12
t11 t10 t12
t2
t9t12 t12 t12
t9t12
Previous
High Byte Valid Hi-Z Previous High
Byte Valid Previous Low
Byte Valid Not Valid High Byte
Valid Low Byte
Valid Hi-Z High Byte
Valid
Acquire Convert Acquire Convert
ADS8507
SLAS381 DECEMBER 2006
To use the parallel output, tie EXT/ INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be leftunconnected. The parallel output is active when R/ C (pin 22) is high and CS (pin 23) is low. Any othercombination of CS and R/ C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes onD7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the 8 most significant bits will be valid with the MSBon D7. When BYTE is high, the 8 least significant bits are valid with the LSB on D0. BYTE can be toggled toread both bytes within one conversion cycle.
Upon initial power up, the parallel output contains indeterminate data.
After conversion Nis completed and the output registers have been updated, BUSY (pin 24) goes high. Validdata from conversion Nis available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch thedata. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications.
Figure 33. Conversion Timing With Parallel Output ( CS and DATACLK Tied Low, EXT/INT Tied High)
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t21
t21 t21 t21
t21 t21
t21
t21
t21 t21
t21 t9t21 t9
Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State
t4
t3
t1
R/C
BUSY
CS
Data Bus
BYTE
PARALLEL OUTPUT (During a Conversion)
ADS8507
SLAS381 DECEMBER 2006
Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs
After conversion Nhas been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs afterthe start of conversion N. Do not attempt to read data beyond 12 µs after the start of conversion Nuntil BUSY(pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 fortiming constraints.
Table 5. Conversion and Data Timing, T
A
= -40 °C to 85 °C
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert pulse width 0.04 12 µst
2
Data valid delay after R/ C low 18 20 µst
3
BUSY delay from start of conversion 85 nst
4
BUSY Low 19 20 µst
5
BUSY delay after end of conversion 90 nst
6
Aperture delay 40 nst
7
Conversion time 19 20 µst
8
Acquisition time 5 nst
9
Bus relinquish time 10 83 nst
10
BUSY delay after data valid 20 60 nst
11
Previous data valid after start of conversion 12 18 µst
12
Bus access time and BYTE delay 83 nst
13
Start of conversion to DATACLK delay 1.4 µst
14
DATACLK period 1.1 µst
15
Data valid to DATACLK high delay 20 75 nst
16
Data valid after DATACLK low delay 400 600 nst
17
External DATACLK period 100 nst
18
External DATACLK low 40 nst
19
External DATACLK high 50 nst
20
CS and R/ C to external DATACLK setup time 25 ns
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SERIAL OUTPUT
INTERNAL DATA CLOCK (During a Conversion)
EXTERNAL DATA CLOCK
EXTERNAL DATA CLOCK (After a Conversion)
EXTERNAL DATA CLOCK (During a Conversion)
ADS8507
SLAS381 DECEMBER 2006
Table 5. Conversion and Data Timing, T
A
= -40 °C to 85 °C (continued)
t
21
R/ C to CS setup time 10 nst
22
Valid data after DATACLK high 25 nst
7
+ t
8
Throughput time 25 µs
Data can be clocked out with the internal data clock or an external data clock. When using serial output, becareful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state wheneverCS (pin 23) is low and R/ C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer tothe Applications Information section for specific serial interfaces. If external clock is used, the TAG input can beused to daisy-chain multiple ADS8507 data pins together.
To use the internal data clock, tie EXT/ INT (pin 8) low. The combination of R/ C (pin 22) and CS (pin 23) lowinitiates conversion Nand activates the internal data clock (typically 900-kHz clock rate). The ADS8507 outputs16 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 16 clock pulses outputon DATACLK (pin 18). The data is valid on both the rising and falling edges of the internal data clock. The risingedge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains low until thenext conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the start oftransmission. Refer to Table 6 and Figure 36 .
To use an external data clock, tie EXT/ INT (pin 8) high. The external data clock is not and cannot besynchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable theoutput mode of the ADS8507, CS (pin 23) must be low and R/ C (pin 22) must be high. DATACLK must be highfor 20% to 70% of the total data clock period; the clock rate can be between DC and 10 MHz. Serial data fromconversion Ncan be output on SDATA (pin 19) after conversion Nis completed or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/ C to initiate conversions.
While this is perfectly acceptable, there is a possible problem when using an external data clock. At anindeterminate point from 12 µs after the start of conversion Nuntil BUSY rises, the internal logic shifts theresults of conversion Ninto the output register. If CS is low, R/ C high, and the external clock is high at this point,data is lost. So, with CS low, either R/ C and/or DATACLK must be low during this period to avoid losing validdata.
After conversion Nis completed and the output registers have been updated, BUSY (pin 24) goes high. With CSlow and R/ C high, valid data from conversion Nis output on SDATA (pin 19) synchronized to the external dataclock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of theexternal data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17thfalling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal outputregisters are updated with the results from the next conversion. Refer to Table 6 and Figure 38 .
After conversion Nhas been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs afterthe start of conversion N. Do not attempt to clock out data from 12 µs after the start of conversion Nuntil BUSY(pin 24) rises; this results in data loss. NOTE: For the best possible performance when using an external dataclock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clockcan cause digital feedthrough degrading the converter's performance. Refer to Table 6 and Figure 39 .
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1 2
tsu1
tsu1
CS
R/C
External
DATACLK
CS Set Low, Discontinuous Ext DA TACLK
tsu1
tsu1
R/C
CS
External
DATACLK
R/C Set Low, Discontinuous Ext DATACLK
tsu2
tsu2
CS
R/C
tsu3
BUSY
External
DATACLK
CS Set Low, Discontinuous Ext DA TACLK
ADS8507
SLAS381 DECEMBER 2006
Table 6. Timing Requirements, T
A
= –40 °C to 85 °C
PARAMETER MIN TYP MAX UNIT
t
w1
Pulse duration, convert 0.04 12 µst
d1
Delay time, BUSY from R/ C low 12 20 nst
w2
Pulse duration, BUSY low 18 20 µst
d2
Delay time, BUSY, after end of conversion 5 nst
d3
Delay time, aperture 5 nst
conv
Conversion time 18 20 µst
acq
Acquisition time 5 7 µst
conv
+ t
acq
Cycle time 25 µst
d4
Delay time, R/ C low to internal DATACLK output 270 nst
c1
Cycle time, internal DATACLK 600 820 850 nst
d5
Delay time, data valid to internal DATACLK high 15 35 nst
d6
Delay time, data valid after internal DATACLK low 20 35 nst
c2
Cycle time, external DATACLK 35 nst
w3
Pulse duration, external DATACLK high 15 nst
w4
Pulse duration, external DATACLK low 15 nst
su1
Setup time, R/ C rise/fall to external DATACLK high 15 nst
su2
Setup time, R/ C transition to CS transition 10 nst
d7
Delay time, SYNC, after external DATACLK high 3 35 nst
d8
Delay time, data valid from external DATCLK high 2 20 nst
d9
Delay time, CS rising edge to external DATACLK rising edge 10 nst
d10
Delay time, previous data available after CS, R/ C low 2 µst
su3
Setup time, BUSY transition to first external DATACLK 5 nst
d11
Delay time, final external DATACLK to BUSY rising edge 1 µst
su3
Setup time, TAG valid 0 nst
h1
Hold time, TAG valid 2 ns
Figure 35. Critical Timing
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R/C
BUSY
STATUS (N+1)th Accquisition (N+1)th Conversion
Error
Correction
Nth Conversion Error
Correction
Internal
DATACLK
(N1)th Conversion Data
SDATA Nth Conversion Data
(N+2)th Accquisition
1 2 16216
D15 D0 D15 D0
TAG = 0 TAG = 0
TAG = 0
8starts READ
CS, EXT/INT, and TAG are tied low
tw1
td1 tw2
td3 td11
td2 td3
tw1
td1 tw2
td11
td2
tconv tacq tconv tacq
td4
td4 tc1
td5 td6
1
BUSY
STATUS (N+1)th Accquisition (N+1)th Conversion
Error
Correction
Nth Conversion Error
Correction
External
DATACLK
SDATA Nth Data (N+1)th Data
(N+2)th Accquisition
TAG = 0
No more
data to
shift out
No more
data to
shift out TAG = 0
TAG = 0
TAG = 0 TAG = 0
R/C
EXT/INT tied high, CS and TAG are tied low tw1 + tsu1 starts READ
tw1 tw1
td1 tw2 td1 tw2
td3 td11
td2 td3 td11
td2
tsu1
tconv tacq tconv tacq
tsu3 tsu1 tsu3
116 12 16 1 16 1216
ADS8507
SLAS381 DECEMBER 2006
Figure 36. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion)
Figure 37. Basic Conversion Timing - External DATACLK
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BUSY
STATUS (N+1)th Accquisition
Error
Correction
Nth Conversion
External
DATACLK
SDATA
Nth Conversion Data
D15
0 1 2 3 1514 16
TAG T01
D05D10D12D13D14
T00 T04
T03T02 T13T12T11T06 T16T15T14 Tyy
54 11 12 1310
D11
T05
D04 D03 D02 D01 Txx
T00
D00 Null
T17
Null
R/C
EXT/INT tied high, CS tied low tw1 + tsu1 starts READ
tw1
td1 tw2 tsu1
td3 td11 td2
tconv tacq
td3
td1
tsu3
tw3
tc2 tw4 tsu1
td8 td8
tsu3 th1
BUSY
STATUS Error
Correction
Nth Conversion
External
DATACLK
SDATA
Nth Conversion Data
D15
01 2 3 1514 16
D05D10D12D13D14
54 11 12 1310
D11 D00D04 D03 D02 D01
R/C
EXT/INT tied high, CS and TAG tied low Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
tw1
td1 tw2
td10
td3
tsu3 tconv
td2
tsu1 tw3
tc2 tw4 td11
td8 td8
TAG FEATURE
ADS8507
SLAS381 DECEMBER 2006
Figure 38. Read After Conversion (Discontinuous External DATACLK)
Figure 39. Read During Conversion (Discontinuous External DATACLK)
The TAG feature allows the data from multiple ADS8507 converters to be read on a single serial line. Theconverters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated inFigure 40 . The DATA pin of the last converter drives the processor's serial data input. Data is then shiftedthrough each converter, synchronous to the externally supplied data clock, onto the serial data line. The internalclock cannot be used for this configuration.
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External
DATACLK
.
2 3 4 3534 361716 20 21191
Null
D Q A00
D Q
Null
D Q B00
D Q
A15
D Q A16
D Q
B15
D Q B16
D Q
TAG(A)
TAG(B)
SDATA (A)
SDATA (B)
DATACLK
(both A & B)
SYNC
(both A & B)
(both A & B)
SDATA ( B )
Nth Conversion Data
B15 A15B00
B13B14 B01 A00A14 A13 A01
SDATA ( A ) A15 A00A13A14 A01
18
Null
A
Null
BNull
A
ADS8507A
TAG DATA
DATACLK
ADS8507B
TAG DATA
DATACLK
Processor
SCLK
GPIO
GPIO
SDI
TAG(A) = 0
TAG(A) = 0
R/C
CS
R/C CS
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
INPUT RANGES
ADS8507
SLAS381 DECEMBER 2006
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be readduring the sampling period because there is not sufficient time to read data from multiple converters during aconversion period without violating the t
d11
constraint (see the EXTERNAL DATACLOCK section). The samplingperiod must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 40 , that a NULL bit separates the data word from each converter. The state of the DATA pin atthe end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READmodes, including the internal clock mode. For example, when a single converter is used in the internal clockmode the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. Whenmultiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with theTAG pin of the first converter grounded as shown in Figure 40 the NULL bit becomes a zero between each dataword.
Figure 40. Timing of TAG Feature With Single Conversion (Using External DATACLK)
The ADS8507 offers three input ranges: standard ±10-V and 0-V to 5-V ranges, and a 0-V to 4-V range forcomplete, single-supply systems. See Figure 42 and Figure 43 for the necessary circuit connections forimplementing each input range and optional offset and gain adjust circuitry. Offset and full-scale errorspecifications are tested with the fixed resistors, see Figure 43 (full-scale error includes offset and gain errorsmeasured at both +FS and -FS). Adjustments for offset and gain are described in the Calibration section of thisdata sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistorscompensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to theCalibration section).
The input impedance, summarized in Table 1 , results from the combination of the internal resistor network (seethe front page of this product data sheet) and the external resistors used for each input range (see Figure 44 ).The input resistor divider network provides inherent over-voltage protection to at least ±5.5 V for R2
IN
and ±12 Vfor R1
IN
.
Analog inputs above or below the expected range yields either positive full-scale or negative full-scale digitaloutputs, respectively. Wrapping or folding over for analog inputs outside the nominal range does not occur.
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OPA 627
GND
GND
GND
GND
GND
Pin1
Pin7
Pin2
+
Pin3 Pin4
Pin 6
15V
+15 V
Vin
2.2 mF
100 nF
2 kW
22 pF
2 kW
22 pF
200 W
100 W
33.2 kW
2.2 mF2.2 mF
100 nF
2.2 mF
R1IN
AGND1
R2IN
R3IN
CAP
REF
ADS8507
OPA 132
or
AGND2
DGND
GND
CALIBRATION
Hardware Calibration
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
2.2 µF
200
VIN R1IN
R2IN
6
50 k
+ 5 V
1 M
+
2.2 µF
33.2 k
50 k
100
+ 5 V
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
200
33.2 k
50 k
50 k
2.2 µF
6
R1IN
R2IN
100
VIN
+
2.2 µF
+5 V
1 M
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
200
33.2 k
50 k
50 k
2.2 µF
6
R1IN
R2IN
100
VIN
+
2.2 µF
+5 V
1 M
±10 V 0 V to 5 V 0 V to 4 V
ADS8507
SLAS381 DECEMBER 2006
INPUT RANGES (continued)
Figure 41. Typical Driving Circuit ( ±10 V, No Trim)
To calibrate the offset and gain of the ADS8507 in hardware, install the resistors shown in Figure 42 .Table 7lists the hardware trim ranges relative to the input for each input range.
Table 7. Offset and Gain Adjust Ranges for Hardware Calibration (see Figure 42 )
INPUT RANGE OFFSET ADJUST RANGE (mV) GAIN ADJUST RANGE (mV)
±10 V ±15 ±600 V to 5 V ±4 ±300 V to 4 V ±3 ±30
Figure 42. Circuit Diagrams (With Hardware Trim)
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Software Calibration
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
2.2 µF
200
VIN R1IN
R2IN
6
66.5 k
+
2.2 µF
100
+ 5 V
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
200
33.2 k
2.2 µF
6
R1IN
R2IN
100
VIN
+
2.2 µF
1
2
3
4
5
AGND2
CAP
REF
AGND1
+
200
33.2 k
2.2 µF
6
R1IN
R2IN
100
VIN
+
2.2 µF
±10 V 0 V to 5 V 0 V to 4 V
No Calibration
ADS8507
SLAS381 DECEMBER 2006
To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheetspecifications for offset and gain, the resistors shown in Figure 43 are necessary. See the No Calibration sectionfor more details on the external resistors. Refer to Table 8 for the range of offset and gain errors with andwithout the external resistors.
Figure 43. Circuit Diagrams (Without Hardware Trim)
Table 8. Range of Offset and Gain Errors With and Without External Resistors
OFFSET ERROR GAIN ERRORINPUT
RANGE WITH RESISTORS WITHOUT RESISTORS WITH RESISTORS WITHOUT RESISTORS(V)
RANGE (mV) RANGE (mV) TYP (mV) RANGE (% FS) RANGE (% FS) TYP
-0.4 G0.4 -0.3 G0.5 0.05±10 -10 BPZ 10 0 BPZ 35 15
0.15 G
(1)
0.15 -0.1 G
(1)
0.2 0.05-0.4 G0.4 -1.0 G0.1 -0.20 to 5 -3 UPO 3 -12 UPO -3 -7.5
0.15 G
(1)
0.1 -0.55 G
(1)
-0.05 -0.2-0.4 G0.4 -1.0 G0.1 -0.20 to 4 -3 UPO 3 -10.5 UPO -1.5 -6
-0.15 G
(1)
0.15 -0.55 G
(1)
-0.05 -0.2
(1) High grade
Figure 43 shows circuit connections. Note that the actual voltage dropped across the external resistors is atleast two orders of magnitude lower than the voltage dropped across the internal resistor divider network. Thisshould be considered when choosing the accuracy and drift specifications of the external resistors. In mostapplications, 1% metal-film resistors are sufficient.
The external resistors, see Figure 43 , may not be necessary in some applications. These resistors providecompensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Notusing the external resistors results in offset and gain errors in addition to those listed in the electricalcharacteristics section. Offset refers to the equivalent voltage of the digital output when converting with the inputgrounded. A positive gain error occurs when the equivalent output voltage of the digital output is larger than theanalog input. Refer to Table 8 for nominal ranges of gain and offset errors with and without the externalresistors. Refer to Figure 44 for typical shifts in the transfer functions which occur when the external resistors areremoved.
22
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+ Full-Scale
Digital Output
Analog Input
− Full-Scale
+ Full-Scale
Digital Output
− Full-Scale
Analog Input
(a) Bipolar (b) Unipolar
Typical T ransfer Functions With External Resistors.
Typical T ransfer Functions Without External Resistors.
VIN
200 39.8 k
9.9 k33.5 k
100
+ 5 V
+ 2.5 V
20 k40 k
+ 2.5 V
CDAC
(0.3125 V to 2.8125 V)
VIN
200 39.8 k
9.9 k
33.5 k
100
+ 2.5 V
20 k40 k
+ 2.5 V
CDAC
(0.3125 V to 2.8125 V)
VIN 200 39.8 k
9.9 k
33.5 k
100
+ 2.5 V
20 k40 k
+ 2.5 V
CDAC
(0.3125 V to 2.8125 V)
ADS8507
SLAS381 DECEMBER 2006
Figure 44. Typical Transfer Functions With and Without External Resistors
To further analyze the effects of removing any combination of the external resistors, consider Figure 45 . Thecombination of the external and the internal resistors form a voltage divider which reduces the input signal to a0.3125-V to 2.8125-V input range at the capacitor digital-to-analog converter (CDAC). The internal resistors arelaser trimmed to high relative accuracy to meet full-scale specifications. The actual input impedance of theinternal resistor network looking into pin 1 or pin 3 however, is only accurate to ±20% due to process variations.This should be taken into account when determining the effects of removing the external resistors.
Figure 45. Circuit Diagrams Showing External and Internal Resistors
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REFERENCE
The ADS8507 can operate with its internal 2.5-V reference or an external reference. By applying an external
Buffer
CDAC
Internal
Reference
ZREF
ZCAP
CAP
(Pin 4)
REF
(Pin 5)
ZCAP
ZREF
PWRD 0
REFD 0
1
6 k
PWRD 0
REFD 1
1
100 M
PWRD 1
REFD 0
200
6 k
PWRD 1
REFD 1
200
100 M
REF
CAP
ADS8507
SLAS381 DECEMBER 2006
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internallywith the output on CAP (pin 4).
The internal reference has an 8 ppm/ °C drift (typical) and accounts for approximately 20% of the full-scale error(FSE = ±0.5% for low grade, ±0.25% for high grade).
The ADS8507 also has an internal buffer for the reference voltage. Figure 46 shows characteristic impedancesat the input and output of the buffer with all combinations of powerdown and reference down.
Figure 46. Characteristic Impedances of the Internal Buffer
REF (pin 5) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF tantalumcapacitor should be connected as close as possible to the REF pin from ground. This capacitor and the outputresistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitorwill introduce more noise to the reference, degrading the SNR and SINAD. The REF pin should not be used todrive external AC or DC loads, as shown in Figure 46 .
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing thereference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF tantalum capacitor should be placed as closeas possible to the CAP pin from ground to provide optimum switching currents for the CDAC throughout theconversions cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor anysmaller than 1 µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC.Capacitor values larger than 2.2 µF have little affect on improving performance. ESR is the total equivalentseries resistance of the compensation capacitor (CAP pin). See Figure 46 and Figure 47 .
24
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3000
0.1
4000
5000
7000
6000
2000
0
1000
1 10 100
CAP − Pin Value − mF
3000
0.1
4000
5000
7000
6000
2000
0
1000
1 10 100
Power−Up Time − ms
REFERENCE AND POWER-DOWN
The ADS8507 has analog power-down and reference power down capabilities via PWRD (pin 25) and REFD
PWRD
REFD
LAYOUT
POWER
ADS8507
SLAS381 DECEMBER 2006
REFERENCE (continued)
Figure 47. Power-Down to Power-Up Time vs Capacitor Value on CAP
The output of the buffer is capable of driving up to 1 mA of current to a DC load. Using an external buffer allowsthe internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC loadwith the output voltage on CAP. This causes performance degradation of the converter.
(pin 26), respectively. PWRD and REFD high powers down all analog circuitry maintaining data from theprevious conversion in the internal registers, provided that the data has not already been shifted out through theserial port. Typical power consumption in this mode is 50 µW. Power recovery is typically 1 ms, using a 2.2-µFcapacitor connected to CAP. Figure 47 shows power-down to power-up recovery time relative to the capacitorvalue on CAP. With +5 V applied to V
DIG
, the digital circuitry of the ADS8507 remains active at all times,regardless of PWRD and REFD states.
PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversionis maintained in the internal registers and can still be read. With PWRD high, a convert command yieldsmeaningless data.
REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, isactive. REFD should be high when using an external reference to minimize power consumption and the loadingeffects on the external reference. See Figure 46 for the characteristic impedance of the reference buffer's inputfor both REFD high and low. The internal reference consumes approximately 5 mW.
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie theanalog and digital grounds together. As noted in the electrical characteristics, the ADS8507 uses 90% of itspower for the analog circuitry. The ADS8507 should be considered as an analog component.
The +5-V power for the A/D converter should be separate from the +5 V used for the system's digital logic.Connecting V
DIG
(pin 28) directly to a digital supply can reduce converter performance due to switching noise
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GROUNDING
SIGNAL CONDITIONING
INTERMEDIATE LATCHES
ADS8507
SLAS381 DECEMBER 2006
LAYOUT (continued)from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply isused for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-Vregulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, besure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both V
DIG
andV
ANA
should be tied to the same +5-V source.
Three ground pins are present on the ADS8507. DGND is the digital supply ground. AGND2 is the analogsupply ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced.AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back tothe power supply.
All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system'sdigital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied tothe system ground as near to the power supplies as possible. This helps to prevent dynamic digital groundcurrents from modulating the analog ground through a common impedance to power ground.
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount ofcharge injection which can cause the driving op amp to oscillate. The amount of charge injection due to thesampling FET switch on the ADS8507 is approximately 5% to 10% of the amount on similar A/D converters withthe charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front endwhich attenuates any charge which is released. The end result is a minimal requirement for the drive capabilityon the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application willbe sufficient to drive the ADS8507.
The resistive front end of the ADS8507 also provides a specified ±25-V overvoltage protection. In most cases,this eliminates the need for external over-voltage protection circuitry.
The ADS8507 does have 3-state outputs for the parallel port, but intermediate latches should be used if the busis active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolatethe A/D converter from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8507 has an internal LSB size of38 µV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, canbe coupled through the substrate to the analog circuitry causing degradation of converter performance.
26
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APPLICATION INFORMATION
TRANSITION NOISE
2
7FFDH7FFEH7FFFH8000H8001H8002H8003H
190
3142
9732
3075
242 1
AVERAGING
QSPI™ INTERFACE
ADS8507
SLAS381 DECEMBER 2006
Apply a DC input to the ADS8507 and initiate 1000 conversions. The digital output of the converter varies inoutput codes due to the internal noise of the ADS8507. This is true for all 16-bit SAR converters. The transitionnoise specification found in the electrical characteristics section is a statistical figure which represents the onesigma limit or rms value of these output codes.
Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bellcurve representing the nominal output code for the input voltage value. The ±1 σ, ±2 σ, and ±3 σdistributionsrepresent 68.3%, 95.5%, and 99.7% of all codes. Multiplying TN by 6 yields the ±3 σdistribution or 99.7% of allcodes. Statistically, up to 3 codes could fall outside the 5 code distribution when executing 1000 conversions.The ADS8507 has a TN of 0.8 LSBs which yields 5 output codes for a ±3 σdistribution. Figure 48 shows 16384conversion histogram results.
Figure 48. Histogram of 16384 Conversions with V
IN
= 0 V in ±10 V Bipolar Range
The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results,transition noise is reduced by a factor of 1/ Hz where n is the number of averages. For example, averaging fourconversion results reduces the TN by ½ to 0.4 LSBs. Averaging should only be used for input signals withfrequencies near DC.
For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in asimilar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves 3 dB.
Figure 49 shows a simple interface between the ADS8507 and any QSPI equipped microcontroller. Thisinterface assumes that the convert pulse does not originate from the microcontroller and that the ADS8507 is theonly serial peripheral.
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R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE
PCS0/SS
MOSI
SCK
QSPI ADS8507
Convert Pulse
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data Valid on Falling Edge)
QSPI Port is in Slave Mode.
R/C
D7 (MSB)
DATACLK
CS
BYTE
PCS0
PCS1
SCK
QSPI ADS8507
CPOL = 0
CPHA = 0
+ 5 V
EXT/INT
MISO
ADS8507
SLAS381 DECEMBER 2006
APPLICATION INFORMATION (continued)
Figure 49. QSPI Interface to the ADS8507
Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line.When a transition from low to high occurs on slave select ( SS) from BUSY (indicating the end of the currentconversion), the port can be enabled. If this is not done, the microcontroller and the A/D converter may beout-of-sync.
Figure 50 shows another interface between the ADS8507 and a QSPI equipped microcontroller which allows themicrocontroller to give the convert pulses while also allowing multiple peripherals to be connected to the serialbus. This interface and the following discussion assume a master clock for the QSPI interface of 16.78 MHz.Notice that the serial data input of the microcontroller is tied to the MSB (D7) of the ADS8507 instead of theserial output (SDATA). Using D7 instead of the serial port offers 3-state capability which allows other peripheralsto be connected to the MISO pin. When communication is desired with those peripherals, PCS0 and PCS1should be left high; that keeps D7 3-stated.
Figure 50. QSPI Interface to the ADS8507, Processor Initiates Conversions
In this configuration, the QSPI interface is actually set to do two different serial transfers. The first, an 8-bittransfer, causes PCS0 (R/ C) and PCS1 ( CS) to go low, starting a conversion. The second, a 16-bit transfer,causes only PCS1 ( CS) to go low. This is when the valid data is transferred.
For both transfers, the DT register (delay after transfer) is used to cause a 19-µs delay. The interface is also setup to wrap to the beginning of the queue. In this manner, the QSPI is a state machine which generates theappropriate timing for the ADS8507. This timing is thus locked to the crystal-based timing of the microcontrollerand not interrupt driven. So, this interface is appropriate for both AC and DC measurements.
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SPI™ INTERFACE
ADS8507
SLAS381 DECEMBER 2006
APPLICATION INFORMATION (continued)For the fastest conversion rate, the baud rate should be set to 2 (4.19-MHz SCK), DT set to 10, the first serialtransfer set to 8 bits, the second set to 16 bits, and DSCK disabled (in the command control byte). This allowsfor a 23-kHz maximum conversion rate. For slower rates, DT should be increased. Do not slow SCK as this mayincrease the chance of affecting the conversion results or accidently initiating a second conversion during thefirst 8-bit transfer.
In addition, CPOL and CPHA should be set to zero (SCK normally low and data captured on the rising edge).The command control byte for the 8-bit transfer should be set to 20
H
and for the 16-bit transfer to 61
H
.
The SPI interface is generally only capable of 8-bit data transfers. For some microcontrollers with SPI interfaces,it might be possible to receive data in a similar manner as shown for the QSPI interface in Figure 49 . Themicrocontroller needs to fetch the 8 most significant bits before the contents are overwritten by the leastsignificant bits.
A modified version of the QSPI interface shown in Figure 50 might be possible. For most microcontrollers with aSPI interface, the automatic generation of the start-of-conversion pulse is impossible and has to be done withsoftware. This limits the interface to DC applications due to the insufficient jitter performance of the convert pulseitself.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS8507IBDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IBDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IBDWR ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IBDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IDWR ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8507IDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8507IBDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
ADS8507IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8507IBDWR SOIC DW 28 1000 367.0 367.0 55.0
ADS8507IDWR SOIC DW 28 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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