w WM8501
24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver
WOLFSON MICROELECTRONICS plc
Production Data, February 2013, Rev 4.3
Copyright 2013 Wolfson Microelectronics plc
DESCRIPTION
The WM8501 is a high performance stereo DAC with an
integrated 1.7Vrms line driver. It is designed for audio
applications that require a high voltage output along with
enhanced load drive capability.
The WM8501 supports data input word lengths from 16 to
24-bits and sampling rates up to 192kHz. The WM8501
consists of a serial interface port, digital interpolation filters,
multi-bit sigma delta modulators and stereo DAC in a 14-
lead SOIC package.
The hardware control interface is used for the selection of
audio data interface format, enable and de-emphasis. The
WM8501 supports I2S, right Justified or DSP interfaces.
Operating on separate analog and digital supplies the
WM8501 offers very lower power consumption from the
digital section, whilst supporting enhanced load drive from
the analogue output.
FEATURES
Stereo DAC with 1.7Vrms line driver from 5V analogue
supply
Audio performance
- 100dB SNR (‘A’ weighted @ 48kHz)
- -88dB THD
DAC Sampling Frequency: 8kHz – 192kHz
Pin Selectable Audio Data Interface Format
- I
2S, 16-bit Right Justified or DSP
14-lead SOIC package
4.5V - 5.5V analogue, 2.7V - 5.5V digital supply operation
APPLICATIONS
STB
DVD
Digital TV
BLOCK DIAGRAM
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TABLE OF CONTENTS
DESCRIPTION ............................................................................................................ 1
FEATURES ................................................................................................................. 1
APPLICATIONS .......................................................................................................... 1
BLOCK DIAGRAM ..................................................................................................... 1
TABLE OF CONTENTS .............................................................................................. 2
PIN CONFIGURATION ............................................................................................... 3
ORDERING INFORMATION ....................................................................................... 3
PIN DESCRIPTION ..................................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ............................................................................. 5
RECOMMENDED OPERATING CONDITIONS .......................................................... 5
ELECTRICAL CHARACTERISTICS .......................................................................... 6
MASTER CLOCK TIMING ..................................................................................................... 7
DIGITAL AUDIO INTERFACE ............................................................................................... 7
DEVICE DESCRIPTION ............................................................................................. 9
GENERAL INTRODUCTION ................................................................................................. 9
DAC CIRCUIT DESCRIPTION .............................................................................................. 9
CLOCKING SCHEMES ....................................................................................................... 10
DIGITAL AUDIO INTERFACE ............................................................................................. 10
AUDIO DATA SAMPLING RATES ...................................................................................... 12
HARDWARE CONTROL MODES ....................................................................................... 12
DIGITAL FILTER CHARACTERISTICS ................................................................... 14
DAC FILTER RESPONSES ................................................................................................ 14
DIGITAL DE-EMPHASIS CHARACTERISTICS ....................................................... 15
APPLICATIONS INFORMATION ............................................................................. 16
RECOMMENDED EXTERNAL COMPONENTS ................................................................. 16
POWER UP/DOWN SEQUENCE ........................................................................................ 17
RECOMMENDED ANALOGUE LOW PASS FILTER .......................................................... 17
PCB LAYOUT RECOMMENDATIONS ................................................................................ 18
PACKAGE DRAWING .............................................................................................. 19
IMPORTANT NOTICE .............................................................................................. 20
ADDRESS: .......................................................................................................................... 20
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PIN CONFIGURATION
ORDERING INFORMATION
DEVICE TEMPERATURE
RANGE PACKAGE MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8501CGED -40 to +85oC 14-lead SOIC
(Pb-free) MSL1 260°C
WM8501CGED/R -40 to +85oC 14-lead SOIC
(Pb-free, tape and reel) MSL1 260°C
Note:
Reel quantity = 3,000
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PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 LRCLK Digital input Sample rate clock input
2 DIN Digital input Serial audio data input
3 BCLK Digital input Bit clock input
4 ENABLE Digital input Enable input – 0 = powered down, 1 = enabled
5 VMID Analogue output Analogue internal reference
6 ROUT Analogue output Right channel DAC output
7 AGND Supply Ground reference for analog circuits and substrate connection
8 AVDD Supply Positive supply for analog circuits
9 LOUT Analogue output Left channel DAC output
10 DGND Digital Supply Digital ground supply
11 DVDD Digital Supply Digital positive supply
12 DEEMPH Digital input De-emphasis select, Internal pull down
High = de-emphasis ON
Low = de-emphasis OFF
13 FORMAT Digital input Data input format select, Internal pull up
Low = 16-bit right justified or DSP (Mode B)
High = 16-24-bit I2S or DSP (Mode A)
14 MCLK Digital input Master clock input
Note:
1. Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION MIN MAX
Analogue supply voltage -0.3V +7V
Digital supply voltage -0.3V +7V
Voltage range digital inputs DGND -0.3V DVDD +0.3V
Master clock frequency 38.462MHz
Operating temperature range, TA -40C +85C
Storage temperature prior to soldering 30C max / 85% RH max
Storage temperature after soldering -65C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital supply range DVDD 2.7 5.5 V
Analogue supply range AVDD 4.5 5.5 V
Ground AGND, DGND 0 V
Difference DGND to AGND -0.3 0 +0.3 V
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device.
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (TTL Levels)
Input LOW level VIL 0.8 V
Input HIGH level VIH 2.0 V
Output LOW VOL IOL = 2mA DGND + 0.3V V
Output HIGH VOH IOH = 2mA DVDD – 0.3V V
Analogue Reference Levels
Reference voltage (VMID) AVDD/2 V
Potential divider resistance RCAP AVDD to VMID and
VMID to GND
50 k
DAC Output (Load = 10k. 50pF)
0dBFs Full scale output voltage At DAC outputs 1.6 x
AVDD/5
1.7 x
AVDD/5
1.8 x
AVDD/5
Vrms
Signal to Noise Ratio (Note
5,6,7)
SNR A-weighted,
@ fs = 48kHz
90 100 dB
A-weighted
@ fs = 96kHz
97 dB
A-weighted
@ fs = 192kHz
97 dB
Dynamic Range (Note 2, 6) DNR A-weighted, -60dB full
scale input
90 100 dB
Total Harmonic Distortion
(Note 7)
THD 1kHz, Load = 10k,
0dBFS
-88 -78 dB
DAC channel separation 93 dB
Analogue Output Levels
Output level (line output) Load = 10k, 0dBFS 1.7 Vrms
Minimum resistance load (line
output)
To midrail or a.c.
coupled
820
Output level (Headphone output) Load = 16, 0dBFS 1.0 Vrms
Minimum resistance load
(Headphone output)
To midrail or a.c.
coupled
16
Gain mismatch
channel-to-channel
±1 %FSR
Output d.c. level AVDD/2 V
Supply Current
Analogue supply current AVDD = 5V 9 mA
Digital supply current DVDD = 5V 8 mA
DVDD = 3.3V 4.5 mA
Power down current (note 4) AVDD=DVDD=5V 0.01 mA
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics.
The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
3. VMID pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Power down occurs 1.5s after MCLK is stopped.
5. Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
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6. Dynamic range (dB) – DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD @ -
60dB= -32dB, DR= 92dB).
7. THD (dB) – THD is a ratio, of the rms values, of Distortion/Signal.
8. Stop band attenuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band).
9. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information
MCLK Master clock pulse width high tMCLKH 8 ns
MCLK Master clock pulse width low tMCLKL 8 ns
MCLK Master clock cycle time tMCLKY 20 ns
MCLK Duty cycle 40:60 60:40
Time from MCLK stopping to power
down.
1.5 12 s
DIGITAL AUDIO INTERFACE
Figure 2 Digital Audio Data Timing
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Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time tBCY 40 ns
BCLK pulse width high tBCH 16 ns
BCLK pulse width low tBCL 16 ns
LRCLK set-up time to BCLK
rising edge
tLRSU 8 ns
LRCLK hold time from
BCLK rising edge
tLRH 8 ns
DIN set-up time to BCLK
rising edge
tDS 8 ns
DIN hold time from BCLK
rising edge
tDH 8 ns
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DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8501 is a high performance DAC with an integrated 1.7Vrms line driver from a 5V
analogue supply, designed for digital consumer audio applications.
The WM8501 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC
and output smoothing filters. It is fully compatible and an ideal partner for a range of industry
standard microprocessors, controllers and DSPs. Control of the internal functionality of the device
is provided by hardware control pins (pin programmed).
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is supported, selection between
clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 96kHz are
allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz
using a master clock of 128fs or 192fs.
The audio data interface supports 16-bit right justified or 16-24-bit I2S (Philips left justified, one bit
delayed) interface formats. A DSP interface is also supported, enhancing the interface options for
the user.
Split analog and digital 2.7-5.5V supply may be used, the output amplitude scaling with absolute
analogue supply level. Low supply voltage operation and low current consumption combined with
the low pin count small package make the WM8501 attractive for many consumer applications. A
power down mode is provided, allowing power consumption to be minimised.
The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8501 DAC is designed to allow playback of 24-bit PCM audio or similar data with high
resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower
sample rates being acceptable provided that the ratio of sample rate (LRCLK) to master clock
(MCLK) is maintained at one of the required rates.
The two DACs on the WM8501 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to generate
a set of samples at a much higher rate than the up to 192kHz input rate. This sample stream is
then digitally modulated to generate a digital pulse stream that is then converted to analogue
signals in a switched capacitor DAC.
The advantage of this technique is that the DAC is linearised using noise shaping techniques,
allowing the 24-bit resolution to be met using non-critical analogue components. A further
advantage is that the high sample rate at the DAC output means that smoothing filters on the
output of the DAC need only have fairly crude characteristics in order to remove the characteristic
steps, or images on the output of the DAC. To prevent the generation of unwanted tones dithering
is used in the digital modulator along with a higher order modulator.
The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and
dramatically reduces out of band noise compared to switched current or single bit techniques.
The voltage on the VMID pin is used as the reference for the DACs. Therefore the amplitude of
the signals at the DAC outputs will scale with the amplitude of the voltage at the VMID pin. An
external reference could be used to drive into the VMID pin if desired, with a value typically of
about midrail ideal for optimum performance.
The outputs of the 2 DACs are buffered out of the device by buffer amplifiers capable of driving
into low impedance line loads as low as 820 or headphone loads down to 16. The buffer
amplifier output voltage level is set to 1.7V rms for line level loads when using a 5V analogue
supply, avoiding the requirement for additional gain stages or higher voltage supplies in many
applications. When driving headphone loads the output voltage level is limited to 1Vrms. The
advanced multi-bit DAC used in WM8501 produces far less out of band noise than single bit
traditional sigma delta DACs, and so in most applications where a line level output is required, no
post DAC filter is required. Typically an AC coupling capacitor and a DC setting resistor to ground
are the only components required on the output of the chip.
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CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master clock can be applied directly through the MCLK input
pin with no configuration necessary for sample rate selection.
Note that on the WM8501, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a
system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
The device can be powered down by stopping MCLK. In this state the power consumption is
substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface
formats are supported:
Right Justified mode
I
2S mode
DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT
is LOW, right justified data format is selected and word lengths of 16-bits may be used. When the
FORMAT pin is HIGH, I2S format is selected and word length of any value up to 24-bits may be
used. (If a word length shorter than 24-bits is used, the unused bits should be padded with zeros).
If LRCLK is 4 BCLKs or less duration, the DSP compatible format is selected. Mode A and Mode B
clock formats are supported, selected by the state of the FORMAT pin.
‘Packed’ mode (i.e. only 32 or 48 clocks per LRCLK period) operation is also supported in both I2S
(16-24 bits) and right justified formats, (16 bit). If a ‘packed’ format of 16-bit word length is applied
(16 BCLKS per LRCLK half period), the device auto-detects this mode and switches to 16-bit data
length.
I2S MODE
The WM8501 supports word lengths of 16-24 bits in I2S mode.
In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used
as a timing reference to indicate the beginning or end of the data words.
In I2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word
length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word
length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements
are met. In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK
transition. LRCLK is low during the left samples and high during the right samples.
Figure 3 I2S Mode Timing Diagram
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RIGHT JUSTIFIED MODE
The WM8501 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used
as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCLKs per LRCLK period is 2 times the selected
word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of
word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
Figure 4 Right Justified Mode Timing Diagram
DSP MODE
A DSP compatible, time division multiplexed format is also supported by the WM8501. This format
is of the type where a ‘synch’ pulse is followed by two data words (left and right) of predetermined
word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is
auto-detected by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less
duration, the DSP compatible format is selected. Mode A and Mode B clock formats are
supported, selected by the state of the FORMAT pin.
Figure 5 DSP Mode A Timing
LRCLK
BCL
K
DIN
Input Word Length (16 bits)
1/f
LEFT CHANNEL
1
21 1
LSBMSB
1
21 1
RIGHT CHANNEL NO VALID DATA
1 1
max 4 BCLK's
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Figure 6 DSP Mode B Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8501 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCLK, although the WM8501 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
(LRCLK)
MASTER CLOCK FREQUENCY (MHz) (MCLK)
128fs 192fs 256fs 384fs 512fs 768fs
32kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1kHz 5.6448 8.467 11.2896 16.9344 22.5792 33.8688
48kHz 6.144 9.216 12.288 18.432 24.576 36.864
96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable
192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
The WM8501 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
ENABLE OPERATION
Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low
power state. If this pin is held high the device is powered up.
To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin
after digital supplies have come on. This can be achieved by providing the ENABLE signal from
an external controller chip or by means of a simple RC network on the ENABLE pin. See
“Recommended External Components” in the “Application Information” section at the end of this
datasheet.
Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC
(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute
control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the
effect of powering down the voltage on the VMID pin. Repeated enabling/disabling of the device
can cause audible pops at the output.
LRCLK
BCLK
DIN
Input Word Length (16 bits)
1/f
LEFT CHANNEL
1
21 1
LSBMSB
16
21 1
RIGHT CHANNEL NO VALID DATA
1
Max 4 BCLK's
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HIGH PERFORMANCE MODE
On the rising edge of ENABLE, the DEEMPH pin is sampled. If it is low the device powers up
normally. If it is high the device goes into a high performance and high power consumption state.
Once ENABLE is high, DEEMPH controls the selection of the de-emphasis filter.
INPUT AUDIO FORMAT SELECTION
FORMAT (pin 13) controls the data input format.
FORMAT INPUT DATA MODE
0 16 bit right justified
1 16–24 bit I2S
Table 2 Input Audio Format Selection
Notes:
1. In 16-24 bit I2S mode, any data from 16-24 bits or more is supported provided that LRCLK is
high for a minimum of data width BCLKs and low for a minimum of data width BCLKs, unless
Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the most
significant 24 bits will be used by the internal processing.
2. If exactly 16 BCLK cycles occur in both the low and high period of LRCLK the WM8501 will
assume the data is 16-bit and accept the data accordingly.
INPUT DSP FORMAT SELECTION
FORMAT 50% LRCLK DUTY CYCLE LRCLK of 4 BCLK or Less Duration
0
16 bit
(MSB-first, right justified)
DSP format –mode B
1 I2S format up to 24 bit
(Philips serial data protocol)
DSP format –mode A
Table 3 DSP Interface Formats
DE-EMPHASIS CONTROL
DEEMPH (pin 12) is an input control for selection of de-emphasis filtering to be applied.
DEEMPH DE-EMPHASIS
0 Off
1 On
Table 4 De-emphasis Control
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DIGITAL FILTER CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Passband Edge -3dB 0.487fs
Passband Ripple f < 0.444fs 0.05 dB
Stopband Attenuation f > 0.555fs -60 dB
Table 5 Digital Filter Characteristics
DAC FILTER RESPONSES
-120
-100
-80
-60
-40
-20
0
0 0.5 1 1.5 2 2.5 3
Response (dB)
Frequency (Fs)
Figure 7 DAC Digital Filter Frequency Response -
44.1, 48 and 96kHz
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Response (dB)
Frequency (Fs)
Figure 8 DAC Digital Filter Ripple -
44.1, 48 and 96kHz
-80
-60
-40
-20
0
0 0.2 0.4 0.6 0.8 1
Response (dB)
Frequency (Fs)
Figure 9 DAC Digital Filter Frequency Response - 192kHz
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Response (dB)
Frequency (Fs)
Figure 10 DAC Digital Filter Ripple - 192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
-10
-8
-6
-4
-2
0
0 2 4 6 8 10 12 14 16
Response (dB)
Frequency (kHz)
Figure 11 De-Emphasis Frequency Response (32kHz)
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
0 2 4 6 8 10 12 14 16
Response (dB)
Frequency (kHz)
Figure 12 De-Emphasis Error (32kHz)
-10
-8
-6
-4
-2
0
0 5 10 15 20
Response (dB)
Frequency (kHz)
Figure 13 De-Emphasis Frequency Response (44.1kHz)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0 5 10 15 20
Response (dB)
Frequency (kHz)
Figure 14 De-Emphasis Error (44.1kHz)
-10
-8
-6
-4
-2
0
0 5 10 15 20
Response (dB)
Frequency (kHz)
Figure 15 De-Emphasis Frequency Response (48kHz)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 5 10 15 20
Response (dB)
Frequency (kHz)
Figure 16 De-Emphasis Error (48kHz)
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 17 External Component Diagram
In an application where ENABLE is fed directly from VDD rather than a dedicated control line,
resistor R3 and capacitor C9 are used on the ENABLE pin to introduce a short delay in the Low to
High transition of ENABLE. This will ensure the pin goes high after power supplies have had time
to settle (see “ENABLE Operation” in the “Hardware Control Modes” section of the datasheet).
However, if the ENABLE signal is being provided from an external controller chip rather than VDD
directly, R3 and C9 will not be required.
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POWER UP/DOWN SEQUENCE
POWER UP/DOWN SEQUENCE
For click free operation, the WM8501 should be powered up and down in a specific sequence.
Power-up:
1. Power up AVDD and DVDD and wait to settle
2. Turn on clocks and data (MCLK, BCLK, LRCLK, SDATA)
3. Switch ENABLE pin from low to high
Power-down:
1. Switch Enable from high to low
2. Remove clocks and data
3. Power down AVDD and DVDD
RECOMMENDED ANALOGUE LOW PASS FILTER
Figure 18 Recommended 1st Order Low Pass Filter
Note: Capacitors should be COG dielectric.
An external single pole RC filter is recommended (see Figure 18) if the device is driving a
wideband amplifier. However the WM8501 does contain an internal low pass filter which should be
adequate in most applications.
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PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8501 is to be mounted to. The
following notes will help in this respect:
1. The VDD supply to the device should be as noise free as possible. This can be
accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a
0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is
best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on
the same layer to minimize track inductance and thus improve device decoupling
effectiveness.
2. The VMID pin should be as noise free as possible. This pin provides the decoupling for
the on chip reference circuits and thus any noise present on this pin will be directly coupled
to the device outputs. In a similar manner to the VDD decoupling described above, this pin
should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as
close to the VMID pin as possible.
3. Separate analogue and digital track routing from each other. The device is split into
analogue (pins 5 – 9) and digital (pins 1 – 4 and pins 10 – 14) sections that allow the routing
of these signals to be easily separated. By physically separating analogue and digital
signals, crosstalk from the PCB can be minimized.
4. Use an unbroken solid GND plane. To achieve best performance from the device, it is
advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a
2 layer PCB to be a GND plane. For double sided implementations it is best to route as
many signals as possible on the device mounted side of the board, with the opposite side
acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions
from the PCB and minimizes crosstalk between signals.
Further advice on this subject is available in WAN0129, available from www.wolfsonmicro.com
Production Data WM8501
w PD, Rev 4.3, February 2013
19
PACKAGE DRAWING
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
Symbols
Dimensions
(MM)
Dimensions
(Inches)
MIN MAX MIN MAX
A1.35 1.75 0.0532 0.0688
A1 0.10 0.25 0.0040 0.0098
B0.33 0.51 0.0130 0.0200
C0.19 0.25 0.0075 0.0098
D8.55 8.75 0.3367 0.3444
E3.80 4.00 0.1497 0.1574
e1.27 BSC 0.05 BSC
H5.80 6.20 0.2284 0.2440
h0.25 0.50 0.0099 0.0196
L0.40 1.27 0.0160 0.0500
0o8o0o8o
REF: JEDEC.95, MS-012
0.10 (0.004)
SEATING PLANE
DM001.C
E
D: 14 PIN SOIC 3.9mm Wide Body
H
B
D
A
A1
C
h x 45
o
-C-
8
71
14
L
e
WM8501 Production Data
w PD, Rev 4.3, February 2013
20
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to
make changes to its products and specifications or to discontinue any product or service without notice. Customers should
therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific
testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product
design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection
or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction
can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products
by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual
property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be
or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval,
licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third
party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied
by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any
unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this
datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that
person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon
by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
Production Data WM8501
w PD, Rev 4.3, February 2013
21
REVISION HISTORY
DATE REV DESCRIPTION OF CHANGES CHANGED BY
31/01/13 4.3
Order codes changed from WM8501GED/V and WM8501GED/RV to
WM8501CGED and WM8501CGED/R to reflect copper wire bonding and MSL
change.
31/01/13 4.3
MSL changed from MSL3 to MSL1.
