LTC3110
1
Rev C
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TYPICAL APPLICATION
FEATURES DESCRIPTION
2A Bidirectional Buck-Boost
DC/DC Regulator and
Charger/Balancer
The LT C
®
3110 is a 2A bidirectional buck-boost DC/DC
regulator with capacitor charger and balancer. Its wide
0.1V to 5.5V capacitor/battery voltage and 1.8V to 5.25V
system backup voltage ranges make it well suited to a
wide variety of backup applications using supercapacitors
or batteries. A proprietary low noise switching algorithm
optimizes efficiency with capacitor/battery voltages that
are above, below or equal to the system output voltage.
The LTC3110 can autonomously transition from charge
to backup mode or switch modes based on an external
command. Pin-selectable Burst Mode operation reduces
standby current and improves light-load efficiency,
which combined with a 1μA shutdown current make the
LTC3110 ideally suited for backup applications. Additional
features include voltage supervisors for direction control
and end of charge, and a general purpose comparator
with open-collector output for interfacing with a µC. The
LTC3110 is available in thermally enhanced, low profile
24-lead TSSOP and 4mm × 4mm QFN packages.
APPLICATIONS
n VCAP Operating Range: 0.1V to 5.5V
n VSYS Operating Range: 1.71V to 5.25V
n Automatic Switchover from Charge to Backup Mode
n Programmable ±2% Accurate Charge Input Current
Limit from 125mA to 2A
n ±1% Backup Voltage Accuracy
n Automatic Backup Capacitor Balancing
n Fixed 1.2MHz Switching Frequency
n Burst Mode
®
Operation: 40μA Quiescent Current
n Built-In Programmable Multipurpose Comparator
with Open-Collector Output
n Open-Collector Outputs to Indicate Direction of
Operation and End of Charge
n Thermally Enhanced TSSOP-24 and 4mm×4mm
QFN-24 Packages
n Supercapacitor Backup Converter and Charger
n Battery Backup Converter and Charger
n Servers, RAID Systems
n RF Systems with Battery/Capacitor Backup
Backup Mode Efficiency
2.2µH
0.1V UP TO 5.5V
SW2
LTC3110
SVSYS VSYS
51.1Ω
47µF
220nF
12V
BUS
1µF
0.1µF
10F
10F
1960k
13.7k
1.50k
976k
221k
1000k
3110 TA01a
1000k
1.2V
1.8V
2.5V
VSYS
3.25V
2A
µC
END OF CHRG
CAPLOW
12V BUS
SUPERVISOR
523k
SW1VCAP
FBVCAP
CMPIN
MODE
RUN PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
SYSTEM
DC/DC
REGULATORS
MAIN
STEP-DOWN DC/DC
FB
ICHARGE
IBACKUP
VCAP (V)
EFFICIENCY (%)
POWER LOSS (W)
0.8
0.6
0.4
0.2
0
3110 TA01b
1.2
1.0
90
85
80
75
70
100
95
1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4
VSYS = 3.25V
ISYS = 0.5A
All registered trademarks and trademarks are the property of their respective owners.
LTC3110
2
Rev C
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS
VCAP, VSYS, SVSYS, VMODE, VCMPIN,
VDIR, VRUN, VCAPOK, VCMPOUT, VCHRG ...... –0.3V to 6V
RSEN DC Current .....................................................1.6A
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 150°C
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3110EFE#PBF LTC3110EFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP –40°C to 125°C
LTC3110IFE#PBF LTC3110IFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP –40°C to 125°C
LTC3110HFE#PBF LTC3110HFE#TRPBF LTC3110FE 24-Lead Plastic TSSOP –40°C to 150°C
LTC3110EUF#PBF LTC3110EUF#TRPBF 3110 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3110IUF#PBF LTC3110IUF#TRPBF 3110 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3110HUF#PBF LTC3110HUF#TRPBF 3110 24-Lead (4mm × 4mm) Plastic QFN –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
PIN CONFIGURATION
Storage Temperature Range .................. –65°C to 150°C
Lead Soldering Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
Reflow Peak Body Temperature (30sec max)
QFN ...................................................................260°C
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
FE PACKAGE
24-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 33°C/W, θJC = 5°C/W, 4 LAYER BOARD
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
24
23
22
21
20
19
18
17
16
15
14
13
CAPOK
CMPOUT
MODE
CMPIN
FBVCAP
SGND
DIR
RUN
FB
PROG
CHRG
SVSYS
VMID
VCAP
VCAP
SW1
SW1
PGND
PGND
SW2
SW2
VSYS
RSEN
VSYS
25
PGND
24 23 22 21 20 19
789
TOP VIEW
25
PGND
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 37°C/W, θJC = 4.5°C/W, 4 LAYER BOARD
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
CMPIN
FBVCAP
SGND
DIR
RUN
FB
SW1
SW1
PGND
PGND
SW2
SW2
MODE
CMPOUT
CAPOK
VMID
VCAP
VCAP
PROG
CHRG
SVSYS
VSYS
RSEN
VSYS
LTC3110
3
Rev C
For more information www.analog.com
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCAP No-Load Operating Range in Backup Operation VSYS ≥ 1.8V 0.1 5.5 V
VCAP Start-Up VSYS < Undervoltage Lockout Threshold l1.8 V
VSYS Operating Range in Charge Operation VDIR = VSYS l1.8 5.25 V
Undervoltage Lockout Threshold VSYS Ramping Down, VCAP = 0V
VSYS Ramping Up, VCAP = 0V
l
1.55
1.71
V
V
VCAP Ramping Down, VSYS = 0V, VRUN = VCAP
VCAP Ramping Up, VSYS = 0V, VRUN = VCAP
l
1.55
1.71
V
V
FB Feedback Voltage 0°C < TJ < 85°C (Note 5)
–40°C < TJ < 150°C
l
0.592
0.589
0.6
0.6
0.608
0.611
V
V
FB Feedback Pin Input Current 0.1 50 nA
FBVCAP End-of-Charge Threshold Rising DIR = VSYS l1.095 1.117 V
FBVCAP End-of-Charge Threshold Falling DIR = VSYS l1.040 1.061 V
FBVCAP Input Current VFBVCAP = 1.1V 0.1 50 nA
FBVCAP Overcharge Threshold Rising 1.125 1.150 1.175 V
FBVCAP Overcharge Hysteresis 35 mV
Quiescent Current, Burst Mode Operation
(IVCAP + IVSYS + ISVSYS)
VMODE = 0V 40 µA
Quiescent Current, End of Charge (IVCAP + IVSYS + ISVSYS) VDIR = VSYS 40 µA
Quiescent Current, Shutdown (IVCAP) VRUN = 0V, VSYS = SVSYS = 0V 0.05 1 µA
Peak Current Limit in Backup Operation (Note 4) 5 6 7 A
DC Current Limit in Backup Operation (Note 4) l3.5 4.5 A
Peak Current Limit in Charge Operation (Note 4) 5 6 7 A
Reverse Current Limit in Backup Operation (Note 4) 1 1.2 2 A
Switch Leakage Switch B, C: VCAP=VSW1=5.5V,
VSYS=VSW2=5.25V,
0.1 µA
Switch A, D: VCAP = 5.5V, VSYS = 5.25V
VSW1 = VSW2 = 0V
0.1 µA
Switch On-Resistance Switch A (Note 6)
Switch B (Note 6)
Switch C (Note 6)
Switch D Including Sense Resistor (Note 6)
64
49
49
86
mΩ
mΩ
mΩ
mΩ
Oscillator Frequency
VCAP = 0.2V
VSYS = 0.2V
l900 1200
300
300
1500 kHz
kHz
kHz
Soft Start-Up Time in Backup Mode From VRUN rising to VFB = 90% 0.8 1.3 1.8 ms
Maximum Duty Cycle in Boost Mode
VCAP = 0.2V
l 91 93
98
96 %
%
Minimum Duty Cycle in Buck Mode l0 %
MODE Input Logic Threshold Enable Burst Mode Operation
Enable PWM Mode Operation
1
0.3 V
V
MODE Input Pull-Down Resistor 6 MΩ
DIR Threshold Rising l1.073 1.095 1.117 V
DIR Threshold Falling l1.024 1.045 1.066 V
DIR Hysteresis l30 50 70 mV
DIR Input Current VDIR = 1.1V 0.1 50 nA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCAP = 3.3V, VSYS = 3.3V, VDIR = VSGND, VMODE = VRUN
= VSYS = SVSYS unless otherwise noted.
LTC3110
4
Rev C
For more information www.analog.com
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCAP = 3.3V, VSYS = 3.3V, VDIR = VSGND, VMODE = VRUN
= VSYS = SVSYS unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
CMPIN Threshold Rising 0.638 0.65 0.662 V
CMPIN Threshold Falling l0.575 0.59 0.605 V
CMPIN Input Current VCMPIN = 5.5V 0.1 50 nA
PROG Voltage VFBVCAP = 1V, DIR = VSYS 0.6 V
PROG Current Gain DIR = VSYS 200 µA/A
IVSYS Input Current Limit RPROG = 24.3k (Notes 7, 8), DIR = VSYS
RPROG = 24.3k (Notes 7, 8, 9), DIR = VSYS,
TJ = –40°C to 125°C
RPROG = 12.1k (Notes 7, 8), DIR = VSYS
RPROG = 12.1k (Notes 7, 8, 9), DIR = VSYS,
TJ = –40°C to 125°C
RPROG = 6.04k (Notes 7, 8), DIR = VSYS
RPROG = 6.04k (Notes 7, 8, 9), DIR = VSYS,
TJ = –40°C to 125°C
RPROG = 3.01k (Notes 7, 8), DIR = VSYS
RPROG = 3.01k (Notes 7, 8, 9), DIR = VSYS,
TJ = –40°C to 125°C
RPROG = 1.5k (Notes 7, 8), DIR = VSYS
RPROG = 1.5k (Notes 7, 8, 9), DIR = VSYS,
TJ = –40°C to 125°C
119
115
241
234
487
473
977
948
1960
1900
123
123
248
248
497
497
997
997
2000
2000
128
135
255
270
507
525
1017
1046
2040
2100
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VMID to VCAP Voltage Ratio VMID = Open Load, VCAP = 5V 0.492 0.5 0.508
VMID Balancing Current VCAP = 5V, VMID = 5V
VCAP = 5V, VMID = 0V
l
l
150 300
–300
–150
mA
mA
VMID Current in Shutdown VRUN = 0V 0.1 1 µA
VMID Suspend Charging Threshold VMID Rising, VCAP = 5V
VMID Falling, VCAP = 5V
2.38
2.6
2.4
2.62 V
V
CHRG, CAPOK, CMPOUT Open-Drain Output Voltage I = 10mA l0.1 0.3 V
RUN Input Logic Threshold l0.3 1 V
RUN Pull-Down Resistor 6 MΩ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3110 is tested under pulsed load conditions such that
TJ ~ TA. The LTC3110E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3110I is guaranteed to meet specifications over the –40°C to 125°C
operating junction temperature range. The LTC3110H is guaranteed
to meet specifications over the full –40°C to 150°C operating junction
temperature range. High temperatures degrade operating lifetime;
operating life time is derated for junction temperatures greater than 125°C.
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. The junction temperature (TJ, in °C) is
calculated from the ambient temperature (TA, in °C) and power dissipation
(PD, in watts) according to the formula:
TJ = TA + (PD • θJA),
where θJA (in °C/W) is the package thermal impedance.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: Current measurements are performed when the LTC3110 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators.
Note 5: Guaranteed by design characterization and correlation with
statistical process controls.
Note 6: Guaranteed by design, correlation and bench measurements.
Note 7: Current measurements are made when the output is not switching.
Note 8: Accuracy of this specification is directly related to the accuracy of
the resistor used to program the parameter.
Note 9: The Input Current Limit is reduced at junction temperatures above
125°C. See Thermal Foldback of Charge Current in the Operation section,
and the graph VPROG Programming Voltage vs Temperature in the Typical
Performance Characteristics section.
LTC3110
5
Rev C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
RDS(ON) of SWA Static
Maximum Load Current
in PWM Mode
Efficiency vs VCAP Voltage
RDS(ON) of SWD Dynamic
Including Sense Resistor
Maximum Load Current
in Burst Mode Operation
Burst Mode Efficiency
RDS(ON) of SWD Static
Including Sense Resistor
RDS(ON) of SWA Dynamic
Charge Efficiency
TA = 25°C unless otherwise noted
VCAP (V)
0
0
IVSYS (A)
1
2
3
4
5
1234
3110 G04
55.5
PULSED LOAD T = 1s
40% DUTY CYCLE
U_VSYS = 1.8V
U_VSYS = 3.3V
U_VSYS = 5.25V
VCAP (V)
0
0
IVSYS (mA)
150
250
350
450
50
100
200
300
400
1234
3110 G05
5 5.5
U_VSYS = 1.8V
U_VSYS = 3.3V
U_VSYS = 5.25V
VCAP (V)
1.5
RDS(ON) (mΩ)
95
105
115
5.5
3110 G06
85
75
65
45 2.5 3.5 4.5
2345
55
135
125 TJ = 155°C
TJ = 130°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –45°C
VCAP > ~75% • VSYS
VCAP (V)
0
RDS(ON) (mΩ)
65
70
75
4.54
3110 G07
60
55
45 123
0.5 5
1.5 2.5 3.5
50
85
80
TJ = 155°C
TJ = 125°C
TJ = –45°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
VCAP < ~75% • VSYS
VSYS (V)
1.5
RDS(ON) (mΩ)
120
150
160
5.5
3110 G08
110
100
60 2.5 3.5 4.5
2345
80
180
170
140
130
90
70
TJ = 155°C
TJ = 130°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –45°C
VSYS > ~75% • VCAP
VSYS (V)
1.5
60
RDS(ON) (mΩ)
65
75
80
85
3.5
105
3110 G09
70
2.5
24
3 4.5
90
95
100
TJ = 155°C
TJ = 125°C
TJ = –45°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
VSYS < ~75% • VCAP
VCAP (V)
0.5
65
EFFICIENCY (%)
80
70
85
75
90
100
95
1.5 2.5 3.5 4.5
3110 G01
5.5
VSYS = 3.25V
PWM MODE
ISYS = 0.2A
ISYS = 0.5A
ISYS = 1A
ISYS = 2A
0.001 0.01 0.1
ISYS (A)
70
75
80
85
90
EFFICIENCY (%)
VCAP = 5V, VSYS = 3.3V
VCAP = 2.5V, VSYS = 1.8V
3110 G02
0.5 1.5 2.5 3.5 4.5 5.5
VCAP (V)
0
0.5
1.0
1.5
2.0
2.5
EFFICIENCY (%)
50
60
70
80
90
100
POWER LOSS (W)
VSYS = 3.3V
RPROG = 3.01k
3110 G03
LTC3110
6
Rev C
For more information www.analog.com
Feedback Voltage vs VCAP Feedback Voltage vs Temperature VSYS Load Regulation
Switching Frequency vs VCAP Switching Frequency vs VSYS
Switching Frequency
vs Temperature
RDS(ON) of SWB RDS(ON) of SWC Switch Leakage vs Temperature
VCAP (V)
200
SWITCHING FREQUENCY (kHz)
600
1000
1400
400
800
1200
1234
3110 G16
5.50.50 1.5 2.5 3.5 4.5 5
VSYS = 3.3V
VSYS = 1.8V
FREQUENCY
FOLDBACK
AT LOW VCAP
VSYS (V)
200
SWITCHING FREQUENCY (kHz)
600
1000
1400
400
800
1200
1234
3110 G17
5.50.50 1.5 2.5 3.5 4.5 5
VCAP = 3.3V
VCAP = 1.8V
FREQUENCY
FOLDBACK
AT LOW VSYS
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
VCAP (V)
1.5
RDS(ON) (mΩ)
80
90
100
105
95
85
75
3.5 4 5
60
70
40
50
55
65
35
45
30 2 2.5 3 4.5 5.5 6
3110 G10
TJ = 155°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –40°C
VSYS (V)
1.5
RDS(ON) (mΩ)
80
90
100
105
95
85
75
3.5 4 5
60
70
40
50
55
65
35
45
30 2 2.5 3 4.5 5.5 6
3110 G11
TJ = 155°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –40°C
TJ (°C)
–45
SWITCH LEAKAGE (µA)
2.0
3.0
155
3110 G12
1.0
0555 105
–20 30 80 130
4.0
1.5
2.5
0.5
3.5
SWITCH B, C
SWITCH A, D
VCAP (V)
0
–1.0
VFB CHANGE FROM VCAP = 2.4V (%)
0.5
0
0.5
1.0
1234
3110 G13
5
ILOAD = 1mA
Burst Mode
OPERATION
PWM MODE
TJ (°C)
–45
VFB
0
0.5
115
–0.5
–1.0 –5 35 75 155
PWM
MODE
1.0
ILOAD = 1mA
Burst Mode
OPERATION
ILOAD (A)
0
–1.0
VOLTAGE CHANGE (%)
–0.5
0
0.5
1.0
0.5 1.0 1.5 2.0
3110 G15
2.5 3.0
Burst Mode
OPERATION
PWM MODE
TJ (°C)
–45
CHANGE FROM 25°C (%)
0
0.5
155
3110 G18
–0.5
–1.0 555 105
1.0
LTC3110
7
Rev C
For more information www.analog.com
VPROG Programming Voltage
vs Temperature
VPROG Programming Voltage
vs Temperature
VPROG Programming Voltage
vs VFBVCAP
VPROG Programming Voltage
vs VCAP
FBVCAP Comparator Thresholds
vs Temperature
VPROG Programming Voltage
vs VSYS
DIR Thresholds vs Temperature
CMPIN Threshold Voltage
vs Temperature
IVSYS Input Current Limit
vs RPROG
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
TJ (°C)
–45
VPROG (V)
0.4
0.5
0.6
105 13030 55 80
3110 G19
0.3
0.2
–20 5 155
0.1
0
0.7
THERMAL CHARGE
CURRENT FOLDBACK
TJ (°C)
–45
–1.0
VPROG CHANGE FROM 25°C (%)
–0.8
–0.4
–0.2
0
1.0
0.4
555 80 105
3110 G20
–0.6
0.6
0.8
0.2
–20 30 130
VFBVCAP (V)
0
0
VPROG (V)
0.1
0.3
0.4
0.5
0.8 1.0 1.2 1.4
0.7
3110 G21
0.2
0.2 0.4 0.6
0.6
END OF
CHARGE
CHARGE CURRENT
FOLDBACK
AT END OF CHARGE
VCAP (V)
0
–0.5
CHANGE IN VPROG FROM VCAP = 1.8V (%)
–0.3
–0.1
0.1
123 4
3110 G22
5
0.3
0.5 RPROG = 6.04k
–0.4
–0.2
0
0.2
0.4
VSYS (V)
1.7
–0.5
CHANGE IN VPROG FROM VSYS = 3.3V (%)
–0.3
–0.1
0.1
2.6 3.5 4.4
3110 G23
0.3
0.5
–0.4
–0.2
0
0.2
0.4
5.3
RPROG = 6.04k
TJ (°C)
–45
0
0.5
115
–0.5
–1.0 –5 35 75 155
1.0
FALLING
RISING
TJ (°C)
–45
VFBVCAP CHANGE FROM 25°C (%)
0.2
0.6
1.0
115
3110 G25
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 –5 35 75
–25 135
15 55 95 155
FALLING
RISING
TJ (°C)
–45
CHANGE FROM 25°C (%)
0
75 155
3110 G26
–0.5
–1.0 –5 35 115
0.5
1.0
FALLING
RISING
RPROG (kΩ)
024
IVSYS (mA)
1000
1500
3110 G27
500
068 10 12 14 16 18 20 22 24
2000
750
1250
250
1750
LTC3110
8
Rev C
For more information www.analog.com
VMID Load Regulation VMID Buffer Current vs VCAP VMID vs Temperature
Input Current Limit Aging Backup Soft-Start Backup Time
IVSYS Input Current vs VCAP
PROG Current Gain
vs Temperature IVCAP Charge Current vs VCAP
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
VCAP (V)
0
0
IVSYS (A)
1
2.00
0.50
1.50
2.50
1.0 2.0 3.0 4.0
3110 G28
5.0
RPROG = 1.50k
RPROG = 3.01k
RPROG = 6.04k
RPROG = 12.4k
TJ (°C)
–45
CHANGE FROM 25°C (%)
0
3110 G29
–1.0
–2.0 15 75
–15 45 105
1.0
2.0
–0.5
–1.5
0.5
1.5
135
RPROG = 6.04k
RPROG = 3.01k
RPROG = 1.50k
VCAP (V)
0
0
CURRENT (A)
2
1
3
5
4
1234
3001 G30
5
RPROG = 1.50k
RPROG = 3.01k
RPROG = 6.04k
RPROG = 12.4k
IMID (A)
–0.3
–1.0
VOLTAGE CHANGE (%)
–0.5
0
0.5
1.0
–0.2 –0.1 0 0.1
3110 G31
0.2 0.3
VCAP = 2.5V
VCAP = 5V
VCAP (V)
0
IVMID (mA)
0
3110 G32
–200
–400 2 4
13 5
200
400
VMID = VCAP
VMID = PGND
–100
–300
100
300
6
TJ (°C)
–45
VOLTAGE CHANGE (%)
0
0.5
115
3110 G33
–0.5
–1.0 –5 35 75 155
1.0
VCAP = 5.5V
NO LOAD
VCAP = 2.6V
TIME (YEAR)
0
–1.00
CHANGE FROM T = 0 YEAR (%)
–0.50
0
0.50
1.00
5 10 15 20
3110 G34
25 30
ACCELERATED LOAD LIFE
TEST DATA SCALED TO
TJ = 105°C, IVSYS = 2A
CONDITIONS
RUN
5V/DIV
VSYS
1V/DIV
0V
0A
200µs/DIV 3110 G35
IL
0.2A/DIV
2s/DIV
ILOAD =
C1 = C2 = 2.4F
2A 1A 0.5A 0.25A
VCAP
2V/DIV
0V
0V
VSYS
2V/DIV
3110 G45
LTC3110
9
Rev C
For more information www.analog.com
Load Step 0A to 2A
Burst Mode Operation
Charge Balancer Operation
C1 > C2
Charge Sleep to Backup Transient
in Autonomous Application
PWM Mode Operation
Charge Balancer Operation
C1 < C2
Backup to Charge Transient in
Autonomous Application
PWM Mode Operation in VCAP
Overvoltage Failure Condition
Single Capacitor Backup
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
ILOAD
1A/DIV
0A
VSYS
200mV/DIV
100µs/DIV 3110 G37
IL
1A/DIV
VSYS
1V/DIV
CHRGB
5V/DIV
0V
200µs/DIV 3110 G38
0A
IL
1A/DIV
VSYS
1V/DIV
CHRGB
5V/DIV
0V
200µs/DIV
BACKUP CHARGING
3110 G39
0A
10ms/DIV
VSYS
50mV/DIV
IL
0.5A/DIV
0A
3110 G40 500ns/DIV
SW1
1V/DIV
SW2
1V/DIV
0A
IL
0.2A/DIV
3110 G41
ISYS = 100mA
500ns/DIV
IL
100mA/DIV
0A
SW1
5V/DIV
SW2
5V/DIV
3110 G42
FBVCAP = 1.2V
VDIR = 0V
1s/DIV
VCAP
VMID
ISYS
1A/DIV
0A
0V
2V/DIV
3110 G43 1s/DIV
VCAP
VMID
ISYS
1A/DIV
0A
0V
2V/DIV
3110 G44
VCAP
1V/DIV
VSYS
1V/DIV
0V
0V
500ms/DIV 3110 G36
ILOAD = 300mA
C1 = 1.2F
LTC3110
10
Rev C
For more information www.analog.com
PIN FUNCTIONS
(FE/UFD)
CAPOK (Pin 1/Pin 22): VCAP Voltage OK Indicator Output.
The open-drain output is pulled low if the FBVCAP voltage
is lower than the FBVCAP falling threshold. The output is
released if FBVCAP is higher than the rising threshold.
CMPOUT (Pin 2/Pin 23): General Purpose Comparator
Output. The open-drain output is pulled low while the
CMPIN pin voltage is above the comparator rising thresh-
old. The output is released when CMPIN is below the
falling threshold.
MODE (Pin 3/Pin 24): Burst/PWM Mode Selection Input.
Driving MODE to a logic 1 state programs fixed frequency,
low noise PWM operation. Driving MODE low programs
Burst Mode operation. Note that the MODE pin has no
effect when operating in charger mode.
CMPIN (Pin 4/Pin 1): General Purpose Comparator
Positive Input with Hysteresis. The voltage at CMPIN is
compared to an internal reference voltage. The pin can be
driven digitally or configured as voltage supervisor with
the help of an external resistor divider. If driven from a
resistor divider or from a source with >200Ω impedance,
connect a 0.1µF capacitor between CMPIN and GND for
best performance. The CMPIN rising threshold is 0.65V
and the falling threshold is 0.59V.
FBVCAP (Pin 5/Pin 2): VCAP End-Of-Charge Voltage
Programming Feedback Divider Input with Hysteresis.
The end-of-charge threshold can be adjusted from 1.1V
to 5.5V. The FBVCAP rising threshold is 1.095V and falling
threshold is 1.061V.
SGND (Pin 6/Pin 3): Signal Ground Connection. A
ground plane is highly recommended. Sensitive analog
components terminated at ground should connect to the
SGND pin with a Kelvin connection, separated from the
high current path in PGND.
DIR (Pin 7/Pin 4): Charge/Backup Mode Selector Input
with Hysteresis. A voltage on DIR above the rising thresh-
old enables the LTC3110 charger mode. A voltage below
the falling threshold enables the backup mode. The pin
can be driven digitally, e.g., from a µC. With the help of
an external resistor divider the pin can be configured as
voltage supervisor input monitoring any system voltage.
The DIR rising threshold is 1.095V and the falling thresh-
old is 1.045V.
RUN (Pin 8/Pin 5): Logic-Controlled Shutdown Input.
RUN ≥ 1.0V: Normal Operation
RUN ≤ 0.3V: Shutdown
FB (Pin 9/Pin 6): VSYS Backup Voltage Feedback Pin.
Connect resistor divider tap here. The VSYS voltage can
be adjusted from 1.8V to 5.25V. The feedback reference
voltage is 0.6V.
PROG (Pin 10/Pin 7): Charger Input Current (IVSYS)
Programming Resistor. A resistor from PROG to SGND
programs the average current flowing in VSYS when oper-
ating in charging mode.
RPROG =
3k
Ω
•A
I
VSYS
for 1.5kΩ < RPROG <24.3kΩ
RPROG can be increased to 48.7k if the charge current fold-
back is avoided with FBV
CAP
held down < 1V or grounded.
LTC3110
11
Rev C
For more information www.analog.com
PIN FUNCTIONS
(FE/UFD)
CHRG (Pin 11/Pin 8): Charge/Backup Mode Indicator
Output. The open-drain output is pulled low while the
regulator is in charge mode. The open-drain output is
released while the regulator is in backup mode.
SV
SYS
(Pin 12/Pin 9): Signal Supply Voltage Input for
Buck/Boost Controller Circuitry. Pin must be shorted to
VSYS or supplied from VSYS through a RC filter. See the
Applications Information section for details.
VSYS (Pins 13, 15/Pins 10, 12): Bidirectional Power
Supply Pin for System Backup Output Voltage and Charge
Current Input Voltage. A bypass capacitor must be con-
nected between VSYS and PGND. Refer to the Typical
Applications schematics and the Applications Information
section for capacitor selection details.
RSEN (Pin 14/Pin 11): Current Sense Resistor Tap at
Junction of Internal Sense Resistor and Switch D. Pin
RSEN is internally shorted to pin VSYS via low impedance.
DC current in RSEN must be limited to 1.6A.
SW2 (Pins 16, 17/Pin 13, 14): Switch Pin Connected to
Internal Switches C and D of the Buck-Boost Regulator.
Connect one side of the buck-boost inductor to SW2.
Provide a short wide PCB trace from the inductor to SW2
to minimize voltage transients and noise.
PGND (Pins 18, 19, Exposed Pad Pin 25/Pins 15,
16, Exposed Pad Pin 25): Power Ground Connection.
Terminate all high current ground paths to PGND. The
exposed pad must be soldered to the PCB ground for
rated thermal performance.
SW1 (Pins 20, 21/Pins 17, 18): Switch Pin Connected to
Internal Switches A and B of the Buck-Boost Regulator.
Connect one side of the buck-boost inductor to SW1.
Provide a short wide PCB trace from the inductor to SW1
to minimize voltage transients and noise.
VCAP (Pins 22, 23/Pins 19, 20): Bidirectional Power
Pin for Connection to Supercap Backup Capacitor(s) or
Backup Battery(ies). When in charge mode a current flows
out of pin VCAP to charge the storage elements connected
between VCAP and PGND. When in backup mode the cur-
rent is flowing into pin VCAP and the stored energy is used
to backup the load on VSYS.
VMID (Pin 24/Pin 21): Active Voltage Balancing Power
Output. This pin should be tied to the junction of two
series supercapacitors. If the output is not used, a com-
pensation capacitor of 1nF must be connected between
pins VMID and PGND.
LTC3110
12
Rev C
For more information www.analog.com
BLOCK DIAGRAM
+
–
+
–
+
–VREF(PROG)
VTH(DIR)
BUCK-BOOST
CONTROL
CHARGER
INPUT
CURRENT
SENSE
VTH(CHRG)
DA
B C
SW1
L1
1.5µH
SW2
+
–
VREF(FB)
EN
FB
R5
HIGH = CHARGING
LOW = BACKUP
CHARGING/BACKUP
RCHRG
R6
CHRG
CHARGER
ENABLE
OSC
RUN
R1
R2
VSYS
RCAPOK
END OF CHARGE
HIGH = FORCED PWM
LOW = Burst Mode
OPERATION
HIGH = ENABLE
LOW = SHUTDOWN
R3
R4
CAPOK
OVERCHARGE
THRESHOLD
ENABLE
BACKUP
RMODE
DIR
VSYS
PROG
VSYS
RPROG
VCAP
BUF
VOLTAGE
BALANCING
MODE
+
–
END OF CHARGE
THRESHOLD
FBVCAP
VMID
VCAP
0.1V TO 5.5V
RSEN
CSVSYS
220nF
RSVSYS
51.1Ω
RSEN
SVSYS VSYS
CSYS
47µF
VSYS
1.8V TO 5.25V
2A
+
–
+
–+
–
+
–
+
–
+
–
EN
RRUN
VCAP
UNDERVOLTAGE
LOCKOUT
VSYS
VREFOK EN
SGND
LOCKOUT
THRESHOLD
CMPOUT
VTH(CMP)
RUN
CMPIN
VREF AND
BIAS
TEMP
SHUTDOWN
VSYS
RCAPLOW
CAPLOW
CCAP
1µF
C1
10F
C2
10F
PGND
3110 BD
COMP
COMP
CCMPIN
0.1µF
LTC3110
13
Rev C
For more information www.analog.com
OPERATION
INTRODUCTION
The LTC3110 is a monolithic buck-boost DC/DC regulator/
charger combination with pin-selectable operation modes
to utilize a single LTC3110 device for charging (V
DIR
=
high) as well as for system backup (VDIR = low). During
charging a limit for the average current drawn from the
system power source can be accurately programmed with
an external resistor. An integrated, active, voltage balanc-
ing buffer at pin VMID prevents capacitor overvoltage con-
ditions caused from capacitor mismatch while charging a
stack of supercapacitors.
The buck-boost regulator utilizes a proprietary switching
algorithm which allows the system voltage, VSYS, to be
regulated above, below, or equal to the voltage on the
storage element, VCAP, without discontinuity in inductor
current or large voltage ripple in the backup voltage VSYS.
With the DIR pin direction control circuitry, the LTC3110
can instantly reverse the inductor current and change
between charging and backup operation modes, react-
ing quickly on a power failure condition by providing the
backup voltage to the system (see Figure1).
The LTC3110 has been optimized to reduce quiescent
current in shutdown and standby for applications that
are sensitive to quiescent current drawn from the system
voltage, V
SYS
, or the storage element, V
CAP
. In charge
operation the standby current is only 40µA. In backup/
Burst Mode operation, the no-load standby current is only
40μA. In shutdown the total supply current is reduced to
less than 1μA.
Figure1. Transition from Charge– into Backup Operation
Figure2. Charge Foldback and Charge Termination
Charging
When powered from the system voltage, VSYS, the buck-
boost regulator is usually set to operate in charge mode
(VDIR = high), that is, a voltage source connected to VSYS
is the power input into the LTC3110 and the converter
charges a backup storage element connected between the
V
CAP
and PGND pins. When operating in charge mode, the
LTC3110’s average current limit circuitry is active. With a
resistor between the PROG and SGND pins, the maximum
average current drawn from VSYS can be programmed to
accurately limit the current demand.
Active Charge Balancer
While charging, the integrated linear charge balancing
buffer regulates the mid-voltage, VMID, of a stack of
capacitors to half of V
CAP
thus equalizing out voltage mis-
matches of top and bottom capacitor, see Figure3. If the
capacitor mismatch is exceeding the current capabilities
of the charge balancer, charging is suspended until VMID
comes back to half of VCAP (see charging waveforms in
the Typical Performance Characteristics section). Note,
the suspend charge function is only active for VCAP >
2.2V=VTH(CHRG) with hysteresis. For VCAP < 2V the char-
ger operation is always continuous.
VSYS
1V/DIV
IL
1A/DIV
0A
200µs/DIV
3110 F01
CHRG
5V/DIV
ISYS
1A/DIV
0A
2V/DIV
1SECOND/DIV 3110 F02
VCAP
VMID
LTC3110
14
Rev C
For more information www.analog.com
OPERATION
VCAP
BUF
VOLTAGE
BALANCING
WINDOW
COMPARATOR
VMID
R
C1
C2 R
3110 F03
1 = ALLOW CHARGING
0 = SUSPEND CHARGING
+
–+
–
LTC3110
Figure3. Active Charge Balancer
Charge Termination
The final charge voltage at pin V
CAP
is programmed with a
resistor divider at FBVCAP, see Figure10 in the Application
Information Section.
If FBVCAP exceeds typically 95% of its end of charge
threshold, the PROG reference voltage and with it the
charge current level begins to fold back (see Figure2).
Before charge termination the charge current is eventually
folded back to a level of typically 30% of the programmed
value (see charging waveforms in the Typical Performance
Characteristic section). When the programmed voltage
level is reached, the controller will terminate charging and
switch off into a low quiescent current state wherein the
charge balancer at the VMID pin is disabled and the CAPOK
pin is released. The low current state is maintained until
the voltage on V
CAP
decays and the FBV
CAP
falling thresh-
old is crossed. After this, controller and charge balancer
will resume operation with the CAPOK pin pulled low until
the regulation voltage is reached again. Note the IC cannot
prevent outside sources leaking current into the capaci-
tors from overvoltaging them.
Backup Operation in Fixed Frequency PWM Mode
With the MODE pin held high while VDIR = low, the
LTC3110 operates in a fixed-frequency pulse-width
modulation (PWM) mode using a voltage mode control
loop. This mode of operation maximizes the VSYS backup
current that can be delivered by the converter, reduces
V
SYS
voltage ripple, and yields a low noise fixed-frequency
switching spectrum. A proprietary switching algorithm
provides seamless transitions between operating modes
and eliminates discontinuities in the average inductor cur-
rent, inductor current ripple, and loop transfer function
throughout all regions of operation. These advantages
result in increased efficiency, improved loop stability, and
lower VSYS voltage ripple in comparison to the traditional
4-switch buck-boost converter.
Figure4 shows the topology of the LTC3110 power stage
which is comprised of two P-channel MOSFET switches
and two N-channel MOSFET switches and their associated
gate drivers. In response to the error amplifier output, an
internal pulse-width modulator generates the appropri-
ate switch duty cycles to maintain regulation of the VSYS
voltage.
When the VCAP voltage is significantly greater than the
VSYS voltage, the buck-boost converter operates in buck
mode. Switch D turns on continuously and switch C
remains off. Switches A and B are pulse-width modu-
lated to produce the required duty cycle to support the
VSYS regulation voltage. As the VCAP voltage decreases,
switch A remains on for a larger portion of the switching
cycle. When the duty cycle reaches approximately 90%,
the switch pair AC begins turning on for a small fraction
of the switching period. As the V
SYS
voltage decreases
further, the AC switch pair remains on for longer dura-
tions and the duration of the BD phase decreases propor-
tionally. At this point, switch A remains on continuously
while switch pair CD is pulse-width modulated to obtain
the desired VSYS voltage. At this point, the converter is
operating solely in boost mode.
Figure4. Buck-Boost Switch Topology
A D
L
B
SW2
LTC3110
3110 F04
SW1VCAP VSYS
C
LTC3110
15
Rev C
For more information www.analog.com
OPERATION
Backup in Burst Mode Operation
When MODE is held low while VDIR = low, the buck-boost
converter operates in Burst Mode operation using a vari-
able frequency switching algorithm that minimizes the
no-load input quiescent current and improves efficiency
at light load by reducing the amount of switching to the
minimum level required to support the load. The VSYS
current capability in Burst Mode operation is substan-
tially lower than in PWM mode and is intended to sup-
port light stand-by loads. Curves showing the maximum
Burst Mode load current as a function of the VCAP and
V
SYS
voltage can be found in the Typical Performance
Characteristics section of this data sheet. If the converter
load in Burst Mode operation exceeds the maximum Burst
Mode current capability, VSYS will lose regulation. Each
Burst Mode cycle is initiated when switches A and C turn
on producing a linearly increasing current through the
inductor. When the inductor current reaches the Burst
Mode peak current limit, switches A and C are turned
off and switchesB and D are turned on, discharging the
energy stored in the inductor into the VSYS capacitor and
load. Once the inductor current reaches zero, all switches
are turned off and the cycle is complete. Current pulses
generated in this manner are repeated as often as neces-
sary to maintain regulation of the VSYS voltage.
VCAP Peak and DC-Current Limits (Backup Mode)
The LTC3110 has two current limit circuits that are
designed to limit the peak inductor current to ensure that
the switch currents remain within the capabilities of the
IC during output short-circuit or overload conditions.
First current limit: In PWM mode the VCAP DC current
limit operates by injecting a current into the feedback pin
(FB). For this current limit feature being most effective,
the Thevenin resistance (RBOT//RTOP) from FB to ground
should exceed 100kΩ.
On a hard VSYS short, with Burst Mode operation or
PWM mode selected, it is possible for the inductor cur-
rent to increase substantially beyond the DC current limit
threshold. In this case the peak current, second current
limit, turns off the power switch until the start of the next
switching cycle.
Reverse Current Limit (Backup Mode)
In PWM mode operation the LTC3110 has the ability to
actively conduct current away from VSYS if it is necessary
to maintain regulation. If VSYS is held above the regula-
tion voltage, it could result in large reverse currents. This
situation can occur if VSYS of the LTC3110 is held up
by another supply. To prevent damage to the part in this
condition, the LTC3110 has a reverse current comparator
that monitors the current entering power switch D from
the load. If this current exceeds 1.2A (typical), switch D
is turned off for the remainder of the switching cycle. For
a no-load current application, the inductor current ripple
must be lower than double the minimum reverse current
limit (1A • 2 = 2A maximum inductor current ripple). See
the Inductor Selection section for information about how
to calculate the inductor current ripple.
Preventing VCAP Overcharge Failure Due to Reverse
DC Current (Backup Mode)
If during PWM backup operation (MODE = high and
DIR=low), an external power supply or any second DC/
DC regulator wrongly drives V
SYS
higher than the pro-
grammed back-up voltage level, the LTC3110 will reverse
its V
SYS
current and simultaneously create reverse current
flow charging V
CAP
. If the wrong V
SYS
voltage level is kept
for a longer period of time, FBVAP may exceed the over-
charge threshold and the LTC3110 stops reversecharging.
Charging through reverse DC current while VDIR is low is
not indicated at pin CHRG, which remains high impedance.
The overcharge condition is generally prevented in the
application by setting the LTC3110 into charge operation,
if VSYS is driven from an external source.
If the external source is supervised from the DIR com-
parator, the CHRG output can drive the gate of a PMOS
and isolate the external source in backup operation, see
applications with PFET on pages 29, 30, 31.
If VSYS is supervised from the DIR comparator, the exter-
nal source must be capable to deliver more than the
maximum reverse current limit of the LTC3110 in backup
direction, see autonomous application on page 36. Only
if the external supply is strong enough, charge operation
can be initiated reliably.
LTC3110
16
Rev C
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OPERATION
FBVCAP Failure Condition
External component failures, e. g., open or shorted resis-
tors or leakage currents at pin FBVCAP, can cause VCAP to
charge up to a higher, undefined voltage. If VCAP exceeds
typically 5.95V, the LTC3110 suspends charging which
protects the LTC3110 from substantially exceeding the
absolute maximum ratings if FBV
CAP
is shorted to ground.
Note supercapacitors and batteries often have a lower
maximum voltage rating than 5.95V. In these cases
the general purpose comparator can be configured to
detect the overvoltage at VCAP (see the figure General
Purpose Comparator as redundant VCAP supervisor in the
Application Information section).
Soft-Start (Backup Mode)
To minimize VCAP current transients on power-up, the
LTC3110 incorporates an internal soft-start circuit. The
soft-start is implemented by a linearly increasing ramp
of the error amplifier reference voltage during the soft-
start duration. During the soft-start period the regulator
is always operating in PWM operation independent of the
MODE pin setting. In case the VSYS voltage at start-up is
already pre-charged above 80% of the target value, the
soft-start is skipped and the LTC3110 immediately enters
the mode of operation that has been set with the MODE
pin. The soft-start period is reset by thermal shutdown
and from undervoltage lockout events.
Error Amplifier and Internal Compensation of VSYS
Backup Voltage Regulation
The buck-boost converter utilizes a voltage mode error
amplifier with an internal compensation network.
Error Amplifier and Internal Compensation of VSYS
Average Current Limit Regulation
The buck-boost converter in charge mode (DIR = high)
utilizes an error amplifier with an internal compensation
network to regulate the average current flowing into the
VSYS pin. The current limit is programmable with RPROG.
RSEN Current Sense Resistor Tap
R
SEN
connects to the junction of FET D and the integrated
sense resistor.
The R
SEN
pin can be left unconnected, otherwise a load
current, I
RSEN
, will simultaneously decrease the average
charge current flowing out of the V
CAP
pin. Note: A fast
voltage step at V
SYS
in the presence of a large R
SEN
capaci-
tor causes a large inrush current through the internal RSEN
resistor, e. g., closure of a mechanical power connection
supplying VSYS. In these cases, the value of the capacitor
between R
SEN
and ground is limited to a maximum of 10µF.
VCAPOK End-Of-Charge Indicator and FBVCAP
Comparator
The LTC3110 includes an open-drain comparator output
pin, VCAPOK, which is used to indicate the charging state
of the energy storage element.
The comparator input, FBVCAP, is typically connected with
a resistor divider from V
CAP
to ground in order to program
the final charge voltage. When FBVCAP exceeds the rising
threshold, the comparator output, VCAPOK, is high imped-
ance. When FBVCAP drops below the falling threshold,
V
CAPOK
is pulled to ground. While RUN = high, CAPOK
continues to pull down with reduced strength until both
V
CAP
and V
SYS
are below the threshold of the internal
pull-down transistor, maximum 1.4V.
The comparator operates in both charge and backup
mode and is unconditionally released if the LTC3110 is
shut down with RUN = low.
CHRG Operation Mode Indicator and DIR Comparator
The LTC3110 includes an open-drain DIR comparator
output pin, CHRG, which is typically used to indicate the
operation mode of the chip: charge or backup. With the
help of a pull-up resistor the output can be used to inter-
face with a microcontroller, or connect to the gate of a
p-channel MOSFET used as an input isolation switch (see
USB application in the Typical Application section).
The DIR comparator has hysteresis and the CHRG pin is
pulled low while V
DIR
is greater than the comparator rising
threshold and CHRG is released while VDIR is lower than
its falling threshold.
LTC3110
17
Rev C
For more information www.analog.com
The CHRG pin is unconditionally released if the LTC3110
is shut down with RUN = low or in undervoltage condition.
Note that the DIR pin can be driven above VCAP or VSYS,
as long as the voltage is limited to less than the absolute
maximum rating.
General Purpose Comparator
The LTC3110 includes a voltage comparator with its input
accessible at the CMPIN pin and with a fixed internal refer-
ence voltage.
The comparator can be used to monitor VCAP, VSYS or any
auxiliary supply voltage. The open-drain output, CMPOUT,
can interface to a microcontroller with the help of a pull-
up resistor. The comparator is typically used to supervise
VCAP and to set a threshold for the lowest VCAP voltage tol-
erated in backup mode before the system needs to reduce
power consumption. The CMPOUT pin is unconditionally
released if the LTC3110 is shut down with RUN = low
or in undervoltage condition (see also the Applications
Information section).
Shutdown
Shutdown of the LTC3110 is accomplished by pulling the
RUN pin below 0.3V and IC operation is enabled by pulling
the RUN pin above 1.0V. The RUN pin has an internal pull-
down resistor. Note that RUN can be driven above VCAP
or VSYS, as long as the voltage is limited to less than the
absolute maximum rating.
Thermal Foldback of Charge Current
To help preventing the LTC3110 from going into ther-
mal shutdown when charging very large capacitors, the
LTC3110 is equipped with a thermal regulator. If the die
temperature exceeds 130°C (typical) the average VSYS
current limit is lowered to help reduce the amount of
power being dissipated in the package. The current limit
is reduced to approximately 15% of the programmed limit
just before thermal shutdown. The current limit will return
to its full value when the die temperature drops below
130°C, typically.
Undervoltage Lockout
If either voltages at VCAP and VSYS drop below the under-
voltage lockout falling threshold, the LTC3110 will stop
operation and the SW1, SW2, VMID, CMPOUT, CHRG and
PROG pins will be high impedance. CAPOK will continue
to pull down with reduced strength until both VCAP and
VSYS are below the threshold of the internal pull-down
transistor, maximum 1.4V. The LTC3110 will resume
operation when at least one pin, V
CAP
or V
SYS
, rises above
the undervoltage lockout rising threshold.
THERMAL CONSIDERATIONS
The power switches in the LTC3110 are designed to oper-
ate continuously with currents up to the internal current
limit thresholds. However, when operating at high current
levels there may be significant heat generated within the
IC. As a result, careful consideration must be given to
the thermal environment of the IC in order to optimize
efficiency and ensure that the LTC3110 is able to provide
its full-rated output current. Specifically, the exposed pad
of both the QFN and TSSOP packages shall be soldered
to the PC board and the PC board should be designed
to maximize the conduction of heat out of the IC pack-
age. If the die temperature exceeds approximately 165°C,
the IC will enter overtemperature shutdown, all switch-
ing will be inhibited and the charge balancer disabled.
Note: Open-drain output pins CAPOK, CMPOUT and CHRG
may still pull down while in thermal shutdown. The part
will remain disabled until the die cools by approximately
10°C. The soft-start circuit is reinitialized in overtempera-
ture shutdown to provide a smooth recovery when the
fault condition is removed.
OPERATION
+
–
VTH(CMP)
CMPOUT
EN
CMPIN
LTC3110
3110 F08
Figure5. General Purpose Comparator
LTC3110
18
Rev C
For more information www.analog.com
The standard LTC3110 application circuit is shown as
the Typical Application on the front page of this data
sheet. The appropriate selection of external components
is dependent upon the required performance of the IC
in each particular application given considerations and
trade-offs such as PCB area, cost, VSYS and VCAP voltage,
allowable ripple voltage, efficiency and thermal consider-
ations. This section of the data sheet provides some basic
guidelines and considerations to aid in the selection of
external components and the design of the application
circuit.
Inductor Selection
The choice of inductor used in LTC3110 application cir-
cuits influences the maximum deliverable backup and
charge current, the magnitude of the inductor current
ripple, and the power conversion efficiency. The inductor
must have low DC series resistance or current capability
and efficiency will be compromised. Larger inductance
values reduce inductor current ripple and will therefore
generally yield greater backup current capability. For a
fixed DC resistance, a larger value of inductance will
yield higher efficiency by reducing the peak current to
be closer to the average backup current and therefore
minimize resistive losses due to high RMS currents.
However, a larger inductor within any given inductor fam-
ily will generally have a greater series resistance, thereby
counteracting this efficiency advantage. An inductor used
in LTC3110 applications should have a saturation current
rating that is greater than the worst-case average induc-
tor current plus half the ripple current. The peak-to-peak
inductor current ripple for each operational mode can be
calculated from the following formula:
ΔIL(P-P)(BUCK) =VSYS
1.2MHz •L
VCAP – VSYS
VCAP
⎛
⎝
⎜⎞
⎠
⎟
ΔIL(P-P)(BOOST) =VCAP
1.2MHz •L
VSYS – VCAP
VSYS
⎛
⎝
⎜⎞
⎠
⎟
L is the inductance in μH.
In addition to its influence on power conversion efficiency,
the inductor DC resistance can also impact the maximum
output capability of the buck-boost converter particularly
at low VCAP voltages. In buck mode, the output current of
the buck-boost converter is limited only by the inductor
current reaching the current limit threshold. However, in
boost mode, especially at large step-up ratios, the VSYS
backup current capability can also be limited by the total
resistive losses in the power stage. These include switch
resistances, inductor resistance and PCB trace resistance.
Use of an inductor with high DC resistance can degrade
the VSYS backup current capability from that shown in the
Typical Performance Characteristics section of this data
sheet. As a guideline, in most applications the inductor DC
resistance should be significantly smaller than the typical
power switch resistance of 60mΩ.
The minimum inductor value must guarantee that the
worst-case average VCAP current plus half the ripple cur-
rent doesn’t reach the V
CAP
current limit threshold. For the
fixed switching frequency of 1.2MHz the recommended
typical inductor value is 1.5µH.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, siz-
ing, and EMI requirements of a particular application.
Table1 provides a small sampling of inductors that are
well suited to many LTC3110 applications.
Table1. Recommended Inductors
VENDOR PART/STYLE
Coilcraft
www.coilcraft.com
XAL50xx Series (XAL5030-222ME_)
XAL60xx Series (XAL6030-222ME_)
EPL7040 Series (EPL7040-222ME_)
Würth Elektronik
www.we-online.com
WE-HCI Series (744310150,
744314200) WE-LHMI Series
(74437346018, 74437349022)
Coiltronics www.
cooperindustries.com
DR73 Series (DR73-2R2-R) DRQ74
Series (DR74-2R2-R)
Vishay
www.vishay.com
IHLP-2525 Series (IHLP-2525AH-01,
IHLP-2525CZ-01) IHLP-2020 Series
(IHLP-2020CZ-A1)
Sumida
www.sumida.com
CDEP6D31ME Series
(CDEP6D31MENP-2R2MC)
Murata
www.murata.com
LQH66S Series (LQH66SN1R5M03)
Taiyo Yuden
www.t-yuden.com
NR6012T2R5NE NR8040T2R0N
TDK
www.component.tdk.com
CLF Series
APPLICATIONS INFORMATION
LTC3110
19
Rev C
For more information www.analog.com
VSYS Capacitor Selection
A low ESR capacitor should be utilized at the VSYS pin in
order to minimize VSYS backup voltage ripple. Multilayer
ceramic capacitors are an excellent option as they have
low ESR and are available in small footprints. The capaci-
tor value should be chosen large enough to reduce the
VSYS voltage ripple to acceptable levels. Neglecting the
capacitor ESR and ESL, the peak-to-peak VSYS voltage
ripple can be calculated by the following formulas, where
CVSYS is the VSYS capacitance and ILOAD is the VSYS load
current.
ΔVP-P(BUCK) =VSYS
8 • 1.2MHz
( )
2•L •CVSYS
VCAP – VSYS
VCAP
⎛
⎝
⎜⎞
⎠
⎟
ΔVP-P(BOOST) =ILOAD
1.2MHz •CVSYS
VSYS – VCAP
VSYS
⎛
⎝
⎜⎞
⎠
⎟
Given the VSYS current is discontinuous in boost mode,
the ripple in this mode will generally be much larger than
the magnitude of the ripple in buck mode. In addition to
VSYS voltage ripple generated across the VSYS capaci-
tance, there is also VSYS voltage ripple produced across
the internal resistance of the V
SYS
capacitor. The ESR-
generated VSYS voltage ripple is proportional to the series
resistance of the VSYS capacitor.
Supercapacitor Selection and Additional Bypass
The LTC3110 is stable with a total CVCAP capacitance
value greater than 2mF, or 4mF for each stacked capacitor.
Supercapacitors are much larger physically than ceramic
or tantalum capacitors, and therefore usually cannot be
placed close to the charger. To minimize layout contri-
bution to capacitor ESR, the trace width connecting the
capacitors to each other and the IC should be as large as
possible. The VMID pin trace is not as critical, as it only
carries 300mA of average current. It is recommended
that a local decoupling capacitor be placed from VCAP
to ground, and the capacitor should be placed as close
to the IC as possible. Multilayer ceramic capacitors are
an excellent choice for voltage decoupling as they have
extremely low ESR and are available in small footprints.
While a 10μF decoupling capacitor is sufficient for most
applications, larger values may be used without limitation.
To minimize voltage ripple and ensure proper operation of
the IC, a low ESR bypass capacitor with a value of 100nF
and a second low ESR bypass capacitor of 10μF should
be located as close to the VCAP pin as possible. The traces
connecting this capacitor to VCAP and the ground plane
should be made as short as possible. If using a single V
SYS
capacitor where balancing is not required, a capacitor of
at least 1nF must be connected between VMID and PGND.
Recommended VCAP and VSYS Bypass Capacitors
The choice of capacitor technology is primarily dictated
by a trade-off between cost, size and leakage current.
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR and
low leakage currents. However, many ceramic capacitors
designed for power applications experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
than 50% of its rated capacitance when operated near
its rated voltage. As a result, it is sometimes necessary
to use a larger value capacitance or a capacitor with a
higher voltage rating than required in order to actually
realize the intended capacitance at the full operating volt-
age. To ensure that the intended capacitance is realized
in the application circuit, be sure to consult the capacitor
vendor’s curve of capacitance versus DC bias voltage. The
capacitors listed in Table3 provide a sampling of small
surface mount ceramic capacitors that are well suited
to LTC3110 application circuits. All listed capacitors are
either X5R or X7R dielectric in order to ensure that capaci-
tance loss over temperature is minimized.
Maximum Capacitor Voltage and Balancing
The service lifetime of a supercapacitor is determined by
its rated voltage, rated temperature, rated lifetime, actual
operating voltage, and operating temperature. To extend
the life of a supercapacitor the operating voltage and tem-
perature should be reduced from the maximum ratings.
The websites for Illinois Capacitor1 and Maxwell2 provide
the means to determine their capacitor lifetime.
APPLICATIONS INFORMATION
1http://www.illinoiscapacitor.com/tech-center/life-calculators.aspx
2http://www.maxwell.com/products/ultracapacitors/docs/
APPLICATIONNOTE1012839_1.PDF
LTC3110
20
Rev C
For more information www.analog.com
Using the suggested derated voltage for each capacitor
will improve lifetime. The LTC3110 will keep each capaci-
tor voltage at VCAP/2 once VCAP is higher than typically
2.2V. To prevent an overvoltage on one of the superca-
pacitors during charging, the VMID voltage is continuously
driven from the voltage balancing buffer output with typi-
cally 300mA of current capability.
The LTC3110 has minimal current draw from VCAP at end
of charge. Care should be taken to limit sources of cur-
rent that may pull VCAP above its programmed regulation
value, as there is no way for the LTC3110 to maintain
regulation.
VSYS Voltage Programming
The V
SYS
voltage is set via an external resistor divider
connected to the FB pin as shown in Figure6.
The resistor divider values determine the VSYS backup
voltage according to the following formula:
VSYS =0.6V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
(1)
The buck-boost converter utilizes voltage mode control and
in addition to setting the VSYS voltage, the value of RTOP
plays an integral role in the dynamics of the feedback loop.
In general, a larger value for RTOP will increase stability and
reduce the speed of the transient response. A smaller value
of RTOP will reduce stability but increase the speed of the
transient response. A good starting point is to choose R
TOP
= 1M and then calculate the required value of RBOT to set
the desired VSYS voltage according to Equation 1. If a large
VSYS capacitor is used, the bandwidth of the converter is
reduced. In such cases RTOP can be reduced to improve the
transient response. If a large inductor or small V
SYS
capaci-
tor is utilized the loop will be less stable and the phase
margin can be improved by increasing the value of RTOP.
VCAP Voltage Programming
The V
CAP
voltage is set via an external resistor divider
connected to the FBVCAP pin as shown in Figure7.
The resistor divider values determine the maximum VCAP
voltage according to the following formula:
VCAP =1.095V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
Care should be taken to limit sources of current that may
pull V
CAP
above its programmed maximum value, as there
is no way for the LTC3110 to maintain VCAP regulation
in charger mode (see also Figure15, Overvoltage Error
Signal Provided to the µC).
APPLICATIONS INFORMATION
RBOT
RTOP
3110 F09
VSYS
FB
SGND
LTC3110
Figure6. Setting the VSYS Backup Voltage
VCAP
VMID
1µF
3110 F11
LTC3110
C1
C2
RTOP
RBOT
VCAP
FBVCAP
1µF
C1
C2
SGND
3110 F10
LTC3110
Figure7. VCAP Voltage Programming
VMID Charge Balancer Output
This pin should be tied to the junction of two series super-
capacitors. A push/pull buffer output forces the VMID pin
to half of the voltage of the VCAP pin. Generally capaci-
tors with equal value of at least 1nF should be connected
from VCAP to VMID and from VMID to PGND if the output
is unused, e.g., for applications with a single supercapaci-
tor or batteries.
Figure8. VMID Charge Balancer Output
LTC3110
21
Rev C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure9. Charge Balancer Unused with Single Capacitor
VCAP
VMID
SINGLE
CAPACITOR
OR BATTERY 1µF
3110 F12
LTC3110
1nF
1nF
Figure10. Setting the DIR Back-Up Supervisor
Threshold Voltage
RTOP
SUPERVISED
VOLTAGE
RBOT
3110 F13
DIR
SGND
LTC3110
DIR Backup Supervisor Threshold Voltage
Programming
The backup supervisor threshold voltage is set via an
external resistor divider connected to the DIR pin as
shown in Figure10.
The resistor divider values determine the DIR supervisor
threshold voltage according to the following formula:
VTH(DIR_RISING) =1.095V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
VTH(DIR_FALLING) =1.045V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
Programming Backup Voltage and DIR Threshold
Voltage with Improved Accuracy
In applications with the DIR pin voltage and the FB pin
voltage divided down from the same VSYS voltage, a single
resistor divider string is reducing the effect of resistor
tolerances and saves one resistor component:
Figure11. Voltage with Reduced Tolerances
RMID
RTOP
BACKUP
VOLTAGE
RBOT
3110 F14
VSYS
FB
DIR
SGND
PGND
LTC3110
CDIR
RTOP
SUPERVISED
VOLTAGE
RBOT
3110 F15
DIR
SGND
PGND
LTC3110
Figure12. Filtering DIR voltage
VTH(DIR_RISING) =1.095V • 1+RTOP
RBOT +RMID
⎛
⎝
⎜⎞
⎠
⎟
VTH(DIR_FALLING) =1.045V • 1+RTOP
RBOT +RMID
⎛
⎝
⎜⎞
⎠
⎟
VSYS =0.6V • 1+RTOP +RMID
RBOT
⎛
⎝
⎜⎞
⎠
⎟
Note the direction supervisor threshold V
TH(DIR_RISING)
must be higher and have enough voltage difference to
the backup voltage VSYS to accommodate for the resistor
tolerances, ripple voltage and voltage dipping from load
current steps. If necessary an RC filter in front of the DIR
pin may reduce the reaction speed of the supervisor, see
Figure12.
Pay attention to the requirement, if the DIR input super-
vises VSYS as in Figure11 or in the autonomous applica-
tions on page 36, the external VSYS supply must be capable
to deliver more than the maximum reverse current limit of
2A of the LTC3110, in order to reliably change into charge
operation.
LTC3110
22
Rev C
For more information www.analog.com
IVSYS Average Current Limit Programming for Charger
Operation (DIR = High)
The VSYS average current limit is set via an external resis-
tor connected between the PROG pin and signal ground,
SGND, as shown in Figure13.
The resistor value determines the average current into
VSYS according to the following formula:
IVSYS =
3kΩ
R
PROG
For applications with a wide temperature range, the
thermal coefficient of resistor RPROG must be taken into
account. If RPROG is > 12.4k, additional RFLT and CFLT are
required for filtering.
APPLICATIONS INFORMATION
If CMPIN is driven from a resistor divider or from any output
with >200Ω impedance, connect a 0.1µF capacitor between
CMPIN and GND for best performance, see Figure14.
General Purpose Comparator Configuration as
Redundant VCAP Supervisor for Overvoltage Failure
Detection
Component failures interrupting the V
CAP
voltage feedback
(FBVCAP) can potentially cause an over voltage condition
at VCAP during charging. The general purpose comparator
can be configured as the supervisor providing an overvolt-
age error signal to the microcontroller (see Figure15).
RPROG
RF LT
6.04k (OPT)
CF LT
10nF (OPT)
3110 F16
PROG
SGND
LTC3110
Figure13. Setting the VSYS Average Current Limit
Figure15. Overvoltage Error Signal Provided to the µC
CMPIN Configuration as General Purpose Voltage
Supervisor with Hysteresis
The resistor divider values, see Figure14, determine ris-
ing and falling threshold VTH according to the following
formula:
VTH(RISING) =0.65V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
VTH(FALLING) =0.59V • 1+RTOP
RBOT
⎛
⎝
⎜⎞
⎠
⎟
VDD
RTOP
RBOT
VTH
3110 F17
CMPIN
CMPOUTOUT
LTC3110
CCMPIN
0.1µF
Figure14. General Purpose Voltage Supervisor
LTC3110
VDD
3110 F18
µC
CMPOUT
RUN
CMPIN
VCAP
RTOP
C1
C2
RBOT
10k ERR
CCMPIN
0.1µF
SVSYS Filtering
In many noise critical applications it is useful to filter the
signal supply pin, SV
SYS
, with a small RC filter on the
PCB, see Figure16. Note, if the filter is added any further
loads connected to the SVSYS pin must be checked if they
are small with respect to the resistor impedance and not
creating undesired voltage drops at SVSYS.
RUN, DIR, MODE, CMPIN Inputs Digitally Controlled
The RUN, DIR, MODE and CMPIN comparator inputs can
be driven digitally from an external microcontroller.
3110 F19
SGND
SVSYS
CSYS
VSYS
RSVSYS
51.1Ω
CSVSYS
220nF
LTC3110
Figure16. SVSYS Filtering
LTC3110
23
Rev C
For more information www.analog.com
APPLICATIONS INFORMATION
Open-Collector Outputs
CHRG, CAPOK and CMPOUT open-collector outputs can
be connected together with other external signals in wired
OR configuration and pull-up resistors for level shifting
when interfacing into µC Inputs.
LTC3110 µC
3110 F20
CMPIN
SGND
MODE
DIR
RUN
Figure17. Inputs RUN, DIR, MODE, CMPIN Driven from a
Microcontroller
LTC3110
µC
VDD
3110 F21
SGND
CMPOUT
CAPOK
CHRG
Figure18. Outputs CHRG, CAPOK, CMPOUT Interfacing to µC
Table2. Recommended Supercapacitors and Ultracapacitors
VENDOR
VALUE
(F)
ESR
(mΩ)
VOLTAGE
(V)
TEMPERATURE
RANGE (°C) SIZE (mm) W × L × H
Murata Electronics
DMF3R5R5L334M3DTA0
DMF3Z5R5H474M3DTA0
0.33
0.47
60
40
4.2 (5.5 Peak)
4.2 (5.5 Peak)
–30 to 70
–30 to 70
14.0 × 21.0 × 2.5
14.0 × 21.0 × 3.2
Tecate
TPL-10/10X30F
TPL-25/16X26F
TPL-100/22X45F
TPLE-25/16X26F
TPLE-100/22X45F
TPLS-400/35X60F
10
25
100
25
100
400
85
42
15
42
15
12
2.7
2.7
2.7
2.3
2.3
2.7
–40 to 65
–40 to 65
–40 to 65
–40 to 85
–40 to 85
–40 to 65
10.0 × 10.0 × 30.0
16.0 × 16.0 × 26.0
22.0 × 22.0 × 45.0
16.0 × 16.0 × 26.0
22.0 × 22.0 × 45.0
35.0 × 35.0 × 60.0
AVX
BZ015A503Z_B
BZ015A104Z_B
0.05
0.1
160
80
5.5
5.5
–20 to 70
–20 to 70
28.0 × 17.0 × 4.1
28.0 × 17.0 × 6.7
CAP-XX
HS206F
HS230
0.6
1.2
70
50
5.5
5.5
–40 to 85
–40 to 85
39.0 × 17.0 × 2.5
39.0 × 17.0 × 3.8
Cooper Bussmann
A1635-2R5475-R
M1325-2R5905-R
HB1625-2R5256-R
HV1860-2R7107-R
4.7
9
25
100
25
20
36
10
2.5
2.5
2.5
2.7
–25 to 70
–40 to 60
–25 to 70
–40 to 65
16.0 × 16.0 × 35.0
13.0 × 13.0 × 26.0
16.0 × 16.0 × 25.0
18.0 × 18.0 × 60.0
Illinois Capacitor
506DER2R5SLZ
357DER2R5SEZ
50
100
30
12
2.5
2.5
–40 to 70
–40 to 70
18.0 × 18.0 × 60.0
35.0 × 35.0 × 60.0
Maxwell
BCAP0005
BCAP0100T01
5
100
170
15
2.7
2.7
–40 to 65
–40 to 65
10.0 × 10.0 × 20.0
22.0 × 22.0 × 45.0
Taiyo Yuden
PAS2026FR2R5504
PAS0815LS2R5105
LIC2540R3R8207
0.5
1
200
55
70
50
2.5
2.5
2.2 to 3.8
–25 to 60
–25 to 70
–25 to 70
26.0 × 20.0 × 0.9
8.0 × 8.0 × 15.0
25.0 × 25.0 × 40.0
The open-collector outputs can also be used to drive small
loads up to 20mA, e.g., miniature lamps or LEDs.
LTC3110
24
Rev C
For more information www.analog.com
PCB Layout Considerations
The LTC3110 switches large currents at high frequencies.
Special care should be given to the PCB layout to ensure
stable, noise-free operation. Figures 19 and 20 depict the
recommended PCB layout to be utilized for the LTC3110,
if a 2-layer PCB is being used. A 4-layer PCB layout is
recommended for thermal and noise reasons. A few key
guidelines follow:
1. All circulating high current paths should be kept as
short as possible. This can be accomplished keeping
the routes to the components in Figures 19 and 20
as short and as wide as possible. Capacitor ground
connections should be connect by vias down to the
ground plane in the shortest route possible. The
bypass capacitors CSYS and CCAP should be placed
as close to the IC as possible and should have the
shortest possible path to ground.
2. The components shown and their connections should
all be placed over a complete ground plane.
3. Use of vias in the die attach pad will enhance the ther-
mal environment of the charger, especially if the vias
extend to a ground plane region on the exposed bottom
surface of the PCB.
4. Keep the connections to the FB, PROG, DIR, CMPIN
and FBVCAP pins as short as possible and away from
the switch pin connections.
APPLICATIONS INFORMATION
Table3. Representative Bypass and VSYS Capacitors
PART NUMBER VALUE (µF) VOLTAGE (V) FOOTPRINT
AVX
12066D106K
12066D226K
12066D476K
10
22
47
6.3
6.3
6.3
0603
0805
0805
Kemet
C0603C106M9PACTU
C0805C226M9PACTU
C0805C476M9PACTU
10
22
47
6.3
6.3
6.3
0603
0805
0805
Murata
GRM188D70J106MA73
GRM219B30J226ME47
GRM21BB30J476ME15
10
22
47
6.3
6.3
6.3
0603
0805
0805
TDK
C1608X7S0J106M080AC
C2012X5R0J226M085AB
C2012X5R0J476M125AC
10
22
47
6.3
6.3
6.3
0603
0805
0805
Taiyo Yuden
JMK107BJ106MA
JMK212ABJ226MD
JMK212BBJ476MG
10
22
47
6.3
6.3
6.3
0603
0805
0805
LTC3110
25
Rev C
For more information www.analog.com
APPLICATIONS INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
17
16
15
14
13
19
18
21
20
C2
BOTTOM COPPER LAYER
C1
CSYS
3110 F22
VIA TO GROUND PLANE
L1
CCAP
COMPONENT NAMES:
SEE TYPICAL APPLICATION
ON PAGE 27
LTC3110
TOP LAYER
Figure19. PCB Component Placement of the TSSOP Package
LTC3110
26
Rev C
For more information www.analog.com
APPLICATIONS INFORMATION
1
2
3
4
5
6
18
7
7
7
10
11
12
24
23
22
21
20
19
C2
BOTTOM COPPER LAYER
C1
L1
CCAP
17
16
15
14
13
CSYS
VIA TO GROUND PLANE
3110 F23
COMPONENT NAMES:
SEE TYPICAL APPLICATION
ON PAGE 27
LTC3110
TOP LAYER
Figure20. PCB Component Placement of the QFN Package
LTC3110
27
Rev C
For more information www.analog.com
TYPICAL APPLICATIONS
3.3V/2A Output from Stack of Supercapacitors Backup/Recharge Application with Active Voltage Balancing
L1
1.5µH
SW2
LTC3110
SVSYS VSYS
CSYS
47µF
CSVSYS
220nF
VSYS
3.25V
2A
CCAP
1µF
C1
10F
C2
10F
R1
1910k
R2
523k
R3
1910k
R4
523k
RPROG
6.04k
RSVSYS
51.1Ω
R5
976k
R6
221k
3110 TA02
SW1VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
CAPOK
CAPLOW
AT VCAP = 2.8V
DIR
1000k 1000k
µC
12V BUS
SUPERVISOR
SGND
12V
BUS
MAIN
STEP-DOWN DC/DC
FB
CCMPIN
0.1µF
1.8V/300mA Output from Single Capacitor Discharged from 2.5V to 1V and with Reserve Available Down to 0.3V
CAPOK
CAPLOW
DIR
1000k 1000k
µC
12V BUS
SUPERVISOR
LTC3110
CSYS
47µF
VSYS
1.83V BACKUP
300mA
CCAP
1µF
CMID2
1nF
CMID1
1nF
C1
10F R1
2000k
R2
1580k
R3
1300k
R4
1870k
RPROG
6.04k
R5
976k
R6
475k
3110 TA03
VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
L1
1.5µH
SW2 SVSYS VSYS
CSVSYS
220nF
VSYS = 1.9V CHARGING
SW1
12V
BUS
MAIN
STEP-DOWN DC/DC
FB
CCMPIN
0.1µF
LTC3110
28
Rev C
For more information www.analog.com
TYPICAL APPLICATIONS
500mA USB Charge/Backup Application with Variable Charging Power, PCHRG, Depending on System Load
L1
1.5µH
SW2
LTC3110
SVSYS VSYS
CSYS
330µF
CFB
10pF
CDIR
1nF
CCAP
1µF
PCHRG = PUSB – PSYS
USB
M1
IRLML6402
C1
10F
C2
10F
R1
1910k
ROFF
3.3k
R2
511k
R7
7.50k
R8
2.49k
RPROG
6.04k
R6
133k
R5
976k
1000k
3110 TA04
1000k
1.2V, 1A
USB
DATA
1.8V, 0.2A
2.5V, 0.1A
5V, 0.1A
5V
µC
END OF CHRG
CAPLOW
SW1VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PSYS
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
SYSTEM
DC/DC
REGULATORS
CSVSYS
220nF RSVSYS
51.1Ω
R3
1910k
R4
1270k
PUSB UP TO 5V • 500mA
CCMPIN
0.1µF
1V/DIV
100µs/DIV 3110 TA04b
ILI
2A/DIV
CHRG
5V/DIV
VUSB
VSYS
BACKUP CHARGING
1V/DIV
100µs/DIV 3110 TA04c
ILI
2A/DIV
CHRG
5V/DIV
VUSB
VSYS
BACKUPCHARGING
DISCONNECT
USB Connect Transition USB Disconnect Transition
LTC3110
29
Rev C
For more information www.analog.com
TYPICAL APPLICATIONS
Autonomous Backup and Recharge Application with Input Isolation Switch
L1
2.2µH
SW2
LTC3110
SVSYS VSYS
CSYS
150µF
CMAIN
47µF
BACK-UP
3.2V
CCAP
1µF
C1
100F
C2
100F
R1
1910k
R2
536k
R4
681k
R3
1910k
RPROG
3.01k
R6
215k
R5
931k
R8
4.53k
R7
9.31k
ROFF
3.3k
RSVSYS
51.1Ω
M1
IRLML6402
1.5A
VMAIN
CHARGING
3.6V ±4%
1000k 1000k
3110 TA08
CAPOK
CAPLOW
1.2V
CHRG
1.8V
2.5V
3.6V/3.21V
SW1VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
SYSTEM
DC/DC
REGULATORS
MAIN
STEP-DOWN
DC/DC
FB
12V BUS
CSVSYS
220nF
CCMPIN
0.1µF
IL
1A/DIV
1V/DIV
CHRGB
2V/DIV
500µs/DIV
CHARGE SLEEP BACKUP
3110 TA06b
0A
VMAIN
VSYS
0V
0V
LTC3110
30
Rev C
For more information www.analog.com
TYPICAL APPLICATIONS
Lead Acid Battery Backup/Recharge Application
L1
1.5µH
SW2
LTC3110
SVSYS VSYS
CSYS
150µF
CCAP
1µF
47µF
CMID1
1nF
CMID2
1nF
12V
M1
IRLML64023.6V
R1
976k
ROFF
10k
R2
316k
R7
9.31k
R8
4.53k
RPROG
6.04k
R6
226k
R5
976k
1000k
3110 TA05
1000k
1.2V
1.8V
2.5V
3.21V/
3.6V
END OF CHRG
BATTLOW
SW1VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
SYSTEM
DC/DC
REGULATORS
R3
1910k
BATT
4V 2.5Ah
R4
604k
+
3.3V LDO OR
BUCK
REGULATOR
CCMPIN
0.1µF
LTC3110
31
Rev C
For more information www.analog.com
TYPICAL APPLICATIONS
NiMH Battery Backup/Recharge Application
LTC3110
CSYS
47µF
VSYS
3.25V
2A
CMID2
1nF
CMID1
1nF
CCAP
1µF
R3
1910k
NiMH
1.2V
3700mAh
×3
R4
604k
RPROG
12.4k
RFAST
8.06k
R5
976k
R6
221k 1000k
3110 TA06
VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
+
µC
L1
1.5µH
SW2 SVSYS VSYS
CSVSYS
220nF RSVSYS
51.1Ω
SW1
DIR
RUN
FASTCHRG
FBVCAP
ADIN
RTEMP
BATTLOW
VCC
VSYS
SUPERVISOR
NOTE ON DIGITAL CONTROL SIGNALS IN NiMH BACKUP/RECHARGE APPLICATION:
CHARGING IS INITIATED BY PULLING DIR = HIGH AND FBVCAP = LOW.
CHARGING IS TERMINATED BY PULLING DIR = HIGH AND FBVCAP = HIGH (FBVCAP MUST BE ≥ 1.2V).
SYSTEM BACK-UP IS INITIATED BY FORCING FBVCAP = LOW, WAITING 5µs, THEN FORCING DIR = LOW.
GENERAL SAFETY NOTE: CHARGING MUST BE TERMINATED IF THE BATTERY VOLTAGE
OR CHARGE TIME HAVE REACHED THEIR MAXIMUM VALUES OR IF THE BATTERY
TEMPERATURE IS ABOVE OR BELOW THE SAVE OPERATING REGION OF THE BATTERY,
SEE DATA SHEET OF THE BATTERY.
THE THERMISTOR, USED FOR MEASURING THE TEMPERATURE, MUST HAVE GOOD
THERMAL CONNECTION TO THE BATTERY PACK.
CCMPIN
0.1µF
LTC3110
32
Rev C
For more information www.analog.com
24h/7d Active Solar Powered Sensor/Transmitter Supply
Charging StatesCharging with Solar Current and 24/7 Backup
L1
2.2µH
SW2
LTC3110
SVSYS VSYS
CSYS1
47µF
CSYS2
4700µF
<30mΩ
CSYS3
4700µF
<30mΩ
CCAP
47µF
VSOLAR
ISOLAR
Q1
PBSS302
D1 SCHOTTKY
OPTIONAL
C1
100F
C2
100F
R1
1910k
R11
348Ω
R2
511k RPROG
3.01k
R6
221k
R7
953k
R8
422k
R9
1000k
R5
976k
3110 TA09
TRANSMITTER
GSM
DISPLAY
SENSOR
MICRO CONTROLLER
END OF
CHARGE CAPLOW
HIGH
BACKUP
POWER
MODE
SW1VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
R10
1000k
CSVSYS
220nF RSVSYS
51.1Ω
R3
1910k
R4
523k
S0
S1
S2
PFO
RST
GND
VCC
LTC2935-2
2A
PULSE
VSYS = 3.25V LOW RIPPLE HIGH BACKUP POWER MODE, MODE = HIGH
3.42V/3.58V SOLAR CHARGING, MODE = LOW
D1
SOLAR CELL
MODULE
6V, 150mA
~12 CELLS
PRIMARY
BATTERY
LITH 3V, 1Ah
OPTIONAL
SUPERCAPS
M1
2N7002
M2
2N7002
+
–
ISYS
CCMPIN
0.1µF
TYPICAL APPLICATIONS
IVCAP
1A/DIV
0A
VSOLAR
5V/DIV
0V
ISOLAR
100mA/DIV
0A
VSYS
AC COUPLED
100mV/DIV
5ms/DIV
3110 TA09C
CHARGING
VCAP = 4V
PRE
CHARGING
MODE = LOW
I
SYS
= 0.5mA
DAY 1
DAY 2
DAY 3
DAY 4
8h/DIV
V
CAP
2V/DIV
V
SYS
2V/DIV
I
SOLAR
20mA/DIV
3110 TA09b
CHARGING WITH SOLAR CURRENT AND 24/7 BACKUP:
IF DAYLIGHT IS PRESENT, THE SUPERCAPACITORS ARE CHARGED UP WITH THE OUTPUT
CURRENT OF THE SOLAR CELLS. WHEN DAYLIGHT IS NOT PRESENT, THE SUPERCAPS
PARTIALLY DISCHARGE AND PROVIDE THE BACKUP POWER TO MAINTAIN VSYS.
HIGH BACKUP POWER MODE (NO WAVEFORM): IF MODE = HIGH AND WITH THE
SUPERCAPACITORS CHARGED, THE APPLICATION CAN PROVIDE THE VSYS BACKUP VOLTAGE
WITH LOW RIPPLE AND FULL OUTPUT CURRENT CAPABILITIES. MODE = HIGH STOPS FURTHER
CHARGING.
CHARGING STATES:
IF MODE = LOW: THE VSYS VOLTAGE IS FED WITH CURRENT FROM THE SOLAR MODULE OR
IS REGULATED FROM THE LTC3110 IN BURST MODE IF SUNLIGHT IS MISSING. IF SUNLIGHT
IS PRESENT, VSYS IS REGULATED WITH A TWO POINT VOLTAGE REGULATION DEFINED BY DIR
RISING AND DIR FALLING THRESHOLDS.
THE APPLICATION HAS THREE STATES OF OPERATION:
1. CSYS PRE-CHARGING STATE: THE SOLAR PANEL OUTPUT CURRENT PRE-CHARGES THE
CAPACITOR CSYS UNTIL THE DIR VOLTAGE RISES ABOVE THE DIR RISING THRESHOLD AND
THE SUPERCAPACITOR CHARGING STATE IS ENTERED.
2. SUPERCAPACITOR CHARGING STATE: THE LTC3110 CHARGES THE SUPERCAPACITORS BY
DRAWING CURRENT FROM CAPACITOR CSYS UNTIL THE VSYS VOLTAGE FALLS BELOW THE
DIR FALLING THRESHOLD AND THE VSYS PRE-CHARGING STATE IS RE-ENTERED.
THE LTC3110 TOGGLES BETWEEN THE PRE-CHARGING STATE AND THE CHARGING STATE
UNTIL FBVCAP IS ABOVE THE FBVCAP RISING THRESHOLD AND THE CHARGE SLEEP STATE IS
ENTERED.
3. CHARGE SLEEP STATE (NO WAVEFORM): VCAP IS FULLY CHARGED AND FBVCAP IS ABOVE THE
FBVCAP FALLING THRESHOLD WHILE THE VSYS VOLTAGE IS REGULATED WITH LTC3110’s
BURST MODE BACKUP OPERATION. IN THE CHARGE SLEEP STATE, THE SOLAR MODULE
IS ISOLATED FROM VSYS.
STARTUP WITH DISCHARGED SUPERCAPS:
THE V
SYS
VOLTAGE IS MONITORED WITH THE LTC2935-2 SUPERVISOR ENABLING THE LTC3110
ONLY AT A VOLTAGE ABOVE 2.7V.
IF POWERED FROM HIGH IMPEDANCE SOURCES (E. G. SOLAR CELLS). VSYS MUST BE
INITIALLY HIGH ENOUGH TO SKIP THE SOFT START FUNCTION OF THE LTC3110, SEE SOFT
START (BACKUP MODE) IN THE OPERATION SECTION.
NOTES: THE REQUIRED PANEL SIZE AND THE NUMBER OF SOLAR CELLS IN SERIES OR IN
PARALLEL STRONGLY DEPENDS ON THE LOCAL SUNLIGHT CONDITIONS. VSOLAR MUST BE
ONE VBE HIGHER THAN VSYS (3.58V + 0.7V = 4.3V) IN THE LOWEST LIGHT CONDITION TO
DELIVER SOLAR CURRENT.
TO PREVENT OVERVOLTAGING OF VSYS, THE IVSYS AVERAGE CURRENT LIMIT MUST BE AT LEAST
FOUR TIMES LARGER THAN THE MAXIMUM SOLAR CURRENT (IVSYS_PROG > 4 × ISOLAR_MAX).
ALTERNATIVELY, OUTPUT CHRG CAN BE ADDITIONALLY CONNECTED TO THE BASE OF Q1 TO
ISOLATE THE SOLAR PANEL DURING CHARGING.
THE ABSOLUTE MAXIMUM OF V
SOLAR
IS DEFINED FROM THE V
CEO
VALUE OF Q1 (E.G. 20V)
WHICH ALLOWS THE CONNECTION OF MODULES WITH OPEN CIRCUIT VOLTAGES OF VOC > 5.25V.
OPTIONALLY A PRIMARY BATTERY CAN BE ADDED AS RESERVE TO COVER POOR LIGHT
CONDITIONS.
EXAMPLE SOLAR MODULE MANUFACTURERS:
SHARP, PANASONIC, POWERFILM
LTC3110
33
Rev C
For more information www.analog.com
PACKAGE DESCRIPTION
FE24 (AA) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12
14 13
7.70 – 7.90*
(.303 – .311)
3.25
(.128)
2.74
(.108)
2021222324 19 18 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.25
(.128)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad Variation AA
LTC3110
34
Rev C
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ±0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ±0.05
(4 SIDES)
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
LTC3110
35
Rev C
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 03/16 Add H-grade option.
Clarified conditions and Note 9 for Input Current Limit.
Changed axis labels VMID Buffer Current, Backup Time, Charge Balancer curves.
Enhanced 1.8V/300mA output circuit.
2, 4
4
8, 9
27
B 11/16 Changed reference page number in Preventing VCAP Overcharge Failure section 15
C 8/18 Changed capacitor value 19
LTC3110
36
Rev C
For more information www.analog.com
ANALOG DEVICES, INC. 2015-2018
D17165-0-7/18(C)
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
Autonomous Backup and Recharge Application (3.6V Nominal, 3.2V Backup Voltage)
LTC3110
CSYS
47µF
3.6V ±4%, 2A NOMINAL FROM MAIN DC/DC
3.21V, 1.5A BACKUP
CCAP
1µF
C1
10F
C2
10F
R1
1910k
R2
681k
R3
1910k
R4
715k
RPROG
6.04k
R6
200k
1000k 1000k 1000k
R5
1020k
R7
280k
3110 TA07
VCAP
FBVCAP
CMPIN
MODE
RUN
PGND
VMID
RSEN
PROG
FB
CHRG
CAPOK
CMPOUT
DIR
SGND
1.2V
CHRG
CAPOK
CAPLOW
1.8V
2.5V
3.6V/3.21V
SYSTEM
DC/DC
REGULATORS
L1
2.2µH
SW2 SVSYS VSYS
CSVSYS
220nF RSVSYS
51.1Ω
SW1
12V
BUS
MAIN STEP-DOWN DC/DC
2A + ISYS = MINIMUM REQUIREMENT
FB
NOTE: THE DRIVING CAPABILITY OF THE MAIN DC/DC SHOULD EXCEED THE MAXIMUM
REVERSE CURRENT LIMIT OF THE LTC3110 PLUS ISYS,THE LOAD CURRENT DEMANDED
FROM THE SYSTEM DC/DC REGULATORS CONNECTED AT VSYS.
CCMPIN
0.1µF
PART NUMBER DESCRIPTION COMMENTS
LTC4040 2.5A Battery Backup Power Manager Step-Up Backup Supply and Step-Down Battery Charger, 6.5A Switches for 2.5A,
Automatic Seamless Switchover to Backup Mode Backup from 3.2V Battery
LTC3226 2-Cell Supercapacitor Charger with Backup
PowerPath
™
Controller
1×/2× Multimode Charge Pump Supercapacitor Charger with Automatic Cell
Balancing. Internal 2A LDO Backup Supply (CPO to VOUT). Automatic Main/Backup
Switchover, 3mm × 3mm QFN-16 Package
LTC3625/LTC3625-1 1A High Efficiency 2-Cell Supercapacitor
Charger with Automatic Cell Balancing
High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors,
Automatic Cell Balancing. Programmable Charging Current Up to 500mA (Single
Inductor), 1A (Dual Inductor), 3mm × 4mm DFN-12 Package
LTC3128 3A Monolithic Buck-Boost Supercapacitor
Charger and Balancer with Accurate Input
Current Limit
±2% Accurate Average Input Current Limit Programmable to 3A, Active Charge
Balancing, Charges 1 or 2 Capacitors, VIN: 1.73V to 5.5V, VOUT: 1.8V to 5.5V
LTC3350 High Current Supercapacitor Backup
Controller and System Monitor
Synchronous Step-Down CC/CV Charging up to Four Series Supercapacitors
VIN: 4.5V to 35V, 14-Bit ADC for Monitoring System Voltages/Currents, Capacitance
and ESR, Internal Active Balancers, 38-Lead 5mm × 7mm QFN Package
LTC4425 Linear SuperCap Charger with Current-
Limited Ideal Diode and V/I Monitor
Constant-Current/Constant-Voltage Linear Charger for 2-cell Series Supercapacitor
Stack, 2A Charge Current, Auto Cell Balancing, 20μA Quiescent Current
LTC3127 1A Buck-Boost DC/DC Converter with
Programmable Input Current Limit
Programmable (0.2A to 1A) ±4% Accurate Average Input Current Limit,
1.8V to 5.5V (Input) and 1.8V to 5.25V (Output) Voltage Range
LTC3125 1.2A IOUT, 1.6MHz, Synchronous Boost DC/DC
Converter With Adjustable Input Current Limit
94% Efficiency, VIN: 1.8V to 5.5V, VOUT(MAX) = 5.25V, IQ = 15μA,
ISD < 1μA, 2mm × 3mm DFN-8 Package
LTC3441/LTC3441-2/
LTC3441-3
1.2A IOUT, 2MHz, Synchronous Buck-Boost
DC/DC Converter
95% Efficiency, VIN: 2.4V to 5.5V, VOUT : 2.4V to 5.25V, IQ = 50µA,
ISD < 1µA, 3mm × 4mm DFN-12 Package
LTC3113 3A Low Noise Buck-Boost DC/DC Converter 96% Efficiency, VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 40µA,
ISD < 1µA, 4mm × 5mm DFN-16 and 20-Lead TSSOP Packages
LTC3355 20V 1A Buck DC/DC with Integrated SCAP
Charger and Backup Regulator
VIN Voltage Range: 3V to 20V, VOUT Voltage Range: 2.7V to 5V, 1A Current
Mode Buck Main Regulator, 5A Boost Backup Regulator Powered from Single
Supercapacitor Down to 0.5V, Overvoltage Protection
LTC3643 2A Bidirectional Power Backup Supply Bidirectional Synchronous Boost Capacitor Charger/Buck Regulator for System
Backup, Wide VIN Voltage Range: 3V to 17V, Up to 40V Capacitor Voltage, 2A
Maximum CAP Charge Current, Low Profile 24-Lead 3mm × 5mm QFN Package