TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL FEATURES 1 * * * * * * * * * * * * * Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transmitter In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With VCC = 3.3 V Up to 48-MHz Clock Rate for up to 3-Mbaud Operation with VCC = 3.3 V (ZQS Package Only, Divisor = 1) Up to 40-MHz Clock Rate for up to 2.5-Mbaud Operation with VCC = 3.3 V (ZQS Package Only, Divisor 2) Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC = 2.5 V In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 -1) and Generates an Internal 16x Clock * * * * * * * * * * * * * Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream 5-V, 3.3-V, and 2.5-V Operation Independent Receiver Clock Input Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled Fully Programmable Serial Interface Characteristics: - 5-, 6-, 7-, or 8-Bit Characters - Even-, Odd-, or No-Parity Bit Generation and Detection - 1-, 1 -, or 2-Stop Bit Generation - Baud Generation (dc to 1 Mbit/s) False-Start Bit Detection Complete Status Reporting Capabilities 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus Line Break Generation and Detection Internal Diagnostic Capabilities: - Loopback Controls for Communications Link Fault Isolation - Break, Parity, Overrun, and Framing Error Simulation Fully Prioritized Interrupt System Controls Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) Available in 48-Pin PT, 48-Pin PFB, 32-Pin RHB, and 24-Pin ZQS Packages DESCRIPTION/ORDERING INFORMATION The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS input signals. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2008, Texas Instruments Incorporated TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16x reference clock for the internal transmitter logic. Provisions are included to use this 16x clock for the receiver logic. The ACE accommodates up to a 1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is 6.7 s (start bit, 8 data bits, stop bit). Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to TXRDY and RXRDY, which provide signaling to a DMA controller. PT/PFB PACKAGE (TOP VIEW) NC D4 D3 D2 D1 D0 VCC RI DCD DSR CTS NC CTS MR DTR RTS INTRPT A0 A1 A2 RHB PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 7 31 30 8 29 9 28 10 27 11 26 12 25 NC MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 NC 24 23 22 21 20 19 18 17 DSR DCD RI VCC D0 D1 D2 D3 25 16 26 15 27 14 28 13 29 12 30 11 10 31 NC NC RD1 VSS WR1 XOUT XIN NC 9 32 1 2 3 4 5 6 7 8 D4 NC D5 D6 D7 SIN SOUT CS2 NC D5 D6 D7 RCLK NC SIN SOUT CS0 CS1 CS2 BAUDOUT NC XIN XOUT WR1 WR2 VSS RD1 RD2 NC DDIS TXRDY ADS 13 14 15 16 17 18 19 20 21 22 23 24 NC - No internal connection NC - No internal connection The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This is accomplished by eliminating some signals that are not required for some applications. These include the CS0, CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUT output signals. There is an internal connection between BAUDOUT and RCLK. All of the functionality of the TL16C550D is maintained in the RHB package. TERMINAL ASSIGNMENTS ZQS PACKAGE (24-Ball ZQS Package) (continued) (TOP VIEW) 1 2 3 4 (24-Ball ZQS Package) 5 1 2 3 4 5 A D5 D4 D2 D0 VCC B D7 D3 D1 MR C SIN SOUT D6 CTS RTS D CS2 WR1 RD1 INTRPT A0 E XIN XOUT VSS A2 A1 A B C D E TERMINAL ASSIGNMENTS 2 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 The TL16C550D is being made available in a reduced pin count package, the 24-pin ZQS package. This is accomplished by eliminating some signals that are not required for some applications. These include the CS0, CS1, ADS, RD2, WR2, DSR, RI, DCD, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, DTR, and BAUDOUT output signals. There is an internal connection between BAUDOUT and RCLK. Most of the functionality of the TL16C550D is maintained in the ZQS package, except that which involves the eliminated signals. DETAILED DESCRIPTION Autoflow Control (see Figure 1) Autoflow control comprises auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency. Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example Auto-RTS (see Figure 1) Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space. Auto-CTS (see Figure 1) The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 3 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Enabling Autoflow Control and Auto-CTS Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control register must be cleared (this assumes that a control signal is driving CTS). Auto-CTS and Auto-RTS Functional Timing A. When CTS is low, the transmitter keeps sending serial data out. B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. C. When CTS goes from high to low, the transmitter begins sending data again. Figure 2. CTS Functional Timing Waveforms The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 3 and Figure 4. A. N = RCV FIFO trigger level (1, 4, or 8 bytes) B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section. Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes Byte 18 A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte. B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than one byte of space available. C. When the receive FIFO is full, the first receive buffer register read reasserts RTS. Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes 4 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM (For PT and PFB Packages) Internal Data Bus 4 -2 47-43 D(7- 0) Data Bus Buffer 8 S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register A1 A2 CS0 CS1 CS2 ADS MR RD1 RD2 WR1 WR2 DDIS TXRDY XIN SIN 5 Receiver Timing and Control Line Control Register A0 7 RCLK 32 27 26 Divisor Latch (LS) 9 Divisor Latch (MS) Baud Generator 12 10 11 24 35 19 20 Transmitter Timing and Control Line Status Register Select and Control Logic Transmitter FIFO Transmitter Holding Register 16 17 8 S e l e c t 8 Transmitter Shift Register BAUDOUT Autoflow Control (AFE) 8 Modem Control Register 23 14 8 38 33 Modem Status Register 8 Modem Control Logic 39 40 41 34 VSS SOUT 22 XOUT 15 29 RXRDY VCC RTS 28 42 18 CTS DTR DSR DCD RI OUT1 31 Power Supply Interrupt Enable Register Interrupt Identification Register 8 Interrupt Control Logic OUT2 30 INTRPT 8 FIFO Control Register Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 5 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM (For RHB Package) Internal Data Bus 5 -3 32-29 D(7- 0) 8 S e l e c t Data Bus Buffer Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register Receiver Timing and Control Line Control Register A0 A1 A2 MR RD1 WR1 XIN 21 18 Divisor Latch (LS) 17 8 23 14 Transmitter Timing and Control Select and Control Logic Transmitter FIFO Transmitter Holding Register 12 8 Modem Control Register 10 S e l e c t 8 Transmitter Shift Register Autoflow Control (AFE) 7 SOUT 8 24 22 Modem Status Register Modem Control Logic 8 25 26 27 VSS RTS Baud Generator Line Status Register XOUT 11 VCC SIN 19 Divisor Latch (MS) CS2 6 CTS DTR DSR DCD RI 28 13 Power Supply Interrupt Enable Register Interrupt Identification Register 8 Interrupt Control Logic 20 INTRPT 8 FIFO Control Register 6 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM (For ZQS Package) Internal Data Bus 5 -3 32-29 D(7- 0) Data Bus Buffer 8 S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register Receiver Timing and Control Line Control Register A0 A1 A2 MR RD1 WR1 XIN E5 Divisor Latch (LS) E4 D1 VSS RTS Baud Generator B5 D3 Transmitter Timing and Control Line Status Register Select and Control Logic Transmitter FIFO Transmitter Holding Register D2 8 Modem Control Register E1 XOUT E2 VCC C5 SIN D5 Divisor Latch (MS) CS2 C1 S e l e c t 8 Transmitter Shift Register Autoflow Control (AFE) C2 SOUT 8 C4 Modem Status Register 8 CTS Modem Control Logic A5 E3 Power Supply Interrupt Enable Register Interrupt Identification Register 8 Interrupt Control Logic D4 INTRPT 8 FIFO Control Register Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 7 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES) TERMINAL NAME NO. I/O DESCRIPTION A0 A1 A2 28 27 26 I Register select. A0-A2 are used during read and write operations to select the ACE register to read from or write to. See Table 1 for register addresses, and see the ADS description. ADS 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal select logic directly; when ADS is high, the register select and chip select signals are held at the logic levels they were in when the low-to-high transition of ADS occurred. BAUDOUT 12 O Baud out. BAUDOUT is a 16x clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK. CS0 CS1 CS2 9 10 11 I Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any of these inputs are inactive, the ACE remains inactive (see the ADS description). Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. CTS 38 I D0 D1 D2 D3 D4 D5 D6 D7 43 44 45 46 47 2 3 4 I/O DCD 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DCD) of the modem status register indicates that DCD has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD changes levels, an interrupt is generated. DDIS 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an external transceiver. I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit. O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. DSR DTR 39 33 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status information between the ACE and the CPU. INTRPT 30 MR 35 NC 1,6,13, 21, 25, 36, 37, 48 I No connection OUT1 OUT2 34 31 O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. RCLK 5 I Receiver clock. RCLK is the 16x baud rate clock for the receiver section of the ACE. RD1 RD2 19 20 I Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input must be tied to its inactive level (i.e., RD2 tied low or RD1 tied high). 8 Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals (see Table 2). Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES) (continued) TERMINAL NAME RI RTS NO. 41 32 I/O DESCRIPTION I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic. RXRDY 29 O Receiver ready. Receiver direct memory access (DMA) signaling is available with RXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY goes active (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high). SIN 7 I Serial data input. SIN is serial data input from a connected communications device. SOUT 8 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set to the marking (high) level as a result of master reset. O Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. TXRDY 23 VCC 42 2.25-V to 5.5-V power supply voltage VSS 18 Supply common WR1 WR2 16 17 I XIN XOUT 14 15 I/O Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input must be tied to its inactive level (i.e., WR2 tied low or WR1 tied high). External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal). Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 9 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (FOR RHB PACKAGE) TERMINAL NAME NO. I/O DESCRIPTION A0 A1 A2 19 18 17 I Register select. A0-A2 are used during read and write operations to select the ACE register to read from or write to. See Table 1 for register addresses, and see the ADS description. CS2 8 I Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any of these inputs are inactive, the ACE remains inactive (see the ADS description). Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. CTS 24 I D0 D1 D2 D3 D4 D5 D6 D7 29 30 31 32 1 3 4 5 I/O DCD 26 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DCD) of the modem status register indicates that DCD has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD changes levels, an interrupt is generated. DSR 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. DTR 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit. O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status information between the ACE and the CPU. INTRPT 30 MR 35 NC 2,9, 15, 16, I No connection RD1 14 I Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RI 27 Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals (see Table 2). RTS 21 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic. SIN 6 I Serial data input. SIN is serial data input from a connected communications device. SOUT 7 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set to the marking (high) level as a result of master reset. VCC 28 2.25-V to 5.5-V power supply voltage VSS 13 Supply common WR1 12 10 I Submit Documentation Feedback Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 TERMINAL FUNCTIONS (FOR RHB PACKAGE) (continued) TERMINAL NAME NO. XIN XOUT 10 11 I/O DESCRIPTION I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal). Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 11 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (FOR ZQS PACKAGE) TERMINAL I/O DESCRIPTION NAME NO. A0 A1 A2 D5 E5 E4 I Register select. A0-A2 are used during read and write operations to select the ACE register to read from or write to. See Table 1 for register addresses, and see the ADS description. CS2 D1 I Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remains inactive. Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. CTS C4 I D0 D1 D2 D3 D4 D5 D6 D7 A4 B4 A3 B3 A2 A1 C3 B1 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status information between the ACE and the CPU. O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. INTRPT D4 MR B5 RD1 D3 Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals (see Table 2). I Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. RTS C5 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic. SIN C1 I Serial data input. SIN is serial data input from a connected communications device. SOUT C2 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set to the marking (high) level as a result of master reset. VCC A5 2.25-V to 5.5-V power supply voltage VSS E3 Supply common, ground WR1 D2 I XIN XOUT E1 E2 I/O 12 Submit Documentation Feedback Write input. When WR1 is active (low) and while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal). Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) -0.5 7 V VI Input voltage range at any input -0.5 7 V VO Output voltage range V TA Operating free-air temperature range Tstg Storage temperature range Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds (1) (2) UNIT -0.5 7 TL16C550D 0 70 TL16C550DI -40 85 -65 150 C 260 C PT/PFB packages C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values with respect to VSS. RECOMMENDED OPERATING CONDITIONS 2.5 V 10% VCC Supply voltage VI Input voltage VIH MIN NOM MAX UNIT 2.25 2.5 2.75 V 0 VCC V High-level input voltage 1.8 2.75 V VIL Low-level input voltage -0.3 0.6 V VO Output voltage 0 VCC IOH High-level output current (all outputs) 1 mA IOL Low-level output current (all outputs) 2 mA 16 MHz UNIT Oscillator/clock speed V 3.3 V 10% MIN NOM MAX 3 3.3 3.6 V VCC V VCC Supply voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage VO Output voltage VCC V IOH High-level output current (all outputs) 1.8 mA IOL Low-level output current (all outputs) 3.2 mA Oscillator/clock speed 20 MHz Oscillator/clock speed (ZQS package only) 48 MHz 0 0.7 x VCC V 0.3 x VCC 0 Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback V 13 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com 5 V 10% VCC Supply voltage VI Input voltage MIN NOM 4.5 5 0 Except XIN MAX UNIT 5.5 V VCC V 2 VIH High-level input voltage VIL Low-level input voltage VO Output voltage IOH High-level output current (all outputs) 4 mA IOL Low-level output current (all outputs) 4 mA 24 MHz MAX UNIT XIN V 0.7 x VCC Except XIN 0.8 0.3 x VCC XIN 0 VCC Oscillator/clock speed V V ELECTRICAL CHARACTERISTICS 2.5 V Nominal over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (2) VOH High-level output voltage VOL Low-level output voltage (2) IOL = 2 mA II Input current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, All other terminals floating High-impedance-state output current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, IOZ IOH = -1 mA Supply current TYP (1) 1.8 V 0.5 V 10 A 20 A 8 mA 15 20 pF 20 30 pF 6 10 pF 10 10 pF Chip selected in write mode or chip deselect VCC = 3.6 V, ICC MIN TA = 25C, SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs are 0.8 V, XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kbit/s Ci(CLK) Clock input capacitance Co(CLK) Clock output capacitance Ci Input capacitance Co Output capacitance (1) (2) 14 VCC = 0, f = 1 MHz, All other terminals grounded VSS = 0, TA = 25C All typical values are at VCC = 2.5 V and TA = 25C. These parameters apply for all outputs except XOUT. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 3.3 V Nominal over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (2) VOH High-level output voltage IOH = -1 mA VOL Low-level output voltage (2) IOL = 2 mA II Input current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, All other terminals floating High-impedance-state output current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, IOZ TYP (1) UNIT V 0.5 V 10 A 20 A 8 mA 15 20 pF 20 30 pF 6 10 pF 10 20 pF TYP (1) MAX Chip selected in write mode or chip deselect TA = 25C, SIN, DSR, DCD, CTS, and RI at 2 V, Supply current MAX 2.4 VCC = 3.6 V, ICC MIN All other inputs are 0.8 V, XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kbit/s Ci(CLK) Clock input capacitance Co(CLK) Clock output capacitance Ci Input capacitance Co Output capacitance (1) (2) VCC = 0, f = 1 MHz, All other terminals grounded VSS = 0, TA = 25C All typical values are at VCC = 3.3 V and TA = 25C. These parameters apply for all outputs except XOUT. 5 V Nominal over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (2) VOH High-level output voltage IOH = -1 mA VOL Low-level output voltage (2) IOL = 2 mA II Input current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, All other terminals floating High-impedance-state output current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, IOZ Supply current 4.0 UNIT V 0.4 V 10 A 20 A 10 mA 15 20 pF 20 30 pF 6 10 pF 10 20 pF Chip selected in write mode or chip deselect VCC = 3.6 V, ICC MIN TA = 25C, SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs are 0.8 V, XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kbit/s Ci(CLK) Clock input capacitance Co(CLK) Clock output capacitance Ci Input capacitance Co Output capacitance (1) (2) VCC = 0, f = 1 MHz, All other terminals grounded VSS = 0, TA = 25C All typical values are at VCC = 5 V and TA = 25C. These parameters apply for all outputs except XOUT. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 15 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com SYSTEM TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns tw1 tw2 Pulse duration, clock high tXH Pulse duration, clock low tXL f = 16 MHz Max, VCC = 2.5 V, See Figure 5 25 f = 20 MHz Max, VCC = 3.3 V, See Figure 5 20 f = 24 MHz Max, VCC = 5 V, See Figure 5 18 f = 48 MHz Max, VCC = 3.3 V, See Figure 5 (ZQS package only) 8 f = 16 MHz Max, VCC = 2.5 V, See Figure 5 25 f = 20 MHz Max, VCC = 3.3 V, See Figure 5 20 f = 24 MHz Max, VCC = 5 V, See Figure 5 18 f = 48 MHz Max, VCC = 3.3 V, See Figure 5 (ZQS package only) 8 Pulse duration, ADS low 9 ns tw6 Pulse duration, WR tWR See Figure 6 40 ns tw7 Pulse duration, RD tRD See Figure 7 40 ns tw8 Pulse duration, MR tMR 1 s tsu1 Setup time, address valid before ADS tAS tsu2 Setup time, CS valid before ADS tCS 8 ns tsu3 Setup time, data valid before WR1 or WR2 tDS See Figure 6 15 ns tsu4 Setup time, CTS before midpoint of stop bit See Figure 17 10 ns th1 Hold time, address low after ADS tAH th2 Hold time, CS valid after ADS tCH 0 ns th3 Hold time, CS valid after WR1 or WR2 tWCS th4 Hold time, address valid after WR1 or WR2 tWA See Figure 6 10 ns th5 Hold time, data valid after WR1 or WR2 tDH See Figure 6 5 ns th6 Hold time, CS valid after RD1 or RD2 tRCS See Figure 7 10 ns th7 Hold time, address valid after RD1 or RD2 tRA See Figure 6 20 ns td4 Delay time, CS valid before WR1 or WR2 (1) tCSW td5 Delay time, address valid before WR1 or WR2 (1) tAW See Figure 6 7 ns td6 Delay time, write cycle, WR1 or WR2 to ADS See Figure 6 40 ns td7 Delay time, CS valid to RD1 or RD2 (1) td8 Delay time, address valid to RD1 or RD2 (1) See Figure 7 7 ns td9 Delay time, read cycle, RD1 or RD2 to ADS tRC See Figure 7 40 td10 Delay time, RD1 or RD2 to data valid tRVD CL = 75 pF, Figure 7 45 ns td11 Delay time, RD1 or RD2 to floating data tHZ CL = 75 pF, See Figure 7 20 ns 16 tWC tCSR tAR See Figure 6 and Figure 7 ns tw5 (1) tADS ns See Figure 6 and Figure 7 See Figure 6 and Figure 7 ns Only applies when ADS is low. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 SYSTEM SWITCHING CHARACTERISTICS (1) over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL tdis(R) Disable time, RD1 or RD2 to DDIS (1) tRDD TEST CONDITIONS MIN MAX UNIT CL = 75 pF, Figure 7 20 ns Charge and discharge are determined by VOL, VOH, and external loading. BAUD GENERATOR SWITCHING CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF (For PT and PFB packages only) PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT tw3 Pulse duration, BADOUT low tLW tw4 Pulse duration, BADOUT high tHW f = 24 MHz, CLK / 2, VCC = 5 V, See Figure 5 td1 Delay time, XIN to BADOUT tBLD See Figure 5 45 ns td2 Delay time, XIN to BADOUT tBHD See Figure 5 45 ns 35 ns RECEIVER SWITCHING CHARACTERISTICS (1) over recommended ranges of supply voltage and operating free-air temperature PARAMETER td12 ALT. SYMBOL Delay time, RCLK to sample TEST CONDITIONS tSCD See Figure 8 10 td13 Delay time, stop to set INTRPT or read RBR to lSI interrupt or stop to RXRDY tSINT See Figure 5, Figure 9, Figure 10, Figure 11, Figure 12 td14 Delay time, read RBR/LSR to reset INTRPT tRINT CL = 75 pF, See Figure 5, Figure 9, Figure 10, Figure 11, Figure 12 (1) MIN MAX UNIT ns RCL 1 K cycle 70 ns In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification register or line status register). TRANSMITTER SWITCHING CHARACTERISTICS (1) over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT td15 Delay time, initial write to transmit start tIRS See Figure 13 8 24 baudout cycles td16 Delay time, start to INTRPT tSTI See Figure 13 8 10 baudout cycles td17 Delay time, WR1 (WR THR) to reset INTRPT tHR CL = 75 pF, See Figure 13 50 ns td18 Delay time, initial write to INTRPT (THRE (1)) tSI See Figure 13 34 baudout cycles td19 Delay time, read IIR (2) to reset INTRPT (THRE (1)) tIR CL = 75 pF, See Figure 13 35 ns td20 Delay time, write to TXRDY inactive tWXI CL = 75 pF, See Figure 14 and Figure 15 35 ns td21 Delay time, start to TXRDY active tSXA CL = 75 pF, See Figure 14 and Figure 15 9 baudout cycles (1) (2) 16 THRE = transmitter holding register empty IIR = Interrupt identification register Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 17 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com MODEM CONTROL SWITCHING CHARACTERISTICS (1) over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT td22 Delay time, WR2 MCR to output tMDO See Figure 15 50 ns td23 Delay time, modem interrupt to set INTRPT tSIM See Figure 16 35 ns td24 Delay time, RD2 MSR to reset INTRPT tRIM See Figure 16 40 ns td25 Delay time, CTS low to SOUT See Figure 17 24 baudout cycles td26 Delay time, RCV threshold byte to RTS See Figure 18 2 baudout cycles td27 Delay time, read of last byte in receive FIFO to RTS See Figure 18 2 baudout cycles td28 Delay time, first data bit of 16th character to RTS See Figure 19 2 baudout cycles td29 Delay time, RBRRD low to RTS See Figure 19 2 baudout cycles (1) THRE = transmitter holding register empty PARAMETER MEASUREMENT INFORMATION Figure 5. Baud Generator Timing Waveforms (for PT and PFB Packages Only) 18 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) tw5 50% ADS (see Note A) 50% 50% tsu1 th1 A0 - A2 50% A 50% Valid Valid 50% tsu2 th2 CS0, CS1, CS2 (see Note B) 50% A 50% Valid Valid th3 tw6 td4 A th4 td5 WR1, WR2 (See Note B) td6 50% Active 50% tsu3 th5 Valid Data D7 - D0 A. Applicable only when ADS is low B. The ADS, CSO, CS1, and WR2 signals are applicable only to the PT and PFB packages. Figure 6. Write Cycle Timing Waveforms Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 19 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) tw5 50% ADS (see Note A) 50% 50% tsu1 th1 A0- A2 Valid 50% A 50% Valid 50% tsu2 th2 50% CS0, CS1, CS2 (see Note B) Valid A 50% Valid 50% th6 td7A tw7 th7A td8A td9 50% RD1, RD2 (see Note B) Active 50% tdis(R) DDIS (see Note B) tdis(R) 50% 50% td10 D7- D0 td11 Valid Data A. Applicable only when ADS is low B. The ADS, CSO, CS1, and WR2 signals are applicable only to the PT and PFB packages. Figure 7. Read Cycle Timing Waveforms 20 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) RCLK td12 8 CLKs Sample Clock TL16C450 Mode: SIN Start Data Bits 5- 8 Parity Stop Sample Clock INTRPT (data ready) 50% 50% 50% td13 INTRPT (RCV error) td14 50% 50% RD1, RD2 (read RBR) 50% RD1, RD2 (read LSR) 50% Active Active td14 A. The RD2 signal is applicable only to the PT and PFB packages. Figure 8. Receiver Timing Waveforms Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 21 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) (FIFO at or above trigger level) (FIFO below trigger level) A. For a time-out interrupt, td13 = 9 RCLKs. Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms (FIFO at or above trigger level) (FIFO below trigger level) (see Note B) (see Note A) (see Note A) A. The RD2 signal is applicable only to the PT and PFB packages. B. For a time-out interrupt, td13 = 9 RCLKs. Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms 22 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) RD1 (RD RBR) 50% Active (see Note B) SIN (first byte) Stop Sample Clock td13 (see Note C) td14 50% 50% RXRDY (see Note A) A. The RXRDY signal is applicable only to the PT and PFB packages. B. This is the reading of the last byte in the FIFO. C. For a time-out interrupt, td13 = 9 RCLKs. Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) RD1 (RD RBR) 50% Active (see Note B) SIN (first byte that reaches the trigger level) Sample Clock td13 (see s Note C) 50% RXRDY (see Note A) A. The RXRDY signal is applicable only to the PT and PFB packages. B. This is the reading of the last byte in the FIFO. C. For a time-out interrupt, td13 = 9 RCLKs. td14 50% Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1) Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 23 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 9 Figure 13. Transmitter Timing Waveforms (see Note A) A. The TXRDY signal is applicable only to the PT and PFB packages. Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) Byte 16 WR1 (WR THR) SOUT 50% Data Parity A. Start 50% td21 td20 TXRDY (see Note A) Stop 50% FIFO Full 50% The TXRDY signal is applicable only to the PT and PFB packages. Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1) 24 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) (see Note A) (see Note A) (see Note A) A. The OUT1, OUT2, RD2, and WR2 signals are applicable only to the PT and PFB packages. Figure 16. Modem Control Timing Waveforms Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms Figure 18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 25 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms 26 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 APPLICATION INFORMATION SOUT D7- D0 D7 - D0 MEMR or I/OR MEMW or I/ON INTR C P U B u s RESET A0 RD1 RTS WR1 DTR INTRPT DSR MR DCD A0 A1 A1 A2 SIN TL16C550D (ACE) EIA-232-D Drivers and Receivers CTS RI A2 ADS XIN WR2 L 3.072 MHz RD2 CS H CS2 XOUT CS1 BAUDOUT CS0 RCLK Figure 20. Basic TL16C550D Configuration (for PT and PFB Packages) SOUT D7- D0 D7 - D0 MEMR or I/OR MEMW or I/ON INTR C P U B u s RESET A0 RD1 RTS WR1 DTR INTRPT DSR MR DCD A0 A1 A1 A2 SIN TL16C550D (ACE) EIA-232-D Drivers and Receivers CTS RI A2 XIN 3.072 MHz CS CS2 XOUT Figure 21. Basic TL16C550D Configuration (for RHB Package) Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 27 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com SOUT D7- D0 D7 - D0 MEMR or I/OR MEMW or I/ON INTR C P U B u s SIN RTS RD1 EIA-232-D Drivers and Receivers WR1 INTRPT RESET MR A0 A0 A1 A1 A2 TL16C550D (ACE) CTS A2 XIN 3.072 MHz CS CS2 XOUT Figure 22. Basic TL16C550D Configuration (for ZQS Package) Receiver Disable WR WR1 TL16C550D (ACE) Microcomputer System Data Bus Data Bus 8-Bit Bus Transceiver D7- D0 DDIS Driver Disable Figure 23. Typical Interface for a High-Capacity Data Bus 28 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 TL16C550D XIN A16-A23 A16-A23 XOUT 14 Alternate Crystal Control 15 12 9 BAUDOUT CS0 Address Decoder CPU 10 11 RCLK CS1 CS2 DTR 24 ADS 35 RSI/ABT RTS 33 20 32 1 34 ADS OUT1 OUT2 MR 31 A0-A2 AD0-AD7 D0-D7 Buffer AD0-AD15 5 41 RI 40 PHI1 8 DCD PHI2 39 6 DSR CTS PHI1 ADS PHI2 RSTO RD 19 TCU 16 WR RD1 38 5 8 SOUT 2 WR1 7 3 SIN INTRPT 30 23 AD0-AD15 TXRDY 20 17 RD2 DDIS WR2 GND (VSS) RXRDY 18 22 7 29 42 1 EIA-232-D Connector VCC Figure 24. Typical TL16C550D Connection to a CPU (for PT and PFB Packages) Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 29 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TL16C550D XIN A16- A23 A16- A23 XOUT Address Decoder 8 10 Alternate Crystal Control 11 CS2 CPU DTR RTS 22 21 20 1 ADS 23 RSI/ABT A0- A2 AD0- AD7 D0- D7 Buffer AD0 - AD15 MR 27 RI 26 PHI1 DCD PHI2 25 DSR CTS PHI1 ADS PHI2 RSTO RD 14 TCU 12 WR RD1 24 8 6 5 7 SOUT 2 WR1 6 SIN INTRPT 3 20 AD0- AD15 GND (VSS) 13 28 VCC 7 1 EIA-232-D Connector Figure 25. Typical TL16C550D Connection to a CPU (for RHB Package) 30 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 TL16C550D XIN A16- A23 A16- A23 XOUT Address Decoder D1 E1 Alternate Crystal Control E2 CS2 CPU 20 RTS C5 1 ADS B5 RSI/ABT A0- A2 AD0- AD7 PHI1 D0- D7 Buffer AD0 - AD15 MR 8 PHI2 6 CTS PHI1 ADS PHI2 RSTO RD D3 TCU D2 WR RD1 C4 5 C2 SOUT 2 WR1 C1 3 SIN INTRPT D4 AD0- AD15 GND (VSS) E3 7 A5 VCC 1 EIA-232-D Connector Figure 26. Typical TL16C550D Connection to a CPU (for ZQS Package) Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 31 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PRINCIPLES OF OPERATION Table 1. Register Selection DLAB (1) (1) A2 A1 A0 0 L L L Receiver buffer (read), transmitter holding register (write) REGISTER 0 L L H Interrupt enable register X L H L Interrupt identification register (read only) X L H L FIFO control register (write) X L H H Line control register X H L L Modem control register X H L H Line status register X H H L Modem status register X H H H Scratch register 1 L L L Divisor latch (LSB) 1 L L H Divisor latch (MSB) The divisor latch access bit (DLAB) is the most significant bit (MSB) of the line control register. The DLAB signal is controlled by writing to this bit location (see Table 4). Table 2. ACE Reset Functions REGISTER/SIGNAL RESET CONTROL RESET STATE Interrupt enable register Master reset All bits cleared (0-3 forced and 4-7 permanent) Interrupt identification register Master reset Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4-5 are permanently cleared FIFO control register Master reset All bits cleared Line control register Master reset All bits cleared Modem control register Master reset All bits cleared (6-7 permanent) Line status register Master reset Bits 5 and 6 are set; all other bits are cleared Modem status register Master reset Bits 0-3 are cleared; bits 4-7 are input signals SOUT Master reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low Read IR/write THR/MR Low Read MSR/MR Low OUT2 Master reset High RTS Master reset High DTR Master reset High OUT1 Master reset High Scratch register Master reset No effect Divisor latch (LSB and MSB) registers Master reset No effect Receiver buffer register Master reset No effect Transmitter holding register Master reset No effect INTRPT (transmitter holding register empty) INTRPT (modem status changes) RCVR FIFO MR/FCR1 - FCR0/FCR0 All bits cleared XMIT FIFO MR/FCR2 - FCR0/FCR0 All bits cleared Accessible Registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. 32 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 Table 3. Summary of Accessible Registers REGISTER ADDRESS BIT NO. 0 (1) (2) 0DLAB = 0 0DLAB = 0 1DLAB = 0 2 2 3 4 5 6 7 0DLAB = 1 1DLAB = 1 Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register Interrupt Indent. Register (Read Only) FIFO Control Register (Write Only) Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Latch (MSB) RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM Data Bit 0 Enable Received Data Available Interrupt (ERBI) 0 if Interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready Data Ready (DR) Delta Clear to Send (CTS) Bit 0 Bit 0 Bit 8 Interrupt ID Bit 1 Receiver FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (DSR) Bit 1 Bit 1 Bit 9 Data Bit 0 (1) 1 Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBEI) 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit 2 Transmitter FIFO Reset Number of Stop Bits (STB) OUT1 Parity Error (PE) Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10 Interrupt ID Bit 3 (2) DMA Mode Select Parity Enable (PEN) OUT2 Framing Error (FE) Delta Data Carrier Detect (DCD) Bit 3 Bit 3 Bit 11 3 Data Bit 3 Data Bit 3 Enable Modem Status Interrupt (EDSSI) 4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Select (EPS) Loop Break Interrupt Clear to Send (CTS) Bit 4 Bit 4 Bit 12 5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity Autoflow Control Enable (AFE) Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 6 Data Bit 6 Data Bit 6 0 FIFOs Enabled (2) Receiver Trigger (LSB) Break Control 0 Transmitter Empty (TEMT) Ring Indicator (RI) Bit 6 Bit 6 Bit 14 7 Data Bit 7 Data Bit 7 0 Receiver Trigger (MSB) Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (2) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15 Bit 0 is the least significant bit. It is the first bit serially transmitted or received. These bits are always 0 in the TL16C450 mode. FIFO Control Register (FCR) The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling. * Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs. * Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self-clearing. * Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self-clearing. * Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1. * Bits 4 and 5: These two bits are reserved for future use. * Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4). Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 33 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Table 4. Receiver FIFO Trigger Level BIT 7 BIT 6 RECEIVER FIFO TRIGGER LEVEL (BYTES) 0 0 01 0 1 04 1 0 08 1 1 14 FIFO Interrupt Mode Operation When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows: 1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level. 2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, it is cleared when the FIFO drops below the trigger level. 3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04) interrupt. 4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It is cleared when the FIFO is empty. When the receiver FIFO and receiver interrupts are enabled: 1. FIFO time-out interrupt occurs if the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay). c. The most recent microprocessor read of the FIFO has occurred more than four continuous character times before. This causes a maximum character received command to interrupt an issued delay of 160 ms at a 300-baud rate with a 12-bit character. 2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to the baud rate). 3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads one character from the receiver FIFO. 4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or after the microprocessor reads the receiver FIFO. When the transmitter FIFO and THRE interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows: 1. The transmitter-holding-register-empty interrupt [IIR (3-0) = 2] occurs when the transmit FIFO is empty. It is cleared [IIR (3-0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read. 2. The transmitter-holding-register-empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled. FIFO-Polled Mode Operation With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO-polled mode of operation. Because the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously: * LSR0 is set as long as one byte is in the receiver FIFO. * LSR1 through LSR4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode; the IIR is not affected since IER2 = 0. * LSR5 indicates when the THR is empty. 34 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 * LSR6 indicates that both the THR and TSR are empty. LSR7 indicates whether any errors are in the receiver FIFO. There is no trigger level reached or time-out condition indicated in the FIFO-polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters. Interrupt Enable Register (IER) The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table 3 and are described in the following bullets. * Bit 0: When set, this bit enables the received data available interrupt. * Bit 1: When set, this bit enables the THRE interrupt. * Bit 2: When set, this bit enables the receiver line status interrupt. * Bit 3: When set, this bit enables the modem status interrupt. * Bits 4 through 7: These bits are not used (always cleared). Interrupt Identification Register (IIR) The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with the most popular microprocessors. The ACE provides four prioritized levels of interrupts: * Priority 1 - Receiver line status (highest priority) * Priority 2 - Receiver data ready or receiver character time-out * Priority 3 - Transmitter holding register empty * Priority 4 - Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 5. Detail on each bit is as follows: * Bit 0: This bit is used either in a hardwire-prioritized or polled-interrupt system. When bit 0 is cleared, an interrupt is pending. If bit 0 is set, no interrupt is pending. * Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3. * Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending. * Bits 4 and 5: These two bits are not used (always cleared). * Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control register is set. Table 5. Interrupt Control Functions INTERRUPT IDENTIFICATION REGISTER BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 1 PRIORITY LEVEL None INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET METHOD None None None Read the line status register Read the receiver buffer register 0 1 1 0 1 Receiver line status Overrun error, parity error, framing error, or break interrupt 0 1 0 0 2 Received data available Receiver data available in the TL16C450 mode or trigger level reached in the FIFO mode Character time-out indication No characters have been removed from or input to the receiver FIFO during the last Read the receiver buffer four character times, and there register is at least one character in it during this time 1 1 0 0 2 Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 35 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Table 5. Interrupt Control Functions (continued) INTERRUPT IDENTIFICATION REGISTER BIT 3 BIT 2 BIT 1 BIT 0 PRIORITY LEVEL INTERRUPT TYPE 0 0 1 0 3 Transmitter holding register empty 0 0 0 0 4 Modem status INTERRUPT SOURCE INTERRUPT RESET METHOD Transmitter holding register empty Read the interrupt identification register (if source of interrupt) or writing into the transmitter holding register Clear to send, data set ready, ring indicator, or data carrier detect Read the modem status register Line Control Register (LCR) The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and described in the following bulleted list. * Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 6. Table 6. Serial Character Word Length * BIT 1 BIT 0 WORD LENGTH 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are shown in Table 7. Table 7. Number of Stop Bits Generated * * * * 36 BIT 2 WORD LENGTH SELECTED BY BITS 1 AND 2 0 Any word length 1 1 5 bits 1 1 6 bits 2 1 7 bits 2 1 8 bits 2 NUMBER OF STOP BITS GENERATED Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked. Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is selected. Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5 is cleared, stick parity is disabled. Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect on the transmitter logic; it only effects SOUT. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 * Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER. Line Status Register (LSR) (1) The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are summarized in Table 3 and described in the following bulleted list. * Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO. * Bit 1 (2): This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full, and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO. * Bit 2 (3): This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. * Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The ACE samples this start bit twice and then accepts the input data. * Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit. * Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO. * Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty. * Bit 7: In the TL16C550D mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO. Modem Control Register (MCR) The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in Table 3 and are described in the following bulleted list. * Bit 0: This bit (DTR) controls the DTR output. * Bit 1: This bit (RTS) controls the RTS output. * Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal. (1) (2) (3) The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment. Bits 1 through 4 are the error conditions that produce a receiver line status interrupt. Bits 1 through 4 are the error conditions that produce a receiver line status interrupt. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 37 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com * Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal. When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared, the associated output is forced high. * Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs: - The transmitter SOUT is set high. - The receiver SIN is disconnected. - The output of the TSR is looped back into the receiver shift register input. - The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. - The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. - The four modem control outputs are forced to the inactive (high) levels. * Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed description is enabled. In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the modem control interrupt's sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER. The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8. Table 8. ACE Flow Configuration MCR BIT 5 (AFE) MCR BIT 1 (RTS) 1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled) 1 0 Auto-CTS only enabled 0 X Auto-RTS and auto-CTS disabled ACE FLOW CONFIGURATION Modem Status Register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list. * Bit 0: This bit is the change in clear-to-send (CTS) indicator. CTS indicates that the CTS input has changed state since the last time it was read by the CPU. When CTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled (CTS is cleared), no interrupt is generated. * Bit 1: This bit is the change in data set ready (DSR) indicator. DSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DSR is set and the modem status interrupt is enabled, a modem status interrupt is generated. * Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated. * Bit 3: This bit is the change in data carrier detect (DCD) indicator. DCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated. * Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS). * Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR). * Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1). 38 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 * Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2). Programmable Baud Generator The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz and divides it by a divisor in the range between 1 and (216 - 1). The output frequency of the baud generator is sixteen times (16x) the baud rate. The formula for the divisor is: divisor = XIN frequency input / (desired baud rate x 16) Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock circuits). Table 9. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16x CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 0.69 2.86 Table 10. Baud Rates Using a 3.072-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16x CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 3840 75 2560 110 1745 0.026 134.5 1428 0.034 150 1280 300 640 600 320 1200 160 Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 39 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Table 10. Baud Rates Using a 3.072-MHz Crystal (continued) DESIRED BAUD RATE DIVISOR USED TO GENERATE 16x CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 1800 107 2000 96 2400 80 3600 53 4800 40 7200 27 9600 20 19200 10 38400 5 0.312 0.628 1.23 TYPICAL CRYSTAL OSCILLATOR NETWORK CRYSTAL Rp RX2 3.072 MHz 1 M 1.5 k 10 - 30 pF 40 - 60 pF 1.8432 MHz 1 M 1.5 k 10 - 30 pF 40 - 60 pF 16 MHz 1 M 0 C1 C2 33 pF 33 pF Figure 27. Typical Clock Circuits Receiver Buffer Register (RBR) The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte FIFO. Timing is supplied by the 16 receiver clock (RCLK). Receiver section control is a function of the ACE line control register. The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. 40 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI TL16C550D,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 Scratch Register The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense that it temporarily holds the programmer's data without affecting any other ACE operation. Transmitter Holding Register (THR) The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control register. The ACE THR receives data off the Internal data bus and when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the transmitter-holding-register-empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI Submit Documentation Feedback 41 TL16C550D,, TL16C550DI SLLS597E - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Revision History Changes from Revision D (May 2006) to Revision E ...................................................................................................... Page * * * * * * * * * * * * 42 Added "Up to 48-MHz Clock Rate for up to 3-Mbaud Operation with VCC = 3.3 V (ZQS Package Only, Divisor = 1)" ........ 1 Added "Up to 40-MHz Clock Rate for up to 2.5-Mbaud Operation with VCC = 3.3 V (ZQS Package Only, Divisor = 2)" ..... 1 Added 24-pin ZQS package .................................................................................................................................................. 1 Added ZQS package drawing ................................................................................................................................................ 2 Added ZQS package terminal assignments table.................................................................................................................. 2 Added ZQS package functional block diagram...................................................................................................................... 7 Added ZQS package terminal functions table ..................................................................................................................... 12 Added oscillator/clock speed for ZQS package ................................................................................................................... 13 Added ZQS tw1, tXH specification.......................................................................................................................................... 16 Added ZQS tw2, tXL specification .......................................................................................................................................... 16 Added basic TL16C550D configuration for ZQS package................................................................................................... 28 Added typical TL16C550D connection to a CPU for ZQS package .................................................................................... 31 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TL16C550D TL16C550DI PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TL16C550DIPFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIPT ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DIPTG4 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DIPTR ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DIPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DIRHB ACTIVE QFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIRHBG4 ACTIVE QFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL16C550DIZQS PREVIEW BGA MI CROSTA R JUNI OR ZQS 24 250 TL16C550DIZQSR ACTIVE BGA MI CROSTA R JUNI OR ZQS 24 2500 Green (RoHS & no Sb/Br) TL16C550DPFB ACTIVE TQFP PFB 48 250 TL16C550DPFBG4 ACTIVE TQFP PFB 48 250 TL16C550DPFBR ACTIVE TQFP PFB TL16C550DPFBRG4 ACTIVE TQFP TL16C550DPT ACTIVE TL16C550DPTG4 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DPTR ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL16C550DRHB ACTIVE QFN RHB 32 CU NIPDAU Level-2-260C-1 YEAR 73 Addendum-Page 1 Green (RoHS & no Sb/Br) PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2009 Orderable Device Status (1) Package Type Package Drawing TL16C550DRHBG4 ACTIVE QFN RHB 32 TL16C550DRHBR ACTIVE QFN RHB TL16C550DRHBRG4 ACTIVE QFN TL16C550DZQSR ACTIVE BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty 73 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ZQS 24 2500 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TL16C550DIPFBR TQFP TL16C550DIPTR TL16C550DIRHBR TL16C550DIZQSR SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1 PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 BGA MI CROSTA R JUNI OR TL16C550DPFBR TQFP TL16C550DPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 TL16C550DRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1 TL16C550DZQSR BGA MI CROSTA R JUNI OR Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jan-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16C550DIPFBR TQFP PFB 48 1000 346.0 346.0 33.0 TL16C550DIPTR LQFP PT 48 1000 346.0 346.0 33.0 TL16C550DIRHBR QFN RHB 32 3000 346.0 346.0 29.0 TL16C550DIZQSR BGA MICROSTAR JUNIOR ZQS 24 2500 340.5 338.1 20.6 TL16C550DPFBR TQFP PFB 48 1000 346.0 346.0 33.0 TL16C550DPTR LQFP PT 48 1000 346.0 346.0 33.0 TL16C550DRHBR QFN RHB 32 3000 346.0 346.0 29.0 TL16C550DZQSR BGA MICROSTAR JUNIOR ZQS 24 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0- 7 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTQF019A - JANUARY 1995 - REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0- 7 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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