STM32L151xx STM32L152xx Ultralow power ARM-based 32-bit MCU with up to 128 KB Flash, RTC, LCD, USB, USART, I2C, SPI, timers, ADC, DAC, comparators Features Operating conditions - Operating power supply range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V (with BOR option) - Temperature range: -40 to 85 C Low power features - 4 modes: Sleep, Low-power run (9 A at 32 kHz), Low-power sleep (4.4 A), Stop with RTC (1.45 A), Stop (570 nA), Standby (300 nA) - Dynamic core voltage scaling down to 233 A/MHz - Ultralow leakage per I/O: 50 nA - Fast wakeup from Stop: 8 s - Three wakeup pins Core: ARM 32-bit CortexTM-M3 CPU - 32 MHz maximum frequency, 33.3 DMIPS peak (Dhrystone 2.1) - Memory protection unit Reset and supply management - Low power, ultrasafe BOR (brownout reset) with 5 selectable thresholds - Ultralow power POR/PDR - Programmable voltage detector (PVD) Clock management - 1 to 24 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 16 MHz factory-trimmed RC - Internal 37 kHz low consumption RC - Internal multispeed low power RC, 65 kHz to 4.2 MHz with consumption down to 1.5 A - PLL for CPU clock and USB (48 MHz) Low power calendar RTC - Alarm, periodic wakeup from Stop/Standby Memories - Up to 128 Kbyte of Flash memory with ECC - 4 Kbyte of data EEPROM with ECC January 2012 LQFP100 14 x 14 mm LQFP64 10 x 10 mm LQFP48 7 x 7 mm BGA100 7 x 7 mm BGA64 5 x 5 mm UFQFPN48 7 x 7 mm - Up to 16 Kbyte of RAM Up to 83 fast I/Os (73 of which are 5 V-tolerant) all mappable on 16 external interrupt vectors Development support - Serial wire debug, JTAG and trace DMA: 7-channel DMA controller, supporting timers, ADC, SPIs, I2Cs and USARTs LCD 8 x 40 or 4 x 44 with step-up converter 12-bit ADC up to 1 Msps/24 channels - Temperature sensor and internal voltage reference - Operates down to 1.8 V 2 x 12-bit DACs with output buffers 2 ultralow power comparators - Window mode and wakeup capability 10 timers: - 6 x 16-bit general-purpose timers, each with up to 4 IC/OC/PWM channels - 2 x 16-bit basic timers - 2 x watchdog timers (independent and window) Up to 8 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 3 x USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 x SPIs (16 Mbit/s) - USB 2.0 full speed interface CRC calculation unit, 96-bit unique ID Table 1. Reference STM32L151xx STM32L152xx Doc ID 17659 Rev 6 Device summary Part number STM32L151CB, STM32L151C8, STM32L151C6, STM32L151RB, STM32L151R8, STM32L151R6, STM32L151VB, STM32L151V8 STM32L152CB, STM32L152C8, STM32L152C6, STM32L152RB, STM32L152R8, STM32L152R6, STM32L152VB, STM32L152V8 1/109 www.st.com 1 Contents STM32L151xx, STM32L152xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2/109 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 ARM(R) CortexTM-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 18 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 Ultralow power comparators and reference voltage . . . . . . . . . . . . . . . . . 21 3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) 22 3.14.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 3.14.5 3.15 Contents Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.1 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 23 3.15.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 24 3.17 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 46 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.5 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.7 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.8 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.10 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 71 6.3.11 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Doc ID 17659 Rev 6 3/109 Contents 7 STM32L151xx, STM32L152xx 6.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.19 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.20 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultralow power STM32L15xxx device features and peripheral counts . . . . . . . . . . . . . . . . 10 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32L15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 45 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Current consumption in Run mode, code with data processing running from Flash. . . . . . 49 Current consumption in Run mode, code with data processing running from RAM . . . . . . 50 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 55 Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 17659 Rev 6 5/109 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/109 STM32L151xx, STM32L152xx ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 UFQFPN48 - ultra thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 98 UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 101 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 102 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 103 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Ultralow power STM32L15xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32L15xxx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32L15xxx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32L15xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32L15xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32L15xxx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32L15xxx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 89 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 89 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Recommended footprint (dimensions in mm)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 98 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 99 UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 101 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 102 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 103 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Doc ID 17659 Rev 6 7/109 Introduction 1 STM32L151xx, STM32L152xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xx and STM32L152xx ultralow power ARM CortexTM-based microcontrollers product line. The ultralow power STM32L15xxx family includes devices in 3 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultralow power STM32L15xxx microcontroller family suitable for a wide range of applications: Medical and handheld equipment Application control and user interface PC peripherals, gaming, GPS and sport equipment Alarm systems, Wired and wireless sensors, Video intercom Utility metering For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g. Figure 1 shows the general block diagram of the device family. 8/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 2 Description Description The ultralow power STM32L15xxx incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes and RAM up to 16 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer a 12-bit ADC, 2 DACs and 2 ultralow power comparators, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L15xxx devices contain standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs and a USB. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage. The ultralow power STM32L15xxx operates from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. It is available in the -40 to +85 C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications. Doc ID 17659 Rev 6 9/109 Description STM32L151xx, STM32L152xx 2.1 Device overview Table 2. Ultralow power STM32L15xxx device features and peripheral counts Peripheral STM32L15xCx STM32L15xRx STM32L15xVx Flash - Kbytes 32 64 128 32 64 128 64 128 RAM - Kbytes 10 10 16 10 10 16 10 16 Timers Communication interfaces Generalpurpose 6 6 6 Basic 2 2 2 SPI 2 2 2 I2C 2 2 2 USART 3 3 3 USB 1 1 1 37 51 83 1 16 channels 1 20 channels 1 24 channels 2 2 2 2 2 2 4x16 4x32 8x28 4x44 8x40 2 2 2 GPIOs 12-bit synchronized ADC Number of channels 12-bit DAC Number of channels LCD (STM32L152xx Only) COM x SEG Comparator CPU frequency Operating voltage Operating temperatures Packages 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 V to 3.6 V without BOR option Ambient temperatures: -40 to +85 C Junction temperature: -40 to + 105 C LQFP48, UFQFPN48 . 10/109 Doc ID 17659 Rev 6 LQFP64, BGA64 LQFP100, BGA100 STM32L151xx, STM32L152xx 2.2 Description Ultralow power device continuum The ultralow power STM32L151xx and STM32L152xx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultralow power strategy which also includes STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture and features. They are all based on STMicroelectronics 0.13 m ultralow leakage process. Note: The ultralow power STM32L and general-purpose STM32Fxxxx families are pin-to-pin compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx devices. Please refer to the STM32F and STM8L documentation for more information on these devices. 2.2.1 Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM CortexTM-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultralow power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy migration from one family to another: 2.2.3 Analog peripherals: ADC, DAC, and comparators Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx families use a common architecture: 2.2.4 Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for STM8L15xx devices) Architecture optimized to reach ultralow consumption both in low power modes and Run mode Fast startup strategy from low power modes Flexible system clock Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST ultralow power continuum also lies in feature compatibility: More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm Memory density ranging from 4 to 128 Kbytes Doc ID 17659 Rev 6 11/109 Functional overview 3 STM32L151xx, STM32L152xx Functional overview Figure 1 shows the block diagrams. Figure 1. Ultralow power STM32L15xxx block diagram 42!#%#+ 42!#%$ 42!#%$ 42!#%$ 42!#%$ 6$$ *4!' 37 4RACE CONTROLLER %4- PBUS &LASH OBL )NT ERFACE #ORTEX - #05 )BUS &MAX -(Z -05 $BUS 3YST EM .6)# '0 $-! !("0#,+ !0"0#,+ (#,+ &#,+ 6$$! "/262%&).4 6$$! 633! 06$ 84!, /3# -(Z CLOCK MANAGEMENT 2# -3 /3#?). /3#?/54 )7$' 2# ,3 )NT #OMP #/-0?). ). 6$$! 0,, 2# (3 0OWER RESET #OMP 0OWER UP 0OWER DOWN 3TANDBY INTERFACE 6$$! !("& MAX -(Z 62%& /54054 3UPPLY MONITORING 6$$ 6 TO 6 633 +" &LASH +" DATA %%02/- 2! +" CHANNELS .234 0/7%2 6/,4 2%' "US-ATRIX .*4234 *4$) *4#+37#+ *4-337$ *4$/ AS !& 6#/2% 84!, K(Z 24# !75 "ACKUP REGISTER /3#?). /3#?/54 3YNC (Z 24#?!& 0!;= '0)/! 0";= '0)/" 0#;= '0)/# 0$;= '0)/$ 4)- #HANNELS 0%;= '0)/% 4)- #HANNELS 0(;= '0)/( 4)- #HANNELS 6,#$ "ACKUP INTERFACE !& %84)4 7+50 -/3) -)3/ 3#+ .33 AS !& 30) !& 6$$2%&?!$# 53!24 !0" &MAX -(Z 28 48 #43 243 3MART#ARD AS !& 6$$! BIT !$# )& 6332%&?!$# 4EMP S ENSOR 'ENERAL PURPOSE TIMERS #HANNE LS !(" !0" !0" & MAX -(Z !(" !0" ,#$ STEP UP CONVERTER 53" 2!- " 53!24 28 48 #43 243 3MART#ARD AS !& 53!24 28 48 #43 243 3MART#ARD A S !& 30) -/3) -)3/ 3#+ .33 AS !& )# 3#, 3$! AS !& )# 3#, 3$! 3-"US 0-"US AS !& 53" &3 DEVICE 77$' ,#$ X X "!3)# 4)-%23 6,#$ 6 TO 6 53"$0 53"$3%'X #/-X 6$$! 4)- 4)- #HANNEL 4)- #HANNEL 4)- BIT $!# $!# AS !& BIT $!# $!# AS !& )& )& 4)- - AIE 1. AF = alternate function on I/O port pin. 12/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 3.1 Functional overview Low power modes The ultralow power STM32L15xxx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system's maximum operating frequency and the external voltage supply: In range 1 (VDD range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to Table 13 for consumption). In range 2 (full VDD range), the CPU runs at up to 16 MHz (refer to Table 13 for consumption) In range 3 (full VDD range), the CPU runs at up to 4 MHz (generated only with the multispeed internal RC oscillator clock source). Refer to Table 13 for consumption. Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption: refer to Table 15. Low power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In the Low power run mode, the clock frequency and the number of enabled peripherals are both limited. Low power run mode consumption: refer to Table 16. Low power sleep mode This mode is achieved by entering the Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator's operating current. In the Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. Low power sleep mode consumption: refer to Table 17. Stop mode (with or without RTC) The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The voltage regulator is in the low power mode. The device can be woken up from the Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm(s), the USB wakeup, the RTC tamper event, the RTC timestamp event, the RTC Wakeup, the Comparator 1 event or Comparator 2 event. Stop mode consumption: refer to Table 18. Doc ID 17659 Rev 6 13/109 Functional overview STM32L151xx, STM32L152xx Standby mode (with or without RTC) The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC CSR). The device exits the Standby mode in 60 s when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event. Standby mode consumption: refer to Table 19. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the Stop or Standby mode. 3.2 ARM(R) CortexTM-M3 core with MPU The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and software. Nested vectored interrupt controller (NVIC) The ultralow power STM32L15xxx embeds a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving, higher-priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 14/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Functional overview 3.3 Reset and supply management 3.3.1 Power supply schemes 3.3.2 VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. For devices operating between 1.8 and 3.6 V, the BOR is always active at power-on and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD min value at power down is 1.65 V). Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled. Consequently, the start-up time at power-on can be decreased down to 1ms typically. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in Run mode (nominal regulation) LPR is used in the Low-power run, Low-power sleep and Stop modes Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Doc ID 17659 Rev 6 15/109 Functional overview 3.3.4 STM32L151xx, STM32L152xx Boot modes At startup, boot pins are used to select one of three boot options: Boot from Flash memory Boot from System Memory Boot from embedded RAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1 or USART2. For further details please refer to AN2606. 3.4 Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features: Clock prescaler: to get the best tradeoff between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Master clock source: three different clock sources can be used to drive the master clock: 16/109 - 1-24 MHz high-speed external crystal (HSE), that can supply a PLL - 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL - Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz) with a consumption proportional to speed, down to 750 nA typical. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a 0.5% accuracy. Auxiliary clock source: two ultralow power clock sources that can be used to drive the LCD controller and the real-time clock: - 32.768 kHz low-speed external crystal (LSE) - 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. Startup clock: after reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Functional overview Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. Figure 2. Clock tree -3) 2# -3) !$##,+ TO !$# 0ERIPHERAL CLOCK ENABLE -(Z (3) 2# (3) -(Z 53"#,+ TO 53" INTERFACE 0,,6#/ 0,,32# /3#?/54 /3#?). 0,,-5, X X X X X X X X X -(Z 37 0,,$)6 (3) 0,,#,+ 393#,+ -(Z MAX (3% (3% /3# #33 (#,+ TO !(" BUS CORE MEMORY AND $-! -(Z MAX !(" 0RESCALER #LOCK %NABLE !0" 0RESCALER TO #ORTEX 3YSTEM TIMER &#,+ #ORTEX FREE RUNNING CLOCK -(Z MAX 0ERIPHERAL #LOCK %NABLE )F !0" PRESCALER X ELSE X 0#,+ TO !0" PERIPHERALS TO 4)- AND 4)-X#,+ 0ERIPHERAL #LOCK %NABLE !0" 0RESCALER -(Z MAX 0ERIPHERAL #LOCK %NABLE )F !0" PRESCALER X ELSE X TO 4IMER %42 /3#?). /3#?/54 ,3% /3# K(Z 0#,+ PERIPHERALS TO !0" TO 4)- AND 4)-X#,+ 0ERIPHERAL #LOCK %NABLE TO 24# ,3% 24##,+ TO ,#$ 24#3%,;= ,3) 2# K(Z -#/ ,3) TO )NDEPENDENT 7ATCHDOG )7$' )7$'#,+ 393#,+ (3) -3) (3% 0,,#,+ ,3) ,3% -#/3%, ,EGEND (3% (IGH SPEED EXTERNAL CLOCK SIGNAL (3) (IGH SPEED INTERNAL CLOCK SIGNAL ,3) ,OW SPEED INTERNAL CLOCK SIGNAL ,3% ,OW SPEED EXTERNAL CLOCK SIGNAL -3) -ULTISPEED INTERNAL CLOCK SIGNAL AIC 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz. Doc ID 17659 Rev 6 17/109 Functional overview 3.5 STM32L151xx, STM32L152xx Low power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 s to 36 hours Stop mode consumption with LSI and Auto-wakeup: 1.2 A (at 1.8 V) and 1.4 A (at 3.0 V) Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 A (at 1.8V), 1.6 A (at 3.0 V) The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. There are twenty 32-bit backup registers provided to store 80 bytes of user application data. They are cleared in case of tamper detection. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high-current-capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines. 18/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 3.7 Functional overview Memories The STM32L15xxx devices have the following features: Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). The non-volatile memory is divided into three arrays: - 32, 64 or 128 Kbyte of embedded Flash program memory - 4 Kbyte of data EEPROM - Options bytes The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 DMA (direct memory access) The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers and ADC. 3.9 LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD Supports static, 1/2, 1/3, 1/4 and 1/8 duty Supports static, 1/2, 1/3 and 1/4 bias Phase inversion to reduce power consumption and EMI Up to 8 pixels can be programmed to blink Unneeded segments and common pins can be used as general I/O pins LCD RAM can be updated at any time owing to a double-buffer The LCD controller can operate in Stop mode Doc ID 17659 Rev 6 19/109 Functional overview 3.10 STM32L151xx, STM32L152xx ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L15xxx devices with up to 24 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, to allow the application to synchronize A/D conversions and timers. The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC's runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel. 3.11 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: two DAC converters: one for each output channel left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channels' independent or simultaneous conversions DMA capability for each channel (including the underrun interrupt) external triggers for conversion input reference voltage VREF+ Eight DAC trigger inputs are used in the STM32L15xxx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 20/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 3.12 Functional overview Ultralow power comparators and reference voltage The STM32L15xxx embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). one comparator with fixed threshold one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: - DAC output - External I/O - Internal reference voltage (VREFINT) or VREFINT submultiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 A typical). 3.13 Routing interface This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the comparator and reference voltage output. 3.14 Timers and watchdogs The ultralow power STM32L15xxx devices include six general-purpose timers, two basic timers and two watchdog timers. Table 3 compares the features of the general-purpose and basic timers. Table 3. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Doc ID 17659 Rev 6 21/109 Functional overview 3.14.1 STM32L151xx, STM32L152xx General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) There are six synchronizable general-purpose timers embedded in the STM32L15xxx devices (see Table 3 for differences). TIM2, TIM3, TIM4 These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.14.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.14.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.14.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 22/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 3.14.5 Functional overview Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15 Communication interfaces 3.15.1 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 3.15.3 Serial peripheral interface (SPI) Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 3.15.4 Universal serial bus (USB) The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). Doc ID 17659 Rev 6 23/109 Functional overview 3.16 STM32L151xx, STM32L152xx CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.17 Development support Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L15xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 24/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 4 Pin descriptions Pin descriptions Figure 3. STM32L15xxx UFBGA100 ballout 2 1 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PC13 PE5 RTC_AF1 WKUP2 PE0 PD2 PD0 PC11 PH2 PA10 VSS_3 PC14 PE6 OSC32_IN WUKP3 PA9 PA8 PC9 VSS_4 PC8 PC7 PC6 VSS_2 VSS_1 VDD_2 VDD_1 C D E PC15 VLCD OSC32_OUT VDD_3 PB5 F PH0 OSC_IN G PH1 VDD_5 OSC_OUT H PC0 NRST VDD_4 PD15 PD14 PD13 J VSSA PC1 PC2 PD12 PD11 PD10 K VREF- PC3 PA2 PA5 PC4 L VREF+ PA0 WKUP1 PA3 PA6 PC5 PB2 M VDDA PA1 PA4 PA7 PB0 PB1 VSS_5 PD9 PD8 PB15 PB14 PB13 PE8 PE10 PE12 PB10 PB11 PB12 PE7 PE9 PE11 PE14 PE15 PE13 ai17096d Doc ID 17659 Rev 6 25/109 Pin descriptions STM32L151xx, STM32L152xx Figure 4. STM32L15xxx TFBGA64 ballout 1 2 3 4 5 6 7 8 PB9 PB4 PB3 PA15 PA14 PA13 A PC14OSC32_IN B PC15OSC32_OUT VLCD PB8 BOOT0 PD2 PC11 PC10 PA12 C PH0OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D PH1OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP1 PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 PC13RTC_AF1 WKUP2 AI16090b 26/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx STM32L15xxx LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 5. Pin descriptions LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 PH2 PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PE2 PE3 PE4 PE5 PE6-WKUP3 VLCD PC13-RTC_AF1-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP1 PA1 PA2 ai15692b Doc ID 17659 Rev 6 27/109 Pin descriptions STM32L15xxx LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 6. STM32L151xx, STM32L152xx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VLCD PC13-RTC_AF1-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT PH0 -OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP1 PA1 PA2 ai15693b STM32L15xxx LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 7. 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VLCD PC13 RTC_AF1-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST VSSA VDDA PA0-WKUP1 PA1 PA2 ai15694 b 28/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 0! 0! 0" 6$$? 0# 24#?!& 633? 0# /3#?). 0! 0# /3#?/54 0! 0( /3#?). 0! 0( /3#?/54 0! .234 0! 633! 0! 6$$! 0" 0! 7+50 0" 0! 0" 0" 0" 0! 5&1&0. 6$$? 633? 0" 0" 0" 0" 0" 0" 0" 0" "//4 0" 0! 0! 0" 0! 633? 6,#$ 0! 6$$? STM32L15xxx UFQFPN48 pinout 0! Figure 8. Pin descriptions AIC Doc ID 17659 Rev 6 29/109 Pin descriptions Table 4. STM32L151xx, STM32L152xx STM32L15xxx pin definitions LQFP48 or UFQFPN48 B2 - PE2 I/O FT PE2 TRACECK/LCD_SEG38/TIM3_ETR 2 - A1 - PE3 I/O FT PE3 TRACED0/LCD_SEG39/TIM3_CH1 3 - B1 - PE4 I/O FT PE4 TRACED1/TIM3_CH2 4 - C2 - PE5 I/O FT PE5 TRACED2/TIM9_CH1 5 - D2 - PE6 I/O FT PE6 TRACED3/WKUP3/TIM9_CH2 6 1 B2 E2 1 VLCD(4) 7 2 A2 C1 2 PC13RTC_AF1 8 3 A1 D1 3 9 4 B1 E1 4 I/O Level(2) UFBGA100 1 - Pin name Type(1) LQFP100 LQFP64 TFBGA64 Pins S I/O FT PC14I/O OSC32_IN(5) PC15OSC32_OUT I/O Main function(3) (after reset) Alternate functions VLCD PC13 RTC_AF1/WKUP2 PC14 OSC32_IN PC15 OSC32_OUT (5) 10 - - F2 - VSS_5 S VSS_5 11 - - G2 - VDD_5 S VDD_5 12 5 C1 F1 5 PH0OSC_IN(6) I PH0 OSC_IN 13 6 D1 G1 6 PH1OSC_OUT O PH1 OSC_OUT 14 7 E1 H2 7 NRST I/O NRST 15 8 E3 H1 - PC0 I/O FT PC0 ADC_IN10/LCD_SEG18/ COMP1_INP 16 9 E2 J2 - PC1 I/O FT PC1 ADC_IN11/LCD_SEG19/ COMP1_INP 17 10 F2 J3 - PC2 I/O FT PC2 ADC_IN12/LCD_SEG20/ COMP1_INP 18 11 -(7) K2 - PC3 I/O PC3 ADC_IN13/LCD_SEG21/ COMP1_INP 19 12 F1 J1 8 VSSA S VSSA 20 - K1 - VREF- S VREF- G1 21 - (7) L1 - VREF+ S VREF+ 22 13 H1 M1 9 VDDA S VDDA 23 14 G2 L2 10 PA0-WKUP1 30/109 - I/O FT PA0 WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR/ COMP1_INP Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Table 4. Pin descriptions STM32L15xxx pin definitions (continued) PA1 I/O FT PA1 USART2_RTS/ADC_IN1/ TIM2_CH2/LCD_SEG0/ COMP1_INP 25 16 F3 K3 12 PA2 I/O FT PA2 USART2_TX/ADC_IN2/ TIM2_CH3/TIM9_CH1/ LCD_SEG1/COMP1_INP 26 17 G3 L3 13 PA3 I/O PA3 USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2/ LCD_SEG2/COMP1_INP 27 18 C2 E3 - VSS_4 S VSS_4 28 19 D2 H3 - VDD_4 S VDD_4 29 20 H3 M3 14 PA4 I/O PA4 SPI1_NSS/ USART2_CK/ ADC_IN4/DAC_OUT1/COMP1_INP 30 21 F4 K4 15 PA5 I/O PA5 SPI1_SCK/ADC_IN5/ DAC_OUT2/TIM2_CH1_ETR/COMP1_INP 31 22 G4 L4 16 PA6 I/O FT PA6 SPI1_MISO/ADC_IN6/TIM3_CH1/ LCD_SEG3/TIM10_CH1/ COMP1_INP 32 23 H4 M4 17 PA7 I/O FT PA7 SPI1_MOSI/ADC_IN7/TIM3_CH2/ LCD_SEG4/TIM11_CH1/COMP1_INP 33 24 H5 K5 - PC4 I/O FT PC4 ADC_IN14/LCD_SEG22/COMP1_INP 34 25 H6 L5 - PC5 I/O FT PC5 ADC_IN15/LCD_SEG23/COMP1_INP 35 26 F5 M5 18 PB0 I/O PB0 ADC_IN8/TIM3_CH3/LCD_SEG5/ COMP1_INP/VREF_OUT 36 27 G5 M6 19 PB1 I/O FT PB1 ADC_IN9/TIM3_CH4/LCD_SEG6/ COMP1_INP/VREF_OUT 37 28 G6 L6 20 PB2 I/O FT PB2/BOOT1 I/O Level(2) 11 Pin name Type(1) LQFP48 or UFQFPN48 24 15 H2 M2 LQFP100 LQFP64 TFBGA64 UFBGA100 Pins Main function(3) (after reset) Alternate functions 38 - - M7 - PE7 I/O PE7 ADC_IN22/COMP1_INP 39 - - L7 - PE8 I/O PE8 ADC_IN23/COMP1_INP 40 - - M8 - PE9 I/O PE9 ADC_IN24/TIM2_CH1_ETR/COMP1_INP 41 - - L8 - PE10 I/O PE10 ADC_IN25/TIM2_CH2/COMP1_INP 42 - - M9 - PE11 I/O FT PE11 TIM2_CH3 43 - - L9 - PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS 44 - - M10 - PE13 I/O FT PE13 SPI1_SCK 45 - - M11 - PE14 I/O FT PE14 SPI1_MISO 46 - - M12 - PE15 I/O FT PE15 SPI1_MOSI Doc ID 17659 Rev 6 31/109 Pin descriptions Table 4. STM32L151xx, STM32L152xx STM32L15xxx pin definitions (continued) I/O Level(2) Pin name Type(1) LQFP48 or UFQFPN48 UFBGA100 LQFP100 LQFP64 TFBGA64 Pins Main function(3) (after reset) Alternate functions 47 29 G7 L10 21 PB10 I/O FT PB10 I2C2_SCL/USART3_TX/TIM2_CH3/LCD_SEG10 48 30 H7 L11 22 PB11 I/O FT PB11 I2C2_SDA/ USART3_RX/TIM2_CH4/LCD_SEG11 49 31 D6 F12 23 VSS_1 S VSS_1 50 32 E6 G12 24 VDD_1 S VDD_1 51 33 H8 L12 25 PB12 I/O FT PB12 SPI2_NSS/I2C2_SMBA/USART3_CK/LCD_SEG12/ ADC_IN18/COMP1_INP/TIM10_CH1 52 34 G8 K12 26 PB13 I/O FT PB13 SPI2_SCK/USART3_CTS/LCD_SEG13/ADC_IN19/ COMP1_INP/TIM9_CH1 53 35 F8 K11 27 PB14 I/O FT PB14 SPI2_MISO/ USART3_RTS/LCD_SEG14/ADC_IN20/ COMP1_INP/TIM9_CH2 54 36 F7 K10 28 PB15 I/O FT PB15 SPI2_MOSI/LCD_SEG15/ADC_IN21/ COMP1_INP/TIM11_CH1/RTC_50_60Hz 55 - - K9 - PD8 I/O FT PD8 USART3_TX/LCD_SEG28 56 - - K8 - PD9 I/O FT PD9 USART3_RX/LCD_SEG29 57 - - J12 - PD10 I/O FT PD10 USART3_CK/LCD_SEG30 58 - - J11 - PD11 I/O FT PD11 USART3_CTS/LCD_SEG31 59 - - J10 - PD12 I/O FT PD12 TIM4_CH1 / USART3_RTS/ LCD_SEG32 60 - - H12 - PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33 61 - - H11 - PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34 62 - - H10 - PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35 63 37 F6 E12 - PC6 I/O FT PC6 TIM3_CH1/LCD_SEG24 64 38 E7 E11 PC7 I/O FT PC7 TIM3_CH2/LCD_SEG25 65 39 E8 E10 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 67 41 D7 D11 29 PA8 I/O FT PA8 USART1_CK/MCO/LCD_COM0 68 42 C7 D10 30 PA9 I/O FT PA9 USART1_TX / LCD_COM1 69 43 C6 C12 31 PA10 I/O FT PA10 USART1_RX / LCD_COM2 70 44 C8 B12 32 PA11 I/O FT PA11 USART1_CTS/ USBDM/SPI1_MISO 71 45 B8 A12 33 PA12 I/O FT PA12 USART1_RTS/USBDP/SPI1_MOSI 72 46 A8 A11 34 PA13 I/O FT JTMS/SWDIO 66 40 D8 D12 32/109 - Doc ID 17659 Rev 6 PA13 STM32L151xx, STM32L152xx Table 4. Pin descriptions STM32L15xxx pin definitions (continued) 73 - - C11 - PH2 I/O Level(2) Pin name Type(1) LQFP48 or UFQFPN48 UFBGA100 LQFP100 LQFP64 TFBGA64 Pins I/O FT Main function(3) (after reset) Alternate functions PH2 I2C2_SMBA 74 47 D5 F11 35 VSS_2 S VSS_2 75 48 E5 G11 36 VDD_2 S VDD_2 76 49 A7 A10 37 PA14 I/O FT JTCK/SWCLK 77 50 A6 A9 38 PA15 I/O FT JTDI TIM2_CH1_ETR/ PA15/SPI1_NSS/LCD_SEG17 78 51 B7 B11 - PC10 I/O FT PC10 USART3_TX/LCD_SEG28/LCD_SEG40/ LCD_COM4 79 52 B6 C10 - PC11 I/O FT PC11 USART3_RX/LCD_SEG29/LCD_SEG41/LCD_COM5 80 53 C5 B10 - PC12 I/O FT PC12 USART3_CK/LCD_SEG30/LCD_SEG42/LCD_COM6 81 - - C9 - PD0 I/O FT PD0 SPI2_NSS/TIM9_CH1 82 - - B9 - PD1 I/O FT PD1 SPI2_SCK PD2 I/O FT PD2 TIM3_ETR/LCD_SEG31/LCD_SEG43/LCD_COM7 83 54 B5 C8 PA14 84 - - B8 - PD3 I/O FT PD3 USART2_CTS/SPI2_MISO 85 - - B7 - PD4 I/O FT PD4 USART2_RTS/SPI2_MOSI 86 - - A6 - PD5 I/O FT PD5 USART2_TX 87 - - B6 - PD6 I/O FT PD6 USART2_RX 88 - - A5 - PD7 I/O FT PD7 USART2_CK/TIM9_CH2 89 55 A5 A8 39 PB3 I/O FT JTDO TIM2_CH2 / PB3/TRACESWO SPI1_SCK/COMP2_INM/LCD_SEG7 90 56 A4 A7 40 PB4 I/O FT JNTRST TIM3_CH1/ PB4/ SPI1_MISO/COMP2_INP/LCD_SEG8 91 57 C4 C5 41 PB5 I/O FT PB5 I2C1_SMBAl/TIM3_CH2 /SPI1_MOSI/COMP2_INP/LCD_SEG9 92 58 D3 B5 42 PB6 I/O FT PB6 I2C1_SCL/TIM4_CH1/ USART1_TX 93 59 C3 B4 43 PB7 I/O FT PB7 I2C1_SDA/TIM4_CH2/ USART1_RX/PVD_IN 94 60 B4 A4 44 BOOT0 95 61 B3 A3 45 PB8 I/O FT PB8 TIM4_CH3/I2C1_SCL / LCD_SEG16/TIM10_CH1 96 62 A3 B3 46 PB9 I/O FT PB9 TIM4_CH4/I2C1_SDA/LCD_COM3 / TIM11_CH1 - PE0 I/O FT PE0 TIM4_ETR/LCD_SEG36 /TIM10_CH1 97 - - C3 I BOOT0 Doc ID 17659 Rev 6 33/109 Pin descriptions Table 4. STM32L151xx, STM32L152xx STM32L15xxx pin definitions (continued) PE1 99 63 D4 D3 47 VSS_3 S VSS_3 10 64 E4 C4 0 48 VDD_3 S VDD_3 - I/O Level(2) - 98 - Pin name Type(1) LQFP48 or UFQFPN48 A2 LQFP100 LQFP64 TFBGA64 UFBGA100 Pins I/O FT Main function(3) (after reset) Alternate functions PE1 LCD_SEG37/TIM11_CH1 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 10. 4. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to VDD. 5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PC14/PC15 I/Os, respectively, when the LSE oscillator is off ( after reset, the LSE oscillator is off ). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L15xxx reference manual (RM0038). 6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on ( by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 34/109 Doc ID 17659 Rev 6 Alternate function input/output Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM BOOT0 BOOT0 NRST NRST TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A USBFS LCD N/A N/A RI SYSTEM Doc ID 17659 Rev 6 PA0-WKUP1 WKUP1 TIM2_CH1_ ETR USART2_ CTS PA1 TIM2_CH2 USART2_ RTS [SEG0] TIMx_IC2 EVENTOUT PA2 TIM2_CH3 TIM9_CH1 USART2_ TX [SEG1] TIMx_IC3 EVENTOUT PA3 TIM2_CH4 TIM9_CH2 USART2_ RX [SEG2] TIMx_IC4 EVENTOUT PA4 SPI1_NSS TIM2_CH1_ ETR PA5 TIMx_IC1 EVENTOUT USART2_ CK TIMx_IC1 EVENTOUT SPI1_SCK PA6 TIM3_CH1 TIM10_CH1 SPI1_MISO PA7 TIM3_CH2 TIM11_CH1 SPI1_MOSI TIMx_IC2 EVENTOUT [SEG3] TIMx_IC3 EVENTOUT [SEG4] TIMx_IC4 EVENTOUT USART1_ CK [COM0] TIMx_IC1 EVENTOUT PA9 USART1_ TX [COM1] TIMx_IC2 EVENTOUT PA10 USART1_ RX [COM2] TIMx_IC3 EVENTOUT PA8 MCO STM32L151xx, STM32L152xx Table 5. SPI1_MISO USART1_ CTS DM TIMx_IC4 EVENTOUT PA12 SPI1_MOSI USART1_ RTS DP TIMx_IC1 EVENTOUT 35/109 PA13 JTMS-SWDAT TIMx_IC2 EVENTOUT PA14 JTCK-SWCLK TIMx_IC3 EVENTOUT Pin descriptions PA11 Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM PA15 AFIO1 JTDI TIM2 PB1 Doc ID 17659 Rev 6 BOOT1 PB3 JTDO PB4 JTRST TIM9/10/11 I2C1/2 TIM2_CH1_ ETR PB0 PB2 TIM3/4 SPI1/2 N/A USART 1/2/3 SPI1_NSS N/A N/A USBFS LCD N/A N/A RI SYSTEM SEG17 TIMx_IC4 EVENTOUT TIM3_CH3 [SEG5] EVENTOUT TIM3_CH4 [SEG6] EVENTOUT EVENTOUT SPI1_SCK [SEG7] EVENTOUT TIM3_CH1 SPI1_MISO [SEG8] EVENTOUT PB5 TIM3_CH2 I2C1_SMB SPI1_MOSI Al [SEG9] EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_ TX EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_ RX EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL * SEG16 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA * [COM3] EVENTOUT TIM2_CH2 TIM2_CH3 I2C2_SCL USART3_ TX SEG10 EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_ RX SEG11 EVENTOUT I2C2_SMB SPI2_NSS Al USART3_ CK SEG12 EVENTOUT PB12 TIM10_CH1 PB13 TIM9_CH1 SPI2_SCK USART3_ CTS SEG13 EVENTOUT PB14 TIM9_CH2 SPI2_MISO USART3_ RTS SEG14 EVENTOUT TIM11_CH1 SPI2_MOSI SEG15 EVENTOUT SEG18 TIMx_IC1 EVENTOUT PC0 RTC 50/60 Hz STM32L151xx, STM32L152xx PB10 PB15 Pin descriptions 36/109 Table 5. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A USBFS LCD N/A N/A RI SYSTEM PC1 SEG19 TIMx_IC2 EVENTOUT PC2 SEG20 TIMx_IC3 EVENTOUT PC3 SEG21 TIMx_IC4 EVENTOUT PC4 SEG22 TIMx_IC1 EVENTOUT PC5 SEG23 TIMx_IC2 EVENTOUT Doc ID 17659 Rev 6 PC6 TIM3_CH1 SEG24 TIMx_IC3 EVENTOUT PC7 TIM3_CH2 SEG25 TIMx_IC4 EVENTOUT PC8 TIM3_CH3 SEG26 TIMx_IC1 EVENTOUT PC9 TIM3_CH4 SEG27 TIMx_IC2 EVENTOUT TIMx_IC3 EVENTOUT PC10 USART3_ TX COM4 / SEG28 / SEG40 PC11 USART3_ RX COM5 / SEG29 / SEG41 TIMx_IC4 EVENTOUT PC12 USART3_ CK COM6 / SEG30 / SEG42 TIMx_IC1 EVENTOUT RTC_AF1 / WKUP2 TIMx_IC2 EVENTOUT PC14OSC32_IN OSC32_IN TIMx_IC3 EVENTOUT PC15OSC32_OUT OSC32_OUT PD0 37/109 PD1 TIMx_IC4 EVENTOUT TIM9_CH1 SPI2_NSS TIMx_IC1 EVENTOUT SPI2_SCK TIMx_IC2 EVENTOUT Pin descriptions PC13RTC_AF1 STM32L151xx, STM32L152xx Table 5. Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM PD2 TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A USBFS LCD COM7 / SEG31 / SEG43 TIM3_ETR N/A N/A RI SYSTEM TIMx_IC3 EVENTOUT Doc ID 17659 Rev 6 PD3 SPI2_MISO USART2_ CTS TIMx_IC4 EVENTOUT PD4 SPI2_MOSI USART2_ RTS TIMx_IC1 EVENTOUT PD5 USART2_ TX TIMx_IC2 EVENTOUT PD6 USART2_ RX TIMx_IC3 EVENTOUT USART2_ CK TIMx_IC4 EVENTOUT PD7 TIM9_CH2 Pin descriptions 38/109 Table 5. USART3_ TX SEG28 TIMx_IC1 EVENTOUT PD9 USART3_ RX SEG29 TIMx_IC2 EVENTOUT PD10 USART3_ CK SEG30 TIMx_IC3 EVENTOUT PD11 USART3_ CTS SEG31 TIMx_IC4 EVENTOUT USART3_ RTS SEG32 TIMx_IC1 EVENTOUT PD12 TIM4_CH1 PD13 TIM4_CH2 SEG33 TIMx_IC2 EVENTOUT PD14 TIM4_CH3 SEG34 TIMx_IC3 EVENTOUT PD15 TIM4_CH4 SEG35 TIMx_IC4 EVENTOUT PE0 TIM4_ETR TIM10_CH1 SEG36 TIMx_IC1 EVENTOUT PE1 TIM11_CH1 SEG37 TIMx_IC2 EVENTOUT PE2 TRACECK TIM3_ETR SEG 38 TIMx_IC3 EVENTOUT PE3 TRACED0 TIM3_CH1 SEG 39 TIMx_IC4 EVENTOUT STM32L151xx, STM32L152xx PD8 Alternate function input/output (continued) Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 TIM3_CH2 N/A USART 1/2/3 N/A N/A USBFS LCD N/A N/A RI SYSTEM PE4 TRACED1 TIMx_IC1 EVENTOUT PE5 TRACED2 TIM9_CH1* TIMx_IC2 EVENTOUT PE6 TRACED3 / WKUP3 TIM9_CH2* TIMx_IC3 EVENTOUT PE7 TIMx_IC4 EVENTOUT PE8 TIMx_IC1 EVENTOUT Doc ID 17659 Rev 6 PE9 TIM2_CH1_ ETR TIMx_IC2 EVENTOUT PE10 TIM2_CH2 TIMx_IC3 EVENTOUT PE11 TIM2_CH3 TIMx_IC4 EVENTOUT PE12 TIM2_CH4 SPI1_NSS TIMx_IC1 EVENTOUT PE13 SPI1_SCK TIMx_IC2 EVENTOUT PE14 SPI1_MISO TIMx_IC3 EVENTOUT PE15 SPI1_MOSI TIMx_IC4 EVENTOUT STM32L151xx, STM32L152xx Table 5. PH0-OSC_IN OSC_IN PH1OSC_OUT OSC_OUT PH2 Pin descriptions 39/109 Memory mapping 5 STM32L151xx, STM32L152xx Memory mapping The memory map is shown in the following figure.Figure 9.Memory map APB memory space 0xFFFF FFFF reserved 0xE010 0000 reserved 0x6000 0000 reserved 0x4002 6400 DMA 0x4002 6000 reserved 0xFFFF FFFF 0x4002 4000 Flash Interface 0x4002 3C00 7 0xE010 0000 0xE000 0000 0x4002 3800 RCC reserved 0x4002 3400 Cortex- M3 Internal Peripherals 0x4002 3000 0x4002 1800 0x4002 1400 0x4002 1000 6 0x4002 0C00 0x4002 0800 0xC000 0000 0x4002 0400 0x4002 0000 CRC reserved Port H Port E Port D Port C Port B Port A reserved 0x4001 3C00 5 0x4001 3800 0x4001 3400 USART1 reserved SPI1 0xA000 0000 0x4001 3000 reserved 0x4001 2800 ADC 0x4001 2400 4 rese rve d 0x4001 1400 TIM11 0x4001 1000 0x8000 0000 TIM10 0x4001 0C00 TIM9 0x4001 0800 EXTI 3 0x4001 0400 0x1FF8 001F Option Bytes 0x1FF8 0000 0x6000 0000 0x4001 0000 SYSCFG reserved rese rved COMP + RI 0x1FF0 0FFF 0x4000 7C00 reserved rese rved 2 DAC1 & 2 System memory 0x4000 0000 0x4000 7800 Peripherals 0x4000 7400 PWR 0x4000 7000 reserved 0x1FF0 0000 0x4000 6200 0x4000 6000 512 byte USB USB Reg isters 0x4000 5C00 1 I2C2 0x4000 5800 I2C1 0x2000 0000 rese rved SRAM 0x4000 5400 reserved 0x4000 4C00 USART3 0x4000 4800 USART2 0 0x4000 4400 reserved 0x0808 0FFF 0x0808 0000 Data EEPROM rese rved 0x0000 0000 0x4000 3C00 SPI2 0x4000 3800 reserved 0x4000 3400 IWDG 0x0801 FFFF 0x4000 3000 WWDG 0x4000 2C00 Flash memory Reserved 0x4000 2800 0x4000 2400 0x0800 0000 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 0x4000 1C00 0x4000 1400 0x4000 1000 RTC LCD reserved TIM7 TIM6 reserved 0x4000 0C00 TIM4 0x4000 0800 0x4000 0400 0x4000 0000 TIM3 TIM2 ai18200b 40/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.6 V (for the 1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage 34-,XXX PIN 34-,XXX PIN # P& 6). AI Doc ID 17659 Rev 6 AI 41/109 Electrical characteristics 6.1.6 STM32L151xx, STM32L152xx Power supply scheme Figure 12. Power supply scheme OUT GP I/Os IN Level shifter Standby-power circuitry (OSC32K,RTC, Wake-up logic RTC backup registers) IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD1/2/.../5 Regulator 11 x 100 nF + 1 x 4.7 F VSS1/2/.../5 VDD VDDA VREF 10 nF + 1 F 10 nF + 1 F VREF+ ADC VREF- Analog: RCs, PLL, ... VSSA ai15401c Caution: In this figure, the 4.7 F capacitor must be connected to VDD2. 6.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme IDD VDD VDDA ai14126b 42/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD-VSS VIN(2) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five-volt tolerant pin VSS -0.3 VDD+4.0 Input voltage on any other pin VSS - 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) |VDDx| Variations between different VDD power pins 50 |VSSX - VSS| Variations between all different ground pins 50 VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.10 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 7 for maximum allowed injected current values. Table 7. Symbol IVDD IVSS Current characteristics Ratings Max. Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin IIO IINJ(PIN) (2) IINJ(PIN) Output current sourced by any I/O and control pin Injected current on five-volt tolerant Injected current on any other pin I/O(3) (4) Total injected current (sum of all I/O and control pins)(5) Unit 80 80 25 - 25 mA +0 /-5 5 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.16. 3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 6 for maximum allowed input voltage values. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Doc ID 17659 Rev 6 43/109 Electrical characteristics Table 8. STM32L151xx, STM32L152xx Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Table 9. Value Unit -65 to +150 C 150 C General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 32 fPCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power on 1.8 3.6 BOR detector disabled, after power on 1.65 3.6 1.65 3.6 VDD VDDA(1) Standard operating voltage Analog operating voltage (ADC and DAC not used) Analog operating voltage (ADC or DAC used) PD Power dissipation at TA = 85 C(3) TA Temperature range TJ Junction temperature range Conditions Must be the same voltage as VDD(2) Unit MHz V V 1.8 3.6 290 Maximum power dissipation -40 85 Low power dissipation(4) -40 105 -40 C TA 105 C -40 105 mW C C 1. When the ADC is used, refer to Table 50: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 64: Thermal characteristics on page 104). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Table 64: Thermal characteristics on page 104). 44/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Table 10. Electrical characteristics Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range VCORE Maximum CPU frequency (fCPU max) I/O operation Not functional Not functional Range 2 or range 3 16 MHz (1ws) 8MHz (0ws) - Degraded speed performance VDD = 1.8 to 2.0 V Conversion time up to 500 Ksps Not functional Range 2 or range 3 16 MHz (1ws) 8MHz (0ws) - Degraded speed performance VDD = 2.0 to 2.4 V Conversion Range 1, range time up to 500 Functional(1) 2 or range 3 Ksps 32 MHz (1ws) 16MHz (0ws) - Full speed operation 32 MHz (1ws) 16MHz (0ws) - Full speed operation Operating power supply range DAC and ADC operation USB VDD = 1.65 to 1.8 V VDD = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(1) Range 1, range 2 or range 3 1. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V. Doc ID 17659 Rev 6 45/109 Electrical characteristics 6.3.2 STM32L151xx, STM32L152xx Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 9. Table 11. Symbol Embedded reset and power control block characteristics Parameter VDD rise time rate tVDD(1) VDD fall time rate TRSTTEMPO(1) Reset temporization VPOR/PDR Power on/power down reset threshold VBOR0 Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 Conditions Min Typ Max BOR detector enabled 0 BOR detector disabled 0 1000 BOR detector enabled 20 BOR detector disabled 0 1000 VDD rising, BOR enabled 2 3.3 0.4 0.7 1.6 Falling edge 1 1.5 1.65 Rising edge 1.3 1.5 1.65 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 Falling edge 2.45 2.55 2.60 Rising edge 2.54 2.66 2.7 Falling edge 2.68 2.8 2.85 Rising edge 2.78 2.9 2.95 Falling edge 1.8 1.85 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 VDD rising, BOR disabled Unit s/V ms V 46/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Table 11. Symbol VPVD6 Vhyst Electrical characteristics Embedded reset and power control block characteristics (continued) Parameter Conditions Min Typ Max Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 PVD threshold 6 Hysteresis voltage Unit V BOR0 threshold 40 All BOR and PVD thresholds excepting BOR0 100 mV 1. Guaranteed by characterisation, not tested in production. Doc ID 17659 Rev 6 47/109 Electrical characteristics 6.3.3 STM32L151xx, STM32L152xx Embedded internal reference voltage The parameters given in Table 12 are based on characterization results, unless otherwise specified. Table 12. Embedded internal reference voltage Symbol Parameter VREFINT out(1) Internal reference voltage IREFINT Internal reference current consumption TVREFINT Internal reference startup time VVREF_MEAS VDDA and VREF+ voltage during VREFINT factory measure AVREF_MEAS Accuracy of factory-measured VREF value(2) Min Typ Max Unit - 40 C < TJ < +105 C 1.202 1.224 1.242 V 1.4 2.3 A 2 3 ms 3 3.01 V 5 mV 2.99 Including uncertainties due to ADC and VDDA/VREF+ values -40 C < TJ < +105 C TCoeff(3) Temperature coefficient ACoeff(3) VDDCoeff(3) TS_vrefint(3)(4) ADC sampling time when reading the internal reference voltage TADC_BUF(3) Startup time of reference voltage buffer for ADC IBUF_ADC(3) Consumption of reference voltage buffer for ADC IVREF_OUT(3) CVREF_OUT(3) ILPBUF(3) Conditions 20 50 ppm/C 0 C < TJ < +50 C 20 Long-term stability 1000 hours, T= 25 C 1000 ppm Voltage coefficient 3.0 V < VDDA < 3.6 V 2000 ppm/V 10 s 10 s 25 A VREF_OUT output current(5) 1 A VREF_OUT output load 50 pF 730 1200 nA 5 13.5 Consumption of reference voltage buffer for VREF_OUT and COMP VREFINT_DIV1(3) 1/4 reference voltage 24 25 26 VREFINT_DIV2(3) 1/2 reference voltage 49 50 51 VREFINT_DIV3(3) 3/4 reference voltage 74 75 76 1. Tested in production; 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 5. To guarantee less than 1% VREF_OUT deviation. 48/109 Doc ID 17659 Rev 6 % VREFINT STM32L151xx, STM32L152xx 6.3.4 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: VDD = 3.6 V All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted depending on fHCLK frequency and voltage range Prefetch and 64-bit access are enabled in configurations with 1 wait state The parameters given in Table 13, Table 9 and Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 13. Current consumption in Run mode, code with data processing running from Flash Conditions Symbol Parameter Range 3, VCORE=1.2 V VOS[1:0] = 11 IDD (Run from Flash) Supply current in Run mode, code executed from Flash fHSE = fHCLK up to 8 MHz, included fHSE = fHCLK/2 above 8 MHz (PLL ON)(2) HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 2, VCORE=1.5 V VOS[1:0] = 10 Max(1) fHCLK Typ Unit 1 MHz 270 400 400 400 2 MHz 470 600 600 600 4 MHz 890 1025 1025 1025 4 MHz 1 1.3 1.3 1.3 8 MHz 2 2.5 2.5 2.5 16 MHz 3.9 5 5 5 55 C 85 C 105 C Range 1, VCORE=1.8 V VOS[1:0] = 01 8 MHz 2.16 3 3 3 16 MHz 4.8 5.5 5.5 5.5 32 MHz 9.6 11 11 11 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 4 5 5 5 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 9.4 11 11 11 65 kHz 0.05 0.085 0.09 0.1 524 kHz 0.15 0.185 0.19 0.2 4.2 MHz 0.9 1 1 1 Range 3, VCORE=1.2 V VOS[1:0] = 11 A mA 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Doc ID 17659 Rev 6 49/109 Electrical characteristics Table 14. STM32L151xx, STM32L152xx Current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 Supply current in Run mode, IDD (Run code executed from from RAM, RAM) Flash switched off fHSE = fHCLK up to 8 MHz, included fHSE = fHCLK/2 above 8 MHz (PLL ON)(2) Typ 1 MHz 200 300 300 300 2 MHz 380 500 500 500 4 MHz 720 860 860 4 MHz 0.9 1 1 1 8 MHz 1.65 2 2 2 16 MHz 3.2 3.7 3.7 3.7 8 MHz 2 2.5 2.5 2.5 16 MHz 4 4.5 4.5 4.5 32 MHz 7.7 8.5 8.5 8.5 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 3.3 3.8 3.8 3.8 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 7.8 9.2 9.2 9.2 65 kHz 40 60 60 80 524 kHz 110 140 140 160 4.2 MHz 700 800 800 820 Range 2, VCORE=1.5 V VOS[1:0] = 10 MSI clock, 65 kHz Range 3, MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 3. Tested in production. 50/109 Unit 55 C 85 C 105 C 860(3) Range 1, VCORE=1.8 V VOS[1:0] = 01 HSI clock source (16 MHz) fHCLK Doc ID 17659 Rev 6 A mA A STM32L151xx, STM32L152xx Table 15. Electrical characteristics Current consumption in Sleep mode Max(1) Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 HSE = 16 MHz(2) (PLL ON for fHCLK >16 MHz) Supply current in Sleep mode, code executed from RAM, Flash switched HSI clock source OFF (16 MHz) Range 2, VCORE=1.5 V VOS[1:0] = 10 Supply current in Sleep mode, code executed from Flash HSI clock source (16 MHz) IDD (Sleep) 1 MHz 80 140 140 140 2 MHz 150 210 210 210 4 MHz 280 330 330 330(3) 4 MHz 280 400 400 400 8 MHz 450 550 550 550 16 MHz 900 1050 1050 1050 8 MHz 550 650 650 16 MHz 1050 1200 1200 1200 32 MHz 2300 2500 2500 2500 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 1000 1100 1100 1100 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 2300 2500 2500 2500 Range 3, VCORE=1.2 V VOS[1:0] = 11 HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz) Unit 55 C 85 C 105 C 650 Range 3, MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz (Sleep) Typ Range 1, VCORE=1.8 V VOS[1:0] = 01 MSI clock, 65 kHz IDD fHCLK Range 2, VCORE=1.5 V VOS[1:0] = 10 65 kHz 30 50 50 60 524 kHz 50 70 70 80 4.2 MHz 200 240 240 250 1 MHz 80 140 140 140 2 MHz 150 210 210 210 4 MHz 290 350 350 350 4 MHz 300 400 400 400 8 MHz 500 600 600 600 16 MHz 1000 1100 1100 1100 8 MHz Range 1, VCORE=1.8 V VOS[1:0] = 01 650 650 650 16 MHz 1050 1200 1200 1200 32 MHz 2300 2500 2500 2500 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 1000 1100 1100 1100 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 2300 2500 2500 2500 Supply MSI clock, 65 kHz current in MSI clock, 524 kHz Sleep Range 3, mode, VCORE=1.2V VOS[1:0] = 11 code MSI clock, 4.2 MHz executed from Flash 550 65 kHz 40 70 70 80 524 kHz 60 90 90 100 A A A 4.2 MHz Doc ID 17659 Rev 6 210 250 250 260 51/109 Electrical characteristics STM32L151xx, STM32L152xx 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) 3. Tested in production Table 16. Symbol Current consumption in Low power run mode Parameter Conditions All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.65 V to 3.6 V IDD (LP Run) Supply current in Low power run mode Max allowed current in Low power run mode MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz MSI clock, 65 kHz fHCLK = 32 kHz All peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V IDD Max (LP Run)(2) MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz Typ TA = -40 C to 25 C Max (1) 9 12 TA = 85 C 17.5 24 TA = 105 C 31 46 TA = -40 C to 25 C 14 17 TA = 85 C 22 29 TA = 105 C 35 51 TA = -40 C to 25 C 37 42 TA = 55 C 37 42 TA = 85 C 37 42 TA = 105 C 48 65 TA = -40 C to 25 C 24 32 TA = 85 C 33 42 TA = 105 C 48 64 TA = -40 C to 25 C 31 40 TA = 85 C 40 48 TA = 105 C 54 70 TA = -40 C to 25 C 48 58 TA = 55 C 54 63 TA = 85 C 56 65 TA = 105 C 70 90 VDD from 1.65 V to 3.6 V 200 1. Based on characterization, not tested in production, unless otherwise specified. 2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator. Consumption of the I/Os is not included in this limitation. 52/109 Doc ID 17659 Rev 6 Unit A STM32L151xx, STM32L152xx Table 17. Symbol Electrical characteristics Current consumption in Low power sleep mode Parameter Conditions MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF MSI clock, 65 kHz fHCLK = 32 kHz Flash ON All peripherals OFF, VDD MSI clock, 65 kHz from 1.65 V f HCLK = 65 kHz, to 3.6 V Flash ON IDD (LP Sleep) Typ TA = -40 C to 25 C MSI clock, 65 kHz fHCLK = 32 kHz TIM9 and USART1 enabled, Flash ON, VDD from 1.65 V to 3.6 V MSI clock, 65 kHz fHCLK = 65 kHz (1) 25 TA = 85 C 22 27 TA = 105 C 31 39 TA = -40 C to 25 C 18 26 TA = 85 C 23 28 TA = 105 C 31 40 22 30 24 32 26 34 34 45 TA = -40 C to 25 C 17.5 25 TA = 85 C 22 27 TA = 105 C 31 39 TA = -40 C to 25 C 18 26 TA = 85 C 23 28 TA = 105 C 31 40 TA = -40 C to 25 C 22 30 24 32 26 34 34 45 MSI clock, 131 kHz TA = 55 C fHCLK = 131 kHz TA = 85 C TA = 105 C Max allowed VDD from current in IDD Max 1.65 V to (LP Sleep) Low power 3.6 V Sleep mode Unit 4.4 TA = -40 C to 25 C 17.5 TA = -40 C to 25 C MSI clock, 131 kHz T = 55 C A fHCLK = 131 kHz, TA = 85 C Flash ON TA = 105 C Supply current in Low power sleep mode Max A 200 1. Based on characterization, not tested in production, unless otherwise specified. Doc ID 17659 Rev 6 53/109 Electrical characteristics Table 18. Symbol STM32L151xx, STM32L152xx Typical and maximum current consumptions in Stop mode Parameter Typ Max(1) Unit Conditions LCD OFF RTC clocked by LSI, regulator in LP mode, HSI and HSE OFF (no independent watchdog) LCD ON (static duty)(2) LCD ON (1/8 duty)(3) LCD OFF Supply current in Stop mode with with RTC) RTC enabled IDD (Stop RTC clocked by LSE external clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no independent watchdog) LCD ON (static duty)(2) LCD ON (1/8 duty)(3) TA = -40C to 25C 1.9 4 TA = 55C 3.1 6 TA= 85C 6.2 10 TA = 105C 14 23 TA = -40C to 25C 4 6 TA = 55C 5 8 TA= 85C 8 12 TA = 105C 18 27 TA = -40C to 25C 8 10 TA = 55C 9 12 TA= 85C 12 16 TA = 105C 25 40 TA = -40C to 25C 1.9 4 TA = 55C 3.1 6 TA= 85C 6.2 10 TA = 105C 14 23 TA = -40C to 25C 4 6 TA = 55C 5 8 TA= 85C 8 12 TA = 105C 14 23 TA = -40C to 25C 8 10 TA = 55C 9 12 TA= 85C 12 16 TA = 105C 25 40 A TA = -40C to 25C 1.45 VDD = 1.8V RTC clocked by LSE (no independent watchdog)(4) T = -40C to 25C LCD OFF A VDD = 3.0V 1.9 TA = -40C to 25C VDD = 3.6V 2.2 Regulator in LP mode, HSI and HSE OFF, independent watchdog TA = -40C to 25C and LSI enabled 1.6 2.2 TA = -40C to 25C 0.6 0.9 TA = 55C 2.5 5 TA= 85C 5 8 TA = 105C 12.5 20(5) Supply current in IDD (Stop) Stop mode ( RTC disabled) Regulator in LP mode, LSI, HSI and HSE OFF (no independent watchdog) 54/109 Doc ID 17659 Rev 6 A STM32L151xx, STM32L152xx Table 18. Symbol Electrical characteristics Typical and maximum current consumptions in Stop mode Parameter Typ Max(1) Unit Conditions 2 RMS (root mean MSI = 4.2 MHz square) supply MSI = 1.05 MHz IDD (WU current during from Stop) wakeup time when exiting MSI = 65 kHz(6) from Stop mode VDD = 3.0 V TA = -40C to 25C 1.45 mA 1.45 1. Based on characterization, not tested in production, unless otherwise specified 2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected 3. LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. 5. Tested in production 6. When MSI = 64 kHz, the RMS current is measured over the first 15 s following the wakeup event. For the remaining time of the wakeup period, the current is similar to the Run mode current. Table 19. Symbol Typical and maximum current consumptions in Standby mode Parameter Conditions Typ TA = -40 C to 25 C 1.4 1.8 TA = 55 C 1.55 2.5 TA= 85 C 2.2 3 TA = 105 C 3.5 5 TA = -40 C to 25 C 1.55 2.9 TA = 55 C 1.7 3.4 TA= 85 C 2.3 4.3 TA = 105 C 4.1 6.3 Independent watchdog and TA = -40 C to 25 C LSI enabled 1.2 1.6 TA = -40 C to 25 C 0.3 0.55 0.5 0.8 1 1.7 TA = 105 C 2.5 4(3) VDD = 3.0 V TA = -40 C to 25 C 0.95 RTC clocked by LSI (no independent watchdog) IDD (Standby Supply current in Standby mode with RTC enabled with RTC) RTC clocked by LSE (no independent watchdog)(2) Supply current in Standby (Standby) mode (RTC disabled) Max(1) Unit IDD Independent watchdog and TA = 55 C LSI OFF TA = 85 C IDD (WU RMS supply current during wakeup time when exiting from Standby) from Standby mode A mA 1. Based on characterization, not tested in production, unless otherwise specified 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. 3. Tested in production Doc ID 17659 Rev 6 55/109 Electrical characteristics STM32L151xx, STM32L152xx Wakeup time from Low power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: Sleep mode: the clock source is the clock that was set before entering Sleep mode Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 20. Typical and maximum timings in Low power modes Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEP_LP Wakeup from Low power sleep mode fHCLK = 262 kHz tWUSTDBY Max(1) Unit 0.36 fHCLK = 262 kHz Flash enabled 32 fHCLK = 262 kHz Flash switched OFF 34 fHCLK = fMSI = 4.2 MHz 8.2 fHCLK = fMSI = 4.2 MHz Voltage range 1 and 2 8.2 9.3 fHCLK = fMSI = 4.2 MHz Voltage range 3 7.8 11.2 10 12 15.5 20 fHCLK = fMSI = 524 kHz 29 35 fHCLK = fMSI = 262 kHz 53 63 fHCLK = fMSI = 131 kHz 105 118 fHCLK = MSI = 65 kHz 210 237 Wakeup from Standby mode fHCLK = MSI = 2.1 MHz FWU bit = 1 50 103 Wakeup from Standby mode fHCLK = MSI = 2.1 MHz FWU bit = 0 2.5 3.2 fHCLK = fMSI = 2.1 MHz Wakeup from Stop mode, regulator in low power mode fHCLK = fMSI = 1.05 MHz 1. Based on characterization, not tested in production, unless otherwise specified 56/109 Typ fHCLK = 32 MHz Wakeup from Stop mode, regulator in Run mode tWUSTOP Conditions Doc ID 17659 Rev 6 s ms STM32L151xx, STM32L152xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on Table 21. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run TIM2 13 10.5 8 10.5 TIM3 14 12 9 12 TIM4 12.5 10.5 8 11 TIM6 5.5 4.5 3.5 4.5 TIM7 5.5 5 3.5 4.5 LCD 5.5 5 3.5 5 4 3.5 2.5 3.5 5.5 5 4 5 USART2 9 8 5.5 8.5 USART3 10.5 9 6 8 I2C1 8.5 7 5.5 7.5 I2C2 8.5 7 5.5 6.5 USB 12.5 10 6.5 10 PWR 4.5 4 3 3.5 DAC 9 7.5 6 7 4.5 4 3.5 4.5 Peripheral WWDG SPI2 APB1 COMP Doc ID 17659 Rev 6 Unit A/MHz (fHCLK) 57/109 Electrical characteristics Table 21. STM32L151xx, STM32L152xx Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run SYSCFG & RI 3 2.5 2 2.5 TIM9 9 7.5 6 7 TIM10 6.5 5.5 4.5 5.5 TIM11 7 6 4.5 5.5 ADC 11.5 9.5 8 9 SPI1 5 4.5 3 4 USART1 9 7.5 6 7.5 GPIOA 5 4.5 3.5 4 GPIOB 5 4.5 3.5 4.5 GPIOC 5 4.5 3.5 4.5 GPIOD 5 4.5 3.5 4.5 GPIOE 5 4.5 3.5 4.5 GPIOH 4 4 3 3.5 CRC 1 0.5 0.5 0.5 FLASH 13 11.5 9 18.5 DMA1 12 10 8 10.5 166 138 106 130 Peripheral APB2 (2) AHB All enabled IDD (RTC) 0.47 IDD (LCD) 3.1 IDD (ADC)(3) 1450 IDD (DAC)(4) 340 IDD (COMP1) 0.16 IDD (COMP2) IDD (PVD / BOR) Slow mode 2 Fast mode 5 (5) Unit A/MHz (fHCLK) A 2.6 IDD (IWDG) 0.25 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production. 2. HSI oscillator is OFF for this measure. 3. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 58/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics 4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 5. Including supply current of internal reference voltage. 6.3.5 External clock source characteristics High-speed external user clock generated from an external source Table 22. High-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit 1 8 32 MHz fHSE_ext User external clock source frequency VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time tr(HSE) tf(HSE) OSC_IN rise or fall time Cin(HSE) 12 ns 20 OSC_IN input capacitance 2.6 DuCy(HSE) Duty cycle IL V 45 OSC_IN Input leakage current VSS VIN VDD pF 55 % 1 A 1. Guaranteed by design, not tested in production. Doc ID 17659 Rev 6 59/109 Electrical characteristics STM32L151xx, STM32L152xx Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 23. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit 1 32.768 1000 kHz fLSE_ext User external clock source frequency VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS tw(LSE) tw(LSE) OSC32_IN high or low time TBD tr(LSE) tf(LSE) OSC32_IN rise or fall time VDD 0.7VDD V CIN(LSE) ns TBD OSC32_IN input capacitance 0.6 DuCy(LSE) Duty cycle IL 0.3VDD TBD OSC32_IN Input leakage current VSS VIN VDD pF TBD % 1 A 1. Guaranteed by design, not tested in production Figure 14. Low-speed external clock source AC timing diagram 6,3%( 6,3%, TR,3% TF,3% T7,3% T7,3% T 4,3% %84%2 .!, #,/#+ 3/52# % F,3%?EXT /3#?). ), 34-,XX AI 60/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 15. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% /3# ?). ), T7(3% T 4(3% %84%2 .!, #,/#+ 3/52# % F(3%?EXT 34-,XX AI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 17659 Rev 6 61/109 Electrical characteristics Table 24. Symbol STM32L151xx, STM32L152xx HSE 1-24 MHz oscillator characteristics(1)(2) Parameter Conditions fOSC_IN Oscillator frequency 1 RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) IHSE IDD(HSE) gm tSU(HSE) (4) HSE driving current HSE oscillator power consumption Oscillator transconductance Startup time Min Typ RS = 30 Max Unit 24 MHz 200 k 20 pF VDD= 3.3 V, VIN = VSS with 30 pF load 3 C = 20 pF fOSC = 16 MHz 2.5 (startup) 0.7 (stabilized) C = 10 pF fOSC = 16 MHz 2.5 (startup) 0.46 (stabilized) Startup VDD is stabilized mA mA mA /V 3.5 1 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. 62/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 16. HSE oscillator circuit diagram F(3% TO CORE 2M ,M 2& #/ #, /3#?). #M GM 2ESONATOR #ONSUMPTION CONTROL 2ESONATOR 34- /3#?/54 #, AI 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 25. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 25. Symbol LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Parameter fLSE Low speed external oscillator frequency RF Feedback resistor C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) ILSE LSE driving current IDD (LSE) (4) Min RS = 30 k Typ LSE oscillator current consumption Startup time Max Unit 32.768 kHz 1.2 M 8 pF VDD = 3.3 V, VIN = VSS 1.1 VDD = 1.8 V 450 VDD = 3.0 V 600 VDD = 3.6V 750 Oscillator transconductance gm tSU(LSE) Conditions A nA 3 VDD is stabilized A/V 1 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details; 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Doc ID 17659 Rev 6 63/109 Electrical characteristics STM32L151xx, STM32L152xx Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 17. Typical application with a 32.768 kHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F,3% /3#?). K( Z RESONATOR #, 2& "IAS CONTROLLED GAIN /3#?/5 4 34-,XXX AI 64/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 6.3.6 Electrical characteristics Internal clock source characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 26. Symbol fHSI TRIM (1)(2) HSI oscillator characteristics Parameter Conditions Min Frequency VDD = 3.0 V HSI user-trimmed resolution Trimming code is not a multiple of 16 Accuracy of the ACCHSI(2) factory-calibrated HSI oscillator Typ Max Unit 16 0.4 MHz 0.7 % 1.5 % VDDA = 3.0 V, TA = 25 C -1(3) 1(3) % VDDA = 3.0 V, TA = 0 to 55 C -1.5 1.5 % VDDA = 3.0 V, TA = -10 to 70 C -2 2 % VDDA = 3.0 V, TA = -10 to 85 C -2.5 2 % VDDA = 3.0 V, TA = -10 to 105 C -4 2 % VDDA = 1.65 V to 3.6 V TA = -40 to 105 C -4 3 % Trimming code is a multiple of 16 tSU(HSI)(2) HSI oscillator startup time 3.7 6 s IDD(HSI)(2) HSI oscillator power consumption 100 140 A 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Based on characterization, not tested in production. 3. Tested in production. Low-speed internal (LSI) RC oscillator Table 27. LSI oscillator characteristics Symbol Parameter Min Typ Max Unit 38 56 kHz 4 % 200 s 510 nA fLSI(1) LSI frequency 26 DLSI(2) LSI oscillator frequency drift 0C TA 85C -10 tsu(LSI)(3) IDD(LSI) (3) LSI oscillator startup time LSI oscillator power consumption 400 1. Tested in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design, not tested in production. Doc ID 17659 Rev 6 65/109 Electrical characteristics STM32L151xx, STM32L152xx Multi-speed internal (MSI) RC oscillator Table 28. MSI oscillator characteristics Symbol Parameter Condition Typ MSI range 0 65.5 MSI range 1 131 MSI range 2 262 MSI range 3 524 MSI range 4 1.05 MSI range 5 2.1 MSI range 6 4.2 Max Unit kHz fMSI ACCMSI Frequency error after factory calibration DTEMP(MSI)(1) MSI oscillator frequency drift 0 C TA 85 C DVOLT(MSI)(1) MSI oscillator frequency drift 1.65 V VDD 3.6 V, TA = 25 C IDD(MSI)(2) tSU(MSI) 66/109 Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 C MSI oscillator power consumption MSI oscillator startup time Doc ID 17659 Rev 6 MHz 0.5 % 3 % 2.5 MSI range 0 0.75 MSI range 1 1 MSI range 2 1.5 MSI range 3 2.5 MSI range 4 4.5 MSI range 5 8 MSI range 6 15 MSI range 0 30 MSI range 1 20 MSI range 2 15 MSI range 3 10 MSI range 4 6 MSI range 5 5 MSI range 6, Voltage range 1 and 2 3.5 MSI range 6, Voltage range 3 5 %/V A s STM32L151xx, STM32L152xx Table 28. Electrical characteristics MSI oscillator characteristics (continued) Symbol tSTAB(MSI)(2) fOVER(MSI) Parameter Condition MSI oscillator stabilization time Typ Max MSI range 0 40 MSI range 1 20 MSI range 2 10 MSI range 3 4 MSI range 4 2.5 MSI range 5 2 MSI range 6, Voltage range 1 and 2 2 MSI range 3, Voltage range 3 3 Any range to range 5 4 MSI oscillator frequency overshoot Unit s MHz Any range to range 6 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Based on characterization, not tested in production. 6.3.7 PLL characteristics The parameters given in Table 29 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 29. PLL characteristics Value Symbol Parameter Min Typ Max(1) Unit PLL input clock(2) 2 24 MHz PLL input clock duty cycle 45 55 % fPLL_OUT PLL output clock 2 32 MHz tLOCK Worst case PLL lock time PLL input = 2 MHz PLL VCO = 96 MHz 130 s Jitter Cycle-to-cycle jitter 600 ps IDDA(PLL) Current consumption on VDDA 220 450 IDD(PLL) Current consumption on VDD 120 150 fPLL_IN 100 A 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Doc ID 17659 Rev 6 67/109 Electrical characteristics 6.3.8 STM32L151xx, STM32L152xx Memory characteristics The characteristics are given at TA = -40 to 105 C unless otherwise specified. RAM memory Table 30. Symbol VRM RAM and hardware registers Parameter Conditions Data retention mode(1) STOP mode (or RESET) Min Typ Max 1.65 Unit V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Flash memory Table 31. Symbol Flash memory characteristics Parameter VDD Operating voltage Read / Write / Erase tprog Programming time for word or half-page Conditions Max(1) Unit 3.6 V Erasing 3.28 3.94 Programming 3.28 3.94 ms Maximum current (peak) during programme/erase operation 300 A TA = 25 C, VDD = 3.6 V 1. Guaranteed by design, not tested in production. 68/109 Typ 1.65 Average current during whole programme/erase operation IDD Min Doc ID 17659 Rev 6 1.5 2.5 mA STM32L151xx, STM32L152xx Table 32. Electrical characteristics Flash memory endurance and data retention Value Symbol NCYC(2) Parameter Cycling (erase / write ) Program memory Cycling (erase / write ) EEPROM data memory Data retention (program memory) after 10 kcycles at TA = 85 C tRET(2) Data retention (EEPROM data memory) after 300 kcycles at TA = 85 C Data retention (program memory) after 10 kcycles at TA = 105 C Data retention (EEPROM data memory) after 300 kcycles at TA = 105 C Conditions Unit Min(1) Typ Max 10 TA = -40C to 105 C kcycles 300 30 TRET = +85 C 30 years 10 TRET = +105 C 10 1. Based on characterization not tested in production. 2. Characterization is done according to JEDEC JESD22-A117. 6.3.9 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 33. They are based on the EMS levels and classes defined in application note AN1709. Table 33. Symbol EMS characteristics Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 32 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 32 MHz conforms to IEC 61000-4-4 4A Doc ID 17659 Rev 6 69/109 Electrical characteristics STM32L151xx, STM32L152xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 34. EMI characteristics Max vs. frequency range Symbol Parameter SEMI 70/109 Conditions VDD = 3.3 V, TA = 25 C, Peak level LQFP100 package compliant with IEC 61967-2 Monitored frequency band 4 MHz 16 MHz 32 MHz voltage voltage voltage range 3 range 2 range 1 0.1 to 30 MHz 3 -6 -5 30 to 130 MHz 18 4 -7 130 MHz to 1GHz 15 5 -7 SAE EMI Level 2.5 2 1 Doc ID 17659 Rev 6 Unit dBV - STM32L151xx, STM32L152xx 6.3.10 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 35. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge TA = +25 C, conforming voltage (human body model) to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge TA = +25 C, conforming voltage (charge device model) to JESD22-C101 II 500 V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 36. Symbol LU 6.3.11 Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Doc ID 17659 Rev 6 71/109 Electrical characteristics STM32L151xx, STM32L152xx Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 37. I/O current injection susceptibility Functional susceptibility Symbol IINJ 72/109 Description Negative injection Positive injection Injected current on true open-drain pins -5 +0 Injected current on all 5 V tolerant (FT) pins -5 +0 Injected current on any other pin -5 +5 Doc ID 17659 Rev 6 Unit mA STM32L151xx, STM32L152xx 6.3.12 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 38. I/O static characteristics Symbol VIL Parameter Conditions Input low level voltage VIL FT (2) Standard I/O Input high level voltage CMOS ports 1.65 V VDD 3.6 V CMOS ports 1.65 V VDD 2.0 V VIH VDD+0.3 2(1) I/O input high level voltage 0.3VDD(3) -0.3 VDD+0.3 0.7 VDD(3)(4) Ilkg RPU Standard I/O Schmitt trigger voltage hysteresis(6) Weak pull-up equivalent resistor(9)(3) Weak pull-down equivalent CIO I/O pin capacitance 5.5 10% VDD(7) Input leakage current (8)(3) RPD V 5.25 CMOS ports 2.0 VVDD 3.6 V Vhys Unit 5.5V CMOS ports 1.65 V VDD 3.6 V FT Max 0.8 I/O input high level voltage Input low level voltage (5) Typ VSS - 0.3 TTL ports 2.7 V VDD3.6 V Standard I/O input high level voltage VIH Min resistor(9)(3) VSS VIN VDD I/Os with LCD 50 VSS VIN VDD I/Os with analog switches 50 VSS VIN VDD I/Os with analog switches and LCD 50 VSS VIN VDD I/Os with USB TBD VSS VIN VDD Standard I/Os 50 nA VIN = VSS 30 45 60 k VIN = VDD 30 45 60 k 5 pF 1. Guaranteed by design. 2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled. 3. Tested in production 4. 0.7VDD for 5V-tolerant receiver 5. FT = Five-volt tolerant. 6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 7. With a minimum of 200 mV. Based on characterization, not tested in production. 8. The max. value may be exceeded if negative current is injected on adjacent pins. Doc ID 17659 Rev 6 73/109 Electrical characteristics STM32L151xx, STM32L152xx 9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with the non-standard VOL/VOH specifications given in Table 39. in the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 39. Output voltage characteristics Symbol Parameter VOL(1)(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3)(4) Conditions IIO = +8 mA 2.7 V < VDD < 3.6 V IIO =+ 4 mA 1.65 V < VDD < 2.7 V Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 4 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 4 pins are sourced at same time IIO = +20 mA 2.7 V < VDD < 3.6 V Min Max Unit 0.4 2.4 0.45 V VDD-0.45 1.3 VDD-1.3 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. Tested in production. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. 74/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 18 and Table 40, respectively. Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 40. OSPEEDRx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 00 tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) 01 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 10 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 11 - tf(IO)out tr(IO)out Output rise and fall time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Max(2) CL = 50 pF, VDD = 2.7 V to 3.6 V 400 CL = 50 pF, VDD = 1.65 V to 2.7 V TBD CL = 50 pF, VDD = 2.7 V to 3.6 V 625 CL = 50 pF, VDD = 1.65 V to 2.7 V TBD CL = 50 pF, VDD = 2.7 V to 3.6 V 2 CL = 50 pF, VDD = 1.65 V to 2.7 V 1 CL = 50 pF, VDD = 2.7 V to 3.6 V 125 CL = 50 pF, VDD = 1.65 V to 2.7 V TBD CL = 50 pF, VDD = 2.7 V to 3.6 V 10 CL = 50 pF, VDD = 1.65 V to 2.7 V 2 CL = 50 pF, VDD = 2.7 V to 3.6 V 25 CL = 50 pF, VDD = 1.65 V to 2.7 V TBD CL = 50 pF, VDD = 2.7 V to 3.6 V 50 CL = 50 pF, VDD = 1.65 V to 2.7 V 8 CL = 30 pF, VDD = 2.7 V to 3.6 V 5 CL = 50 pF, VDD = 1.65 V to 2.7 V TBD Unit kHz ns MHz ns MHz ns MHz ns 8 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xxx reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. Not tested in production. 3. The maximum frequency is defined in Figure 18. Doc ID 17659 Rev 6 75/109 Electrical characteristics STM32L151xx, STM32L152xx Figure 18. I/O AC characteristics definition %XTERNAL /UTPUT ON P& TR ) / OUT TF) / OUT 4 -AXIMUM FREQUENCY IS ACHIEVED IF T R TF a 4 AND IF THE DUTY CYCLE IS WHEN LOADED BY P& AIB 6.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 41. NRST pin characteristics Symbol VIL(NRST) (1) Parameter Conditions NRST input low level voltage VIH(NRST)(1) NRST input high level voltage VOL(NRST) (1) Vhys(NRST)(1) NRST output low level voltage Weak pull-up equivalent resistor(3) VF(NRST)(1) NRST input filtered pulse VNF(NRST)(1) NRST input not filtered pulse Typ Max Unit VSS 0.8 1.4 VDD IOL = 2 mA 2.7 V < VDD < 3.6 V V 0.4 IOL = 1.5 mA 1.65 V < VDD < 2.7 V NRST Schmitt trigger voltage hysteresis RPU Min 10%VDD(2) VIN = VSS 30 350 mV 45 60 k 50 ns ns 1. Guaranteed by design, not tested in production. 2. 200 mV minimum value 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 76/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 19. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL RESET &ILTER & 34-,XXX AI 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 41. Otherwise the reset will not be taken into account by the device. 6.3.14 TIM timer characteristics The parameters given in the following table are guaranteed by design. Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 42. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 31.25 ns Timer resolution time fTIMxCLK = 32 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 32 MHz 0 fTIMxCLK/2 MHz 0 16 MHz 16 bit 65536 tTIMxCLK 2048 s 65536 x 65536 tTIMxCLK 134.2 s Timer resolution 16-bit counter clock period 1 when internal clock is selected (timer's prescaler f TIMxCLK = 32 MHz 0.0312 disabled) tMAX_COUNT Maximum possible count Unit fTIMxCLK = 32 MHz 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. Doc ID 17659 Rev 6 77/109 Electrical characteristics 6.3.15 STM32L151xx, STM32L152xx Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not "true" open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 43. Refer also to Section 6.3.11: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 43. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line s ns 300 s 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode IC frequencies. It must be at least 4 MHz to achieve fast mode IC frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum IC fast mode clock. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 78/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 20. I2C bus AC waveforms and measurement circuit 6$$ 6$$ K1/2 K1/2 1/2 34-,XXX 3$! )# BUS 1/2 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! TSU3$! TW3#+, 3#, TW3#+( TR3#+ TSU34!34/ 3 4/0 TH3$! TSU34/ TF3#+ AI 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 44. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 2 1. RP = External pull-up resistance, fSCL = I C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 17659 Rev 6 79/109 Electrical characteristics STM32L151xx, STM32L152xx SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 6.3.11: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 45. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) SPI characteristics(1) Parameter Conditions Min SPI clock rise and fall time 16 Slave mode 16 Capacitive load: C = 30 pF TBD ns 70 % MHz SPI slave input clock duty Slave mode cycle 30 NSS setup time Slave mode 4tPCLK th(NSS) NSS hold time Slave mode 2tPCLK SCK high and low time Master mode, fPCLK = 16 MHz, presc = 4 tsu(MI) tsu(SI) th(MI) TBD TBD Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 0 3tPCLK TBD TBD Data input setup time Data input hold time th(SI) ta(SO)(3) Data output access time Slave mode, fPCLK = 20 MHz tdis(SO)(4) ns Data output disable time Slave mode (2) Data output valid time Slave mode (after enable edge) TBD tv(MO)(2) Data output valid time Master mode (after enable edge) TBD tv(SO) th(SO)(2) th(MO) (2) Unit Master mode SPI clock frequency tsu(NSS) tw(SCKH) tw(SCKL) Max(2) Slave mode (after enable edge) TBD Master mode (after enable edge) TBD Data output hold time 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z. 80/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 21. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 22. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 17659 Rev 6 81/109 Electrical characteristics STM32L151xx, STM32L152xx Figure 23. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTPUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (full speed). Table 46. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time 1. Guaranteed by design, not tested in production. 82/109 Doc ID 17659 Rev 6 Max Unit 1 s STM32L151xx, STM32L152xx Table 47. Electrical characteristics USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD (4) USB operating voltage(2) I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 VDI Differential input sensitivity Output levels VOL(5) Static output level low RL of 1.5 k to 3.6 V(6) VOH(5) Static output level high RL of 15 k to VSS(6) 0.3 V 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32L15xxx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by characterization, not tested in production. 5. Tested in production. 6. RL is the load connected on the USB drivers. Figure 24. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S Table 48. tr tf ai14137 USB: full speed electrical characteristics Driver characteristics(1) Symbol Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Fall Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm VCRS Parameter Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). Doc ID 17659 Rev 6 83/109 Electrical characteristics 6.3.16 STM32L151xx, STM32L152xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 50 are guaranteed by design. Table 49. Symbol ADC clock frequency Parameter Conditions 2.4 V VDDA 3.6 V fADC ADC clock frequency Voltage range 1 & 2 Min VREF+ = VDDA 16 VREF+ < VDDA VREF+ > 2.4 V 8 VREF+ < VDDA VREF+ 2.4 V 1.8 V VDDA 2.4 V Max 4 0.480 VREF+ = VDDA 8 VREF+ < VDDA 4 Voltage range 3 Table 50. Symbol ADC characteristics Parameter Conditions Min Typ Power supply VREF+ Positive reference voltage VREF- Negative reference voltage VSSA IVDDA Current on the VDDA input pin 1000 VAIN Current on the VREF input pin Conversion voltage 2.4 V VDDA 3.6 V VREF+ must be below or equal to VDDA Max 1.8 3.6 1.8(1) VDDA V A Peak 700 400 Average range(3) 450 0(4) VREF+ Direct channels 0.03 1 Multiplexed channels 0.03 0.76 Direct channels 0.03 1.07 Multiplexed channels 0.03 0.8 Direct channels 0.03 1.23 Multiplexed channels 0.03 0.89 Direct channels 0.03 1.45 Multiplexed channels 0.03 1 V Msps 10-bit sampling rate fS Unit 1450 12-bit sampling rate Msps 8-bit sampling rate Msps 6-bit sampling rate 84/109 MHz 4 VDDA IVREF(2) Unit Msps Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Table 50. Symbol tS Electrical characteristics ADC characteristics (continued) Parameter Sampling time Conditions Min Direct channels 2.4 V VDDA 3.6 V 0.25(5) Multiplexed channels 2.4 V VDDA 3.6 V 0.56(5) Direct channels 1.8 V VDDA 2.4 V 0.56 CADC Internal sample and hold capacitor fTRIG External trigger frequency Regular sequencer fTRIG External trigger frequency Injected sequencer RAIN(6) External input impedance tlat Injection trigger conversion latency fADC = 16 MHz tlatr Regular trigger conversion latency fADC = 16 MHz tSTAB Unit (5) 1(5) fADC = 16 MHz tCONV Max s Multiplexed channels 1.8 V VDDA 2.4 V Total conversion time (including sampling time) Typ 4 384 1/fADC 1 24.75 s 4 to 384 (sampling phase) +12 (successive approximation) 1/fADC 16 pF Direct channels Multiplexed channels 12-bit conversions Tconv+1 1/fADC 6/8/10-bit conversions Tconv 1/fADC 12-bit conversions Tconv+2 1/fADC 6/8/10-bit conversions Tconv+1 1/fADC 50 k 0.5 219 281 ns 3.5 4.5 1/fADC 156 219 ns 2.5 3.5 1/fADC 3.5 s Power-up time 1. The Vref+ input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 A) - one variable (max 400 A), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 A and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 A at 1Msps 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pin descriptions for further details. 4. VSSA or VREF- must be tied to ground. 5. Minimum sampling and conversion time is reached for maximum Rext = 0.5 k. 6. For 1 Msps, maximum Rext is 0.5 k. Doc ID 17659 Rev 6 85/109 Electrical characteristics Table 51. ADC accuracy(1)(2) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Effective number of bits SINAD Signal-to-noise and distorsion ratio SNR Signal-to-noise ratio THD Total harmonic distorsion ET STM32L151xx, STM32L152xx 2.4 V VDDA 3.6 V 2.4 V VREF+ 3.6 V fADC = 8 MHz, RAIN = 50 TA = -40 to 105 C 2.4 V VDDA 3.6 V VDDA = VREF+ fADC = 16 MHz, RAIN = 50 TA = -40 to 105 C 1 kHz Finput 100 kHz Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 2.4 V VDDA 3.6 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C 1.8 V VDDA 2.4 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C Min(3) Typ Max(3) - 2 4 - 1 2 - 1.5 3.5 - 1 2 - 1.7 3 9.2 10 - 57.5 62 - 57.5 62 - -74 -75 - - 4 6.5 - 2 4 - 4 6 - 1 2 - 1.5 3 2 3 1 1.5 1.5 2 1 2 1 1.5 Unit LSB bits dB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.11 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. 86/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 25. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 26. Typical connection diagram using the ADC 6$$ 2!). 6!). 64 6 !).X #PARASITIC 64 6 ), N! 34-,XXX 3AMPLE AND HOLD !$# CONVERTER 2!$# BIT CONVERTER #!$# AIB 1. Refer to Table 50 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. Doc ID 17659 Rev 6 87/109 Electrical characteristics STM32L151xx, STM32L152xx Figure 27. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700A 300A Table 52. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (s) Multiplexed channels Direct channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. Guaranteed by design, not tested in production. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 28 or Figure 29, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. 88/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Electrical characteristics Figure 28. Power supply and reference decoupling (VREF+ not connected to VDDA) 34-,XXX 62%& SEE NOTE & N& 6$$! & N& 633! 62%&n SEE NOTE AIB 1. VREF+ and VREF- inputs are available only on 100-pin packages. Figure 29. Power supply and reference decoupling (VREF+ connected to VDDA) 34-,XXX 62%& 6$$! 3EE NOTE & N& 62%&n633! 3EE NOTE AIA 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 17659 Rev 6 89/109 Electrical characteristics 6.3.17 STM32L151xx, STM32L152xx DAC electrical specifications Data guaranteed by design, not tested in production, unless otherwise specified. Table 53. DAC characteristics Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage Current consumption on VREF+ supply VREF+ = 3.3 V No load, middle code (0x800) 130 220 IDDVREF+(1) No load, worst code (0x000) 220 350 No load, middle code (0x800) 210 320 IDDA(1) Current consumption on VDDA supply VDDA = 3.3 V No load, worst code (0xF1C) 320 520 RL(2) Resistive load CL 1.8 3.6 V VSSA A 5 k Capacitive load Output impedance RO VDAC_OUT DNL(1) (1) Offset 3.6 DAC output buffer ON (2) INL VREF+ must always be below VDDA 1.8 Unit Offset1(1) 90/109 pF 10 k DAC output buffer OFF 6 DAC output buffer ON 0.2 VDDA - 0.2 V DAC output buffer OFF 0.5 VREF+ - 1LSB mV Voltage on DAC_OUT output Differential non linearity(3) Integral non linearity (1) 8 50 (4) CL 50 pF, RL 5 k DAC output buffer ON 1.5 3 No RLOAD, CL 50 pF DAC output buffer OFF 1.5 3 CL 50 pF, RL 5 k DAC output buffer ON 2 4 No RLOAD, CL 50 pF DAC output buffer OFF 2 4 10 25 No RLOAD, CL 50 pF DAC output buffer OFF 5 8 No RLOAD, CL 50 pF DAC output buffer OFF 1.5 5 CL 50 pF, RL 5 k DAC output buffer ON Offset error at code 0x800 (5) Offset error at code 0x001(6) Doc ID 17659 Rev 6 LSB STM32L151xx, STM32L152xx Table 53. DAC characteristics (continued) Symbol dOffset/dT(1) (1) Gain dGain/dT(1) TUE(1) tSETTLING Electrical characteristics Parameter Offset error temperature coefficient (code 0x800) Gain error(7) Gain error temperature coefficient Total unadjusted error Conditions VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer OFF VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer ON Min Typ Max -20 -10 0 V/C 0 CL 50 pF, RL 5 k DAC output buffer ON VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer ON 20 50 +0.1 / -0.2% +0.2 / -0.5% % No RLOAD, CL 50 pF DAC output buffer OFF VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer OFF Unit -10 +0 / -0.2% +0 / -0.4% -2 0 V/C -8 0 CL 50 pF, RL 5 k DAC output buffer ON 12 30 No RLOAD, CL 50 pF DAC output buffer OFF 8 12 7 12 s 1 Msps Settling time (full scale: for a 12-bit code transition between the lowest and C 50 pF, RL 5 k the highest input codes till L DAC_OUT reaches final value 1LSB -40 LSB Max frequency for a correct DAC_OUT change Update rate (95% of final value) with 1 CL 50 pF, RL 5 k LSB variation in the input code tWAKEUP Wakeup time from off state (setting the ENx bit in the DAC Control register)(8) CL 50 pF, RL 5 k 9 15 s PSRR+ VDDA supply rejection ratio CL 50 pF, RL 5 k (static DC measurement) -60 -35 dB 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. Doc ID 17659 Rev 6 91/109 Electrical characteristics STM32L151xx, STM32L152xx 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA - 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 30. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.18 Temperature sensor characteristics Table 54. TS characteristics Symbol Parameter TL(1) VSENSE linearity with temperature Avg_Slope(1) Average slope Voltage at 110C V110 (3) 5C(2) IDDA(TEMP) Current consumption tSTART(3) Startup time TS_temp(4)(3) ADC sampling time when reading the temperature Min Typ Max Unit 1 2 C TBD 1.66 TBD mV/C 612 626.8 641.5 mV 3.4 6 A 10 s 10 1. Guaranteed by characterization, not tested in production. 2. Measured at VDD = 3 V 10 mV. V110 ADC conversion result is stored in the TS_Factory_CONV_V110 byte. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 92/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 6.3.19 Electrical characteristics Comparator Table 55. Symbol Comparator 1 characteristics Parameter Conditions Min(1) Typ VDDA Analog supply voltage R400K R400K value 400 R10K R10K value 10 VIN tSTART Voffset Comparator offset ICOMP1 0.6 Comparator startup time Propagation delay Unit 3.6 V k Comparator 1 input voltage range td dVoffset/dt 1.65 Max(1) V 7 10 3 10 3 10 mV 1.5 10 mV/1000 h 160 260 nA s (2) Comparator offset variation in worst voltage stress conditions VDDA VDDA = 3.6 V VIN+ = 0 V VIN- = VREFINT TA = 25 C 0 Current consumption(3) 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Doc ID 17659 Rev 6 93/109 Electrical characteristics Table 56. Symbol VDDA VIN STM32L151xx, STM32L152xx Comparator 2 characteristics Min Typ Max(1) Unit Analog supply voltage 1.65 3.6 V Comparator 2 input voltage range 0 VDDA V Parameter tSTART Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ Threshold voltage temperature dt coefficient ICOMP2 Current consumption(3) Conditions Fast mode 15 20 Slow mode 20 25 1.65 V VDDA 2.7 V 1.8 3.5 2.7 V VDDA 3.6 V 2.5 6 1.65 V VDDA 2.7 V 0.8 2 2.7 V VDDA 3.6 V 1.2 4 4 20 mV VDDA = 3.3V TA = 0 to 50 C V- = VREF+, 3/4 VREF+, 1/2 VREF+, 1/4 VREF+. 15 30 ppm /C Fast mode 3.5 5 Slow mode 0.5 2 s A 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 94/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 6.3.20 Electrical characteristics LCD controller (STM32L152xx only) The STM32L152xx embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 57. Symbol LCD controller characteristics Parameter Min Typ VLCD LCD external voltage VLCD0 LCD internal reference voltage 0 2.6 VLCD1 LCD internal reference voltage 1 2.73 VLCD2 LCD internal reference voltage 2 2.86 VLCD3 LCD internal reference voltage 3 2.98 VLCD4 LCD internal reference voltage 4 3.12 VLCD5 LCD internal reference voltage 5 3.26 VLCD6 LCD internal reference voltage 6 3.4 VLCD7 LCD internal reference voltage 7 3.55 Cext ILCD(1) RHtot(2) RL (2) Unit 3.6 VLCD external capacitance 0.1 V 2 Supply current at VDD = 2.2 V 3.3 Supply current at VDD = 3.0 V 3.1 F A Low drive resistive network overall value 5.28 6.6 7.92 M High drive resistive network total value 192 240 288 k VLCD V V44 Segment/Common highest level voltage V34 Segment/Common 3/4 level voltage 3/4 VLCD V23 Segment/Common 2/3 level voltage 2/3 VLCD V12 Segment/Common 1/2 level voltage 1/2 VLCD V13 Segment/Common 1/3 level voltage 1/3 VLCD V14 Segment/Common 1/4 level voltage 1/4 VLCD V0 Segment/Common lowest level voltage Vxx(3) Max Segment/Common level voltage error TA = -40 to 85 C V 0 50 mV 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected 2. Guaranteed by design, not tested in production. 3. Based on characterization, not tested in production. Doc ID 17659 Rev 6 95/109 Package characteristics STM32L151xx, STM32L152xx 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 96/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Package characteristics Figure 31. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 32. Recommended footprint outline(1)(2)(3) (dimensions in mm)(1) 7.30 48 37 1 ! 36 4 6.20 0.20 7.30 B E 6.20 5.60 5.80 5.60 0.30 12 25 13 0.55 24 5.80 0.50 0.75 ai15697 !"?-) 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. Table 58. UFQFPN48 - ultra thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T b e 0.152 0.200 0.250 0.0060 0.300 0.0079 0.500 0.0098 0.0118 0.0197 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 17659 Rev 6 97/109 Package characteristics STM32L151xx, STM32L152xx Figure 33. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline B D D1 A A e A1 F H F G F E E1 E D C B A e 1 2 3 A1 ball pad corner A3 4 5 6 7 8 Ob (64 balls) A4 A2 Seating C plane Bottom view ME_R8 1. Drawing is not to scale. Table 59. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.200 0.150 Max 0.0472 0.0059 A2 0.785 0.0309 A3 0.200 0.0079 A4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 E 3.500 4.850 5.000 0.1378 5.150 0.1909 0.1969 E1 3.500 0.1378 e 0.500 0.0197 F 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 98/109 Typ Doc ID 17659 Rev 6 0.2028 STM32L151xx, STM32L152xx Package characteristics Figure 34. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process Doc ID 17659 Rev 6 99/109 Package characteristics STM32L151xx, STM32L152xx Figure 35. UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline 0.10 Z D1 D X A1 ball pad corner FD Y A1 ball pad corner 0.50 1.75 b 1.75 E1 E e A1 A 0.10 Side view Top view FE A2 Bottom view A0C2_ME 1. Drawing is not to scale. Table 60. UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.46 0.53 0.6 0.0181 0.0209 0.0236 A1 0.06 0.08 0.1 0.0024 0.0031 0.0039 A2 0.4 0.45 0.5 0.0157 0.0177 0.0197 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 D 7 0.2756 D1 5.5 0.2165 E 7 0.2756 E1 5.5 0.2165 e 0.5 0.0197 FD 0.75 0.0295 FE 0.75 0.0295 1. Values in inches are converted from mm and rounded to 4 decimal digits. 100/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Package characteristics Figure 36. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline(1) Figure 37. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 61. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.6 A1 0.05 A2 1.35 b 0.17 c 0.09 D 15.8 D1 13.8 D3 Max 0.063 0.15 0.002 1.4 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.2 0.0035 16 16.2 0.622 0.6299 0.6378 14 14.2 0.5433 0.5512 0.5591 12 0.0059 0.0079 0.4724 E 15.8 16 16.2 0.622 0.6299 0.6378 E1 13.8 14 14.2 0.5433 0.5512 0.5591 E3 12 e L 0.5 0.45 L1 k ccc 0.4724 0.6 0.0197 0.75 0.0177 1 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.08 0.0 3.5 7.0 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 17659 Rev 6 101/109 Package characteristics STM32L151xx, STM32L152xx Figure 38. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline(1) Figure 39. Recommended footprint(1)(2) A A2 48 33 A1 0.3 49 E 32 0.5 b E1 12.7 10.3 10.3 e 64 17 1.2 1 16 7.8 D1 c 12.7 L1 D ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 62. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 102/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Package characteristics Figure 40. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 41. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 0.25 mm Gage plane C 1.20 D 36 0.30 25 37 D1 24 k D3 36 A1 L 25 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 5.80 E3 E1 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 63. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.600 A1 0.050 0.150 Max 0.0630 0.0020 0.0059 A2 1.400 1.350 1.450 0.0551 0.0531 0.0571 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.090 0.200 0.0035 0.0079 c D 9.000 8.800 9.200 0.3543 0.3465 0.3622 D1 7.000 6.800 7.200 0.2756 0.2677 0.2835 D3 5.500 E 9.000 8.800 9.200 0.3543 0.3465 0.3622 E1 7.000 6.800 7.200 0.2756 0.2677 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.600 0.0177 0.0295 L1 1.000 k 3.5 0 7 ccc 0.2165 0.450 0.750 0.0236 0.0394 0 7 0.080 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 17659 Rev 6 103/109 Package characteristics 7.2 STM32L151xx, STM32L152xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 64. Thermal characteristics Symbol JA 7.2.1 Parameter Value Thermal resistance junction-ambient BGA100 - 7 x 7 mm 59 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm / 0.5 mm pitch 16 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 104/109 Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx 8 Ordering information scheme Ordering information scheme Table 65. Ordering information scheme Example: STM32 L 151 C 8 T 6 D xxx Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low power Device subfamily 151: Devices without LCD 152: Devices with LCD Pin count C = 48 pins R = 64 pins V = 100 pins Flash memory size 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package H = BGA T = LQFP U = UFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C Options No character = VDD range: 1.8 to 3.6 V and BOR enabled D = VDD range: 1.65 to 3.6 V and BOR disabled Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 17659 Rev 6 105/109 Revision history 9 STM32L151xx, STM32L152xx Revision history on Table 66. Document revision history Date Revision 02-Jul-2010 1 Initial release. 2 Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Table 4: STM32L15xxx pin definitions on page 30 Updated Table 11: Embedded reset and power control block characteristics on page 46 Updated Table 12: Embedded internal reference voltage on page 48 Added Table 49: ADC clock frequency on page 84 Updated Table 50: ADC characteristics on page 84 3 Modified consumptions on page 1 and in Section 3.1: Low power modes on page 13 LED_SEG8 removed on PB6 Updated Section 6: Electrical characteristics on page 41 VFQFPN48 replaced by UFQFPN48 4 Features: updated value of Low-power sleep. Section 3.3.2: Power supply supervisor: updated note. Table 4: STM32L15xxx pin definitions: modified main function (after reset) and alternate function for OSC_IN and OSC_OUT pins; modified footnote 5; added footnote to OSC32_IN and OSC32_OUT pins; C1 and D1 removed on PD0 and PD1 pins (TFBGA64 column). Section 3.11: DAC (digital-to-analog converter): updated bullet list. Table 6: Voltage characteristics on page 43: updated footnote 3 regarding IINJ(PIN). Table 7: Current characteristics on page 43: updated footnote 4 regarding positive and negative injection. Table 11: Embedded reset and power control block characteristics on page 46: updated typ and max values for TRSTTEMPO (VDD rising, BOR enabled). Table 13: Current consumption in Run mode, code with data processing running from Flash on page 49: removed values for HSI clock source (16 MHz), Range 3. Table 14: Current consumption in Run mode, code with data processing running from RAM on page 50: removed values for HSI clock source (16 MHz), Range 3. Table 15: Current consumption in Sleep mode on page 51: removed values for HSI clock source (16 MHz), Range 3 for both RAM and Flash; changed units. Table 16: Current consumption in Low power run mode on page 52: updated parameter and max value of IDD Max (LP Run). Table 17: Current consumption in Low power sleep mode on page 53: updated symbol, parameter, and max value of IDD Max (LP Sleep). Table 18: Typical and maximum current consumptions in Stop mode: updated values for IDD (Stop with RTC) - RTC clocked by LSE external clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no independent watchdog). 01-Oct-2010 16-Dec-2010 25-Feb-2011 106/109 Changes Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Table 66. Revision history Document revision history (continued) Date 25-Feb-2011 Revision Changes 4 cont'd Updated Table 19: Typical and maximum current consumptions in Standby mode on page 55 (IDD (WU from Standby) instead of (IDD (WU from Stop). Table 20: Typical and maximum timings in Low power modes on page 56: updated condition for Wakeup from Stop mode, regulator in Run mode; updated max values for Wakeup from Stop mode, regulator in low power mode; updated max values for tWUSTDBY. Table 21: Peripheral current consumption on page 57: updated values for column Low power sleep and run; updated Flash values; renamed ADC1 to ADC; updated IDD (LCD) value; updated units; added values for IDD (RTC) and IDD (IWDG); updated footnote 1 and 3; added foot note 2 concerning ADC. Table 22: High-speed external user clock characteristics on page 59: added min value for tw(HSE)/tw(HSE) OSC_IN high or low time; added max value for tr(HSE)/tf(HSE) OSC_IN rise or fall time; updated IL for typ and max values. Table 23: Low-speed external user clock characteristics on page 60: updated max value for IL. Table 24: HSE 1-24 MHz oscillator characteristics on page 62: renamed i2 as IHSE and updated max value; updated max values for IDD(HSE). Table 25: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 63: updated max value for ILSE. Table 26: HSI oscillator characteristics on page 65: updated some min and max values for ACCHSI. Table 28: MSI oscillator characteristics on page 66: updated parameter, typ, and max values for DVOLT(MSI). Table 31: Flash memory characteristics on page 68: updated typ values for tprog. Table 40: I/O AC characteristics on page 75: updated some max values for 01, 10, and 11; updated min value; updated footnotes. Table 51: ADC accuracy on page 86: updated typ values and some of the test conditions for ENOB, SINAD, SNR, and THD. Table 53: DAC characteristics on page 90: updated footnote 7 and added footnote 8. Updated leakage value in Figure 26: Typical connection diagram using the ADC. Added Figure 27: Maximum dynamic current consumption on VREF+ supply pin during ADC conversion. Added Table 52: RAIN max for fADC = 16 MHz on page 88 Figure 28: Power supply and reference decoupling (VREF+ not connected to VDDA): replaced all 10 nF capacitors with 100 nF capacitors. Figure 29: Power supply and reference decoupling (VREF+ connected to VDDA): replaced 10 nF capacitor with 100 nF capacitor. Doc ID 17659 Rev 6 107/109 Revision history STM32L151xx, STM32L152xx Table 66. Document revision history (continued) Date 17-June-2011 25-Jan-2012 108/109 Revision Changes 5 Modified 1st page (low power features) Added STM32L15xC6 and STM32L15xR6 devices (32 Kbytes of Flash memory). Modified Section 3.6: GPIOs (general-purpose inputs/outputs) on page 18 Modified Section 6.3: Operating conditions on page 44 Modified Table 51: ADC accuracy on page 86, Table 53: DAC characteristics on page 90 and Table 55: Comparator 1 characteristics on page 93 6 Features: updated internal multispeed low power RC. Table 2: Ultralow power STM32L15xxx device features and peripheral counts: LCD 4x44 and 8x40 available for both 64- and 128-Kbyte devices; two comparators available for all devices. Figure 8: STM32L15xxx UFQFPN48 pinout: replaced VFQPN48 by UFQFPN48 as name of package. Table 4: STM32L15xxx pin definitions: replaced PH0/PH1 by PC14/PC15. Table 5: Alternate function input/output: removed EVENT OUT from PH2 port, AFIO15 column. Table 10: Functionalities depending on the operating power supply range: added footnote 1. Table 15: Current consumption in Sleep mode: updated MSI conditions and fHCLK. Table 16: Current consumption in Low power run mode: updated some temperature conditions; added footnote 2. Table 17: Current consumption in Low power sleep mode: updated some temperature conditions and one of the MSI clock conditions. Table 18: Typical and maximum current consumptions in Stop mode: updated IDD (WU from Stop) parameter. Table 19: Typical and maximum current consumptions in Standby mode: updated IDD (WU from Standby) parameter. Table 20: Typical and maximum timings in Low power modes: updated fHCLK value for tWUSLEEP_LP; updated typical value of parameter "Wakeup from Stop mode, regulator in Run mode". Table 21: Peripheral current consumption: replaced GPIOF by GPIOH. Table 29: PLL characteristics: updated "PLL output clock" Table 31: Flash memory characteristics: updated all information for IDD. Figure 18: I/O AC characteristics definition: replaced the falling edge "tr(IO)out" by "tf(IO)out". Table 43: I2C characteristics: amended footnote 2. Table 50: ADC characteristics: updated fS max value for direct channels, 6-bit sampling rate. Table 51: ADC accuracy: Updated the first, third and fourth fADC test condition. Table 54: TS characteristics: updated typ, min, and max values of the TS_temp parameter. Doc ID 17659 Rev 6 STM32L151xx, STM32L152xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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