This is information on a product in full production.
December 2015 DocID027590 Rev 3 1/222
STM32F745xx
STM32F746xx
ARM
®
-based Cortex
®
-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB
RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD
Datasheet - production data
Features
•Core: ARM® 32-bit Cortex®-M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator™) and L1-cache: 4KB data cache
and 4KB instruction cache, allowing 0-wait
state execution from embedded Flash memory
and external memories, frequency up to
216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions.
•Memories
– Up to 1MB of Flash memory
– 1024 bytes of OTP memory
– SRAM: 320KB (including 64KB of data
TCM RAM for critical real time data) +
16KB of instruction TCM RAM (for critical
real time routines) + 4KB of backup SRAM
(available in the lowest power modes)
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
•Dual mode Quad-SPI
•LCD parallel interface, 8080/6800 modes
•LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for
enhanced graphic content creation (DMA2D)
•Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
•Low-power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC, 32×32 bit backup
registers + 4KB backup SRAM
•3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
•2×12-bit D/A converters
•Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
•General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
•Debug mode
– SWD & JTAG interfaces
–Cortex
®-M7 Trace Macrocell™
•Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
•Up to 25 communication interfaces
– Up to 4× I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (up to 50 Mbits/s), 3 with
muxed simplex I2S for audio class
accuracy via internal audio PLL or external
clock
– 2 x SAIs (serial audio interface)
– 2 × CANs (2.0B active) and SDMMC
interface
– SPDIFRX interface
– HDMI-CEC
•Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
•8- to 14-bit parallel camera interface up to
54 Mbytes/s
•True random number generator
•CRC calculation unit
•RTC: subsecond accuracy, hardware calendar
•96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F745xx STM32F745IE, STM32F745VE, STM32F745VG,
STM32F745ZE, STM32F745ZG, STM32F745IG
STM32F746xx
STM32F746BE, STM32F746BG, STM32F746IE,
STM32F746IG, STM32F746NE, STM32F746NG,
STM32F746VE, STM32F746VG, STM32F746ZE,
STM32F746ZG
LQFP100 (14x14 mm)
LQFP144 (20x20 mm)
LQFP176 (24x24 mm) UFBGA176 (10x10 mm)
)%*$
TFBGA216 (13x13 mm)
LQFP208 (28x28 mm)
WLCSP143
(4.5x5.8 mm)
www.st.com
Contents STM32F745xx STM32F746xx
2/222 DocID027590 Rev 3
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18
2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 22
2.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30
2.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30
2.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
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2.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37
2.25 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 38
2.26 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.27 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.30 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 40
2.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40
2.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41
2.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41
2.35 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.36 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.37 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.38 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.39 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.40 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.41 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.42 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.43 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 100
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 100
5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 100
5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 130
5.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 136
5.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.20 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3.26 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.27 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.3.28 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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5.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 190
5.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 191
5.3.31 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 193
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.1 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 195
6.2 WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip
scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 201
6.4 LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . 204
6.5 LQFP208 28 x 28 mm low-profile quad flat package information . . . . . . 208
6.6 UFBGA 176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.7 TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 220
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
List of tables STM32F745xx STM32F746xx
6/222 DocID027590 Rev 3
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F745xx and STM32F746xx features and peripheral counts . . . . . . . . . . . . . . . . . . 13
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. Voltage regulator modes in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. STM32F745xx and STM32F746xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 12. STM32F745xx and STM32F746xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75
Table 13. STM32F745xx and STM32F746xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 89
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 99
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 100
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 100
Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 105
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 106
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 29. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 108
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 108
Table 31. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 109
Table 32. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 110
Table 33. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 111
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 39. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 41. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 43. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 44. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 45. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 46. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 48. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 49. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 50. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 51. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 52. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 53. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 54. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 55. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 56. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 60. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 61. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 63. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 64. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 65. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 66. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 147
Table 67. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 147
Table 68. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 69. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 71. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 72. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 73. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 74. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 75. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 76. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 77. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 78. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 79. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 80. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 81. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 82. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 83. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 84. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 85. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 86. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 87. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 170
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 170
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 171
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 172
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173
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Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 194
Table 111. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 194
Table 112. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 196
Table 113. WLCSP143 - 143-ball, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 114. WLCSP143 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 115. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 117. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 213
Table 120. TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 121. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 216
Table 122. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 123. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 124. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 220
Table 125. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
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List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. STM32F745xx and STM32F746xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. STM32F745xx and STM32F746xx AXI-AHB bus matrix architecture . . . . . . . . . . . . . . . . 19
Figure 4. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25
Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. STM32F74xVx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. STM32F74xZx WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13. STM32F74xZx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. STM32F74xIx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. STM32F74xBx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. STM32F74xIx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. STM32F74xNx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 24. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 25. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 26. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 27. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 28. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 29. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 30. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 31. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 33. HSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 34. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 37. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 38. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 39. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 149
Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 149
Figure 44. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 46. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 47. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 48. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 49. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 50. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 51. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 52. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 163
Figure 53. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 54. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 55. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 56. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 169
Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 171
Figure 59. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 60. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 61. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 62. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 63. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 64. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 66. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 67. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 184
Figure 68. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 184
Figure 69. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 70. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 71. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 72. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 74. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 75. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 76. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 77. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 78. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 195
Figure 79. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 80. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 81. WLCSP143 - 143-ball, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 82. WLCSP143 - 143-ball, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 83. WLCSP143, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 84. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 201
Figure 85. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 86. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DocID027590 Rev 3 11/222
STM32F745xx STM32F746xx List of figures
11
Figure 87. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 204
Figure 88. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 89. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 90. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 208
Figure 91. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 92. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 93. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 94. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 95. UFBGA176+25, 10 × 10 × 0.6 mm ultra thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 96. TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 97. TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 98. TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Description STM32F745xx STM32F746xx
12/222 DocID027590 Rev 3
1 Description
The STM32F745xx and STM32F746xx devices are based on the high-performance ARM®
Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core
features a single floating point unit (SFPU) precision which supports all ARM® single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances the application security.
The STM32F745xx and STM32F746xx devices incorporate high-speed embedded
memories with Flash memory up to 1 Mbyte, 320 Kbytes of SRAM (including 64 Kbytes of
Data TCM RAM for critical real time data), 16 Kbytes of instruction TCM RAM (for critical
real time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal
and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-
purpose 16-bit timers including two PWM timers for motor control and one low-power timer
available in Stop mode, two general-purpose 32-bit timers, a true random number generator
(RNG). They also feature standard and advanced communication interfaces.
•Up to four I2Cs
•Six SPIs, three I2Ss in duplex mode. To achieve the audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
•Four USARTs plus four UARTs
•An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•Two CANs
•Two SAI serial audio interfaces
•An SDMMC host interface
•Ethernet and camera interfaces
•LCD-TFT display controller
•Chrom-ART Accelerator™
•SPDIFRX interface
•HDMI-CEC
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. Refer
to Table 2: STM32F745xx and STM32F746xx features and peripheral counts for the list of
peripherals available on each part number.
The STM32F745xx and STM32F746xx devices operate in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply. A dedicated supply input for USB (OTG_FS and
OTG_HS) is available on all the packages except LQFP100 for a greater power supply
choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 2.17.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F745xx and STM32F746xx devices offer devices in 7 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
STM32F745xx STM32F746xx Description
DocID027590 Rev 3 13/222
These features make the STM32F745xx and STM32F746xx microcontrollers suitable for a wide range of applications:
•Motor drive and application control,
•Medical equipment,
•Industrial applications: PLC, inverters, circuit breakers,
•Printers, and scanners,
•Alarm systems, video intercom, and HVAC,
•Home audio appliances,
•Mobile applications, Internet of Things,
•Wearable devices: smartwatches.
Figure 2 shows the general block diagram of the device family.
Table 2. STM32F745xx and STM32F746xx features and peripheral counts
Peripherals STM32F745Vx STM32F746Vx STM32F745Zx STM32F746Zx STM32F745Ix STM32F746Ix STM32F745Bx STM32F746Bx STM32F745Nx STM32F746Nx
Flash memory in Kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024
SRAM in
Kbytes
System 320(240+16+64)
Instruction 16
Backup 4
FMC memory controller Yes(1)
Ethernet Yes
Timers
General-
purpose 10
Advanced-
control 2
Basic 2
Low-power 1
Random number generator Yes
Description STM32F745xx STM32F746xx
14/222 DocID027590 Rev 3
Communication
interfaces
SPI / I2S 4/3 (simplex)(2) 6/3 (simplex)(2)
I2C 4
USART/
UART 4/4
USB OTG
FS Yes
USB OTG
HS Yes
CAN 2
SAI 2
SPDIFRX 4 inputs
SDMMC Yes
Camera interface Yes
LCD-TFT No Yes No Yes No Yes No Yes No Yes
Chrom-ART Accelerator™
(DMA2D) Yes
GPIOs 82 114 140 168
12-bit ADC
Number of channels
3
16 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 216 MHz(3)
Operating voltage 1.7 to 3.6 V(4)
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP100 WLCSP143
LQFP144
UFBGA176
LQFP176 LQFP208 TFBGA216
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. 216 MHz maximum frequency for -40°C to + 85°C ambient temperature range (200 MHz maximum frequency for -40°C to + 105°C ambient temperature range).
4. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.17.2: Internal reset OFF).
Table 2. STM32F745xx and STM32F746xx features and peripheral counts (continued)
Peripherals STM32F745Vx STM32F746Vx STM32F745Zx STM32F746Zx STM32F745Ix STM32F746Ix STM32F745Bx STM32F746Bx STM32F745Nx STM32F746Nx
DocID027590 Rev 3 15/222
STM32F745xx STM32F746xx Description
44
1.1 Full compatibility throughout the family
The STM32F745xx and STM32F746xx devices are fully pin-to-pin, compatible with the
STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher
performances (higher frequency) for a greater degree of freedom during the development
cycle.
Figure 1 give compatible board designs between the STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
The STM32F745xx and STM32F746xx LQFP144, LQFP176, LQFP208, TFBGA216,
UFBGA176, WLCSP143 packages are fully pin to pin compatible with STM32F4xxxx
devices.
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Description STM32F745xx STM32F746xx
16/222 DocID027590 Rev 3
Figure 2. STM32F745xx and STM32F746xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
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DocID027590 Rev 3 17/222
STM32F745xx STM32F746xx Functional overview
44
2 Functional overview
2.1 ARM® Cortex®-M7 with FPU
The ARM® Cortex®-M7 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and a low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
– Six-stage dual-issue pipeline
– Dynamic branch prediction
– Harvard caches (4 Kbytes of I-cache and 4 Kbytes of D-cache)
– 64-bit AXI4 interface
– 64-bit ITCM interface
– 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
•Tightly Coupled Memory (TCM) interface.
•Harvard instruction and data caches and AXI master (AXIM) interface.
•Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up the software development by using
metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F745xx and STM32F746xx
devices.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
2.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F745xx STM32F746xx
18/222 DocID027590 Rev 3
2.3 Embedded Flash memory
The STM32F745xx and STM32F746xx devices embed a Flash memory of up to 1 Mbytes
available for storing programs and data.
2.4 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify the data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.5 Embedded SRAM
All the devices features:
•System SRAM up to 320 Kbytes:
– SRAM1 on AHB bus Matrix: 240 Kbytes
– SRAM2 on AHB bus Matrix: 16 Kbytes
– DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for
critical real time data.
•Instruction RAM (ITCM-RAM) 16 Kbytes:
– It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The TCM RAM instruction is reserved only for CPU. It is accessed at
CPU clock speed with 0-wait states.
•4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.6 AXI-AHB bus matrix
The STM32F745xx and STM32F746xx system architecture is based on 2 sub-systems:
•An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix
– 1x AXI to 64-bit AHB bridge connected to the embedded flash
•A multi-AHB Bus-Matrix:
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM,
FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and an
efficient operation even when several high-speed peripherals work
simultaneously.
DocID027590 Rev 3 19/222
STM32F745xx STM32F746xx Functional overview
44
Figure 3. STM32F745xx and STM32F746xx AXI-AHB bus matrix architecture
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
2.7 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
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Functional overview STM32F745xx STM32F746xx
20/222 DocID027590 Rev 3
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C
•USART
•General-purpose, basic and advanced-control timers TIMx
•DAC
•SDMMC
•Camera interface (DCMI)
•ADC
•SAI
•SPDIFRX
•Quad-SPI
•HDMI-CEC
2.8 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•The NOR/PSRAM memory controller
•The NAND/memory controller
•The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•8-,16-,32-bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•Read FIFO for SDRAM controller
•The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
DocID027590 Rev 3 21/222
STM32F745xx STM32F746xx Functional overview
44
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
2.9 Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•Direct mode through registers.
•External flash status register polling mode.
•Memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.10 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•2 displays layers with dedicated FIFO (64x32-bit)
•Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•Up to 8 Input color formats selectable per layer
•Flexible blending between two layers using alpha value (per pixel or constant)
•Flexible programmable parameters for each layer
•Color keying (transparency color)
•Up to 4 programmable interrupt events.
2.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•Rectangle filling with a fixed color
•Rectangle copy
•Rectangle copy with pixel format conversion
•Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
Functional overview STM32F745xx STM32F746xx
22/222 DocID027590 Rev 3
2.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M7 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.13 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
2.14 Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
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STM32F745xx STM32F746xx Functional overview
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2.15 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•All Flash address space mapped on ITCM or AXIM interface
•All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
2.16 Power supply schemes
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•VDD = 1.7 to 3.6 Vexternal power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
•VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when
device is powered at 1.8V, an independent power supply 3.3V can be connected to
VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to
disappear. The following conditions VDDUSB must be respected:
– During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
– During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDSUB rising and falling time rate specifications must be respected (see Table 20
and Table 21)
– In operating mode phase, VDDUSB could be lower or higher than VDD:
- If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
Functional overview STM32F745xx STM32F746xx
24/222 DocID027590 Rev 3
Figure 4. VDDUSB connected to VDD power supply
Figure 5. VDDUSB connected to external power supply
2.17 Power supply supervisor
2.17.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
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STM32F745xx STM32F746xx Functional overview
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reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.17.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•The brownout reset (BOR) circuitry must be disabled
•The embedded programmable voltage detector (PVD) is disabled
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
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Figure 7. PDR_ON control with internal reset OFF
2.18 Voltage regulator
The regulator has four operating modes:
•Regulator ON
– Main regulator mode (MR)
– Low-power regulator (LPR)
– Power-down
•Regulator OFF
2.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between the maximum frequency and dynamic power
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STM32F745xx STM32F746xx Functional overview
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