TUSB7320, TUSB7340
USB 3.0 xHCI HOST CONTROLLER
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLSE76E
March 2011–Revised July 2011
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
www.ti.com
Contents
1 INTRODUCTION ................................................................................................................. 13
1.1 Features .................................................................................................................... 13
1.2 Target Applications ........................................................................................................ 13
2 OVERVIEW ....................................................................................................................... 14
2.1 Description ................................................................................................................. 14
2.2 Related Documents ....................................................................................................... 15
2.3 Document's Conventions ................................................................................................. 15
2.4 Available Options .......................................................................................................... 15
2.5 ORDERING INFORMATION ............................................................................................. 15
2.6 Terminal Assignments .................................................................................................... 16
2.7 Terminal Descriptions ..................................................................................................... 18
3 FEATURE/PROTOCOL DESCRIPTIONS ................................................................................ 22
3.1 Power-Up/-Down Sequencing ........................................................................................... 22
3.1.1 Power-Up Sequence ........................................................................................... 22
3.1.2 Power-Down Sequence ........................................................................................ 23
3.2 Two-Wire Serial-Bus Interface ........................................................................................... 23
3.2.1 Serial-Bus Interface Implementation ......................................................................... 23
3.2.2 Serial-Bus Interface Protocol .................................................................................. 25
3.2.3 Serial-Bus EEPROM Application ............................................................................. 27
3.3 System Management Interrupt ........................................................................................... 28
4 CLASSIC PCI CONFIGURATION SPACE ............................................................................... 29
4.1 The PCI Configuration Map .............................................................................................. 29
4.2 Vendor ID Register ........................................................................................................ 30
4.3 Device ID Register ........................................................................................................ 30
4.4 Command Register ........................................................................................................ 31
4.5 Status Register ............................................................................................................ 32
4.6 Class Code and Revision ID Register .................................................................................. 33
4.7 Cache Line Size Register ................................................................................................ 33
4.8 Latency Timer Register ................................................................................................... 34
4.9 Header Type Register .................................................................................................... 34
4.10 BIST Register .............................................................................................................. 34
4.11 Base Address Register 0 ................................................................................................. 35
4.12 Base Address Register 1 ................................................................................................. 35
4.13 Base Address Register 2 ................................................................................................. 36
4.14 Base Address Register 3 ................................................................................................. 36
4.15 Subsystem Vendor ID Register .......................................................................................... 37
4.16 Subsystem ID Register ................................................................................................... 37
4.17 Capabilities Pointer Register ............................................................................................. 37
4.18 Interrupt Line Register .................................................................................................... 38
4.19 Interrupt Pin Register ..................................................................................................... 38
4.20 Min Grant Register ........................................................................................................ 38
4.21 Max Latency Register ..................................................................................................... 38
4.22 Capability ID Register ..................................................................................................... 39
4.23 Next Item Pointer Register ............................................................................................... 39
4.24 Power Management Capabilities Register ............................................................................. 39
2Contents Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
4.25 Power Management Control/Status Register .......................................................................... 40
4.26 Power Management Bridge Support Extension Register ............................................................ 40
4.27 Power Management Data Register ..................................................................................... 41
4.28 MSI Capability ID Register ............................................................................................... 41
4.29 Next Item Pointer Register ............................................................................................... 41
4.30 MSI Message Control Register .......................................................................................... 41
4.31 MSI Lower Message Address Register ................................................................................. 42
4.32 MSI Upper Message Address Register ................................................................................. 43
4.33 MSI Message Data Register ............................................................................................. 43
4.34 Serial Bus Release Number Register (SBRN) ......................................................................... 44
4.35 Frame Length Adjustment Register (FLADJ) .......................................................................... 44
4.36 PCI Express Capability ID Register ..................................................................................... 44
4.37 Next Item Pointer Register ............................................................................................... 45
4.38 PCI Express Capabilities Register ...................................................................................... 45
4.39 Device Capabilities Register ............................................................................................. 46
4.40 Device Control Register .................................................................................................. 47
4.41 Device Status Register ................................................................................................... 48
4.42 Link Capabilities Register ................................................................................................ 48
4.43 Link Control Register ...................................................................................................... 49
4.44 Link Status Register ....................................................................................................... 50
4.45 Device Capabilities 2 Register ........................................................................................... 50
4.46 Device Control 2 Register ................................................................................................ 51
4.47 Link Control 2 Register ................................................................................................... 51
4.48 Link Status 2 Register .................................................................................................... 52
4.49 Serial Bus Data Register ................................................................................................. 52
4.50 Serial Bus Index Register ................................................................................................ 53
4.51 Serial Bus Slave Address Regsiter ..................................................................................... 53
4.52 Serial Bus Control and Status Register ................................................................................ 53
4.53 GPIO Control Register .................................................................................................... 54
4.54 GPIO Data Register ....................................................................................................... 55
4.55 MSI-X Capability ID Register ............................................................................................ 56
4.56 Next Item Pointer Register ............................................................................................... 56
4.57 MSI-X Message Control Register ....................................................................................... 56
4.58 MSI-X Table Offset and BIR Register .................................................................................. 57
4.59 MSI-X PBA Offset and BIR Register .................................................................................... 57
4.60 Subsystem Access Register ............................................................................................. 58
4.61 General Control 0 Register ............................................................................................... 58
4.62 General Control 1 Register ............................................................................................... 59
4.63 General Control 2 Register ............................................................................................... 60
4.64 USB Control Register ..................................................................................................... 60
4.65 De-Emphasis and Swing Control Register ............................................................................. 62
4.66 Equalizer Control Register ............................................................................................... 63
4.67 Custom PHY Transmit/Receive Control Register ..................................................................... 64
5 PCI EXPRESS EXTENDED CONFIGURATION SPACE ............................................................. 66
5.1 The PCI Express Extended Configuration Map ....................................................................... 66
5.2 Advanced Error Reporting capability Register ......................................................................... 66
Copyright ©2011, Texas Instruments Incorporated Contents 3
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
www.ti.com
5.3 Next Capability Offset / Capability Version Register .................................................................. 67
5.4 Uncorrectable Error Status Register .................................................................................... 67
5.5 Uncorrectable Error Mask Register ..................................................................................... 68
5.6 Uncorrectable Error Severity Register .................................................................................. 69
5.7 correctable Error Severity Register ..................................................................................... 70
5.8 correctable Error Mask Register ......................................................................................... 71
5.9 Advanced Error Capabilities and control Register .................................................................... 72
5.10 Header Log Register ...................................................................................................... 73
5.11 Device Serial Number Capability ID Register .......................................................................... 73
5.12 Next Capability Offset/Capability Version Register ................................................................... 73
5.13 Device Serial Number Register .......................................................................................... 74
6 xHCI MEMORY MAPPED REGISTER SPACE ......................................................................... 75
6.1 The xHCI Register Map ................................................................................................... 75
6.2 Host Controller Capability Registers .................................................................................... 75
6.2.1 Capability Registers Length ................................................................................... 75
6.2.2 Host Controller Interface Version Number .................................................................. 76
6.2.3 Host Controller Structural Parameters 1 ..................................................................... 76
6.2.4 Host Controller Structural Parameters 2 ..................................................................... 77
6.2.5 Host Controller Structural Parameters 3 ..................................................................... 77
6.2.6 Host Controller Capability Parameters ....................................................................... 78
6.2.7 Doorbell Offset .................................................................................................. 79
6.2.8 Runtime Register Space Offset ............................................................................... 79
6.3 Host Controller Operational Registers .................................................................................. 80
6.3.1 USB Command Register ...................................................................................... 80
6.3.2 USB Command Register ...................................................................................... 81
6.3.3 USB Status Register ........................................................................................... 81
6.3.4 Page Size Register ............................................................................................. 82
6.3.5 Device Notification Control Register ......................................................................... 83
6.3.6 Command Ring Control Register ............................................................................. 83
6.3.7 Device Context Base Address Array Pointer Register ..................................................... 84
6.3.8 Configure Register .............................................................................................. 85
6.3.9 Port Status and Control Register ............................................................................. 85
6.3.10 Port PM Status and Control Register (USB 3.0 Ports) .................................................... 86
6.3.11 Port PM Status and Control Register (USB 2.0 Ports) .................................................... 87
6.3.12 Port Link Info Register ......................................................................................... 87
6.4 Host Controller Runtime Registers ...................................................................................... 88
6.4.1 Microframe Index Register .................................................................................... 88
6.4.2 Interrupter Management Register ............................................................................ 89
6.4.3 Interrupter Moderation Register .............................................................................. 89
6.4.4 Event Ring Segment Table Size Register ................................................................... 90
6.4.5 Event Ring Segment Table Base Address Register ....................................................... 90
6.4.6 Event Ring Dequeue Pointer Register ....................................................................... 91
6.5 Host Controller Doorbell Registers ...................................................................................... 92
6.6 xHCI Extended Capabilities Registers .................................................................................. 92
6.6.1 USB Legacy Support Capability Register ................................................................... 92
6.6.2 USB Legacy Support Control/Status Register .............................................................. 93
4Contents Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
6.6.3 xHCI Supported Protocol Capability Register (USB 2.0) .................................................. 94
6.6.4 xHCI Supported Protocol Name String Register (USB 2.0) ............................................... 94
6.6.5 xHCI Supported Protocol Port Register (USB 2.0) ......................................................... 95
6.6.6 xHCI Supported Protocol Capability Register (USB 3.0) .................................................. 95
6.6.7 xHCI Supported Protocol Name String Register (USB 3.0) ............................................... 96
6.6.8 xHCI Supported Protocol Port Register (USB 3.0) ......................................................... 96
7 MSI-X MEMORY MAPPED REGISTER SPACE ........................................................................ 98
7.1 The MSI-X Table and PBA in Memory Mapped Register Space .................................................... 98
8 PHY CONTROL .................................................................................................................. 99
8.1 Output Voltage Swing Control ........................................................................................... 99
8.2 De-Emphasis Control .................................................................................................... 100
8.3 Adaptive Equalizer ....................................................................................................... 100
9 INPUT CLOCK ................................................................................................................. 102
9.1 Clock Source Requirements ............................................................................................ 102
9.2 External clock ............................................................................................................. 103
9.3 External crystal ........................................................................................................... 103
10 PCI EXPRESS POWER MANAGEMENT ............................................................................... 104
10.1 Power Management ..................................................................................................... 104
10.2 PCI Express Link Power Management States ....................................................................... 104
10.3 PCI Express Power Management D-States .......................................................................... 104
10.4 Power Management Event (PME) ..................................................................................... 105
10.4.1 PME Support .................................................................................................. 105
11 ELECTRICAL CHARACTERISTICS ..................................................................................... 106
11.1 ABSOLUTE MAXIMUM RATINGS .................................................................................... 106
11.2 RECOMMENDED OPERATING CONDITIONS ..................................................................... 106
11.3 THERMAL INFORMATION ............................................................................................. 107
11.4 3.3-V I/O ELECTRICAL CHARACTERISTICS ....................................................................... 107
11.5 POWER CONSUMPTION FOR TUSB7320 .......................................................................... 108
11.6 POWER CONSUMPTION FOR TUSB7340 .......................................................................... 108
Copyright ©2011, Texas Instruments Incorporated Contents 5
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
www.ti.com
List of Figures
2-1 Typical Application ............................................................................................................... 14
2-2 TUSB7320 RKM Package (Top View)......................................................................................... 17
2-3 TUSB7340 RKM Package (Top View)......................................................................................... 17
3-1 Power-Up Sequence............................................................................................................. 23
3-2 Power-Down Sequence ......................................................................................................... 23
3-3 Serial EEPROM Application .................................................................................................... 24
3-4 Serial-Bus Start/Stop Conditions and Bit Transfers.......................................................................... 25
3-5 Serial-Bus Protocol Acknowledge.............................................................................................. 25
3-6 Serial-Bus Protocal - Byte Write................................................................................................ 26
3-7 Serial-Bus Protocal - Byte Read ............................................................................................... 26
3-8 Serial-Bus Protocal - Multibyte Read.......................................................................................... 26
9-1 Oscillation Circuit ............................................................................................................... 102
6List of Figures Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
List of Tables
2-1 Package Information............................................................................................................. 14
2-2 Clock and Reset Signals ........................................................................................................ 18
2-3 PCI Express Signals............................................................................................................. 18
2-4 USB Downstream Signals....................................................................................................... 19
2-5 I2C Signals ........................................................................................................................ 20
2-6 Test and Miscellaneous Signals................................................................................................ 20
2-7 Power Signals .................................................................................................................... 21
3-1 EEPROM Register Loading Map............................................................................................... 27
4-1 PCI Configuration Register Map................................................................................................ 29
4-2 PCI Register 00h ................................................................................................................. 30
4-3 PCI Register 02h ................................................................................................................. 30
4-4 PCI Register 04h ................................................................................................................. 31
4-5 Bit Command Register Description ............................................................................................ 31
4-6 PCI Register 06h ................................................................................................................. 32
4-7 Status Register Description..................................................................................................... 32
4-8 PCI Register 06h ................................................................................................................. 33
4-9 Class Code and Revision ID Register Description........................................................................... 33
4-10 PCI Register 0Ch................................................................................................................. 33
4-11 PCI Register 0Dh................................................................................................................. 34
4-12 PCI Register 0Eh................................................................................................................. 34
4-13 PCI Register 0Fh................................................................................................................. 34
4-14 PCI Register 10h ................................................................................................................. 35
4-15 Base Address Register 0 Description ......................................................................................... 35
4-16 PCI Register 14h ................................................................................................................. 35
4-17 Base Address Register 1 Description ......................................................................................... 35
4-18 PCI Register 18h ................................................................................................................. 36
4-19 Base Address Register 2 Description ......................................................................................... 36
4-20 PCI Register 1Ch................................................................................................................. 36
4-21 Table 9‑3 Base Address Register 3 Description ............................................................................. 36
4-22 PCI Register 2Ch................................................................................................................. 37
4-23 PCI Register 2Eh................................................................................................................. 37
4-24 PCI Register 34h ................................................................................................................. 37
4-25 PCI Register 3Ch................................................................................................................. 38
4-26 PCI Register 3Dh................................................................................................................. 38
4-27 PCI Register 3Eh................................................................................................................. 38
4-28 PCI Register 3Fh................................................................................................................. 38
4-29 PCI Register 40h ................................................................................................................. 39
4-30 PCI Register 41h ................................................................................................................. 39
4-31 PCI Register 42h ................................................................................................................. 39
4-32 Power Management Capabilities Register Description...................................................................... 39
4-33 PCI Register 44h ................................................................................................................. 40
4-34 Power Management Control/Status Register Description................................................................... 40
4-35 PCI Register 46h ................................................................................................................. 40
4-36 PCI Register 47h ................................................................................................................. 41
4-37 PCI Register 48h ................................................................................................................. 41
4-38 PCI Register 49h ................................................................................................................. 41
4-39 PCI Register 4Ah................................................................................................................. 41
Copyright ©2011, Texas Instruments Incorporated List of Tables 7
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
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4-40 MSI Message Control Register Description................................................................................... 42
4-41 PCI Register 4Ch................................................................................................................. 42
4-42 MSI Lower Message Address Register Description ......................................................................... 42
4-43 PCI Register 4Ch................................................................................................................. 43
4-44 PCI Register 54h ................................................................................................................. 43
4-45 MSI Message Data Register Description...................................................................................... 43
4-46 PCI Register 60h ................................................................................................................. 44
4-47 PCI Register 61h ................................................................................................................. 44
4-48 Frame Length Adjustment Register Description ............................................................................. 44
4-49 PCI Register 70h ................................................................................................................. 44
4-50 PCI Register 71h ................................................................................................................. 45
4-51 PCI Register 72h ................................................................................................................. 45
4-52 PCI Express Capabilities Register Description............................................................................... 45
4-53 PCI Register 74h ................................................................................................................. 46
4-54 Device Capabilities Register Description...................................................................................... 46
4-55 PCI Register 78h ................................................................................................................. 47
4-56 Device Control Register Description........................................................................................... 47
4-57 PCI Register 7Ah................................................................................................................. 48
4-58 Device Status Register Description............................................................................................ 48
4-59 PCI Register 7Ch................................................................................................................. 48
4-60 Link Capabilities Register Description......................................................................................... 48
4-61 PCI Register 80h ................................................................................................................. 49
4-62 Link Control Register Description .............................................................................................. 49
4-63 PCI Register 82h ................................................................................................................. 50
4-64 Link Status Register Description ............................................................................................... 50
4-65 PCI Register 94h ................................................................................................................. 51
4-66 Device Capabilities 2 Register Description ................................................................................... 51
4-67 PCI Register 98h ................................................................................................................. 51
4-68 Device Control 2 Register Description......................................................................................... 51
4-69 PCI Register A0h................................................................................................................. 51
4-70 Link Control 2 Register Description............................................................................................ 52
4-71 PCI Register A2h................................................................................................................. 52
4-72 Link Status 2 Register Description............................................................................................. 52
4-73 PCI Register B0h................................................................................................................. 52
4-74 PCI Register B1h................................................................................................................. 53
4-75 PCI Register B2h................................................................................................................. 53
4-76 Serial Bus Slave Address Register Description.............................................................................. 53
4-77 PCI Register B3h................................................................................................................. 54
4-78 Serial Bus Control and Status Register Description......................................................................... 54
4-79 PCI Register B4h................................................................................................................. 54
4-80 GPIO Control Register Description ............................................................................................ 55
4-81 PCI Register B6h................................................................................................................. 55
4-82 GPIO Data Register Description ............................................................................................... 55
4-83 PCI Register C0h................................................................................................................. 56
4-84 PCI Register C1h................................................................................................................. 56
4-85 PCI Register C2h................................................................................................................. 56
4-86 MSI-X Message Control Register Description................................................................................ 56
4-87 PCI Register C4h................................................................................................................. 57
8List of Tables Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
4-88 MSI-X Table Offset and BIR Register Description........................................................................... 57
4-89 PCI Register C8h................................................................................................................. 57
4-90 MSI-X PBA Offset and BIR Register Descriptions........................................................................... 57
4-91 PCI Register D0h................................................................................................................. 58
4-92 Subsystem Access Register Description...................................................................................... 58
4-93 PCI Register D4h................................................................................................................. 58
4-94 General Control 0 Register Description ....................................................................................... 59
4-95 PCI Register D8h................................................................................................................. 59
4-96 General Control 1 Register Description ....................................................................................... 59
4-97 PCI Register DCh ................................................................................................................ 60
4-98 General Control 2 Register Description ....................................................................................... 60
4-99 PCI Register E0h................................................................................................................. 61
4-100 USB Control Register Description.............................................................................................. 61
4-101 PCI Register E4h................................................................................................................. 62
4-102 De-Emphasis and Swing Control Register Description ..................................................................... 63
4-103 PCI Register E8h................................................................................................................. 63
4-104 Equalizer Control Register Description........................................................................................ 64
4-105 PCI Register ECh ................................................................................................................ 64
4-106 Custom PHY Transmit/Receive Control Register Description.............................................................. 65
5-1 PCI Express Extended Configuration Register Map......................................................................... 66
5-2 PCI Express Extended Register 100h......................................................................................... 66
5-3 PCI Express Extended Register 102h......................................................................................... 67
5-4 PCI Express Extended Register 104h......................................................................................... 67
5-5 Custom PHY Transmit/Receive Control Register Description.............................................................. 67
5-6 PCI Express Extended Register 108h......................................................................................... 68
5-7 Bit Descriptions –Uncorrectable Error Mask Register ...................................................................... 68
5-8 PCI Express Extended Register 10Ch ........................................................................................ 69
5-9 Bit Descriptions –Uncorrectable Error Severity Register................................................................... 69
5-10 PCI Express Extended Register 110h......................................................................................... 70
5-11 Bit Descriptions –Correctable Error Severity Register...................................................................... 70
5-12 PCI Express Extended Register 114h......................................................................................... 71
5-13 Bit Descriptions –Correctable Error Mask Register......................................................................... 71
5-14 PCI Express Extended Register 118h......................................................................................... 72
5-15 Bit Descriptions –Advanced Error Capabilities and Control Register..................................................... 72
5-16 PCI Express Extended Register 11Ch, 120, 124h, and 128h.............................................................. 73
5-17 Device Serial Number Capability ID Register ................................................................................ 73
5-18 Next Capability Offset/Capability Version Register .......................................................................... 73
5-19 Device Serial Number Register................................................................................................. 74
5-20 Bit Descriptions - Device Serial Number Register ........................................................................... 74
6-1 xHCI Register Map............................................................................................................... 75
6-2 Host Controller Capability Register Map ...................................................................................... 75
6-3 HC Capability Register 00h..................................................................................................... 75
6-4 HC Capability Register 02h..................................................................................................... 76
6-5 HC Capability Register 04h..................................................................................................... 76
6-6 HC Structural Parameters 1 Description ...................................................................................... 76
6-7 HC Capability Register 08h..................................................................................................... 77
6-8 HC Structural Parameters 2 Description ...................................................................................... 77
6-9 HC Capability Register 0Ch..................................................................................................... 77
Copyright ©2011, Texas Instruments Incorporated List of Tables 9
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
www.ti.com
6-10 HC Structural Parameters 3 Description ...................................................................................... 78
6-11 HC Capability Register 10h..................................................................................................... 78
6-12 HC Capability Parameters Description ........................................................................................ 78
6-13 HC Capability Register 14h..................................................................................................... 79
6-14 HC Capability Register 18h..................................................................................................... 79
6-15 Host Controller Operational Register Map .................................................................................... 80
6-16 HC Operational Register (Operational Base + 00h) ......................................................................... 80
6-17 HC Operational Register (Operational Base + 00h) ......................................................................... 81
6-18 USB Command Register Description.......................................................................................... 81
6-19 HC Operational Register (Operational Base + 04h) ......................................................................... 81
6-20 USB Status Register Description............................................................................................... 82
6-21 HC Operational Register (Operational Base + 08h) ......................................................................... 82
6-22 Page Size Register Description ................................................................................................ 82
6-23 HC Operational Register (Operational Base + 14h) ......................................................................... 83
6-24 Device Notification Control Register Description............................................................................. 83
6-25 HC Operational Register (Operational Base + 18h) ......................................................................... 83
6-26 Command Ring Control Register Description ................................................................................ 84
6-27 HC Operational Register (Operational Base + 30h) ......................................................................... 84
6-28 Device Context Base Address Array Pointer Register Description........................................................ 84
6-29 HC Operational Register (Operational Base + 38h) ......................................................................... 85
6-30 Configure Register Description................................................................................................. 85
6-31 HC Operational Register (Operational Base + 400h + (10h*(n-1))), where n = Port Number.......................... 85
6-32 Port Status and Control Register Description ................................................................................ 85
6-33 HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number.......................... 86
6-34 Port PM Status and Control Register (USB 3.0) Description............................................................... 86
6-35 HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number.......................... 87
6-36 Port PM Status and Control Register (USB 2.0) Description............................................................... 87
6-37 HC Operational Register (Operational Base + 408h + (10h*(n-1))), where n = Port Number.......................... 87
6-38 Port Link Info Register Description............................................................................................. 88
6-39 Host Controller Runtime Register Map........................................................................................ 88
6-40 HC Runtime Register (Runtime Base + 00h)................................................................................. 88
6-41 Microframe Index Register Description........................................................................................ 88
6-42 HC Runtime Register (Runtime Base + 20h + (20h*Interrupter)),
where Interrupter = 0 through 7 ................................................................................................ 89
6-43 Interrupter Management Register Description................................................................................ 89
6-44 HC Runtime Register (Runtime Base + 24h + (20h*Interrupter)),
where Interrupter = 0 through 7 ................................................................................................ 89
6-45 Interrupter Management Register Description................................................................................ 89
6-46 HC Runtime Register (Runtime Base + 28h + (20h*Interrupter)),
where Interrupter = 0 through 7 ................................................................................................ 90
6-47 Event Ring Segment Table Size Register Description ...................................................................... 90
6-48 HC Runtime Register (Runtime Base + 30h + (20h*Interrupter)),
where Interrupter = 0 through 7 ................................................................................................ 90
6-49 Event Ring Segment Table Base Address Register Description........................................................... 91
6-50 HC Runtime Register (Runtime Base + 38h + (20h*Interrupter)),
where Interrupter = 0 through 7 ................................................................................................ 91
6-51 Event Ring Dequeue Pointer Register Description .......................................................................... 91
6-52 HC Doorbell Register (Doorbell Base + (04h*Device Slot)), where Device Slot = 0 through 64 ...................... 92
6-53 Interrupter Management Register Description................................................................................ 92
6-54 xHCI Extended Capabilities Register Map.................................................................................... 92
10 List of Tables Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
6-55 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 00h)........................................ 93
6-56 USB Legacy Support Capability Register Description....................................................................... 93
6-57 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 04h)........................................ 93
6-58 USB Legacy Support Control/Status Register Description ................................................................. 93
6-59 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 10h)........................................ 94
6-60 xHCI Supported Protocol Capability Register (USB 2.0) Description ..................................................... 94
6-61 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 14h)........................................ 95
6-62 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 18h)........................................ 95
6-63 xHCI Supported Protocol Capability Register (USB 2.0) Description ..................................................... 95
6-64 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 20h)........................................ 96
6-65 xHCI Supported Protocol Capability Register (USB 3.0) Description ..................................................... 96
6-66 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 24h)........................................ 96
6-67 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 28h)........................................ 97
6-68 xHCI Supported Protocol Capability Register (USB 3.0) Description ..................................................... 97
7-1 MSI-X Table and PBA Register Map .......................................................................................... 98
8-1 Differential Output Swing........................................................................................................ 99
8-2 Differential Output De-Emphasis ............................................................................................. 100
8-3 Receiver Equalizer Configuration............................................................................................. 101
9-1 Input Clock Specification....................................................................................................... 103
9-2 Input Clock 1.8-V DC Characteristics ........................................................................................ 103
9-3 Crystal Specification............................................................................................................ 103
10-1 PCI Express Link Power Management States.............................................................................. 104
10-2 PCI Express Power Management D-States................................................................................. 104
10-3 PME Support .................................................................................................................... 105
Copyright ©2011, Texas Instruments Incorporated List of Tables 11
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011–REVISED JULY 2011
www.ti.com
12 List of Tables Copyright ©2011, Texas Instruments Incorporated
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011–REVISED JULY 2011
USB 3.0 xHCI HOST CONTROLLER
Check for Samples: TUSB7320,TUSB7340
1 INTRODUCTION
1.1 Features
1•USB 3.0 Compliant xHCI Host Controller
–PCIe x1 Gen2 Interface
–Four Downstream Ports
•Two or Four Downstream Ports
•Each Downstream Port
–May Be Independently Enabled or Disabled
–Has Adjustments for Transmit Swing, De-Emphasis, and Equalization Settings
–May Be Marked as Removable/Non-Removable
–Has Independent Power Control and Overcurrent Detection
•Requires No External Flash for Default Configuration
–Optional Serial EEPROM for Custom Configuration
•Internal Spread Spectrum Generation
–Low Cost Crystal or Oscillator Support
•Supports Input Frequencies Between 20 MHz and 50 MHz
–Allows Use of 48-MHz System Reference Clock
•Best-In-Class Adaptive Receiver Equalizer Design
1.2 Target Applications
•Notebooks
•Desktop Computers
•Workstations
•Servers
•Add-In Cards and ExpressCard Implementations
•PCI Express-Based Embedded Host Controllers for HDTVs, Set-Top Boxes and Gaming Console
Applications
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PC
SS USB Device
Or
HS/FS/LS USB
Device
SS USB Device
Or
HS/FS/LS USB
Device
SS USB Device
Or
HS/FS/LS USB
Device
SS USB Device
Or
HS/FS/LS USB
Device
TUSB7340
PCIe Gen2
To
USB 3.0
Host Controller
TUSB7320, TUSB7340
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2 OVERVIEW
2.1 Description
The TUSB7320 supports up to two downstream ports. The TUSB7340 is a USB 3.0 xHCI compliant host
controller that supports up to four downstream ports. Both parts are available in a pin-compatible 100-pin
RKM package. For the remainder of this document, the name TUSB73x0 is used to reference both the
TUSB7320 and the TUSB7340.
Table 2-1. Package Information
PART NO. DOWNSTREAM PORTS PACKAGE
TUSB7320 2 100-pin RKM
TUSB7340 4 100-pin RKM
The TUSB73x0 interfaces to the host system via a PCIe x1 Gen 2 interface and provides SuperSpeed,
high-speed, full-speed, or low-speed connections on the downstream USB ports.
A typical system view of the TUSB73x0 is shown below.
Figure 2-1. Typical Application
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2.2 Related Documents
•Universal Serial Bus 2.0 Specification
•Universal Serial Bus 3.0 Specification
•eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 0.96
•PCI Express Base Specification, Revision 2.1
•PCI Express Card Electromechanical Specification, Revision 2.0
•ExpressCard Standard, Release 2.0
•PCI Express Mini Card Electromechanical Specification, Revision 1.2
•PCI Bus Power Management Interface Specification, Revision 1.2
•PCI Local Bus Specification, Revision 3.0
•Guidelines for 64-Bit Global Identifier (EUI-64) Registration Authroity
2.3 Document's Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit
binary field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. Differential signal names end with P, N, +, or –designators. The P or + designators signify the positive
signal associated with the differential pair. The N or –designators signify the negative signal
associated with the differential pair.
6. RSVD indicates that the referenced item is reserved.
7. In Section 4 through Section 6, the configuration space for the host controller is defined. For each
register bit, the software access method is identified in an access column. The legend for this access
column includes the following entries:
–r–read access by software
–u–updates by the host controller internal hardware
–w–write access by software
–c–clear an asserted bit with a write-back of 1b by software. Write of zero to the field has no effect
–s–the field may be set by a write of one. Write of zero to the field has no effect
–na –not accessible or not applicable
2.4 Available Options
2.5 ORDERING INFORMATION(1)
TAPACKAGE(2) ORDERABLE PART NUMBER
TUSB7320RKM
0°C to 70°C 100-terminal (Lead-Free) (RKM) PWQFN TUSB7340RKM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright ©2011, Texas Instruments Incorporated OVERVIEW 15
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VDD33
CLKREQ#
VDD11
WAKE#
OVERCUR2#
PWRON2#
OVERCUR1#
PWRON1#
JTAG_TDI
JTAG_RST#
VDD33
JTAG_TDO
VDD11
JTAG_TMS
JTAG_TCK
NC
VDD11
NC
NC
NC
NC
NC
VDD11
NC
NC
A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27
PERST# A40 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 A26 NC
VDD11 B37 B24 VDD11
PCIE_TXN A41 A25 VDDA_3P3
PCIE_TXP B38 B23 R1EXTRTN
PCIE_RXN A42 A24 R1EXT
PCIE_RXP B39 B22 VDDA_3P3
NC A43 A23 XI
VDD11 B40 B21 VSS_OSC
VDDA_3P3 A44 A22 XO
PCIE_REFCLKN B41 B20 VSS
PCIE_REFCLKP A45 A21 VDDA_3P3
VDD11 B42 B19 VDD11
NC A46 A20 USB_DP_DN1
NC B43 B18 USB_DM_DN1
VDD33 A47 A19 VDDA_3P3
VDD11 B44 B17 VDD11
NC A48 A18 USB_SSRXP_DN1
NC B45 B16 USB_SSRXN_DN1
GPIO0 A49 A17 USB_SSTXP_DN1
GPIO1 B46 B15 USB_SSTXN_DN1
VDD11 A50 A16 VDD11
GPIO2 B47 B14 FREQSEL
VDD33 A51 A15 GRST#
GPIO3 B48 B13 NC
AUX_DET A52 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 A14 NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
VDD11
VDD11
SDA
SCL
VDD33
SMI
VDD11
NC
NC
NC
VDD11
NC
NC
NC
NC
NC
VDD11
USB_SSRXP_DN2
USB_SSRXN_DN2
USB_SSTXN_DN2
USB_SSTXP_DN2
VDDA_3P3
VDD11
USB_DP_DN2
USB_DM_DN2
VSS
TUSB7320, TUSB7340
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2.6 Terminal Assignments
Figure 2-2. TUSB7320 RKM Package (Top View)
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VDD33
CLKREQ#
VDD11
WAKE#
OVERCUR2#
PWRON2#
OVERCUR1#
PWRON1#
JTAG_TDI
JTAG_RST#
VDD33
JTAG_TDO
VDD11
JTAG_TMS
JTAG_TCK
NC
VDD11
USB_SSTXP_DN3
USB_SSTXN_DN3
USB_SSRXP_DN3
USB_SSRXN_DN3
VDDA_3P3
VDD11
USB_DP_DN3
USB_DM_DN3
A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27
PERST# A40 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 A26 NC
VDD11 B37 B24 VDD11
PCIE_TXN A41 A25 VDDA_3P3
PCIE_TXP B38 B23 R1EXTRTN
PCIE_RXN A42 A24 R1EXT
PCIE_RXP B39 B22 VDDA_3P3
NC A43 A23 XI
VDD11 B40 B21 VSS_OSC
VDDA_3P3 A44 A22 XO
PCIE_REFCLKN B41 B20 VSS
PCIE_REFCLKP A45 A21 VDDA_3P3
VDD11 B42 B19 VDD11
PWRON3# A46 A20 USB_DP_DN1
OVERCUR3# B43 B18 USB_DM_DN1
VDD33 A47 A19 VDDA_3P3
VDD11 B44 B17 VDD11
PWRON4# A48 A18 USB_SSRXP_DN1
OVERCUR4# B45 B16 USB_SSRXN_DN1
GPIO0 A49 A17 USB_SSTXP_DN1
GPIO1 B46 B15 USB_SSTXN_DN1
VDD11 A50 A16 VDD11
GPIO2 B47 B14 FREQSEL
VDD33 A51 A15 GRST#
GPIO3 B48 B13 NC
AUX_DET A52 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 A14 NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
VDD11
VDD11
SDA
SCL
VDD33
SMI
VDD11
VDDA_3P3
USB_DM_DN4
USB_DP_DN4
VDD11
USB_SSRXP_DN4
USB_SSRXN_DN4
USB_SSTXP_DN4
USB_SSTXN_DN4
NC
VDD11
USB_SSRXP_DN2
USB_SSRXN_DN2
USB_SSTXN_DN2
USB_SSTXP_DN2
VDDA_3P3
VDD11
USB_DP_DN2
USB_DM_DN2
VSS
TUSB7320, TUSB7340
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Figure 2-3. TUSB7340 RKM Package (Top View)
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2.7 Terminal Descriptions
The following tables give a description of the terminals. These terminals are grouped in tables by
functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
TYPE DESCRIPTION
I Input
O Output
I/O Input/Output
PD, PU Internal pull-down/pull-up
S Strapping pin
P Power supply
G Ground
Table 2-2. Clock and Reset Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
Global power reset. This reset brings all of the TUSB73x0 internal registers to their
I
GRST# A15 A15 default states. When GRST# is asserted, the device is completely nonfunctional. GRST#
PU should be asserted until all power rails are valid at the device.
Crystal input. This terminal is the crystal input for the internal oscillator. The input may
XI A23 A23 I alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ
feedback resistor is required between XI and XO.
Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an
XO A22 A22 O external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ
feedback resistor is required between XI and XO.
Frequency select. This terminal indicates the oscillator input frequency and is used to
configure the correct PLL multiplier.
FREQSEL B14 B14 I If the FREQSEL pin is '0', the frequency used is 48 MHz. If the FREQSEL pin is '1', refer
to Table 4-100: USB Control Register Description.
PCIE_ PCI Express Reference Clock. PCIE_REFCLKP and PCIE_REFCLKN comprise the
REFCLKP A45 A45 differential input pair for the 100-MHz system reference clock.
I
PCIE_ B41 B41
REFCLKN PCI Express Reset Input. The PERST# signal is used to signal when the system power is
PERST# A40 A40 I stable. The PERST# signal is also used to generate an internal power on reset
Table 2-3. PCI Express Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
PCIE_TXP B38 B38 O PCI Express transmitter differential pair (positive).
PCIE_TXN A41 A41 O PCI Express transmitter differential pair (negative).
PCIE_RXP B39 B39 I PCI Express receiver differential pair (positive).
PCIE_RXN A42 A42 I PCI Express receiver differential pair (negative).
Wake. Wake is an active low signal that is driven low to reactivate the PCI Express link
hierarchy’s main power rails and reference clocks.
WAKE#(1) B35 B35 O Note: WAKE# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
PCI Express REFCLK Request signal.
CLKREQ#(1) B36 B36 O Note: CLKREQ# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
(1) The only failsafe pins in the device are WAKE and CLKREQ#. No other pins are failsafe.
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Table 2-4. USB Downstream Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_ A17 A17 O Note: When routing, it is permissible to swap the positive and negative signals in Port 1
DN1 SSTX differential pair.
USB_SSTXN_ USB SuperSpeed transmitter differential pair (negative).
DN1 B15 B15 O Note: When routing, it is permissible to swap the positive and negative signals in Port 1
SSTX differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_ A18 A18 I Note: When routing, it is permissible to swap the positive and negative signals in Port 1
DN1 SSRX differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_ B16 B16 I Note: When routing, it is permissible to swap the positive and negative signals in Port 1
DN1 SSRX differential pair.
USB_DP_DN1 A20 A20 I/O USB High-speed differential transceiver (positive).
USB_DM_DN1 B18 B18 I/O USB High-speed differential transceiver (negative).
USB DS Port 1 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON1# B33 B33 PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 1 Over-Current Detection.
I
OVERCUR1# A36 A36 0: over-current detected;
PU 1: over-current not detected
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_ A11 A11 O Note: When routing, it is permissible to swap the positive and negative signals in Port 2
DN2 SSTX differential pair.
USB SuperSpeed transmitter differential pair (negative).
USB_SSTXN_ B10 B10 O Note: When routing, it is permissible to swap the positive and negative signals in Port 2
DN2 SSTX differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_ B9 B9 I Note: When routing, it is permissible to swap the positive and negative signals in Port 2
DN2 SSRX differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_ A10 A10 I Note: When routing, it is permissible to swap the positive and negative signals in Port 2
DN2 SSRX differential pair.
USB_DP_DN2 B12 B12 I/O USB High-speed differential transceiver (positive).
USB_DM_DN2 A13 A13 I/O USB High-speed differential transceiver (negative).
USB DS Port 2 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON2# B34 B34 PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 2 Over-Current Detection.
I
OVERCUR2# A37 A37 0: over-current detected;
PU 1: over-current not detected
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_ N/A B28 O Note: When routing, it is permissible to swap the positive and negative signals in Port 3
DN3 SSTX differential pair.
USB SuperSpeed transmitter differential pair (negative).
USB_SSTXN_ N/A A30 O Note: When routing, it is permissible to swap the positive and negative signals in Port 3
DN3 SSTX differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_ N/A B27 I Note: When routing, it is permissible to swap the positive and negative signals in Port 3
DN3 SSRX differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_ N/A A29 I Note: When routing, it is permissible to swap the positive and negative signals in Port 3
DN3 SSRX differential pair.
USB_DP_DN3 N/A B25 I/O USB High-speed differential transceiver (positive).
USB_DM_DN3 N/A A27 I/O USB High-speed differential transceiver (negative).
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Table 2-4. USB Downstream Signals (continued)
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
USB DS Port 3 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON3# N/A A46 PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 3 Over-Current Detection.
I
OVERCUR3# N/A B43 0: over-current detected;
PU 1: over-current not detected
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_ N/A B7 O Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4 SSTX differential pair.
USB SuperSpeed transmitter differential pair (negative).
USB_SSTXN_ N/A A8 O Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4 SSTX differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_ N/A B6 I Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4 SSRX differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_ N/A A7 I Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4 SSRX differential pair.
USB_DP_DN4 N/A B5 I/O USB High-speed differential transceiver (positive).
USB_DM_DN4 N/A A5 I/O USB High-speed differential transceiver (negative).
USB DS Port 4 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON4# N/A A48 PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 4 Over-Current Detection.
I
OVERCUR4# N/A B45 0: over-current detected;
PU 1: over-current not detected
Table 2-5. I2C Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
SCL B2 B2 I/O I2C Clock - If no I2C device is present, pull this line down to disable.
SDA A2 A2 I/O I2C Data - If no I2C device is present, pull this line down to disable.
Table 2-6. Test and Miscellaneous Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
I
JTAG_TCK A32 A32 JTAG test clock
PD
I
JTAG_TDI A35 A35 JTAG test data in
PU
O
JTAG_TDO B31 B31 JTAG test data out
PD
I
JTAG_TMS B30 B30 JTAG test mode select
PU
I
JTAG_RST# B32 B32 JTAG reset. Should be pulled low for normal operation.
PD
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Table 2-6. Test and Miscellaneous Signals (continued)
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
GPIO[0]
GPIO[1] A49, B46, A49, B46, I/O General purpose I/O
GPIO[2] B47, B48 B47, B48 PU
GPIO[3] System management interrupt
SMI B3 B3 O Note: This pin is active high and should not be pulled up/down.
R1EXT High precision external resistor used for calibration. A resister value of 9.09 KΩ ±1%
A24, B23 A24, B23 OI
R1EXTRTN accuracy is connected between the terminals R1EXT and R1EXTRTN.
Auxiliary power detect. This pin indicates if the TUSB73X0 is enabled for wakeup from
D3cold.
AUX_DET A52 A52 I Note: If this feature is implemented, AUX_DET must be pulled to VDD33 to prevent
leakage.
B4, A5, B5,
B6, A7, B7,
A8, B8, B13,
A14, B25,
A26, B26, A14, B8, Pins are not connected internally.
NC A27, B27, B13, A26, I/O Note: TUSB7320 pins B4 and B26 may be connected to VDDA_3P3 to support a
B28, A29, B29, A43 dual-layout option with the TUSB7340.
B29, A30,
A43, B43,
B45, A46,
A48
Table 2-7. Power Signals
TERMINAL I/O DESCRIPTION
TUSB7320 TUSB7340
NAME PIN NO. PIN NO.
A3, A34, A3, A34, PW
VDD33 A39, A47, A39, A47, 3.3-V I/O power rail
R
A51 A51
B4, B11,
B11, A19, A19, A21, PW
VDDA_3P3 A21, A25, 3.3-V analog power rail
A25, B22, R
B22, A44 B26, A44
A1, B1, A4, A1, B1, A4,
A6, A9, A12, A6, A9,
A16, B17, A12, A16,
B19, B24, B17, B19, PW
VDD11 A28, A33, B24, A28, 1.1-V core power rail
R
A31, A38, A33, A31,
B37, B40, A38, B37,
B42, B44, B40, B42,
A50 B44, A50 PW
VSS B20, A53 B20, A53 Ground. The ground pad is labeled A53 for schematic purposes.
R
C1, C2, C3, C1, C2, C3, PW The corner pins, which are for mechanical stability of the package, are connected to
VSS_NC C4 C4 R ground internally. These pins may be connected to VSS or left unconnected.
Oscillator return.
PW If using a crystal, the load capacitors should use this signal as the return path and it
VSS_OSC B21 B21 R should not be connected to the PCB ground.
If using an oscillator, this should be connected to PCB Ground.
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PERST#
VDDA_3P3
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GRST#
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3 FEATURE/PROTOCOL DESCRIPTIONS
3.1 Power-Up/-Down Sequencing
The host controller contains both 1.1-V and 3.3-V power terminals. The following power-up and
power-down sequences describe how power is applied to these terminals.
In addition, the host controller has three resets: PERST#, GRST#, and an internal power- on reset. These
resets are fully described in the next section. The following power-up and power-down sequences
describe how PERST# is applied to the host controller.
The application of the PCI Express reference clock (PCIE_REFCLK) is important to the power-up/-down
sequence and is included in the following power-up and power-down descriptions.
3.1.1 Power-Up Sequence
1. Assert PERST# to the device.
2. Apply 1.1-V and 3.3-V voltages.
3. GRST# must remain asserted until both the 1.1-V and 3.3-V voltages have reached the minimum
recommended operating voltage, see Section 11.2.
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two
delay requirements are satisfied:
Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit satisfies
the requirement for stable device clocks by the de-assertion of PERST.
Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the de-assertion of PERST.
See the power-up sequencing diagram in Figure 3-1.
Figure 3-1. Power-Up Sequence
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VDDA_3P3
and VDD33
PCIE_REFCLK
PERST#
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3.1.2 Power-Down Sequence
1. Assert PERST# to the device.
2. Remove the reference clock.
3. Remove the 3.3-V and 1.1-V voltages
See the power power-down sequencing diagram in Figure 3-2. If the VDD33_AUX terminal is to remain
powered after a system shutdown, then the host controller power-down sequence is exactly the same as
shown in Figure 3-2.
Figure 3-2. Power-Down Sequence
3.2 Two-Wire Serial-Bus Interface
The host controller provides a two-wire serial-bus interface to load subsystem identification information
and specific register defaults from an external EEPROM. The serial-bus interface signals include SDA and
SCL. The use of an external EEPROM is optional. The TUSB73x0 will function with the default settings.
For motherboard down applications, BIOS can be used to set all of the options available on the
TUSB73x0.
On a PCIe Add-in Card, an EEPROM is only needed if a any of the following is true:
•Use of a crystal other than 48 MHz.
•Mark one or more USB ports as non-removable.
•Disable one or more USB ports.
•Set a PCIe Subsystem ID and Subsystem Vendor ID.
•Change the default de-emphasis/swing/equalizer settings of the SuperSpeed USB ports.
•Change the default L0s and L1 latency values for PCIe.
•Change the default PWRON polarity to active high instead of active low.
3.2.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pull-up resistor must be implemented on the SCL signal. At the rising
edge of PERST# or GRST#, whichever occurs later in time, the SCL terminal is checked for a pull-up
resistor. If one is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see
Section 4.52) is set. Software may disable the serial-bus interface at any time by writing a 0b to the
SBDETECT bit. If no external EEPROM is required, then the serial-bus interface is permanently disabled
by attaching a pulldown resistor to the SCL signal.
The host controller implements a two-terminal serial interface with one clock signal (SCL) and one data
signal (SDA). The SCL signal is a unidirectional output from the host controller and the SDA signal is
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SDA
VDD33
A0
A1
A2
SCL
SDA
TUSB73x0
Serial
EEPROM
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bidirectional. Both are open-drain signals and require pull-up resistors. The host controller is a bus master
device and drives SCL at approximately 60 kHz during data transfers and places SCL in a
high-impedance state (0 frequency) during bus idle states. The serial EEPROM is a bus slave device and
must acknowledge a slave address equal to A0h. Figure 3-3 illustrates an example application
implementing the two-wire serial bus.
Figure 3-3. Serial EEPROM Application
24 FEATURE/PROTOCOL DESCRIPTIONS Copyright ©2011, Texas Instruments Incorporated
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SCL From
Master 1 2 3 7 8 9
SDA Output
By Transmitter
SDA Output
By Receiver
TUSB7320, TUSB7340
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SLLSE76E–MARCH 2011–REVISED JULY 2011
3.2.2 Serial-Bus Interface Protocol
All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a
start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high
state, as illustrated in Figure 3-4. The end of a requested data transfer is indicated by a stop condition,
which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-4.
Data