TUSB7320, TUSB7340 USB 3.0 xHCI HOST CONTROLLER Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLLSE76E March 2011 - Revised July 2011 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Contents 1 2 3 4 2 INTRODUCTION ................................................................................................................. 13 .................................................................................................................... 13 ........................................................................................................ 13 OVERVIEW ....................................................................................................................... 14 2.1 Description ................................................................................................................. 14 2.2 Related Documents ....................................................................................................... 15 2.3 Document's Conventions ................................................................................................. 15 2.4 Available Options .......................................................................................................... 15 2.5 ORDERING INFORMATION ............................................................................................. 15 2.6 Terminal Assignments .................................................................................................... 16 2.7 Terminal Descriptions ..................................................................................................... 18 FEATURE/PROTOCOL DESCRIPTIONS ................................................................................ 22 3.1 Power-Up/-Down Sequencing ........................................................................................... 22 3.1.1 Power-Up Sequence ........................................................................................... 22 3.1.2 Power-Down Sequence ........................................................................................ 23 3.2 Two-Wire Serial-Bus Interface ........................................................................................... 23 3.2.1 Serial-Bus Interface Implementation ......................................................................... 23 3.2.2 Serial-Bus Interface Protocol .................................................................................. 25 3.2.3 Serial-Bus EEPROM Application ............................................................................. 27 3.3 System Management Interrupt ........................................................................................... 28 CLASSIC PCI CONFIGURATION SPACE ............................................................................... 29 4.1 The PCI Configuration Map .............................................................................................. 29 4.2 Vendor ID Register ........................................................................................................ 30 4.3 Device ID Register ........................................................................................................ 30 4.4 Command Register ........................................................................................................ 31 4.5 Status Register ............................................................................................................ 32 4.6 Class Code and Revision ID Register .................................................................................. 33 4.7 Cache Line Size Register ................................................................................................ 33 4.8 Latency Timer Register ................................................................................................... 34 4.9 Header Type Register .................................................................................................... 34 4.10 BIST Register .............................................................................................................. 34 4.11 Base Address Register 0 ................................................................................................. 35 4.12 Base Address Register 1 ................................................................................................. 35 4.13 Base Address Register 2 ................................................................................................. 36 4.14 Base Address Register 3 ................................................................................................. 36 4.15 Subsystem Vendor ID Register .......................................................................................... 37 4.16 Subsystem ID Register ................................................................................................... 37 4.17 Capabilities Pointer Register ............................................................................................. 37 4.18 Interrupt Line Register .................................................................................................... 38 4.19 Interrupt Pin Register ..................................................................................................... 38 4.20 Min Grant Register ........................................................................................................ 38 4.21 Max Latency Register ..................................................................................................... 38 4.22 Capability ID Register ..................................................................................................... 39 4.23 Next Item Pointer Register ............................................................................................... 39 4.24 Power Management Capabilities Register ............................................................................. 39 1.1 Features 1.2 Target Applications Contents Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 5 .......................................................................... 40 ............................................................ 40 4.27 Power Management Data Register ..................................................................................... 41 4.28 MSI Capability ID Register ............................................................................................... 41 4.29 Next Item Pointer Register ............................................................................................... 41 4.30 MSI Message Control Register .......................................................................................... 41 4.31 MSI Lower Message Address Register ................................................................................. 42 4.32 MSI Upper Message Address Register ................................................................................. 43 4.33 MSI Message Data Register ............................................................................................. 43 4.34 Serial Bus Release Number Register (SBRN) ......................................................................... 44 4.35 Frame Length Adjustment Register (FLADJ) .......................................................................... 44 4.36 PCI Express Capability ID Register ..................................................................................... 44 4.37 Next Item Pointer Register ............................................................................................... 45 4.38 PCI Express Capabilities Register ...................................................................................... 45 4.39 Device Capabilities Register ............................................................................................. 46 4.40 Device Control Register .................................................................................................. 47 4.41 Device Status Register ................................................................................................... 48 4.42 Link Capabilities Register ................................................................................................ 48 4.43 Link Control Register ...................................................................................................... 49 4.44 Link Status Register ....................................................................................................... 50 4.45 Device Capabilities 2 Register ........................................................................................... 50 4.46 Device Control 2 Register ................................................................................................ 51 4.47 Link Control 2 Register ................................................................................................... 51 4.48 Link Status 2 Register .................................................................................................... 52 4.49 Serial Bus Data Register ................................................................................................. 52 4.50 Serial Bus Index Register ................................................................................................ 53 4.51 Serial Bus Slave Address Regsiter ..................................................................................... 53 4.52 Serial Bus Control and Status Register ................................................................................ 53 4.53 GPIO Control Register .................................................................................................... 54 4.54 GPIO Data Register ....................................................................................................... 55 4.55 MSI-X Capability ID Register ............................................................................................ 56 4.56 Next Item Pointer Register ............................................................................................... 56 4.57 MSI-X Message Control Register ....................................................................................... 56 4.58 MSI-X Table Offset and BIR Register .................................................................................. 57 4.59 MSI-X PBA Offset and BIR Register .................................................................................... 57 4.60 Subsystem Access Register ............................................................................................. 58 4.61 General Control 0 Register ............................................................................................... 58 4.62 General Control 1 Register ............................................................................................... 59 4.63 General Control 2 Register ............................................................................................... 60 4.64 USB Control Register ..................................................................................................... 60 4.65 De-Emphasis and Swing Control Register ............................................................................. 62 4.66 Equalizer Control Register ............................................................................................... 63 4.67 Custom PHY Transmit/Receive Control Register ..................................................................... 64 PCI EXPRESS EXTENDED CONFIGURATION SPACE ............................................................. 66 5.1 The PCI Express Extended Configuration Map ....................................................................... 66 5.2 Advanced Error Reporting capability Register ......................................................................... 66 4.25 Power Management Control/Status Register 4.26 Power Management Bridge Support Extension Register Copyright (c) 2011, Texas Instruments Incorporated Contents 3 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 6 4 www.ti.com .................................................................. 67 .................................................................................... 67 5.5 Uncorrectable Error Mask Register ..................................................................................... 68 5.6 Uncorrectable Error Severity Register .................................................................................. 69 5.7 correctable Error Severity Register ..................................................................................... 70 5.8 correctable Error Mask Register ......................................................................................... 71 5.9 Advanced Error Capabilities and control Register .................................................................... 72 5.10 Header Log Register ...................................................................................................... 73 5.11 Device Serial Number Capability ID Register .......................................................................... 73 5.12 Next Capability Offset/Capability Version Register ................................................................... 73 5.13 Device Serial Number Register .......................................................................................... 74 xHCI MEMORY MAPPED REGISTER SPACE ......................................................................... 75 6.1 The xHCI Register Map ................................................................................................... 75 6.2 Host Controller Capability Registers .................................................................................... 75 6.2.1 Capability Registers Length ................................................................................... 75 6.2.2 Host Controller Interface Version Number .................................................................. 76 6.2.3 Host Controller Structural Parameters 1 ..................................................................... 76 6.2.4 Host Controller Structural Parameters 2 ..................................................................... 77 6.2.5 Host Controller Structural Parameters 3 ..................................................................... 77 6.2.6 Host Controller Capability Parameters ....................................................................... 78 6.2.7 Doorbell Offset .................................................................................................. 79 6.2.8 Runtime Register Space Offset ............................................................................... 79 6.3 Host Controller Operational Registers .................................................................................. 80 6.3.1 USB Command Register ...................................................................................... 80 6.3.2 USB Command Register ...................................................................................... 81 6.3.3 USB Status Register ........................................................................................... 81 6.3.4 Page Size Register ............................................................................................. 82 6.3.5 Device Notification Control Register ......................................................................... 83 6.3.6 Command Ring Control Register ............................................................................. 83 6.3.7 Device Context Base Address Array Pointer Register ..................................................... 84 6.3.8 Configure Register .............................................................................................. 85 6.3.9 Port Status and Control Register ............................................................................. 85 6.3.10 Port PM Status and Control Register (USB 3.0 Ports) .................................................... 86 6.3.11 Port PM Status and Control Register (USB 2.0 Ports) .................................................... 87 6.3.12 Port Link Info Register ......................................................................................... 87 6.4 Host Controller Runtime Registers ...................................................................................... 88 6.4.1 Microframe Index Register .................................................................................... 88 6.4.2 Interrupter Management Register ............................................................................ 89 6.4.3 Interrupter Moderation Register .............................................................................. 89 6.4.4 Event Ring Segment Table Size Register ................................................................... 90 6.4.5 Event Ring Segment Table Base Address Register ....................................................... 90 6.4.6 Event Ring Dequeue Pointer Register ....................................................................... 91 6.5 Host Controller Doorbell Registers ...................................................................................... 92 6.6 xHCI Extended Capabilities Registers .................................................................................. 92 6.6.1 USB Legacy Support Capability Register ................................................................... 92 6.6.2 USB Legacy Support Control/Status Register .............................................................. 93 5.3 Next Capability Offset / Capability Version Register 5.4 Uncorrectable Error Status Register Contents Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 7 8 9 10 11 .................................................. 94 ............................................... 94 6.6.5 xHCI Supported Protocol Port Register (USB 2.0) ......................................................... 95 6.6.6 xHCI Supported Protocol Capability Register (USB 3.0) .................................................. 95 6.6.7 xHCI Supported Protocol Name String Register (USB 3.0) ............................................... 96 6.6.8 xHCI Supported Protocol Port Register (USB 3.0) ......................................................... 96 MSI-X MEMORY MAPPED REGISTER SPACE ........................................................................ 98 7.1 The MSI-X Table and PBA in Memory Mapped Register Space .................................................... 98 PHY CONTROL .................................................................................................................. 99 8.1 Output Voltage Swing Control ........................................................................................... 99 8.2 De-Emphasis Control .................................................................................................... 100 8.3 Adaptive Equalizer ....................................................................................................... 100 INPUT CLOCK ................................................................................................................. 102 9.1 Clock Source Requirements ............................................................................................ 102 9.2 External clock ............................................................................................................. 103 9.3 External crystal ........................................................................................................... 103 PCI EXPRESS POWER MANAGEMENT ............................................................................... 104 10.1 Power Management ..................................................................................................... 104 10.2 PCI Express Link Power Management States ....................................................................... 104 10.3 PCI Express Power Management D-States .......................................................................... 104 10.4 Power Management Event (PME) ..................................................................................... 105 10.4.1 PME Support .................................................................................................. 105 ELECTRICAL CHARACTERISTICS ..................................................................................... 106 11.1 ABSOLUTE MAXIMUM RATINGS .................................................................................... 106 11.2 RECOMMENDED OPERATING CONDITIONS ..................................................................... 106 11.3 THERMAL INFORMATION ............................................................................................. 107 11.4 3.3-V I/O ELECTRICAL CHARACTERISTICS ....................................................................... 107 11.5 POWER CONSUMPTION FOR TUSB7320 .......................................................................... 108 11.6 POWER CONSUMPTION FOR TUSB7340 .......................................................................... 108 6.6.3 xHCI Supported Protocol Capability Register (USB 2.0) 6.6.4 xHCI Supported Protocol Name String Register (USB 2.0) Copyright (c) 2011, Texas Instruments Incorporated Contents 5 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com List of Figures 2-1 Typical Application ............................................................................................................... 14 2-2 TUSB7320 RKM Package (Top View)......................................................................................... 17 2-3 TUSB7340 RKM Package (Top View)......................................................................................... 17 3-1 Power-Up Sequence ............................................................................................................. 23 3-2 Power-Down Sequence 3-3 Serial EEPROM Application 3-4 3-5 3-6 3-7 3-8 9-1 6 ......................................................................................................... .................................................................................................... Serial-Bus Start/Stop Conditions and Bit Transfers.......................................................................... Serial-Bus Protocol Acknowledge .............................................................................................. Serial-Bus Protocal - Byte Write ................................................................................................ Serial-Bus Protocal - Byte Read ............................................................................................... Serial-Bus Protocal - Multibyte Read .......................................................................................... Oscillation Circuit ............................................................................................................... List of Figures 23 24 25 25 26 26 26 102 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com List of Tables 2-1 Package Information ............................................................................................................. 14 2-2 Clock and Reset Signals ........................................................................................................ 18 2-3 PCI Express Signals ............................................................................................................. 18 2-4 USB Downstream Signals ....................................................................................................... 19 2-5 I2C Signals 2-6 Test and Miscellaneous Signals ................................................................................................ 20 2-7 Power Signals 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 ........................................................................................................................ .................................................................................................................... EEPROM Register Loading Map ............................................................................................... PCI Configuration Register Map................................................................................................ PCI Register 00h ................................................................................................................. PCI Register 02h ................................................................................................................. PCI Register 04h ................................................................................................................. Bit Command Register Description ............................................................................................ PCI Register 06h ................................................................................................................. Status Register Description ..................................................................................................... PCI Register 06h ................................................................................................................. Class Code and Revision ID Register Description ........................................................................... PCI Register 0Ch ................................................................................................................. PCI Register 0Dh ................................................................................................................. PCI Register 0Eh ................................................................................................................. PCI Register 0Fh ................................................................................................................. PCI Register 10h ................................................................................................................. Base Address Register 0 Description ......................................................................................... PCI Register 14h ................................................................................................................. Base Address Register 1 Description ......................................................................................... PCI Register 18h ................................................................................................................. Base Address Register 2 Description ......................................................................................... PCI Register 1Ch ................................................................................................................. Table 93 Base Address Register 3 Description ............................................................................. PCI Register 2Ch ................................................................................................................. PCI Register 2Eh ................................................................................................................. PCI Register 34h ................................................................................................................. PCI Register 3Ch ................................................................................................................. PCI Register 3Dh ................................................................................................................. PCI Register 3Eh ................................................................................................................. PCI Register 3Fh ................................................................................................................. PCI Register 40h ................................................................................................................. PCI Register 41h ................................................................................................................. PCI Register 42h ................................................................................................................. Power Management Capabilities Register Description ...................................................................... PCI Register 44h ................................................................................................................. Power Management Control/Status Register Description................................................................... PCI Register 46h ................................................................................................................. PCI Register 47h ................................................................................................................. PCI Register 48h ................................................................................................................. PCI Register 49h ................................................................................................................. PCI Register 4Ah ................................................................................................................. Copyright (c) 2011, Texas Instruments Incorporated List of Tables 20 21 27 29 30 30 31 31 32 32 33 33 33 34 34 34 35 35 35 35 36 36 36 36 37 37 37 38 38 38 38 39 39 39 39 40 40 40 41 41 41 41 7 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4-40 MSI Message Control Register Description................................................................................... 42 4-41 PCI Register 4Ch ................................................................................................................. 42 4-42 MSI Lower Message Address Register Description ......................................................................... 42 4-43 PCI Register 4Ch ................................................................................................................. 43 4-44 PCI Register 54h ................................................................................................................. 43 4-45 MSI Message Data Register Description...................................................................................... 43 4-46 PCI Register 60h ................................................................................................................. 44 4-47 PCI Register 61h ................................................................................................................. 44 4-48 Frame Length Adjustment Register Description 4-49 4-50 4-51 4-52 4-53 4-54 4-55 4-56 4-57 4-58 4-59 4-60 4-61 4-62 4-63 4-64 4-65 4-66 4-67 4-68 4-69 4-70 4-71 4-72 4-73 4-74 4-75 4-76 4-77 4-78 4-79 4-80 4-81 4-82 4-83 4-84 4-85 4-86 4-87 8 ............................................................................. PCI Register 70h ................................................................................................................. PCI Register 71h ................................................................................................................. PCI Register 72h ................................................................................................................. PCI Express Capabilities Register Description ............................................................................... PCI Register 74h ................................................................................................................. Device Capabilities Register Description ...................................................................................... PCI Register 78h ................................................................................................................. Device Control Register Description ........................................................................................... PCI Register 7Ah ................................................................................................................. Device Status Register Description ............................................................................................ PCI Register 7Ch ................................................................................................................. Link Capabilities Register Description ......................................................................................... PCI Register 80h ................................................................................................................. Link Control Register Description .............................................................................................. PCI Register 82h ................................................................................................................. Link Status Register Description ............................................................................................... PCI Register 94h ................................................................................................................. Device Capabilities 2 Register Description ................................................................................... PCI Register 98h ................................................................................................................. Device Control 2 Register Description......................................................................................... PCI Register A0h ................................................................................................................. Link Control 2 Register Description ............................................................................................ PCI Register A2h ................................................................................................................. Link Status 2 Register Description ............................................................................................. PCI Register B0h ................................................................................................................. PCI Register B1h ................................................................................................................. PCI Register B2h ................................................................................................................. Serial Bus Slave Address Register Description .............................................................................. PCI Register B3h ................................................................................................................. Serial Bus Control and Status Register Description ......................................................................... PCI Register B4h ................................................................................................................. GPIO Control Register Description ............................................................................................ PCI Register B6h ................................................................................................................. GPIO Data Register Description ............................................................................................... PCI Register C0h ................................................................................................................. PCI Register C1h ................................................................................................................. PCI Register C2h ................................................................................................................. MSI-X Message Control Register Description ................................................................................ PCI Register C4h ................................................................................................................. List of Tables 44 44 45 45 45 46 46 47 47 48 48 48 48 49 49 50 50 51 51 51 51 51 52 52 52 52 53 53 53 54 54 54 55 55 55 56 56 56 56 57 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4-88 MSI-X Table Offset and BIR Register Description ........................................................................... 57 4-89 PCI Register C8h ................................................................................................................. 57 4-90 MSI-X PBA Offset and BIR Register Descriptions ........................................................................... 57 4-91 PCI Register D0h ................................................................................................................. 58 4-92 Subsystem Access Register Description ...................................................................................... 58 4-93 PCI Register D4h ................................................................................................................. 58 4-94 General Control 0 Register Description ....................................................................................... 59 4-95 PCI Register D8h ................................................................................................................. 59 4-96 General Control 1 Register Description ....................................................................................... 59 4-97 PCI Register DCh ................................................................................................................ 60 4-98 General Control 2 Register Description ....................................................................................... 60 4-99 PCI Register E0h ................................................................................................................. 61 4-100 USB Control Register Description.............................................................................................. 61 4-101 PCI Register E4h ................................................................................................................. 62 4-102 De-Emphasis and Swing Control Register Description 4-103 PCI Register E8h ................................................................................................................. 63 4-104 Equalizer Control Register Description ........................................................................................ 64 4-105 PCI Register ECh 4-106 Custom PHY Transmit/Receive Control Register Description .............................................................. 65 5-1 PCI Express Extended Configuration Register Map ......................................................................... 66 5-2 PCI Express Extended Register 100h ......................................................................................... 66 5-3 PCI Express Extended Register 102h ......................................................................................... 67 5-4 PCI Express Extended Register 104h ......................................................................................... 67 5-5 Custom PHY Transmit/Receive Control Register Description .............................................................. 67 5-6 PCI Express Extended Register 108h ......................................................................................... 68 5-7 Bit Descriptions - Uncorrectable Error Mask Register ...................................................................... 68 5-8 PCI Express Extended Register 10Ch 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 ..................................................................... ................................................................................................................ ........................................................................................ Bit Descriptions - Uncorrectable Error Severity Register ................................................................... PCI Express Extended Register 110h ......................................................................................... Bit Descriptions - Correctable Error Severity Register ...................................................................... PCI Express Extended Register 114h ......................................................................................... Bit Descriptions - Correctable Error Mask Register ......................................................................... PCI Express Extended Register 118h ......................................................................................... Bit Descriptions - Advanced Error Capabilities and Control Register ..................................................... PCI Express Extended Register 11Ch, 120, 124h, and 128h .............................................................. Device Serial Number Capability ID Register ................................................................................ Next Capability Offset/Capability Version Register .......................................................................... Device Serial Number Register................................................................................................. Bit Descriptions - Device Serial Number Register ........................................................................... xHCI Register Map ............................................................................................................... Host Controller Capability Register Map ...................................................................................... HC Capability Register 00h ..................................................................................................... HC Capability Register 02h ..................................................................................................... HC Capability Register 04h ..................................................................................................... HC Structural Parameters 1 Description ...................................................................................... HC Capability Register 08h ..................................................................................................... HC Structural Parameters 2 Description ...................................................................................... HC Capability Register 0Ch ..................................................................................................... Copyright (c) 2011, Texas Instruments Incorporated List of Tables 63 64 69 69 70 70 71 71 72 72 73 73 73 74 74 75 75 75 76 76 76 77 77 77 9 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6-10 HC Structural Parameters 3 Description ...................................................................................... 78 6-11 HC Capability Register 10h ..................................................................................................... 78 6-12 HC Capability Parameters Description ........................................................................................ 78 6-13 HC Capability Register 14h ..................................................................................................... 79 6-14 HC Capability Register 18h ..................................................................................................... 79 6-15 Host Controller Operational Register Map .................................................................................... 80 6-16 HC Operational Register (Operational Base + 00h) ......................................................................... 80 6-17 HC Operational Register (Operational Base + 00h) ......................................................................... 81 6-18 USB Command Register Description .......................................................................................... 81 6-19 HC Operational Register (Operational Base + 04h) ......................................................................... 81 6-20 USB Status Register Description ............................................................................................... 82 6-21 HC Operational Register (Operational Base + 08h) ......................................................................... 82 6-22 Page Size Register Description ................................................................................................ 82 6-23 HC Operational Register (Operational Base + 14h) ......................................................................... 83 6-24 Device Notification Control Register Description ............................................................................. 83 6-25 HC Operational Register (Operational Base + 18h) ......................................................................... 83 6-26 Command Ring Control Register Description 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 ................................................................................ HC Operational Register (Operational Base + 30h) ......................................................................... Device Context Base Address Array Pointer Register Description ........................................................ HC Operational Register (Operational Base + 38h) ......................................................................... Configure Register Description ................................................................................................. HC Operational Register (Operational Base + 400h + (10h*(n-1))), where n = Port Number.......................... Port Status and Control Register Description ................................................................................ HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number.......................... Port PM Status and Control Register (USB 3.0) Description ............................................................... HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number.......................... Port PM Status and Control Register (USB 2.0) Description ............................................................... HC Operational Register (Operational Base + 408h + (10h*(n-1))), where n = Port Number.......................... Port Link Info Register Description ............................................................................................. Host Controller Runtime Register Map ........................................................................................ HC Runtime Register (Runtime Base + 00h) ................................................................................. Microframe Index Register Description ........................................................................................ 84 84 84 85 85 85 85 86 86 87 87 87 88 88 88 88 6-42 HC Runtime Register (Runtime Base + 20h + (20h*Interrupter)), where Interrupter = 0 through 7 ................................................................................................ 89 6-43 Interrupter Management Register Description ................................................................................ 89 6-44 HC Runtime Register (Runtime Base + 24h + (20h*Interrupter)), where Interrupter = 0 through 7 ................................................................................................ 89 6-45 Interrupter Management Register Description ................................................................................ 89 6-46 HC Runtime Register (Runtime Base + 28h + (20h*Interrupter)), where Interrupter = 0 through 7 ................................................................................................ 90 6-47 Event Ring Segment Table Size Register Description ...................................................................... 90 6-48 HC Runtime Register (Runtime Base + 30h + (20h*Interrupter)), where Interrupter = 0 through 7 ................................................................................................ 90 6-49 Event Ring Segment Table Base Address Register Description........................................................... 91 6-50 HC Runtime Register (Runtime Base + 38h + (20h*Interrupter)), where Interrupter = 0 through 7 ................................................................................................ 91 6-51 Event Ring Dequeue Pointer Register Description .......................................................................... 91 6-52 HC Doorbell Register (Doorbell Base + (04h*Device Slot)), where Device Slot = 0 through 64 6-53 6-54 10 ...................... Interrupter Management Register Description ................................................................................ xHCI Extended Capabilities Register Map .................................................................................... List of Tables 92 92 92 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 www.ti.com SLLSE76E - MARCH 2011 - REVISED JULY 2011 6-55 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 00h) ........................................ 93 6-56 USB Legacy Support Capability Register Description ....................................................................... 93 6-57 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 04h) ........................................ 93 6-58 ................................................................. 93 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 10h) ........................................ 94 xHCI Supported Protocol Capability Register (USB 2.0) Description ..................................................... 94 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 14h) ........................................ 95 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 18h) ........................................ 95 xHCI Supported Protocol Capability Register (USB 2.0) Description ..................................................... 95 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 20h) ........................................ 96 xHCI Supported Protocol Capability Register (USB 3.0) Description ..................................................... 96 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 24h) ........................................ 96 xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 28h) ........................................ 97 xHCI Supported Protocol Capability Register (USB 3.0) Description ..................................................... 97 MSI-X Table and PBA Register Map .......................................................................................... 98 Differential Output Swing ........................................................................................................ 99 Differential Output De-Emphasis ............................................................................................. 100 Receiver Equalizer Configuration ............................................................................................. 101 Input Clock Specification ....................................................................................................... 103 Input Clock 1.8-V DC Characteristics ........................................................................................ 103 Crystal Specification ............................................................................................................ 103 PCI Express Link Power Management States .............................................................................. 104 PCI Express Power Management D-States ................................................................................. 104 PME Support .................................................................................................................... 105 6-59 6-60 6-61 6-62 6-63 6-64 6-65 6-66 6-67 6-68 7-1 8-1 8-2 8-3 9-1 9-2 9-3 10-1 10-2 10-3 USB Legacy Support Control/Status Register Description Copyright (c) 2011, Texas Instruments Incorporated List of Tables 11 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 12 List of Tables www.ti.com Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com USB 3.0 xHCI HOST CONTROLLER Check for Samples: TUSB7320, TUSB7340 1 INTRODUCTION 1.1 Features * USB 3.0 Compliant xHCI Host Controller - PCIe x1 Gen2 Interface - Four Downstream Ports * Two or Four Downstream Ports * Each Downstream Port - May Be Independently Enabled or Disabled - Has Adjustments for Transmit Swing, De-Emphasis, and Equalization Settings - May Be Marked as Removable/Non-Removable - Has Independent Power Control and Overcurrent Detection * Requires No External Flash for Default Configuration - Optional Serial EEPROM for Custom Configuration * Internal Spread Spectrum Generation - Low Cost Crystal or Oscillator Support * Supports Input Frequencies Between 20 MHz and 50 MHz - Allows Use of 48-MHz System Reference Clock * Best-In-Class Adaptive Receiver Equalizer Design 1 1.2 * * * * * * Target Applications Notebooks Desktop Computers Workstations Servers Add-In Cards and ExpressCard Implementations PCI Express-Based Embedded Host Controllers for HDTVs, Set-Top Boxes and Gaming Console Applications 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 2 OVERVIEW 2.1 Description www.ti.com The TUSB7320 supports up to two downstream ports. The TUSB7340 is a USB 3.0 xHCI compliant host controller that supports up to four downstream ports. Both parts are available in a pin-compatible 100-pin RKM package. For the remainder of this document, the name TUSB73x0 is used to reference both the TUSB7320 and the TUSB7340. Table 2-1. Package Information PART NO. DOWNSTREAM PORTS PACKAGE TUSB7320 2 100-pin RKM TUSB7340 4 100-pin RKM The TUSB73x0 interfaces to the host system via a PCIe x1 Gen 2 interface and provides SuperSpeed, high-speed, full-speed, or low-speed connections on the downstream USB ports. A typical system view of the TUSB73x0 is shown below. SS USB Device Or HS/FS/LS USB Device SS USB Device Or TUSB7340 HS/FS/LS USB Device PCIe Gen2 PC To USB 3.0 Host Controller SS USB Device Or HS/FS/LS USB Device SS USB Device Or HS/FS/LS USB Device Figure 2-1. Typical Application 14 OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 2.2 Related Documents * * * * * * * * * * 2.3 Universal Serial Bus 2.0 Specification Universal Serial Bus 3.0 Specification eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 0.96 PCI Express Base Specification, Revision 2.1 PCI Express Card Electromechanical Specification, Revision 2.0 ExpressCard Standard, Release 2.0 PCI Express Mini Card Electromechanical Specification, Revision 1.2 PCI Bus Power Management Interface Specification, Revision 1.2 PCI Local Bus Specification, Revision 3.0 Guidelines for 64-Bit Global Identifier (EUI-64) Registration Authroity Document's Conventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. 4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b. 5. Differential signal names end with P, N, +, or - designators. The P or + designators signify the positive signal associated with the differential pair. The N or - designators signify the negative signal associated with the differential pair. 6. RSVD indicates that the referenced item is reserved. 7. In Section 4 through Section 6, the configuration space for the host controller is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries: - r - read access by software - u - updates by the host controller internal hardware - w - write access by software - c - clear an asserted bit with a write-back of 1b by software. Write of zero to the field has no effect - s - the field may be set by a write of one. Write of zero to the field has no effect - na - not accessible or not applicable 2.4 Available Options 2.5 ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) 0C to 70C 100-terminal (Lead-Free) (RKM) PWQFN ORDERABLE PART NUMBER TUSB7320RKM TUSB7340RKM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 15 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 A39 A40 NC NC NC NC NC NC VDD11 NC JTAG_TCK NC VDD11 JTAG_TMS JTAG_TDO JTAG_RST# VDD33 PWRON1# JTAG_TDI PWRON2# OVERCUR1# WAKE# OVERCUR2# VDD11 B25 A25 VDDA_3P3 A24 R1EXT A23 XI A22 XO A21 VDDA_3P3 A20 USB_DP_DN1 A19 VDDA_3P3 A18 USB_SSRXP_DN1 VDD11 R1EXTRTN VDDA_3P3 VSS_OSC B21 VSS B20 VDD11 B19 B43 USB_DM_DN1 B18 A47 B44 VDD11 B17 A48 B45 USB_SSRXN_DN1 B16 A49 B46 A17 USB_SSTXP_DN1 A16 VDD11 A15 GRST# USB_SSTXN_DN1 B15 A50 B47 FREQSEL B14 A51 B48 NC B13 B12 A14 NC USB_DM_DN2 A13 USB_DP_DN2 A12 VDDA_3P3 A11 USB_SSTXN_DN2 USB_SSRXN_DN2 USB_SSRXP_DN2 A10 B11 VDD11 B10 USB_SSTXP_DN2 B9 A9 NC NC A8 NC NC A7 B8 VDD11 B7 NC B6 A6 NC A5 NC VDD11 SMI A4 B5 VDD11 B4 NC B3 A3 SCL A2 VDD11 A1 B2 VDD33 B1 VDD11 NC B22 VSS A52 A26 B23 B42 GPIO3 AUX_DET B26 A27 B24 A46 GPIO2 VDD33 B27 A28 B41 GPIO1 VDD11 B28 A29 A45 NC GPIO0 B29 A30 B40 VDD11 NC B30 A31 A44 NC VDD33 B31 A32 B39 VDD11 NC B32 A33 A43 PCIE_REFCLKN PCIE_REFCLKP B33 A34 B38 VDD11 VDDA_3P3 B34 A35 A42 PCIE_RXP NC B35 A36 A41 PCIE_TXP PCIE_RXN B36 A37 B37 VDD11 PCIE_TXN A38 SDA PERST# VDD11 VDD33 Terminal Assignments CLKREQ# 2.6 www.ti.com Figure 2-2. TUSB7320 RKM Package (Top View) 16 OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 A40 VDD11 USB_DM_DN3 VDD11 USB_SSRXN_DN3 USB_SSTXN_DN3 USB_SSRXP_DN3 USB_SSTXP_DN3 NC VDD11 JTAG_TMS JTAG_TCK JTAG_TDO VDD11 JTAG_RST# VDD33 JTAG_TDI OVERCUR1# PWRON1# OVERCUR2# PWRON2# VDD11 USB_DP_DN3 B25 A26 B24 B38 B23 B39 B22 B40 B21 B41 B20 B42 B19 A20 B14 B48 B13 B12 VDD11 NC A14 NC A13 USB_DP_DN2 VDDA_3P3 A12 GRST# USB_DM_DN2 B11 A11 USB_SSTXN_DN2 USB_SSRXN_DN2 A10 USB_SSRXP_DN2 A9 NC A8 B10 USB_SSTXP_DN2 B9 VDD11 USB_SSTXP_DN4 B8 USB_SSTXN_DN4 B7 A7 USB_SSRXP_DN4 A6 VDD11 A5 B6 USB_SSRXN_DN4 B5 USB_DP_DN4 VDD11 A4 VDDA_3P3 A3 B4 USB_DM_DN4 B3 SMI VDD11 A2 VDD11 A1 B2 VDD33 B1 VDD11 FREQSEL A15 A52 USB_SSTXP_DN1 USB_SSTXN_DN1 A16 A51 USB_SSRXP_DN1 USB_SSRXN_DN1 A17 B47 VDDA_3P3 VDD11 A18 B15 USB_DP_DN1 USB_DM_DN1 A19 B46 VDDA_3P3 VDD11 B18 B16 XO VSS A21 B45 XI VSS_OSC A22 B17 R1EXT VDDA_3P3 A23 B44 VDDA_3P3 R1EXTRTN A24 VSS NC VDD11 A25 A50 GPIO3 AUX_DET B26 A27 A49 GPIO2 VDD33 B27 A28 A48 GPIO1 VDD11 B28 A29 A47 OVERCUR4# GPIO0 B29 A30 B43 VDD11 PWRON4# B30 A31 B37 A46 OVERCUR3# VDD33 B31 A32 A45 VDD11 PWRON3# B32 A33 A44 PCIE_REFCLKN PCIE_REFCLKP B33 A34 A43 VDD11 VDDA_3P3 B34 A35 A42 PCIE_RXP NC B35 A36 A41 PCIE_TXP PCIE_RXN B36 A37 SCL PCIE_TXN A38 SDA PERST# WAKE# VDD33 CLKREQ# A39 VDDA_3P3 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Figure 2-3. TUSB7340 RKM Package (Top View) OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 17 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 2.7 www.ti.com Terminal Descriptions The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description. TYPE DESCRIPTION I Input O Output I/O Input/Output PD, PU Internal pull-down/pull-up S Strapping pin P Power supply G Ground Table 2-2. Clock and Reset Signals TERMINAL I/O DESCRIPTION TUSB7320 PIN NO. TUSB7340 PIN NO. GRST# A15 A15 XI A23 A23 I Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-M feedback resistor is required between XI and XO. XO A22 A22 O Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-M feedback resistor is required between XI and XO. I Frequency select. This terminal indicates the oscillator input frequency and is used to configure the correct PLL multiplier. If the FREQSEL pin is '0', the frequency used is 48 MHz. If the FREQSEL pin is '1', refer to Table 4-100: USB Control Register Description. NAME Global power reset. This reset brings all of the TUSB73x0 internal registers to their I default states. When GRST# is asserted, the device is completely nonfunctional. GRST# PU should be asserted until all power rails are valid at the device. FREQSEL B14 B14 PCIE_ REFCLKP PCIE_ REFCLKN A45 B41 A45 B41 I PERST# A40 A40 I PCI Express Reference Clock. PCIE_REFCLKP and PCIE_REFCLKN comprise the differential input pair for the 100-MHz system reference clock. PCI Express Reset Input. The PERST# signal is used to signal when the system power is stable. The PERST# signal is also used to generate an internal power on reset Table 2-3. PCI Express Signals TERMINAL TUSB7320 PIN NO. TUSB7340 PIN NO. I/O PCIE_TXP B38 B38 O PCI Express transmitter differential pair (positive). PCIE_TXN A41 A41 O PCI Express transmitter differential pair (negative). PCIE_RXP B39 B39 I PCI Express receiver differential pair (positive). PCIE_RXN A42 A42 I PCI Express receiver differential pair (negative). NAME WAKE# (1) CLKREQ# (1) (1) 18 DESCRIPTION B35 B35 O Wake. Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy's main power rails and reference clocks. Note: WAKE# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while VDD33 is not present. B36 B36 O PCI Express REFCLK Request signal. Note: CLKREQ# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while VDD33 is not present. The only failsafe pins in the device are WAKE and CLKREQ#. No other pins are failsafe. OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 2-4. USB Downstream Signals TERMINAL NAME TUSB7320 PIN NO. TUSB7340 PIN NO. I/O USB_SSTXP_ DN1 A17 A17 O USB SuperSpeed transmitter differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX differential pair. B15 B15 O USB SuperSpeed transmitter differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX differential pair. USB_SSRXP_ DN1 A18 A18 I USB SuperSpeed receiver differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX differential pair. USB_SSRXN_ DN1 B16 B16 I USB SuperSpeed receiver differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX differential pair. USB_DP_DN1 A20 A20 I/O USB High-speed differential transceiver (positive). USB_DM_DN1 B18 B18 I/O USB High-speed differential transceiver (negative). PWRON1# B33 B33 USB DS Port 1 Power On Control for Downstream Power. The terminal is used for O control of the downstream power switch. If the PWRON_POLARITY bit is set to `1', this PD pin is active high and the internal pull-down is disabled. This pin may be at low impedance when power rails are removed. OVERCUR1# A36 A36 USB DS Port 1 Over-Current Detection. I 0: over-current detected; PU 1: over-current not detected USB_SSTXP_ DN2 A11 A11 O USB SuperSpeed transmitter differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSTX differential pair. USB_SSTXN_ DN2 B10 B10 O USB SuperSpeed transmitter differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSTX differential pair. USB_SSRXP_ DN2 B9 B9 I USB SuperSpeed receiver differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSRX differential pair. USB_SSRXN_ DN2 A10 A10 I USB SuperSpeed receiver differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSRX differential pair. USB_DP_DN2 B12 B12 I/O USB High-speed differential transceiver (positive). USB_DM_DN2 A13 A13 I/O USB High-speed differential transceiver (negative). PWRON2# B34 B34 USB DS Port 2 Power On Control for Downstream Power. The terminal is used for O control of the downstream power switch. If the PWRON_POLARITY bit is set to `1', this PD pin is active high and the internal pull-down is disabled. This pin may be at low impedance when power rails are removed. OVERCUR2# A37 A37 USB DS Port 2 Over-Current Detection. I 0: over-current detected; PU 1: over-current not detected USB_SSTXP_ DN3 N/A B28 O USB SuperSpeed transmitter differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSTX differential pair. USB_SSTXN_ DN3 N/A A30 O USB SuperSpeed transmitter differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSTX differential pair. USB_SSRXP_ DN3 N/A B27 I USB SuperSpeed receiver differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSRX differential pair. USB_SSRXN_ DN3 N/A A29 I USB SuperSpeed receiver differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 3 SSRX differential pair. USB_DP_DN3 N/A B25 I/O USB High-speed differential transceiver (positive). USB_DM_DN3 N/A A27 I/O USB High-speed differential transceiver (negative). USB_SSTXN_ DN1 DESCRIPTION OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 19 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 2-4. USB Downstream Signals (continued) TERMINAL I/O DESCRIPTION TUSB7320 PIN NO. TUSB7340 PIN NO. PWRON3# N/A A46 USB DS Port 3 Power On Control for Downstream Power. The terminal is used for O control of the downstream power switch. If the PWRON_POLARITY bit is set to `1', this PD pin is active high and the internal pull-down is disabled. This pin may be at low impedance when power rails are removed. OVERCUR3# N/A B43 USB DS Port 3 Over-Current Detection. I 0: over-current detected; PU 1: over-current not detected USB_SSTXP_ DN4 N/A B7 O USB SuperSpeed transmitter differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSTX differential pair. USB_SSTXN_ DN4 N/A A8 O USB SuperSpeed transmitter differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSTX differential pair. USB_SSRXP_ DN4 N/A B6 I USB SuperSpeed receiver differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSRX differential pair. USB_SSRXN_ DN4 N/A A7 I USB SuperSpeed receiver differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 4 SSRX differential pair. USB_DP_DN4 N/A B5 I/O USB High-speed differential transceiver (positive). USB_DM_DN4 N/A A5 I/O USB High-speed differential transceiver (negative). PWRON4# N/A A48 USB DS Port 4 Power On Control for Downstream Power. The terminal is used for O control of the downstream power switch. If the PWRON_POLARITY bit is set to `1', this PD pin is active high and the internal pull-down is disabled. This pin may be at low impedance when power rails are removed. OVERCUR4# N/A B45 USB DS Port 4 Over-Current Detection. I 0: over-current detected; PU 1: over-current not detected NAME Table 2-5. I2C Signals TERMINAL I/O DESCRIPTION TUSB7320 PIN NO. TUSB7340 PIN NO. SCL B2 B2 I/O I2C Clock - If no I2C device is present, pull this line down to disable. SDA A2 A2 I/O I2C Data - If no I2C device is present, pull this line down to disable. NAME Table 2-6. Test and Miscellaneous Signals TERMINAL I/O DESCRIPTION TUSB7320 PIN NO. TUSB7340 PIN NO. JTAG_TCK A32 A32 I JTAG test clock PD JTAG_TDI A35 A35 I JTAG test data in PU JTAG_TDO B31 B31 O JTAG test data out PD JTAG_TMS B30 B30 I JTAG test mode select PU JTAG_RST# B32 B32 I JTAG reset. Should be pulled low for normal operation. PD NAME 20 OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 2-6. Test and Miscellaneous Signals (continued) TERMINAL NAME GPIO[0] GPIO[1] GPIO[2] GPIO[3] SMI R1EXT R1EXTRTN AUX_DET NC TUSB7320 PIN NO. TUSB7340 PIN NO. I/O A49, B46, B47, B48 A49, B46, B47, B48 I/O General purpose I/O PU B3 B3 O System management interrupt Note: This pin is active high and should not be pulled up/down. A24, B23 A24, B23 OI High precision external resistor used for calibration. A resister value of 9.09 K 1% accuracy is connected between the terminals R1EXT and R1EXTRTN. A52 A52 B4, A5, B5, B6, A7, B7, A8, B8, B13, A14, B25, A26, B26, A27, B27, B28, A29, B29, A30, A43, B43, B45, A46, A48 A14, B8, B13, A26, B29, A43 I DESCRIPTION Auxiliary power detect. This pin indicates if the TUSB73X0 is enabled for wakeup from D3cold. Note: If this feature is implemented, AUX_DET must be pulled to VDD33 to prevent leakage. Pins are not connected internally. I/O Note: TUSB7320 pins B4 and B26 may be connected to VDDA_3P3 to support a dual-layout option with the TUSB7340. Table 2-7. Power Signals TERMINAL I/O TUSB7320 PIN NO. TUSB7340 PIN NO. VDD33 A3, A34, A39, A47, A51 A3, A34, A39, A47, A51 PW 3.3-V I/O power rail R VDDA_3P3 B11, A19, A21, A25, B22, A44 B4, B11, A19, A21, A25, B22, B26, A44 PW 3.3-V analog power rail R NAME VDD11 VSS VSS_NC VSS_OSC A1, B1, A4, A6, A9, A12, A16, B17, B19, B24, A28, A33, A31, A38, B37, B40, B42, B44, A50 B20, A53 C1, C2, C3, C4 B21 DESCRIPTION A1, B1, A4, A6, A9, A12, A16, B17, B19, PW B24, A28, 1.1-V core power rail R A33, A31, A38, B37, B40, B42, B44, A50 B20, A53 PW Ground. The ground pad is labeled A53 for schematic purposes. R C1, C2, C3, PW The corner pins, which are for mechanical stability of the package, are connected to C4 R ground internally. These pins may be connected to VSS or left unconnected. B21 Oscillator return. PW If using a crystal, the load capacitors should use this signal as the return path and it R should not be connected to the PCB ground. If using an oscillator, this should be connected to PCB Ground. OVERVIEW Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 21 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 3 FEATURE/PROTOCOL DESCRIPTIONS 3.1 Power-Up/-Down Sequencing The host controller contains both 1.1-V and 3.3-V power terminals. The following power-up and power-down sequences describe how power is applied to these terminals. In addition, the host controller has three resets: PERST#, GRST#, and an internal power- on reset. These resets are fully described in the next section. The following power-up and power-down sequences describe how PERST# is applied to the host controller. The application of the PCI Express reference clock (PCIE_REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions. 3.1.1 Power-Up Sequence 1. Assert PERST# to the device. 2. Apply 1.1-V and 3.3-V voltages. 3. GRST# must remain asserted until both the 1.1-V and 3.3-V voltages have reached the minimum recommended operating voltage, see Section 11.2. 4. Apply a stable PCI Express reference clock. 5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: Wait a minimum of 100 s after applying a stable PCI Express reference clock. The 100-s limit satisfies the requirement for stable device clocks by the de-assertion of PERST. Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by the de-assertion of PERST. See the power-up sequencing diagram in Figure 3-1. VDD11 VDDA_3P3 and VDD33 PCIE_REFCLK PERST# GRST# Figure 3-1. Power-Up Sequence 22 FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 3.1.2 Power-Down Sequence 1. Assert PERST# to the device. 2. Remove the reference clock. 3. Remove the 3.3-V and 1.1-V voltages See the power power-down sequencing diagram in Figure 3-2. If the VDD33_AUX terminal is to remain powered after a system shutdown, then the host controller power-down sequence is exactly the same as shown in Figure 3-2. VDD11 VDDA_3P3 and VDD33 PCIE_REFCLK PERST# Figure 3-2. Power-Down Sequence 3.2 Two-Wire Serial-Bus Interface The host controller provides a two-wire serial-bus interface to load subsystem identification information and specific register defaults from an external EEPROM. The serial-bus interface signals include SDA and SCL. The use of an external EEPROM is optional. The TUSB73x0 will function with the default settings. For motherboard down applications, BIOS can be used to set all of the options available on the TUSB73x0. * * * * * * * 3.2.1 On a PCIe Add-in Card, an EEPROM is only needed if a any of the following is true: Use of a crystal other than 48 MHz. Mark one or more USB ports as non-removable. Disable one or more USB ports. Set a PCIe Subsystem ID and Subsystem Vendor ID. Change the default de-emphasis/swing/equalizer settings of the SuperSpeed USB ports. Change the default L0s and L1 latency values for PCIe. Change the default PWRON polarity to active high instead of active low. Serial-Bus Interface Implementation To enable the serial-bus interface, a pull-up resistor must be implemented on the SCL signal. At the rising edge of PERST# or GRST#, whichever occurs later in time, the SCL terminal is checked for a pull-up resistor. If one is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.52) is set. Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor to the SCL signal. The host controller implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is a unidirectional output from the host controller and the SDA signal is Copyright (c) 2011, Texas Instruments Incorporated FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 23 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com bidirectional. Both are open-drain signals and require pull-up resistors. The host controller is a bus master device and drives SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3-3 illustrates an example application implementing the two-wire serial bus. VDD33 Serial EEPROM TUSB73x0 A0 A1 SCL SCL A2 SDA SDA Figure 3-3. Serial EEPROM Application 24 FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 3.2.2 Serial-Bus Interface Protocol All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as illustrated in Figure 3-4. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-4. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or stop condition. Figure 3-4. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3-5 illustrates the acknowledge protocol. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3-5. Serial-Bus Protocol Acknowledge The host controller performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte reads. The single byte operations occur under software control. The multibyte read operations are performed by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See Section 11.6, Serial-Bus EEPROM Application, for details on how the host controller automatically loads the subsystem identification and other register defaults from the serial-bus EEPROM. Figure 3-6 illustrates a single byte write. The host controller issues a start condition and sends the 7-bit slave device address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received by the host controller, then bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset BCh, see Section 4.52). Next, the EEPROM word address is sent by the host controller, and another slave acknowledgment is expected. Then the host controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition. Copyright (c) 2011, Texas Instruments Incorporated FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 25 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Figure 3-6. Serial-Bus Protocal - Byte Write Figure 3-7 illustrates a single byte read. The host controller issues a start condition and sends the 7-bit slave device address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the slave address. Next, the EEPROM word address is sent by the host controller, and another slave acknowledgment is expected. Then, the host controller issues a restart condition followed by the 7-bit slave address and the R/W command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the host controller responds with no acknowledge (logic high) indicating the last data byte. Finally, the host controller issues a stop condition. Figure 3-7. Serial-Bus Protocal - Byte Read Figure 3-8 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred. The number of transferred data bytes is controlled by the host controller master. After each data byte, the host controller master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a host controller master no acknowledge (logic high) followed by a stop condition. Figure 3-8. Serial-Bus Protocal - Multibyte Read Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol. This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM devices. 26 FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 3.2.3 Serial-Bus EEPROM Application A serial EEPROM interface is implemented to pre-load several registers. The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3-1. Table 3-1. EEPROM Register Loading Map SERIAL EEPROM WORD ADDRESS BYTE DESCRIPTION 00h TUSB73X0 Function Indicator (00h) 01h Number of Bytes (19h) 02h PCI D0h, Subsystem Vendor ID, Byte 0 03h PCI D1h, Subsystem Vendor ID, Byte 1 04h PCI D2h, Subsystem ID, Byte 0 05h PCI D3h, Subsystem ID, Byte 1 06h PCI D4h, General Control 0, Byte 0 07h PCI D5h, General Control 0, Byte 1 08h PCI D8h, General Control 1, Byte 0 09h PCI DCh, General Control 2, Byte 0 0Ah PCI E0h, USB Control, Byte 0 0Bh PCI E1h, USB Control, Byte 1 0Ch PCI E2h, USB Control, Byte 2 0Dh PCI E3h, USB Control, Byte 3 0Eh PCI E4h, De-emphasis and Swing Control, Byte 0 0Fh PCI E5h, De-emphasis and Swing Control, Byte 1 10h PCI E6h, De-emphasis and Swing Control, Byte 2 11h PCI E7h, De-emphasis and Swing Control, Byte 3 12h PCI E8h, Equalizer Control, Byte 0 13h PCI E9h, Equalizer Control, Byte 1 14h PCI EAh, Equalizer Control, Byte 2 15h PCI EBh, Equalizer Control, Byte 3 16h PCI ECh, Custom PHY Transmit/Receive Control, Byte 0 17h PCI EDh, Custom PHY Transmit/Receive Control, Byte 1 18h PCI EEh, Custom PHY Transmit/Receive Control, Byte 2 19h PCI EFh, Custom PHY Transmit/Receive Control, Byte 3 1Ah PCI 61h, Frame Length Adjustment Register 1Bh End of List Indicator (80h) This format must be explicitly followed for the host controller to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM. The serial EEPROM is addressed by the host controller at slave address 1010 000b. This slave address is internally hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit (Figure 3-3) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to VSS. During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be monitored to verify a successful download. Copyright (c) 2011, Texas Instruments Incorporated FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 27 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 3.3 www.ti.com System Management Interrupt The TUSB73X0 includes a System Management Interrupt (SMI) pin to allow for USB support in the BIOS of a system that implements the TUSB73X0. The SMI pin is controlled by the bits in the USB Legacy Support Control/Status Register. See Section 6.6.2 for more information. If there are no SMI events pending or if all sources for SMI are disabled, the TUSB73X0 drives the SMI pin low. When an SMI event occurs and the corresponding event is enabled, the TUSB73X0 drives the SMI pin high until the event is cleared or disabled. 28 FEATURE/PROTOCOL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4 CLASSIC PCI CONFIGURATION SPACE 4.1 The PCI Configuration Map The programming model of the TUSB73X0 USB 3.0 Host Controller is compliant to the standard PCI device programming model. The PCI configuration map uses the type 0 PCI header. All bits marked with a '*' are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset. All bits marked with a '' are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the internally-generated power-on reset. Table 4-1. PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 000h Status Command 004h Class Code BIST Header Type Latency Timer Revision ID 008h Cache Line Size 00Ch Base Address Register 0 010h Base Address Register 1 014h Base Address Register 2 018h Base Address Register 3 01Ch Reserved 020h-028h Subsystem ID Subsystem Vendor ID 02Ch Reserved 030h Reserved Capabilities Pointer 034h Interrupt Pin Interrupt Line 03Ch Next Item Pointer PM CAP ID 040h Reserved Max Latency Min Grant Power Management Capabilities PM Data (RSVD) 038h PMCSR_BSE Power Management CSR MSI Message Control Next Item Pointer MSI CAP ID 048h MSI Message Address 04Ch MSI Upper Message Address 050h Reserved MSI Message Data 054h Reserved 058h-05Ch Reserved FLADJ SBRN Next Item Pointer PCI Express Capability ID Reserved PCI Express Capabilities Register Device Status Device Control Link Status Link Control 080h 084h-090h Device Capabilities2 Device Status2 094h Device Control2 Link Capabilities2 Link Control2 Copyright (c) 2011, Texas Instruments Incorporated 0A0h 0A4h-0ACh Serial Bus Index Serial Bus Data GPIO Control Reserved 098h 09Ch Reserved GPIO Data 078h 07Ch Reserved Serial Bus Slave Address 070h 074h Link Capabilities Link Status2 60h 064h-06Ch Device Capabilities Serial Bus CSR 044h 0B0h 0B4h 0B8h-0BCh CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 29 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-1. PCI Configuration Register Map (continued) MSI-X Message Control Next Item Pointer MSI-X CAP ID 0C0h MSI-X Table Offset and BIR 4.2 0C4h MSI-X PBA Offset and BIR 0C8h Reserved 0CCh Subsystem Access 0D0h General Control 0 0D4h General Control 1 0D8h General Control 2 0DCh USB Control 0E0h Deemphasis and Swing Control 0E4h Equalizer Control 0E8h Custom PHY Transmit/Receive Control 0ECh Reserved 0F0h-0FCh Vendor ID Register This 16-bit read only register contains the value 104Ch, which is the vendor ID assigned to Texas Instruments. PCI register offset: 00h Register type: Read-only Default value: 104Ch Table 4-2. PCI Register 00h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 4.3 Device ID Register This 16-bit read only register contains the value 8241h, which is the device ID assigned by TI to the TUSB73X0. PCI register offset: 02h Register type: Read-only Default value: 8241h Table 4-3. PCI Register 02h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 30 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.4 Command Register The Command register provides control over the TUSB73X0 interface to the PCIe interface PCI register offset: 04h Register type:Read-only, Read/Write Default value: 0000h Table 4-4. PCI Register 04h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-5. Bit Command Register Description Bit Field Name Access 15:11 RSVD r 10 INT_DISABLE rw 9 FBB_ENB r 8 SERR_ENB rw 7 STEP_ENB r Description Reserved. Returns zeros when read. INTx# Disable. This bit enables device specific interrupts. Fast back-to-back enable. The host controller does not generate fast back-to-back transactions; therefore, this bit returns 0 when read. SERR enable bit. When this bit is set, the host controller can signal fatal and nonfatal errors on the PCI Express interface on behalf of SERR assertions detected on the PCI bus. 0 = Disable the reporting of nonfatal errors and fatal errors (default) 1 = Enable the reporting of nonfatal errors and fatal errors Address/data stepping control. The host controller does not support address/data stepping, and this bit is hardwired to 0b. 6 PERR_ENB rw Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.5) in response to a received poisoned TLP from PCI Express. A received poisoned TLP is forwarded with bad parity to conventional PCI regardless of the setting of this bit. 0 = Disables the setting of the master data parity error bit (default) 1 = Enables the setting of the master data parity error bit 5 VGA_ENB r VGA palette snoop enable. The host controller does not support VGA palette snooping; therefore, this bit returns 0b when read. 4 MWI_ENB r Memory write and invalidate enable. The host controller does not support memory write and invalidate enable; therefore, this bit returns 0b when read. 3 SPECIAL r Special cycle enable. This host controller does not respond to special cycle transactions; therefore, this bit returns 0 when read. 2 1 0 MASTER_ENB MEMORY_ENB IO_ENB Copyright (c) 2011, Texas Instruments Incorporated rw Bus master enable. When this bit is set, the host controller is enabled to initiate transactions on the PCI Express interface. 0 = PCI Express interface cannot initiate transactions. The host controller must disable the response to memory and I/O transactions on the PCI interface (default). 1 = PCI Express interface can initiate transactions. The host controller can forward memory and I/O transactions from PCI secondary interface to the PCI Express interface. rw Memory space enable. Setting this bit enables the host controller to respond to memory transactions on the PCI Express interface. 0 = PCI Express receiver cannot process downstream memory transactions and must respond with an unsupported request (default) 1 = PCI Express receiver can process downstream memory transactions. The host controller can forward memory transactions to the PCI interface. r I/O space enable. Setting this bit enables the host controller to respond to I/O transactions on the PCI Express interface. 0 = PCI Express receiver cannot process downstream I/O transactions and must respond with an unsupported request (default) 1 = PCI Express receiver can process downstream I/O transactions. The host controller can forward I/O transactions to the PCI interface. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 31 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 4.5 www.ti.com Status Register The status register provides information about the PCI Express interface to the system. PCI register offset: 06h Register type:Read-only, Read/Clear Default value: 0010h Table 4-6. PCI Register 06h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-7. Status Register Description Bit Field Name 15 PAR_ERR 14 SYS_ERR 13 MABORT 12 32 TABORT_REC Access Description rcu Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP. This bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see Section 4.4). 0 = No parity error detected 1 = Parity error detected rcu Signaled system error. This bit is set when the host controller sends an ERR_FATAL or ERR_NONFATAL message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.4) is set. 0 = No error signaled 1 = ERR_FATAL or ERR_NONFATAL signaled rcu Received master abort. This bit is set when the PCI Express interface of the host controller receives a completion-with-unsupported-request status. 0 = Unsupported request not received on the PCI Express interface 1 = Unsupported request received on the PCI Express interface rcu Received target abort. This bit is set when the PCI Express interface of the host controller receives a completion-with-completer-abort status. 0 = Completer abort not received on the PCI Express interface 1 = Completer abort received on the PCI Express interface Signaled target abort. This bit is set when the PCI Express interface completes a request with completer abort status. 0 = Completer abort not signaled on the PCI Express interface 1 = Completer abort signaled on the PCI Express interface 11 TABORT_SIG rcu 10:9 DEVSEL_TIMING r DEVSEL Timing. These bits are read only zero, because they do not apply to PCI Express. 8 DATAPAR rcu Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset 04h, see Section 4.4) is set and the host controller receives a completion with data marked as poisoned on the PCI Express interface or poisons a write request received on the PCI Express interface. 0 = No uncorrectable data error detected on the primary interface 1 = Uncorrectable data error detected on the primary interface. 7 FBB_CAP r Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device and is hardwired to 0b. 6 RSVD r Reserved. Returns zeros when read. 5 66MHZ r 66 MHz capable. This bit does not have a meaningful context for a PCI Express device and is hardwired to 0b. 4 CAPLIST r Capabilities list. This bit returns 1b when read, indicating that the host controller supports additional PCI capabilities. 3 INT_STATUS ru Interrupt Status. This bit reflects the interrupt status of the function. 2:0 RSVD r Reserved. Returns zeros when read. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.6 Class Code and Revision ID Register This read only register categorizes the Base Class, Sub Class, and Programming Interface of the TUSB73X0. The Base Class is 0Ch, identifying the device as a Serial Bus Controller. The Sub Class is 03h, identifying the function as a Universal Serial Bus Host Controller, and the Programming Interface is 30h, identifying the function as a USB 3.0 xHCI Host Controller. Furthermore, the TI chip revision is indicated in the lower byte (02h). PCI register offset: 08h Register type:Read-only Default value: 0C03 3002h Table 4-8. PCI Register 06h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Table 4-9. Class Code and Revision ID Register Description Bit Field Name Access Description 31:24 BASECLASS r Base Class. This field returns 0Ch when read, which classifies the function as a Serial Bus Controller. 23:16 SUBCLASS r Sub Class. This field returns 03h when read, which specifically classifies the function as a Universal Serial Bus Host Controller. 15:8 PGMIF r Programming Interface. This field returns 30h when read, which identifies the function as a USB 3.0 xHCI Host Controller. 7:0 CHIPREV r Silicon Revision. This field returns the silicon revision of the function. This field is 02h. 4.7 Cache Line Size Register This 8-bit register is read/write for legacy compatibility purposes and is not applicable to the functionality of the TUSB73X0. PCI register offset: 0Ch Register type:Read/Write Default value: 00h Table 4-10. PCI Register 0Ch Bit No. 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 33 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 4.8 www.ti.com Latency Timer Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 0Dh Register type:Read-only Default value: 00h Table 4-11. PCI Register 0Dh Bit No. 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 4.9 Header Type Register This read only register indicates that this function has a type 0 PCI header. Bit seven of this register is zero indicating that the TUSB73X0 is not a Multifunction device. PCI register offset: 0Eh Register type:Read-only Default value: 00h Table 4-12. PCI Register 0Eh Bit No. 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 4.10 BIST Register Since the TUSB73X0 does not support a built-in self test (BIST), this read only register returns the value of 00h when read. PCI register offset: 0Fh Register type:Read-only Default value: 00h Table 4-13. PCI Register 0Fh Bit No. 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 34 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.11 Base Address Register 0 This register is used to program the memory address used to access the device control registers. PCI register offset: 10h Register type:Read/Write,Read-only Default value: 0000 0004h Table 4-14. PCI Register 10h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 4-15. Base Address Register 0 Description Bit Field Name Access Description Memory Address. The lower 32 bits of the 64-bit memory address field for the TUSB73X0. The TUSB73X0 uses 16 read/write bits indicating that 64 kB of memory space is required. 31:16 ADDRESS rw 15:4 RSVD r Reserved. These bits are read-only and return zeros when read. 3 PRE_FETCH r Pre-fetchable. This bit is read only 0 indicating that this memory window is not prefetchable. 2:1 MEM_TYPE r Memory Type. This field is read only 10b indicating that this window can be located anywhere in the 64-bit address space. 0 MEM_IND r Memory Space Indicator. This field returns 0 indicating that memory space is used. 4.12 Base Address Register 1 This register is used to program the memory address used to access the device control registers. PCI register offset: 14h Register type:Read/Write Default value: 0000 0000h Table 4-16. PCI Register 14h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-17. Base Address Register 1 Description Bit Field Name Access 31:0 ADDRESS rw Copyright (c) 2011, Texas Instruments Incorporated Description Memory Address. T his field indicates the upper 32 bits of the 64-bit memory address for the TUSB73X0. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 35 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.13 Base Address Register 2 This register is used to program the memory address used to access the MSI-X Table and PBA. PCI register offset: 18h Register type:Read/Write, Read-only Default value: 0000 0004h Table 4-18. PCI Register 18h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 4-19. Base Address Register 2 Description Bit Field Name Access Description Memory Address. The lower 32 bits of the 64-bit memory address field for the TUSB73X0 uses 19 read/write bits indicating that 8 MB of memory space is required. 31:20 ADDRESS rw 19:4 RSVD r Reserved. These bits are read-only and returns zeros when read. 3 PRE_FETCH r Pre-fetchable. This bit is read only 0 indicating that this memory window is not prefetchable. 2:1 MEM_TYPE r Memory Type. This field is read only 10b indicating that this window can be located anywhere in the 64-bit address space. 0 MEM_IND r Memory Space Indicator. This field returns 0 indicating that memory space is used. 4.14 Base Address Register 3 This register is used to program the memory address used to access the MSI-X Table and PBA. PCI register offset: 1Ch Register type:Read/Write Default value: 0000 0000h Table 4-20. PCI Register 1Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-21. Table 93 Base Address Register 3 Description 36 Bit Field Name Access 31:0 ADDRESS rw Description Memory Address. This field indicates the upper 32 bits of the 64-bit memory address for the TUSB73X0. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.15 Subsystem Vendor ID Register This register, which is used for system and option card identification purposes, may be required for certain operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is read/write and is initialized through the EEPROM (if present) or can be written through the Subsystem Alias Register at PCI Offset D0h. PCI register offset: 2Ch Register type:Read-only Default value: 0000h Table 4-22. PCI Register 2Ch Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.16 Subsystem ID Register This register, which is used for system and option card identification purposes, may be required for certain operating systems. This read-only register is a direct reflection of the Subsystem Access register, which is read/write and is initialized through the EEPROM (if present) or can be written through the Subsystem Alias Register at PCI Offset D0h. PCI register offset: 2Eh Register type:Read-only Default value: 0000h Table 4-23. PCI Register 2Eh Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.17 Capabilities Pointer Register This read-only register provides a pointer into the PCI configuration header where the PCI power management block resides. Since the PCI power management registers begin at 40h, this register is hardwired to 40h. PCI register offset: 34h Register type:Read-only Default value: 40h Table 4-24. PCI Register 34h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 1 0 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 37 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.18 Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the TUSB73X0 has been assigned. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function PCI register offset: 3Ch Register type:Read-only Default value: FFh Table 4-25. PCI Register 3Ch Bit No. 7 6 5 4 3 2 1 0 Reset State 1 1 1 1 1 1 1 1 4.19 Interrupt Pin Register The Interrupt Pin register is read-only 01h indicating that the TUSB73X0 uses INTA. PCI register offset: 3Dh Register type:Read-only Default value: 01h Table 4-26. PCI Register 3Dh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 1 4.20 Min Grant Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Eh Register type:Read-only Default value: 00h Table 4-27. PCI Register 3Eh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.21 Max Latency Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Fh Register type:Read-only Default value: 00h Table 4-28. PCI Register 3Fh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 38 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.22 Capability ID Register This read-only register identifies the linked list item as the register for PCI Power management. The register returns 01h when read. PCI register offset: 40h Register type:Read-only Default value: 01h Table 4-29. PCI Register 40h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 1 4.23 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0. This register reads 48h pointing to the MSI Capability registers. PCI register offset: 41h Register type:Read-only Default value: 48h Table 4-30. PCI Register 41h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 1 0 0 1 0 0 0 4.24 Power Management Capabilities Register The read-only register indicates the capabilities of the TUSB73X0 related to PCI power management. PCI register offset: 42h Register type:Read-only Default value: xxx3h Table 4-31. PCI Register 42h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State x 1 1 1 1 1 1 x x x 0 0 0 0 1 1 Table 4-32. Power Management Capabilities Register Description Bit Field Name Access Description 15:11 PME_SUPPORT r PME# support. This five-bit field indicates the power states from which the TUSB73X0 may assert PME#. If the AUX_DET pin is `1', this field is `11111'. If the AUX_DET pin is `0', this field is `01111'. 10 D2_SUPPORT r This bit returns a 1 when read, indicating that the function supports the D2 device power state. 9 D1_SUPPORT r This bit returns a 1 when read, indicating that the function supports the D1 device power state. 8:6 AUX_CURRENT r 3.3 Vaux auxiliary current requirements. If the AUX_DET pin is `1', this field is 010. IF the AUX_DET pin is `0', this field is `000'. Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 39 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-32. Power Management Capabilities Register Description (continued) DSI r Device Specific Initialization. This bit returns 0 when read, indicating that the TUSB73X0 does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD r Reserved. Returns zero when read. 3 PME_CLK r PME# Clock. 2:0 PM_VERSION r Power Mgmt Version. This field returns 3'b011 indicating Rev 1.2 compatibility. 5 4.25 Power Management Control/Status Register This register determines and changes the current power state of the TUSB73X0. PCI register offset: 44h Register type:Read/Write, Read-only Default value: 0008h Table 4-33. PCI Register 44h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Table 4-34. Power Management Control/Status Register Description Bit Field Name Access 15 PME_STAT rc PME# Status. This bit is sticky and is only reset by a Global Reset. Description 14:13 DATA_SCALE r Data Scale. This 2-bit field returns 0's when read since the TUSB73X0 does not use the Data Register. 12:9 DATA_SEL r Data Select. This 4-bit field returns 0's when read since the TUSB73X0 does not use the Data Register. 8 PME_EN rw 7:4 RSVD r Reserved. Returns zero when read. 3 NO_SOFT_RESET r No Soft Reset. This bit returns `1' indicating that no internal reset is generated and the device retains its configuration context when transitioning from the D3hot state to the D0 state. 2 RSVD r Reserved. Returns zero when read. 1:0 PWR_STATE rw PME# Enable. This bit is sticky and is only reset by a Global Reset. Power State. This 2-bit field is used both to determine the current power state of the function and to set the function into a new power state. This field is encoded as follows:00 = D001 = D110 = D211 = D3hot. 4.26 Power Management Bridge Support Extension Register This read-only register is not applicable to the TUSB73X0 and returns 00h when read. PCI register offset: 46h Register type:Read-only Default value: 00h Table 4-35. PCI Register 46h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 40 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.27 Power Management Data Register This read-only register is not applicable to the TUSB73X0 and returns 00h when read. PCI register offset: 47h Register type:Read-only Default value: 00h Table 4-36. PCI Register 47h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.28 MSI Capability ID Register This read-only register identifies the linked list item as the register for Message Signaled Interrupts Capabilities. The register returns 05h when read. PCI register offset: 48h Register type:Read-only Default value: 05h Table 4-37. PCI Register 48h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 1 4.29 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0. This register reads 70h pointing to the PCI Express Capability registers. PCI register offset: 49h Register type:Read-only Default value: 70h Table 4-38. PCI Register 49h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 1 1 1 0 0 0 0 4.30 MSI Message Control Register The register is used to control the sending of MSI messages. PCI register offset: 4Ah Register type:Read/Write, Read-only Default value: 0086h Table 4-39. PCI Register 4Ah Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 41 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-40. MSI Message Control Register Description Bit Field Name Access Description 15:8 RSVD r Reserved. Returns zeros when read. 8 PVM_CAP r Per-vector Masking Capable. This bit is read only 0 indicating that the TUSB73X0 does not support per-vector masking. 7 64CAP r 64 Bit Message Capability. This bit is read only 1 indicating that the TUSB73X0 supports 64 bit MSI message addressing. 6:4 MM_EN rw Multiple Message Enable. This bit indicates the number of distinct messages that the TUSB73X0 is allowed to generate. 000 - 1 Message (All interrupters mapped to the same message) 001 - 2 Messages (Interrupters 0, 2, 4, and 6 mapped to message 0 and Interrupters 1, 3, 5, and 7 mapped to message 1) 010 - 4 Messages (Interrupters 0 and 4 mapped to message 0, Interrupters 1 and 5 mapped to message 1, Interrupters 2 and 6 mapped to message 2, Interrupters 3 and 7 mapped to message 3) 011 - 8 Messages (Interrupter # mapped to corresponding message #) 100 - 16 Messages (Interrupter # mapped to corresponding message #) 101 - 32 Messages (Interrupter # mapped to corresponding message #) 110 - Reserved111 - Reserved 3:1 MM_CAP r Multiple Message Capabilities. This field indicates the number of distinct messages that TUSB73X0 is capable of generating. This field is read only `011' indicating that the TUSB73X0 can signal 8 distinct messages. 0 MSI_EN MSI Enable. This bit is used to enable MSI interrupt signaling. MSI signaling must be enabled by software for the TUSB73X0 to signal an MSI 0 - MSI signaling is prohibited 1 - MSI signaling is enabled rw 4.31 MSI Lower Message Address Register This register contains the lower 32 bits of the address that a MSI message is written to when an interrupt is to be signaled. PCI register offset: 4Ch Register type:Read/Write Default value: 0000 0000h Table 4-41. PCI Register 4Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-42. MSI Lower Message Address Register Description 42 Bit Field Name Access Description 31:2 ADDRESS rw System Specified Message Address 1:0 RSVD r Reserved. Return zeros when read. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.32 MSI Upper Message Address Register This register contains the upper 32 bits of the address that a MSI message is written to when an interrupt is to be signaled. If this register is 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is used. PCI register offset: 50h Register type:Read/Write Default value: 0000 0000h Table 4-43. PCI Register 4Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.33 MSI Message Data Register This 16-bit register contains the data that software programmed the device to send when it sends a MSI message. PCI register offset: 54h Register type:Read/Write Default value: 0000h Table 4-44. PCI Register 54h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-45. MSI Message Data Register Description Bit Field Name Access Description 15:4 MSG rw System Specific Message. This field contains the portion of the message that the TUSB73X0 can never modify. rw Message Number. This portion of the message field may be modified to contain the message number if multiple messages are enabled. The number of bits that are modifiable depends on the number of messages enabled in the Message Control Register. 1 Message - No message data bits can be modified 2 messages - Bit 0 can be modified 4 messages - Bits 0:1 can be modified 8 messages - Bits 0:2 can be modified 16 messages - Bits 0:3 can be modified 32 messages - Bits 0:4 can be modified 3:0 MSG_NUM Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 43 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.34 Serial Bus Release Number Register (SBRN) This read only register is set to 30h to indicate that the TUSB73X0 is compliant to release 3.0 of the Universal Serial Bus Specification. PCI register offset: 60h Register type:Read-only Default value: 00h Table 4-46. PCI Register 60h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 1 1 0 0 0 0 4.35 Frame Length Adjustment Register (FLADJ) This register is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written to this register, the length of the frame is adjusted for all USB buses implemented by the TUSB73X0. This register is only reset by a Global Reset. PCI register offset: 61h Register type:Read/Write Default value: 20h Table 4-47. PCI Register 61h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 1 0 0 0 0 0 Table 4-48. Frame Length Adjustment Register Description Bit Field Name Access 7:6 RSVD r 5:0 FRAME_LENGTH * rw Description Reserved. Return zeros when read. Frame Length Timing Value. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time is equal to 59488 plus the value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. 4.36 PCI Express Capability ID Register This read-only register identifies the linked list item as the register for PCI Express Capabilities. The register returns 10h when read. PCI register offset: 70h Register type:Read-only Default value: 10h Table 4-49. PCI Register 70h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 0 44 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.37 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0. This register reads C0h pointing to the MSI-X Capability registers. PCI register offset: 71h Register type:Read-only Default value: C0h Table 4-50. PCI Register 71h Bit No. 7 6 5 4 3 2 1 0 Reset State 1 1 0 0 0 0 0 0 4.38 PCI Express Capabilities Register This register indicates the capabilities of the TUSB73X0 related to PCI Express. PCI register offset: 72h Register type:Read-only Default value: 0002h Table 4-51. PCI Register 72h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 4-52. PCI Express Capabilities Register Description Bit Field Name Access 15:14 RSVD r Reserved. Returns zeros when read. 13:9 INT_NUM r Interrupt Message Number. This field is used for MSI and MSI-X support. 8 SLOT r Slot Implemented. This bit is not valid for the TUSB73X0 and is read only zero. 7:4 DEV_TYPE r Device/Port Type. This read only field returns 0000b indicating that the device is a PCI Express Endpoint. 3:0 VERSION r Capability Version. This field returns 0010b indicating revision two of the PCI Express capability. Copyright (c) 2011, Texas Instruments Incorporated Description CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 45 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.39 Device Capabilities Register The Device Capabilities Register indicates the device specific capabilities of the TUSB73X0. PCI register offset: 74h Register type:Read-only, Hardware Update Default value: 0000 8FC3h Table 4-53. PCI Register 74h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 Table 4-54. Device Capabilities Register Description Bit Field Name Access 31:29 RSVD r Reserved. Return zeros when read. 28 FLR r Function Level Reset. This bit is set to 0 since the TUSB73X0 has only one function. ru Captured Slot Power Limit Scale. The value in this register is programmed by the host by issuing a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received bits 9:8 are written to this field. The value in this register specifies the scale used for the Slot Power Limit. 00 - 1.0x 01 - 0.1x 10 - 0.01x 11 - 0.001x 27:26 25:18 CSPLV ru Captured Slot power Limit Value. The value in this register is programmed by the host by issuing a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received bits 7:0 are written to this field. The value in this register in combination with the Slot power Limit Scale value, specifies the upper limit of power supplied to the slot. The power limit is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. 17:16 RSVD r Reserved. Return zeros when read. 15 RBER r Role Based Error Reporting. This bit is hardwired to 1 indicating that the TUSB73X0 supports Role Based Error Reporting 14:12 RSVD r Reserved. Return zeros when read. r Endpoint L1 Acceptable Latency. This field indicates the acceptable latency for a transition from L1 to L0 State. This field can be programmed by writing to the L1_LATENCY field in the General Control Register 2. The default value for this register is the latency for the PHY to exit the L1 state. This field cannot be programmed to be less than the latency for the PHY to exit the L1 state. 11:9 46 CSPLS Description EP_L1_LAT 8:6 EP_L0S_LAT r Endpoint L0s Acceptable Latency. This field indicates the acceptable latency for a transition from L0s to L0 State. This field can be programmed by writing to the L0s_LATENCY field in the General Control Register 2. The default value for this register is the latency for the PHY to exit the L0s state. This field cannot be programmed to be less than the latency for the PHY to exit the L0s state. 5 ETFS r Extended Tag Field Supported. This field indicates the size of the tag field and is encoded as 0. 4:3 PFS r Phantom Functions Supported. This field is read only 00b indicating that function numbers are not used for phantom functions. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-54. Device Capabilities Register Description (continued) 2:0 MPSS Max Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. This field is encoded as 011b indicating the Max Payload size for a TLP is 1 Kbyte. r 4.40 Device Control Register The Device Control Register controls PCI Express device specific parameters. PCI register offset: 78h Register type:Read/Write Default value: 2810h Table 4-55. PCI Register 78h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 Table 4-56. Device Control Register Description Bit 15 14:12 Field Name INITIATE_FLR MRRS Access Description rw Initiate Function Level Reset. A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b. rw Max Read Request Size. This field is programmed by host software to set the maximum size of a read request that the TUSB73X0 can generate. This field is encoded as: 000 - 128B 001 - 256B 010 - 512B (default) 011 - 1024B 100 - 2048B101 - 4096B 110 - Reserved 111 - Reserved 11 ENS rw Enable No Snoop. Controls the setting of the "No Snoop" flag within the TLP header for upstream memory transactions mapped to any traffic class mapped to a virtual channel other than VC0 through the Upstream Decode Windows. 0 - No snoop field is `0' 1 - No snoop field is `1' (default) 10 APPE rw Auxiliary Power PM Enable. This bit is only reset by a Global Reset. 9 PFE r 8 ETFE rw Extended Tag Field Enable. 7:5 MPS rw Max Payload Size. 4 ERO rw Enable Relaxed Ordering. 3 URRE rw Unsupported Request Reporting Enable. 2 FERE rw Fatal Error Reporting Enable. 1 NFERE rw Non-Fatal Error Reporting Enable. 0 CERE rw Correctable Error Reporting Enable. Copyright (c) 2011, Texas Instruments Incorporated Phantom Function Enable. Since the TUSB73X0 does not support phantom functions this bit is read only zero. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 47 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.41 Device Status Register The Device Status Register controls PCI Express device specific parameters. PCI register offset: 7Ah Register type:Read Only, Clear by a Write of One, Hardware Update Default value: 00x0h Table 4-57. PCI Register 7Ah Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 Table 4-58. Device Status Register Description Bit Field Name Access Description 15:6 RSVD r Reserved. Return zeros when read. 5 PEND ru Transaction Pending. 4 APD ru AUX Power Detected. This bit indicates that AUX power is present. 0 - No AUX power detected. (AUX_DET pin is `0') 1 - AUX power detected. (AUX_DET pin is `1') This bit is set based upon the state of the AUX_DET pin. 3 URD rcu Unsupported Request Detected. 2 FED rcu Fatal Error Detected. 1 NFED rcu Non-Fatal Error Detected. 0 CED rcu Correctable Error Detected. 4.42 Link Capabilities Register The Link Capabilities Register indicates the link specific capabilities of the TUSB73X0. PCI register offset: 7Ch Register type:Read-only Default value: 0007 xC12h Table 4-59. PCI Register 7Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 x x 1 1 1 0 0 0 0 0 1 0 0 1 0 Table 4-60. Link Capabilities Register Description Bit 48 Field Name Access Description 31:24 PORT_NUM r Port Number. This field indicates port number for the PCI Express link. This field is read only 00h indicating that the Link is associated with port zero. 23:19 RSVD r Reserved. Returns zeros when read. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-60. Link Capabilities Register Description (continued) 18 CLK_PM r Clock Power Management. This bit is hardwired to 1 to indicate that the TUSB73X0 supports Clock Power Management through the CLKREQ# protocol. 17:15 L1_LATENCY r L1 Exit Latency. This field indicates the time that it takes to transition from the L1 state to the L0 state. The value reported by this field is determined by either the L1_EXIT_LAT_ASYNC field or the L1_EXIT_LAT_COMMON field in the General Control Register 0. 14:12 L0S_LATENCY r L0s Exit Latency. This field indicates the time that it takes to transition from the L0s state to the L0 state. The value reported by this field is determined by either the L0s_EXIT_LAT_ASYNC field or the L0s_EXIT_LAT_COMMON field in the General Control Register 0. 11:10 ASLPMS r Active State Link PM Support. This field indicates the level of active state power management that the TUSB73X0 supports. The value 11b indicates support for both L0s and L1 through active state power management. 9:4 MLW r Maximum Link Width. This field is encoded 000001b to indicate that the TUSB73X0 only supports a 1x PCI Express link. 3:0 MLS r Maximum Link Speed. This field is encoded 0010b to indicate that the TUSB73X0 supports link speeds of 5 Gb/s and 2.5 Gb/s. 4.43 Link Control Register The Link Control Register indicates is used to control link specific behavior. PCI register offset: 80h Register type:Read-only, Read/Write Default value: 0000h Table 4-61. PCI Register 80h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-62. Link Control Register Description Bit Field Name Access 15:9 RSVD r Description 8 EN_CPM rw Enable Clock Power Management. 7 ES rw Extended Synch. Common Clock Configuration. This bit is set when a common clock is provided to both ends of the PCI Express link. This bit is also used to select the L0s exit latency and L1 exit latency. 0 - Reference clock is asynchronous (L0s exit latency and L1 exit latency based on the L0s_EXIT_LAT_ASYNC and L1_EXIT_LAT_ASYNC fields in the General Control Register 0) 1 - Reference clock is synchronous (L0s exit latency and L1 exit latency based on the L0s_EXIT_LAT_COMMON and L1_EXIT_LAT_COMMON fields in the General Control Register 0) Reserved. Returns zeros when read. 6 CCC rw 5 RL r Retrain Link. This bit has no function and is read only zero. Link Disable. This bit has no function and is read only zero. 4 LD r 3 RCB rw 2 RSVD r Copyright (c) 2011, Texas Instruments Incorporated Read Completion Boundary. Reserved. Returns zero when read. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 49 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-62. Link Control Register Description (continued) 1:0 ASLPMC Active State Link PM Control. This field is used to enable and disable active state PM. 00 - Active State PM Disabled 01 - L0s Entry Enabled 10 - L1 Entry Enabled 11 - L0s and L1 Entry Enable rw 4.44 Link Status Register The Link Status Register indicates current state of the PCI Express Link. PCI register offset: 82h Register type:Read-only Default value: 101xh Table 4-63. PCI Register 82h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 0 0 0 0 1 0 0 x x Table 4-64. Link Status Register Description Bit Field Name Access Description 15 LINK_ABS r Link Autonomous Bandwidth Status. This bit has no function and is read only zero. 14 LINK_BMS r Link Bandwidth Management Status. This bit has no function and is read only zero. 13 DLL_ACTIVE r Data Link Layer Active. This bit has no function and is read only zero. 12 SCC r Slot Clock Configuration. This bit is `1', since the TUSB73X0 uses the 100-MHz differential reference clock provided by the platform. 11 LT r Link Training. This bit has no function and is read only zero. 10 TE r Retrain Link. This bit has no function and is read only zero. 9:4 NLW r Negotiated Link Width. This field is read only 000001b indicating the lane width is 1x. 3:0 LS r Link Speed. This field indicates the negotiated link speed. 4.45 Device Capabilities 2 Register The Device Capabilities 2 Register indicates the device specific capabilities of the TUSB73X0. PCI register offset: 94h Register type:Read-only Default value: 0000 0010h 50 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-65. PCI Register 94h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 4-66. Device Capabilities 2 Register Description Bit Field Name Access Description 31:5 RSVD r Reserved. Returns zeros when read. 4 CPLT_TO_DIS_SUP r Completion Timeout Disable Supported. This bit is read only 1b indicating that the completion timeout disable mechanism is supported. 3:0 CPLT_TO_RANGES r Completion Timeout Ranges Supported. This field is read only 0000b indicating that completion timeout programming is not supported. 4.46 Device Control 2 Register The Device Control 2 Register controls PCI Express device specific parameters. PCI register offset: 98h Register type:Read-only, Read/Write Default value: 0800h Table 4-67. PCI Register 98h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Table 4-68. Device Control 2 Register Description Bit Field Name Access 15:5 RSVD r 4 CPTL_TO_DIS rw 3:0 CPLT_TO_VALUE r Description Reserved. Returns zeros when read. Completion Timeout Disable. Completion Timeout Value. This field is read only 0000b indicating that completion timeout programming is not supported. 4.47 Link Control 2 Register The Link Control 2 Register indicates is used to control link specific behavior. PCI register offset: A0h Register type:Read-only, Read/Write Default value: 0000h Table 4-69. PCI Register A0h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 51 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-70. Link Control 2 Register Description Bit Field Name Access Description 15:13 RSVD r 12 COMPLIANCE_DEEMPH* rw Compliance De-Emphasis. This bit is sticky and is only reset by a Global Reset. 11 COMPLIANCE_SOS* rw Compliance SOS. This bit is sticky and is only reset by a Global Reset. 10 ENT_MOD_COMPLIANCE* rw Enter Modified Compliance. This bit is sticky and is only reset by a Global Reset. 9:7 TRANSMIT_MARGIN* rw Transmit Margin. This bit is sticky and is only reset by a Global Reset. 6 SEL_DEEMPH r Selectable De-Emphasis. This bit has no function and is read only zero. 5 HW_AUTO_SPEED_DIS r Hardware Autonomous Speed Disable. This bit is read only zero since this function is not supported. 4 ENTER_COMPL* rw Enter Compliance. This bit is sticky and is only reset by a Global Reset. 3:0 TGT_LINK_SPEED* rw Target Link Speed. This bit is sticky and is only reset by a Global Reset. Reserved. Returns zeros when read. 4.48 Link Status 2 Register The Link Status 2 Register indicates current state of the PCI Express Link. PCI register offset: A2h Register type:Read-only Default value: 000xh Table 4-71. PCI Register A2h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x Table 4-72. Link Status 2 Register Description Bit Field Name Access 15:1 RSVD r Reserved. Returns zeros when read. Description 0 DEEMPH_LEVEL r Current De-Emphasis Level. 4.49 Serial Bus Data Register The Serial Bus Data register is used to read and write data on the serial bus interface. When writing data to the serial bus, this register must be written before writing to the Serial Bus Address register to initiate the cycle. When reading data from the serial bus, this register will contain the data read after the REQBUSY (bit 5 Serial Bus Control Register) bit is cleared. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B0h Register type:Read/Write Default value: 00h Table 4-73. PCI Register B0h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 52 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.50 Serial Bus Index Register The value written to the Serial Bus Index register represents the byte address of the byte being read or written from the serial bus device. The Serial Bus Index register must be written before the before initiating a serial bus cycle by writing to the Serial Bus Slave Address register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B1h Register type:Read/Write Default value: 00h Table 4-74. PCI Register B1h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.51 Serial Bus Slave Address Regsiter The Serial Bus Slave Address register is used to indicate the address of the device being targeted by the serial bus cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates the cycle on the serial interface. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B2h Register type:Read/Write Default value: 00h Table 4-75. PCI Register B2h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 Table 4-76. Serial Bus Slave Address Register Description (1) Bit (1) Field Name Access Description 7:1 SLAVE_ADDR rw Serial Bus Slave Address. This bit field represents the slave address of a read or write transaction on the serial interface. 0 RW_CMD rw Read/Write Command. This bit is used to determine if the serial bus cycle will be a read or a write cycle. 0 - A single byte write is requested. 1 - A single byte read is requested. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. 4.52 Serial Bus Control and Status Register The Serial Bus Control and Status register is used to control the behavior of the Serial bus interface. This register also provides status information about the state of the serial bus. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B3h Register type:Read/Write, Read-Only, Read/Clear Default value: 00h Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 53 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-77. PCI Register B3h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 Table 4-78. Serial Bus Control and Status Register Description (1) Bit Field Name Access 7 PROT_SEL rw 6 RSVD r Reserved. Returns zero when read. 5 REQBUSY r Requested Serial Bus Access Busy. This bit is set when a serial bus cycle is in progress. 0 - No serial bus cycle 1 - Serial bus cycle in progress r Serial EEPROM Access Busy. This bit is set when the serial EEPROM circuitry in the TUSB73X0 is downloading register defaults from a serial EEPROM. 0 - No EEPROM activity 1 - EEPROM download in progress 4 (1) ROMBUSY Description Protocol Select. This bit is used to select the serial bus address mode used. 0 - Slave Address and Byte Address are sent on the serial bus. 1 - Only the Slave address is sent on the serial bus. 3 SBDETECT rwu Serial EEPROM Detected. This bit is automatically set when a serial EEPROM is detected by the TUSB73X0. The value of this bit is used to enable the serial bus interface and to control whether or not the EEPROM load takes place. Note that a serial EEPROM is only detected once following a PERST# or a GRST#. 0 - No EEPROM present, EEPROM load process does not happen 1 - EEPROM present, EEPROM load process takes place Note that even if a serial EERPOM is not detected following PERST# or a GRST#, software can still set this bit to enable the serial bus interface. In this situation, the EEPROM load process will not happen. 2 SBTEST rw Serial Bus Test. This bit is used for internal test purposes. This bit controls the clock source for the serial interface clock. 0 - Serial bus clock at normal operating frequency ~ 100 kHz 1 - Serial bus clock frequency increased for test purposes 1 SB_ERR rc Serial Bus Error. This bit is set when an error occurs during a software initiated serial bus cycle. 0 - No error 1 - Serial bus error 0 ROM_ERR rc Serial EEPROM Load Error. This bit is set when an error occurs while downloading registers from a serial EEPROM. 0 - No Error 1 - EEPROM load error Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. 4.53 GPIO Control Register This register is used to control the direction of the eight GPIO pins. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B4h Register type:Read/Write, Read-Only Default value: 0000h Table 4-79. PCI Register B4h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-80. GPIO Control Register Description (1) (1) Bit Field Name Access Description 15:4 RSVD r 3 GPIO3_DIR rw GPIO 3 Data Direction. This bit selects whether GPIO3 is in input or output mode. 0 - Input 1 - Output 2 GPIO2_DIR rw GPIO 2 Data Direction. This bit selects whether GPIO2 is in input or output mode. 0 - Input 1 - Output 1 GPIO1_DIR rw GPIO 1 Data Direction. This bit selects whether GPIO1 is in input or output mode. 0 - Input 1 - Output 0 GPIO0_DIR rw GPIO 0 Data Direction. This bit selects whether GPIO0 is in input or output mode. 0 - Input 1 - Output Reserved. Returns zero when read. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. 4.54 GPIO Data Register This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in output mode. Writing to a bit that is in input mode will be ignored. The default value at power up depends on the state of the GPIO terminals as they default to general purpose inputs. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: B6h Register type:Read/Write, Read-Only Default value: 0000h Table 4-81. PCI Register B6h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 x x x x Table 4-82. GPIO Data Register Description (1) (1) Bit Field Name Access Description 15:4 RSVD r 3 GPIO3_DATA rw GPIO 3 Data. This bit is used to read the state of GPIO3 or change the state of GPIO3 in output mode. 2 GPIO2_DATA rw GPIO 2 Data. This bit is used to read the state of GPIO2 or change the state of GPIO2 in output mode. 1 GPIO1_DATA rw GPIO 1 Data. This bit is used to read the state of GPIO1 or change the state of GPIO1 in output mode. 0 GPIO0_DATA rw GPIO 0 Data. This bit is used to read the state of GPIO0 or change the state of GPIO0 in output mode. Reserved. Returns zero when read. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 55 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.55 MSI-X Capability ID Register This read-only register identifies the linked list item as the register for MSI-X Capabilities. The register returns 11h when read. PCI register offset: C0h Register type:Read-Only Default value: 11h Table 4-83. PCI Register C0h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 1 4.56 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0. This register reads 00h indicating that no additional capabilities are supported. PCI register offset: C1h Register type:Read-Only Default value: 11h Table 4-84. PCI Register C1h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.57 MSI-X Message Control Register This register is used to control the sending of MSI-X messages. PCI register offset: C2h Register type:Read-Only, Read/Write Default value: 0007h Table 4-85. PCI Register C2h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Table 4-86. MSI-X Message Control Register Description 56 Bit Field Name Access 15 MSIX_EN rw MSI-X Enable. Description 14 FUNC_MASK rw Function Mask. 13:11 RSVD r Reserved. Returns zero when read. 10:0 TABLE_SIZE r MSI-X Table Size. This field is set to 07h to indicate a table size of 8 entries. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.58 MSI-X Table Offset and BIR Register This register indicates into which BAR and offset the MSI-X table is mapped. PCI register offset: C4h Register type:Read-Only Default value: 0000 0002h Table 4-87. PCI Register C4h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 4-88. MSI-X Table Offset and BIR Register Description Bit Field Name Access Description 31:3 TABLE_OFFSET r Table Offset. This field is set to 000h to indicate that the MSI-X Table is at an offset of 0000h from the beginning of the BAR at offset 18h. 2:0 TABLE_BIR r Table BIR. This field is set to 010b to indicate that the MSI-X table is mapped into the BAR at offset 18h. 4.59 MSI-X PBA Offset and BIR Register This register indicates into which BAR and offset the MSI-X PBA is mapped. PCI register offset: C8h Register type:Read-Only Default value: 0000 1000h Table 4-89. PCI Register C8h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-90. MSI-X PBA Offset and BIR Register Descriptions Bit Field Name Access Description 31:3 PBA_OFFSET r PBA Offset. This field is set to 200h to indicate that the MSI-X PBA is at an offset of 1000h from the beginning of the BAR at offset 18h. 2:0 PBA_BIR r PBA BIR. This field is set to 010b to indicate that the MSI-X PBA is mapped into the BAR at offset 18h. Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 57 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.60 Subsystem Access Register This register is a read/write register and the contents of this register are aliased to the Subsystem Vendor ID and Subsystem ID Registers at PCI Offsets 2Ch and 2Eh. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: D0h Register type:Read/Write Default value: 0000 0000h Table 4-91. PCI Register D0h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-92. Subsystem Access Register Description Bit Field Name Access Description 31:16 SubsystemID rw Subsystem ID. The value written to this field is aliased to the Subsystem ID Register at PCI Offset 2Eh. 15:0 SubsystemVendorID rw Subsystem Vendor ID. The value written to this field is aliased to the Subsystem Vendor ID Register at PCI Offset 2Ch. 4.61 General Control 0 Register This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: D4h Register type:Read/Write Default value: 0000 0D9Bh Table 4-93. PCI Register D4h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 58 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-94. General Control 0 Register Description Bit Field Name Access Description 31:12 RSVD r 11:9 L1_EXIT_LAT_ASYNC rw L1 Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is `0'. This field defaults to 110b. 8:6 L1_EXIT_LAT_COMMON rw L1 Exit Latency for Common Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is `1'. This field defaults to 110b. 5:3 L0s_EXIT_LAT_ASYNC rw L0s Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is `0'. This field defaults to 011b. 2:0 L0s_EXIT_LAT_COMMON rw L0s Exit Latency for Common Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is `1'. This field defaults to 011b. Reserved. Returns zeros when read. 4.62 General Control 1 Register This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: D8h Register type:Read-Only,Read/Write Default value: 0000 001Bh Table 4-95. PCI Register D8h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Table 4-96. General Control 1 Register Description Bit Field Name Access 31:6 RSVD r 5:3 L1ASPM_ENTRY_TIMER rw L1ASPM Entry Timer. This field specifies the value of the L1ASPM Entry Timer. This field defaults to `011', corresponding to a value of 8 s. 2:0 L0s_ENTRY_TIMER rw L0s Entry timer. This field specifies the value of the L0s Entry timer. This field defaults to `011', corresponding to a value of 4 s. Copyright (c) 2011, Texas Instruments Incorporated Description Reserved. Returns zeros when read. CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 59 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 4.63 General Control 2 Register This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. Note: For Pass 1.0 of the TUSB73X0 design, this register is read only zeros and has no effect. PCI register offset: DCh Register type:Read-Only,Read/Write Default value: 0000 001Bh Table 4-97. PCI Register DCh Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Table 4-98. General Control 2 Register Description Bit Field Name Access 31:6 RSVD r 5:3 2:0 L1_LATENCY L0s_LATENCY Description Reserved. Returns zeros when read. rw L1 Maximum Exit Latency. This field is used to program the maximum acceptable latency when exiting the L1 state. This is used to set the L1 Acceptable Latency field in the Device capabilities register. 000 - Less than 1s 001 - 1 s up to less than 2 s 010 - 2 s up to less than 4 s 011 - 4 s up to less than 8 s (default) 100 - 8 s up to less than 16 s 101 - 16 s up to less than 32 s 110 - 32 s to 64 s 111 - more than 64 s rw L0s Maximum Exit Latency. This field is used to program the maximum acceptable latency when exiting the L0s state. This is used to set the L0s Acceptable Latency field in the Device capabilities register. 000 - Less than 64 ns 001 - 64 ns up to less than 128 ns 010 - 128 ns up to less than 256 ns 011 - 256 ns up to less than 512 ns (default) 100 - 512 ns up to less than 1 s 101 - 1 s up to less than 2 s 110 - 2 s to 4 s 111 - more than 4 s 4.64 USB Control Register This register is a read/write register is used to control USB settings in the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: E0h Register type:Read/Write Default value: 0000 0000h 60 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-99. PCI Register E0h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-100. USB Control Register Description (1) (2) Bit Field Name Access 31 USB_SPREAD_DIS rw USB Spread Spectrum Disable. When this bit is set to `1', spread spectrum generation for the USB 3.0 clock is disabled. rw Frequency Select Enable. When this bit is set to 1, the oscillator is restarted with the PLL multiplier value and the oscillator frequency controls set according to the value specified in the PLL_FREQ_SEL field. This bit can only be written to once after power up. 30* (1) (2) FREQ_SEL_EN* Description 29:24* PLL_FREQ_SEL* rw PLL Frequency Select. If the FREQSEL pin is `1', then the value in this field controls the Frequency Select inputs to the PLL. In addition, the frequency selector inputs to the Oscillator are set appropriately for the frequency selected. If the FREQSEL pin is `0', then this field has no effect. Once the FREQ_SEL_EN bit has been set, this field will be locked and cannot be changed. 000110 - 20 MHz xxxxxxxxxxxxxxx 010110 - 36 MHz 000111 - 21 MHz xxxxxxxxxxxxxxx 010111 - 37 MHz 001000 - 22 MHz xxxxxxxxxxxxxxx 011000 - 38 MHz 001001 - 23 MHz xxxxxxxxxxxxxxx 011001 - 38.4 MHz 001010 - 24 MHz xxxxxxxxxxxxxxx 011010 - 39 MHz 001011 - 25 MHz xxxxxxxxxxxxxxx 011011 - 40 MHz 001100 - 26 MHz xxxxxxxxxxxxxxx 011100 - 41 MHz 001101 - 27 MHz xxxxxxxxxxxxxxx 011101 - 42 MHz 001110 - 28 MHz xxxxxxxxxxxxxxx 011110 - 43 MHz 001111 - 29 MHz xxxxxxxxxxxxxxx 011111 - 44 MHz 010000 - 30 MHz xxxxxxxxxxxxxxx 100000 - 45 MHz 010001 - 31 MHz xxxxxxxxxxxxxxx 100001 - 46 MHz 010010 - 32 MHz xxxxxxxxxxxxxxx 100010 - 47 MHz 010011 - 33 MHz xxxxxxxxxxxxxxx 100011 - 48 MHz 010100 - 34 MHz xxxxxxxxxxxxxxx 100100 - 49 MHz 010101 - 35 MHz xxxxxxxxxxxxxxx 100101 - 50 MHz All other values are reserved. 23 HIDE_MSIX rw Hide MSI-X. When this bit is set, the Next Item Pointer Register (offset 71h) for the PCI Express Capability is set to 00h, and BAR2 (offset 18h) and BAR3 (offset 1Ch) are only zeros. 22* PWRON_POLARITY* rw PWRONx Polarity. When this bit is `0' (default), the PWRONx# pins are active low and their internal pull-down resistors are enabled. When this bit is `1', the PWRONx# pins are active high and their internal pull-down resistors are disabled. 21:17 RSVD r Reserved. Returns zero when read. 16 PPC_NOT_PRESENT rw Port Power Control Not Present. When this bit is `0', the TUSB73X0 forces the PPC bit to `1' in the Host Controller Capability Parameters, indicating that the system supports port power switches. When this bit is set to `1', the TUSB73X0 forces the PPC bit to `0' in the Host Controller Capability Parameters, indicating that the system does not support port power switches. 15:12 RSVD rw Reserved. Returns zeros when read. 11 PORT4_DIS rw USB Port 4 Disable. When this bit is set to `1', port 4 of the TUSB73X0 is disabled. For the TUSB7320 Port 4 is not present and this bit has no effect. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset Bits marked with * are reset by a GRST# Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 61 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-100. USB Control Register Description(1)(2) (continued) Bit Field Name Access Description 10 PORT3_DIS rw USB Port 3 Disable. When this bit is set to `1', port 3 of the TUSB73X0 is disabled. For the TUSB7320 Port 3 is not present and this bit has no effect. 9 PORT2_DIS rw USB Port 2 Disable. When this bit is set to `1', port 2 of the TUSB73X0 is disabled. 8 PORT1_DIS rw USB Port 1 Disable. When this bit is set to `1', port 1 of the TUSB73X0 is disabled. rw USB 3.0 Port 4 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 3.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. 7 USB3_PORT4_NON_REM 6 USB3_PORT3_NON_REM rw USB 3.0 Port 3 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 3.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. 5 USB3_PORT2_NON_REM rw USB 3.0 Port 2 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 3.0 Port 2. 4 USB3_PORT1_NON_REM rw USB 3.0 Port 1 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 3.0 Port 1. 3 USB2_PORT4_NON_REM rw USB 2.0 Port 4 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 2.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. 2 USB2_PORT3_NON_REM rw USB 2.0 Port 3 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 2.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. 1 USB2_PORT2_NON_REM rw USB 2.0 Port 2 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 2.0 Port 2. 0 USB2_PORT1_NON_REM rw USB 2.0 Port 1 Non-Removable. When this bit is set to `1', the TUSB73X0 forces the DR bit to `1' in the Port Status and Control Register corresponding to USB 2.0 Port 1. 4.65 De-Emphasis and Swing Control Register This register is used to control the de-emphasis and transmit swing settings for each of the USB 3.0 ports when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: E4h Register type:Read/Write Default value: 0000 0000h Table 4-101. PCI Register E4h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-102. De-Emphasis and Swing Control Register Description (1) (1) Bit Field Name Access Description 31:28 PORT4_SWING rw Port 4 Swing. When the PORT4_SWING_OV bit is set to `1', these bits are used to set the output swing for port 4. For details on the behavior of the swing signals refer to Table 8-1. For the TUSB7320 Port 4 is not present and these bits have no effect. 27:24 PORT4_DE rw Port 4 Deemphasis. When the PORT4_DE_OV bit is set to `1', these bits are used to set the de-emphasis value for port 4. For details on the behavior of the swing signals refer to Table 8-2. For the TUSB7320 Port 4 is not present and these bits have no effect. 23:20 PORT3_SWING rw Port 3 Swing. When the PORT3_SWING_OV bit is set to `1' these bits are used to set the output swing for port 3. For details on the behavior of the swing signals refer to Table 8-1. For the TUSB7320 Port 3 is not present and these bits have no effect. 19:16 PORT3_DE rw Port 3 Deemphasis. When the PORT3_DE_OV bit is set to `1' these bits are used to set the de-emphasis value for port 3. For details on the behavior of the swing signals refer to Table 8-2. For the TUSB7320 Port 3 is not present and these bits have no effect. 15:12 PORT2_SWING rw Port 2 Swing. When the PORT2_SWING_OV bit is set to `1', these bits are used to set the output swing for port 2.For details on the behavior of the swing signals refer to Table 8-1. 11:8 PORT2_DE rw Port 2 Deemphasis. When the PORT2_DE_OV bit is set to `1' these bits are used to set the de-emphasis value for port 2. For details on the behavior of the swing signals refer to Table 8-2. 7:4 PORT1_SWING rw Port 1 Swing. When the PORT1_SWING_OV bit is set to `1', these bits are used to set the output swing for port 1. For details on the behavior of the swing signals refer to Table 8-1. 3:0 PORT1_DE rw Port 1 Deemphasis. When the PORT1_DE_OV bit is set to `1', these bits are used to set the de-emphasis value for port 1. For details on the behavior of the swing signals refer to Table 8-2. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset 4.66 Equalizer Control Register This register is used to control the equalizer settings for each of the USB 3.0 ports when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: E8h Register type:Read/Write Default value: 0000 0000h Table 4-103. PCI Register E8h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 63 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-104. Equalizer Control Register Description (1) Bit Field Name 31:28 PORT4_EQ_INIT 27:24 PORT4_EQ_FUNC 23:20 (1) PORT3_EQ_INIT Access Description rw Port 4 Equalizer - Initialization Mode. When the PORT4_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer init values for port 4 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. For the TUSB7320 Port 4 is not present and these bits have no effect. rw Port 4 Equalizer- Functional Mode. When the PORT4_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer func values for port 4 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. For the TUSB7320 Port 4 is not present and these bits have no effect. rw Port 3 Equalizer - Initialization Mode. When the PORT3_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer init values for port 3 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. For the TUSB7320 Port 3 is not present and these bits have no effect. 19:16 PORT3_EQ_FUNC rw Port 3 Equalizer- Functional Mode. When the PORT3_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer func values for port 3 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. For the TUSB7320 Port 3 is not present and these bits have no effect. 15:12 PORT2_EQ_INIT rw Port 2 Equalizer - Initialization Mode. When the PORT2_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer init values for port 3 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. 11:8 PORT2_EQ_FUNC rw Port 2 Equalizer- Functional Mode. When the PORT2_EQ_OV bit is set to `1', these bits are used as the source for the Equalizer func values for port 3 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. 7:4 PORT1_EQ_INIT rw Port 1 Equalizer - Initialization Mode. When the PORT1_EQ_OV bit is set to `1', these bits are used as the source for Equalizer init values for port 1 of the PHY. For details on the behavior of the equalizer values refer to Error: Reference source not found. 3:0 PORT1_EQ_FUNC rw Port 1 Equalizer- Functional Mode. When the PORT1_EQ_OV bit is set to `1', these bits are used as the source for Equalizer func values for port 1 of the PHY. For details on the behavior of the equalizer values refer to Table 8-3. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset 4.67 Custom PHY Transmit/Receive Control Register This register is used to enable the override of the default de-emphasis, transmit swing, and receiver equalization settings for each of the USB 3.0 ports. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: ECh Register type:Read/Write Default value: 0000 0000h Table 4-105. PCI Register ECh Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 4-106. Custom PHY Transmit/Receive Control Register Description (1) Bit Field Name Access 31:27 RSVD r 26 25 (1) PORT4_EQ_OV PORT4_SWING_OV Description Reserved. Returns zeros when read. rw Port 4 Equalization Override. When this bit is set to `1', the TUSB73X0 overrides the default equalization settings for port 4 with the values in the PORT4_EQ_FUNC field and the PORT4_EQ_INIT field of the Equalizer Control Register. For the TUSB7320 Port 4 is not present and this bit has no effect. rw Port 4 Swing Override. When this bit is set to `1', the TUSB73X0 overrides the default swing settings for port 4 with the values in the PORT4_SWING field of the Deemphasis and Swing Control Register. For the TUSB7320 Port 4 is not present and this bit has no effect. Port 4 Deemphasis Override. When this bit is set to `1', the TUSB73X0 overrides the default de-emphasis settings for port 4 with the values in the PORT4_DE field of the Deemphasis and Swing Control Register. For the TUSB7320 Port 4 is not present and this bit has no effect. 24 PORT4_DE_OV rw 23:19 RSVD r Reserved. Returns zeros when read. 18 PORT3_EQ_OV rw Port 3 Equalization Override. When this bit is set to `1', the TUSB73X0 overrides the default equalization settings for port 3 with the values in the PORT3_EQ_FUNC field and the PORT3_EQ_INIT field of the Equalizer Control Register. For the TUSB7320 Port 3 is not present and this bit has no effect. 17 PORT3_SWING_OV rw Port 3 Swing Override. When this bit is set to `1', the TUSB73X0 overrides the default swing settings for port 3 with the values in the PORT3_SWING field of the Deemphasis and Swing Control Register. For the TUSB7320 Port 3 is not present and this bit has no effect. 16 PORT3_DE_OV rw Port 3 Deemphasis Override. When this bit is set to `1', the TUSB73X0 overrides the default de-emphasis settings for port 3 with the values in the PORT3_DE field of the Deemphasis and Swing Control Register. For the TUSB7320 Port 3 is not present and this bit has no effect. 15:11 RSVD r Reserved. Returns zeros when read. 10 PORT2_EQ_OV rw Port 2 Equalization Override. When this bit is set to `1', the TUSB73X0 overrides the default equalization settings for port 2 with the values in the PORT2_EQ_FUNC field and the PORT2_EQ_INIT field of the Equalizer Control Register. 9 PORT2_SWING_OV rw Port 2 Swing Override. When this bit is set to `1', the TUSB73X0 overrides the default swing settings for port 2 with the values in the PORT2_SWING field of the Deemphasis and Swing Control Register. 8 PORT2_DE_OV rw Port 2 Deemphasis Override. When this bit is set to `1', the TUSB73X0 overrides the default de-emphasis settings for port 2 with the values in the PORT2_DE field of the Deemphasis and Swing Control Register. 7:3 RSVD r Reserved. Returns zeros when read. 2 PORT1_EQ_OV rw Port 1 Equalization Override. When this bit is set to `1', the TUSB73X0 overrides the default equalization settings for port 1 with the values in the PORT1_EQ_FUNC field and the PORT1_EQ_INIT field of the Equalizer Control Register. 1 PORT1_SWING_OV rw Port 1 Swing Override. When this bit is set to `1', the TUSB73X0 overrides the default swing settings for port 1 with the values in the PORT1_SWING field of the Deemphasis and Swing Control Register. 0 PORT1_DE_OV rw Port 1 Deemphasis Override. When this bit is set to `1', the TUSB73X0 overrides the default de-emphasis settings for port 1 with the values in the PORT1_DE field of the Deemphasis and Swing Control Register. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset Copyright (c) 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 65 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 5 PCI EXPRESS EXTENDED CONFIGURATION SPACE 5.1 The PCI Express Extended Configuration Map Table 5-1. PCI Express Extended Configuration Register Map Register Name Offset PCI Express Advanced Error Reporting Capabilities ID Next Capability Offset / Capability Version 100h Uncorrectable Error Status Register 104h Uncorrectable Error Mask Register 108h Uncorrectable Error Severity Register 10Ch Correctable Error Status Register 110h Correctable Error Mask Register 114h Advanced Error Capabilities and Control Register 118h Header Log Register 11Ch Header Log Register 120h Header Log Register 124h Header Log Register 128h Reserved 12Ch-14Fh Next Capability Offset / Capability Version Device Serial Number Capability ID 150h Serial Number Register (Lower DW) 5.2 154h Serial Number Register (Upper DW) 158h Reserved 15C-FFFh Advanced Error Reporting capability Register This read-only register identifies the linked list item as the register for PCI Express Advanced Error Reporting Capabilities. The register returns 0001h when read. PCI Express Extended Register Offset: 100h Register type:Read-Only Default value: 0001h Table 5-2. PCI Express Extended Register 100h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 66 PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 5.3 Next Capability Offset / Capability Version Register This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The upper 12 bits in this register shall be 150h, indicating that the Device Serial Number Capability starts at offset 150h. The least significant four bits identify the revision of the current capability block as 2h. PCI Express Extended Register Offset: 100h Register type:Read-Only Default value: 1502h Table 5-3. PCI Express Extended Register 102h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 5.4 Uncorrectable Error Status Register The Uncorrectable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 104h Register type:Read-Only, Read/Clear Default value: 0000 0000h Table 5-4. PCI Express Extended Register 104h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-5. Custom PHY Transmit/Receive Control Register Description (1) (1) Bit Field Name Access Description 31:21 RSVD r 20 UR_ERROR rcu Unsupported Request Error. This bit is asserted when an Unsupported Request is received. 19 ECRC_ERROR rcu Extended CRC Error. This bit is asserted when an Extended CRC error is detected. 18 MAL_TLP rcu Malformed TLP. This bit is asserted when a malformed TLP is detected. 17 RX_OVERFLOW rcu Receiver Overflow. This bit is asserted when the flow control logic detects that the transmitting device has illegally exceeded the number of credits that were issued. 16 UNXP_CPL rcu Unexpected Completion. This bit is asserted when a completion packet is received that does not correspond to an issued request. 15 CPL_ABORT rcu Completer Abort. This bit is asserted when the TUSB73X0 signals a Completer Abort. 14 CPL_TIMEOUT rcu Completion Timeout. This bit is asserted when no completion has been received for an issued request before the timeout period. Reserved. Returns zeros when read. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset Copyright (c) 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 67 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 5-5. Custom PHY Transmit/Receive Control Register Description(1) (continued) 13 FC_ERROR rcu Flow Control Error. This bit is asserted when a flow control protocol error is detected either during initialization or during normal operation. Poisoned TLP. This bit is asserted when a poisoned TLP is received. 12 PSN_TLP rcu 11:5 RSVD r 4 DLL_ERROR rcu 3:0 RSVD r 5.5 Reserved. Returns zeros when read. Data Link Protocol Error. This bit is asserted if a data link layer protocol error is detected. Reserved. Returns zeros when read. Uncorrectable Error Mask Register The Uncorrectable Error Mask Register controls the reporting of individual errors as they occur. When a bit is set to one, the corresponding error condition will not be logged, and does not update any of the status bits within the Extended Error Reporting Capability block. PCI Express Extended Register Offset: 108h Register type:Read-Only, Read/Write Default value: 0000 0000h Table 5-6. PCI Express Extended Register 108h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-7. Bit Descriptions - Uncorrectable Error Mask Register (1) (1) 68 Bit Field Name Access Description 31:21 RSVD r 20 UR_ERROR_MASK rw Unsupported Request Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 19 ECRC_ERROR_MASK rw Extended CRC Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 18 MAL_TLP_MASK rw Malformed TLP Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 17 RX_OVERFLOW_MASK rw Receiver Overflow Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 16 UNXP_CPL_MASK rw Unexpected Completion Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 15 CPL_ABORT_MASK rw Completer Abort Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 14 CPL_TIMEOUT_MASK rw Completion Timeout Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked Reserved. Returns zeros when read. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 5-7. Bit Descriptions - Uncorrectable Error Mask Register(1) (continued) 13 FC_ERROR_MASK rw Flow Control Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 12 PSN_TLP_MASK rw Poisoned TLP Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 11:5 RSVD r 4 DLL_ERROR_MASK rw 3:0 RSVD r 5.6 Reserved. Returns zeros when read. Data Link Protocol Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked Reserved. Returns zeros when read. Uncorrectable Error Severity Register The Uncorrectable Error Severity Register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition will be identified as fatal. When a bit is clear, the corresponding error condition will be identified as non-fatal. PCI Express Extended Register Offset: 10Ch Register type:Read-Only, Read/Write Default value: 0026 2030h Table 5-8. PCI Express Extended Register 10Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Table 5-9. Bit Descriptions - Uncorrectable Error Severity Register (1) (1) Bit Field Name Access Description 31:23 RSVD r Reserved. Returns zeros when read. 22 RSVD r Reserved. Returns `1' when read. 21 RSVD r Reserved. Returns zeros when read. 20 UR_ERROR_SEVR rw Unsupported Request Error Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 19 ECRC_ERROR_SEVR rw Extended CRC Error Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 18 MAL_TLP_SEVR rw Malformed TLP Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 17 RX_OVERFLOW_SEVR rw Receiver Overflow Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 16 UNXP_CPL_SEVR rw Unexpected Completion Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset Copyright (c) 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 69 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 5-9. Bit Descriptions - Uncorrectable Error Severity Register(1) (continued) 15 CPL_ABORT_SEVR rw Completer Abort Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 14 CPL_TIMEOUT_SEVR rw Completion Timeout Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 13 FC_ERROR_SEVR rw Flow Control Error Severity. 0 - Error Condition is signaled using ERR_NONFATAL1 - Error Condition is signaled using ERR_FATAL 12 PSN_TLP_SEVR rw Poisoned TLP Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL 11:6 RSVD r Reserved. Returns zeros when read. 5 RSVD r Reserved. Returns `1' when read. 4 DLL_ERROR_SEVR rw 3:0 RSVD r 5.7 Data Link Protocol Error Severity. 0 - Error Condition is signaled using ERR_NONFATAL 1 - Error Condition is signaled using ERR_FATAL Reserved. Returns zeros when read. correctable Error Severity Register The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 110h Register type:Read-Only, Read/Clear Default value: 0000 0000h Table 5-10. PCI Express Extended Register 110h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-11. Bit Descriptions - Correctable Error Severity Register (1) (1) 70 Bit Field Name Access 31:14 RSVD r Description 13 ANFES rcu Advisory Non-Fatal Error Status. This bit is asserted when an Advisory Non-Fatal Error has been reported. 12 REPLAY_TMOUT rcu Replay Timer Timeout. This bit is asserted when the replay timer expires for a pending request or completion that has not been acknowledged. 11:9 RSVD r 8 REPLAY_ROLL rcu REPLAY_NUM Rollover. This bit is asserted when the replay counter rolls over when a pending request or completion has not been acknowledged. 7 BAD_DLLP rcu Bad DLLP Error. This bit is asserted when an 8b/10b error was detected by the PHY during the reception of a DLLP. 6 BAD_TLP rcu Bad TLP Error. This bit is asserted when an 8b/10b error was detected by the PHY during the reception of a TLP. 5:1 RSVD r Reserved. Returns zeros when read. Reserved. Returns zeros when read. Reserved. Returns zeros when read. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 5-11. Bit Descriptions - Correctable Error Severity Register(1) (continued) RX_ERROR 0 5.8 Receiver Error. This bit is asserted when an 8b/10b error is detected by the PHY at any time. rcu correctable Error Mask Register The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 114h Register type:Read-Only, Read/Write Default value: 0000 2000h Table 5-12. PCI Express Extended Register 114h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-13. Bit Descriptions - Correctable Error Mask Register (1) (1) Bit Field Name Access 31:14 RSVD r Description 13 ANFEM rw Advisory Non-Fatal Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 12 REPLAY_TMOUT_MASK rw Replay Timer Timeout Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 11:9 RSVD r 8 REPLAY_ROLL_MASK rw REPLAY_NUM Rollover Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 7 BAD_DLLP_MASK rw Bad DLLP Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 6 BAD_TLP_MASK rw Bad TLP Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked 5:1 RSVD r 0 RX_ERROR_MASK rw Reserved. Returns zeros when read. Reserved. Returns zeros when read. Reserved. Returns zeros when read. Receiver Error Mask. 0 - Error Condition is Unmasked 1 - Error Condition is Masked Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset Copyright (c) 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 71 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 5.9 www.ti.com Advanced Error Capabilities and control Register The Advanced Error Capabilities and Control Register allows the system to monitor and control the advanced error reporting capabilities. PCI Express Extended Register Offset: 118h Register type:Read-Only, Read/Write Default value: 0000 0050h Table 5-14. PCI Express Extended Register 118h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Table 5-15. Bit Descriptions - Advanced Error Capabilities and Control Register (1) (1) 72 Bit Field Name Access 31:9 RSVD r Description 8 ECRC_CHK_EN rw 7 ECRC_CHK_CAPABLE r 6 ECRC_GEN_EN rw 5 ECRC_GEN_CAPABLE r Extended CRC Generation Capable. This read-only bit returns a value of `1' indicating that the TUSB73X0 is capable of generating extended CRC information. 4:0 FIRST_ERR ru First Error Pointer. This five bit value reflects the bit position within the Uncorrectable Error Status Register corresponding to the class of the first error condition that was detected. Reserved. Returns zeros when read. Extended CRC Check Enable. 0 - Extended CRC checking is Disabled 1 - Extended CRC checking is Enabled Extended CRC Check Capable. This read-only bit returns a value of `1' indicating that the TUSB73X0 is capable of checking extended CRC information. Extended CRC Generation Enable. 0 - Extended CRC generation is Disabled 1 - Extended CRC generation is Enabled Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 5.10 Header Log Register The Header Log Register stores the TLP header for the packet that lead to the most recently detected error condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW TLP header. Each DWORD is stored with the least significant byte representing the earliest transmitted. PCI Express Extended Register Offset: 11Ch, 120h, 124h, 128h Register type:Read-Only Default value: 0000 0000h Table 5-16. PCI Express Extended Register 11Ch, 120, 124h, and 128h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.11 Device Serial Number Capability ID Register This read-only register identifies the linked list item as the Device Serial Number Capability. This register returns 0003h when read. PCI Express Extended Register Offset: 150h Register type:Read-Only Default value: 0003h Table 5-17. Device Serial Number Capability ID Register Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 5.12 Next Capability Offset/Capability Version Register This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The upper 12 bits in this register are 000h, indicating that the Device Serial Number Capability is the last capability in the list. The least significant four bits identify the revision of the current capability block as 1h. PCI Express Extended Register Offset: 152h Register type:Read-Only Default value: 0001h Table 5-18. Next Capability Offset/Capability Version Register Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Copyright (c) 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 73 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 5.13 Device Serial Number Register This read-only register identifies the Device Serial Number for the TUSB73x0. The Device Serial Number is in the format of an IEEE defined 64-bit extended unique identifier (EUI-64). The EUI-64 consists of TI's 24-bit company ID (called an OUI-24) plus a 40 bit extension identifier. TI's OUI-24 is 080028h and is hardwired into bits 63:40 of the Device Serial Number Register. The TUSB73x0 has been assigned the range of 00 0000 0000h to 00 0FFF FFFFh for the 40-bit extension identifier. As such, bits 39:32 of the Device Serial Number Register are hardwired to 00h, and bits 31:0 of the Device Serial Number Register are defined by a value unique for each device. PCI Express Extended Register Offset: 154h Register type:Read-Only Default value: 0800 2800 XXXX XXXX h Table 5-19. Device Serial Number Register Bit No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Reset State 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit No. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reset State 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State X X X X X X X X X X X X X X X X Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State X X X X X X X X X X X X X X X X Table 5-20. Bit Descriptions - Device Serial Number Register (1) Bit (1) 74 Field Name Access Description 63:32 SERIAL_NUM_UPPER r Serial Number - Upper DW. The upper DW of the Serial Number is hardwired to 0800 2800h. 31:0 SERIAL_NUM_LOWER r Serial Number - Lower DW. The lower DW of the Serial Number is unique for each device. Bits marked with are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset PCI EXPRESS EXTENDED CONFIGURATION SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6 xHCI MEMORY MAPPED REGISTER SPACE 6.1 The xHCI Register Map The TUSB73X0 includes xHCI registers in memory mapped register space. These registers are accessible via the address programmed into the Base Address Register 0/1. All bits marked with a `*' are sticky bits and are only reset by a Global Reset (GRST#). Table 6-1. xHCI Register Map 6.2 Register Name Offset Host Controller Capability Registers 000h-01Fh Host Controller Operational Registers 020h-49Fh Runtime Registers 4A0h-5BFh Doorbell Registers 5C0h-6C3h Reserved 6C4-9BFh xHCI Extended Capabilities Registers 9C0h-9EBh Reserved 9ECh-FFFFFh Host Controller Capability Registers These registers specify the limits and capabilities of the TUSB7340. The offset in then table is from the address programmed into the Base Address Register 0. Table 6-2. Host Controller Capability Register Map Register Name HC Interface Version Offset Reserved Capability Length 00h HC Structural Parameters 1 6.2.1 04h HC Structural Parameters 2 08h HC Structural Parameters 3 0Ch HC Capability Parameters 10h Doorbell Offset 14h Runtime Register Space Offset 18h Reserved 1Ch-1Fh Capability Registers Length This read only register returns 20h when read to indicate that the beginning of the Operational Register Space is at an offset of 20h from the address programmed into the Base Address Register 0. BAR0 register offset: 00h Register type:Read-Only Default value: 0020h Table 6-3. HC Capability Register 00h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 75 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 6.2.2 www.ti.com Host Controller Interface Version Number This read only register indicates the xHCI specification revision number supported by the TUSB73X0. BAR0 register offset: 02h Register type:Read-Only Default value: 0096h Table 6-4. HC Capability Register 02h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 6.2.3 Host Controller Structural Parameters 1 This read only register defines basic structural parameters supported by the TUSB73X0. BAR0 register offset: 04h Register type:Read-Only Default value: 0800 0840h Table 6-5. HC Capability Register 04h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 Table 6-6. HC Structural Parameters 1 Description 76 Bit Field Name Access Description 31:24 MAX_PORTS r Number of Ports. For the TUSB7340, this field is 08h to indicate that 8 ports are supported. For the TUSB7320, this field is 04h to indicate that 4 ports are supported. This field also indicates the number of sets of port registers that are addressable in the Operational Register Space. 23:19 RSVD r Reserved. Returns zeros when read. 18:8 MAX_INTRS r Number of Interrupters. This field specifies the number of Interrupters that are implemented. The TUSB73x0 implements 8 Interrupters. Each Interrupter is allocated to a vector of MSI-X. 7:0 MAX_SLOTS r Number of Device Slots. This field specifies the maximum number of Device Context Structures and Doorbell Array entries that are supported. The TUSB73x0 supports 64 Device Slots. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.2.4 Host Controller Structural Parameters 2 This read only register defines basic structural parameters supported by the TUSB73X0. BAR0 register offset: 08h Register type:Read-Only Default value: 0C00 00F1h Table 6-7. HC Capability Register 08h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 Table 6-8. HC Structural Parameters 2 Description Bit Field Name Access Description 31:27 MAX_SCRATCH_BUF r Max Scratchpad Buffers. This field indicates the number of Scratchpad Buffers system software reserves. The TUSB73X0 uses one Scratchpad Buffer. 26 SPR r Scratchpad Restore. This bit is 1b to indicate that the TUSB73X0 requires the integrity of the Scratchpad Buffer space to be maintained across power events. 25:13 RSVD r Reserved. Returns zeros when read. 12:8 IOC_INTERVAL r IOC Interval. This field is 0b. 7:4 ERST_MAX r Event Ring Segment Table Max. This field is 1111b to indicate that the TUSB73X0 supports up to 32K Event Ring Segment Table entries. 3:0 IST r Isochronous Scheduling Threshold. This field is 0001b to indicate that software can add a TRB no later than 1 Microframes before that TRB is scheduled to be executed. 6.2.5 Host Controller Structural Parameters 3 This read only register defines basic structural parameters supported by the TUSB73X0. BAR0 register offset: 0Ch Register type:Read-Only Default value: 07FF 00A0h Table 6-9. HC Capability Register 0Ch Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 77 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-10. HC Structural Parameters 3 Description Bit Field Name Access 31:16 U2_EXIT_LAT r U2 Device Exit Latency. This field is 07FFh to indicate that the worst case latency for the TUSB73X0 to transition from U2 to U0 is 2047 s. 15:8 RSVD r Reserved. Returns zeros when read. 7:0 U1_EXIT_LAT r U1 Device Exit Latency. This field is 0Ah to indicate that the worst case latency for the TUSB73X0 to transition a root hub Port Link State from U1 to U0 is 10 s. 6.2.6 Description Host Controller Capability Parameters This read only register defines capability parameters supported by the TUSB73X0. BAR0 register offset: 10h Register type:Read-Only Default value: 0270 102Xh Table 6-11. HC Capability Register 10h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 1 1 1 1 0 0 0 0 0 1 1 0 x 1 0 1 Table 6-12. HC Capability Parameters Description 78 Bit Field Name Access Description 31:16 XECP r xHCI Extended Capabilities Pointer. This field is 0270h to indicate that the beginning of the first xHCI Extended Capability is at an offset of 09C0h from the address programmed into the Base Address Register 0. 15:12 MAX_PSA_SIZE r Maximum Primary Stream Array Size. This field is `1111' to indicate that the TUSB73X0 supports a Primary Stream Array size of 64K. 11:10 RSVD r Reserved. Returns zeros when read. 9 SBD r Secondary Bandwidth Domain Reporting. This bit is `0' to indicate that the TUSB73X0 does not support Secondary Bandwidth Domain reporting. 8 FSE r Force Stopped Event. This bit is `0' to indicate that theTUSB73X0 does not support Force Stopped Events. 7 NSS r No Secondary SID Support. This bit is `0' to indicate that the TUSB73X0 supports Secondary Stream ID decoding. 6 LTC r Latency Tolerance Messaging Capability. This bit is `1' to indicate that the TUSB73X0 supports Latency Tolerance Messaging. 5 LHRC r Light HC Reset Capability. This bit is `1' to indicate that the TUSB73X0 supports Light Host Controller Resets. 4 PIND r Port Indicators. This bit is `0' to indicate that the TUSB73X0 does not support port indicators. 3 PPC r Port Power Control. This value of this bit is determined by the PPC_NOT_PRESENT bit in the USB Control Register. 2 CSZ r Context Size. This bit is `1' to indicate that the TUSB73X0 uses 64 byte Context data structures. 1 BNC r Bandwidth Negotiation Capability. This bit is `0' to indicate that the TUSB73X0 does not implement Bandwidth Negotiation. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-12. HC Capability Parameters Description (continued) 0 6.2.7 AC64 64-bit Addressing Capability. This bit is `1' to indicate that the TUSB73X0 implements 64-bit address memory pointers. r Doorbell Offset This read only register returns 0000 05C0h when read to indicate that the beginning of the Doorbell Array is at an offset of 5C0h from the address programmed into the Base Address Register 0. BAR0 register offset: 14h Register type:Read-Only Default value: 0000 05C0h Table 6-13. HC Capability Register 14h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 6.2.8 Runtime Register Space Offset This read only register returns 0000 04A0h when read to indicate that the beginning of the Runtime Register Space is at an offset of 4A0h from the address programmed into the Base Address Register 0. BAR0 register offset: 18h Register type:Read-Only Default value: 0000 04A0h Table 6-14. HC Capability Register 18h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 79 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 6.3 www.ti.com Host Controller Operational Registers These registers control the operation of the TUSB73X0. The offset in Table 6-15 is from the Operational Base, which is the address programmed into the Base Address Register 0 plus the value programmed into the Capability Registers Length (see Section 6.2.1). Table 6-15. Host Controller Operational Register Map 6.3.1 Register Name Offset USB Command 00h USB Status 04h Page Size 08h Reserved 0Ch-13h Device Notification Control 14h Command Ring Control 18h-1Fh Reserved 20h-2Fh Device Context Base Address Array Pointer 30h-37h Configure 38h Reserved 3Ch-3FFh Port Register Set 1-8 400h-47Fh USB Command Register This register indicates the command to be executed by the TUSB73X0. Operational Base register offset:00h Register type:Read-Only,Read/Write Default value: 0000 0000h Table 6-16. HC Operational Register (Operational Base + 00h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.3.2 USB Command Register This register indicates the command to be executed by the TUSB73X0. Operational Base register offset:00h Register type:Read-Only,Read/Write Default value: 0000 0000h Table 6-17. HC Operational Register (Operational Base + 00h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-18. USB Command Register Description Bit Field Name Access 31:12 RSVD r 11 EU3S rw Enable U3 MFINDEX Stop 10 EWE rw Enable Wrap Event 9 CRS rw Controller Restore State 8 CSS rw Controller Save State 7 LHCRST rw Light Host Controller Reset 6:4 RSVD r 3 HSEE rw Host System Error Enable 2 INTE rw Interrupter Enable 1 HCRST rw Host Controller Reset 0 R/S rw Run/Stop. 6.3.3 Description Reserved. Returns zeros when read. Reserved. Returns zeros when read. USB Status Register This register indicates pending interrupts and various states of the TUSB73X0. Operational Base register offset:04h Register type:Read-Only, Read/Clear Default value: 0000 0801h Table 6-19. HC Operational Register (Operational Base + 04h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 81 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-20. USB Status Register Description Bit Field Name Access 31:13 RSVD r Reserved. Returns zeros when read. 12 HCE r Host Controller Error 11 CNR r Controller Not Ready 10 SRE rc Save/Restore Error. 9 RSS r Restore State Status. 8 SSS r Save State Status. 7:5 RSVD r Reserved. Returns zeros when read. 4 PCD rc Port Change Detect 3 EINT rc Event Interrupt. 2 HSE rc Host System Error. 1 RSVD r Reserved. Returns zeros when read. 0 HCH r HC Halted. 6.3.4 Description Page Size Register This register indicates the page size supported by the TUSB73X0. Operational Base register offset:08h Register type:Read-Only Default value: 0000 0001h Table 6-21. HC Operational Register (Operational Base + 08h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 6-22. Page Size Register Description 82 Bit Field Name Access Description 31:16 RSVD r Reserved. Returns zeros when read. 15:0 PAGE_SIZE r Page Size. The TUSB73X0 supports a 4k byte page size, so this field is set to 0000 0001h. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.3.5 Device Notification Control Register This register is used by software to enable or disable the reporting of the reception of specific USB Device Notification Transaction Packets. Operational Base register offset:14h Register type:Read-Only, Read/Write Default value: 0000 0000h Table 6-23. HC Operational Register (Operational Base + 14h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-24. Device Notification Control Register Description Bit Field Name Access 31:16 RSVD r 15:0 NOTE_EN rw 6.3.6 Description Reserved. Returns zeros when read. Notification Enable (N0-N15). Command Ring Control Register This 64-bit register provides Command Ring control and status capabilities, and identifies the address and Cycle bit state of the Command Ring Dequeue Pointer. Operational Base register offset:18h Register type:Read-Only, Read/Write Default value: 0000 0000 0000 0000h Table 6-25. HC Operational Register (Operational Base + 18h) Bit No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 83 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-26. Command Ring Control Register Description Bit Field Name Access 31:6 COM_RING_POINT rw 5:4 RSVD r Reserved. Returns zeros when read. 3 CRR r Command Ring Running. 2 CA rw Command Abort. 1 CS rw Command Stop. 0 RCS rw Ring Cycle State. 6.3.7 Description Command Ring Pointer. Device Context Base Address Array Pointer Register This 64-bit register identifies the base address of the Device Context Base Address Array. Operational Base register offset:30h Register type:Read-Only, Read/Write Default value: 0000 0000 0000 0000h Table 6-27. HC Operational Register (Operational Base + 30h) Bit No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-28. Device Context Base Address Array Pointer Register Description 84 Bit Field Name Access 31:6 DCBAAP rw 5:0 RSVD r Description Device Context Base Address Array Pointer. Reserved. Returns zeros when read. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.3.8 Configure Register This register defines runtime xHC configuration parameters. Operational Base register offset:38h Register type:Read-Only, Read/Write Default value: 0000 0000h Table 6-29. HC Operational Register (Operational Base + 38h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-30. Configure Register Description Bit Field Name Access 31:8 RSVD r 7:0 MAX_SLOTS_EN rw 6.3.9 Description Reserved. Returns zeros when read. Max Device Slots Enabled. Port Status and Control Register The TUSB73X0 implements a Port Status and Control Register for each port that is implemented. The number of Port Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see 6.1.3). Operational Base register offset:400h + (10h*(n-1))), where n = Port Number Register type:Read-Only, Read/Write, Read/Clear Default value: X000 02A0h Table 6-31. HC Operational Register (Operational Base + 400h + (10h*(n-1))), where n = Port Number Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 Table 6-32. Port Status and Control Register Description Bit Field Name Access Description 31 WPR * rc or r Warm Port Reset. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved. 30 DR r Device Removable. The value of this bit depends on the value programmed into the USBx_PORTy_NON_REM bit in the USB Control Register that corresponds to the port number and port type associated with this register. 29:28 RSVD r Reserved. Returns zeros when read. 27 WOE * rw Copyright (c) 2011, Texas Instruments Incorporated Wake on Over-current Enable. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 85 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-32. Port Status and Control Register Description (continued) 26 WDE * rw Wake on Disconnect Enable. 25 WCE * rw Wake on Connect Enable. 24 RSVD r 23 CEC * rc or r 22 PLC * rc Port Link State Change. 21 PRC * rc Port Reset Change. 20 OCC * rc Over-current Change. 19 WRC * rc or r 18 PEC * rc Port Enabled/Disabled Change. 17 CSC * rc Connect Status Change. 16 LWS w Port Link State Write Strobe. This bit returns a zero when read. 15:14 PIC * rw Port Indicator Control. Since the TUSB73X0 does not support port indicators, this field has no effect. 13:10 PORT_SPEED * r Port Speed 9 PP * rw Port Power. 8:5 PLS * rw Port Link State 4 PR * rs Port Reset. 3 OCA r Over-current Active. 2 RSVD r Reserved. Returns zero when read. 1 PED * rc Port Enabled/Disabled. 0 CCS * r Current Connect Status. Reserved. Return zero when read. Port Config Error Change. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved. Warm Port Reset Change. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved. 6.3.10 Port PM Status and Control Register (USB 3.0 Ports) The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Section 6.2.3). Operational Base register offset:404h + (10h*(n-1))), where n = Port Number Register type:Read-Only, Read/Write Default value: 0000 0000h Table 6-33. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-34. Port PM Status and Control Register (USB 3.0) Description 86 Bit Field Name Access 31:17 RSVD r Description Reserved. Returns zeros when read. 16 FLA rw Force Link PM Accept. 15:8 U2_TIMEOUT* rw U2 Timeout. 7:0 U1_TIMEOUT* rw U1 Timeout. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.3.11 Port PM Status and Control Register (USB 2.0 Ports) The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Section 6.2.3). Operational Base register offset:404h + (10h*(n-1))), where n = Port Number Register type:Read-Only, Read/Write Default value: 0000 0000h Table 6-35. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-36. Port PM Status and Control Register (USB 2.0) Description Bit Field Name Access 31:28 PORT_TEST_CTRL rw Description Port Test Control. 27:16 RSVD r 15:8 L1_DEV_SLOT rw Reserved. Returns zeros when read. L1 Device Slot. 7:4 HIRD rw Host Initiated Resume Duration. 3 RWE rw Remote Wake Enable. 2:0 L1S r L1 Status. 6.3.12 Port Link Info Register The TUSB73X0 implements a Port Link Info Register for each port USB 3.0 port that is implemented. For USB 2.0 ports, the Port Link Info Register is reserved and returns zeros when read. The number of Port Link Info Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Section 6.2.3). Operational Base register offset:408h + (10h*(n-1))), where n = Port Number Register type:Read-Only Default value: 0000 0000h Table 6-37. HC Operational Register (Operational Base + 408h + (10h*(n-1))), where n = Port Number Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 87 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-38. Port Link Info Register Description Bit Field Name Access 31:16 RSVD r Reserved. Returns zeros when read. 15:0 LINK_ERROR_COUNT r Link Error Count. 6.4 Description Host Controller Runtime Registers These registers are used to read the current microframe and to control the interrupters of the TUSB73X0. The offset in Table 6-39 is from the Runtime Base, which is the address programmed into the Base Address Register 0 plus the value programmed into the Runtime Register Space Offset (see Section 6.2.8). Table 6-39. Host Controller Runtime Register Map Register Name 6.4.1 Offset Microframe Index 00h Reserved 04h-1Fh Interrupter Register Set 0 20h-3Fh Interrupter Register Set 1 40h-5Fh Interrupter Register Set 2 60h-7Fh Interrupter Register Set 3 80h-9Fh Interrupter Register Set 4 A0h-BFh Interrupter Register Set 5 C0h-DFh Interrupter Register Set 6 E0h-FFh Interrupter Register Set 7 100h-11Fh Microframe Index Register This register is used by the system software to determine the current periodic frame. The register value is incremented every 125 microseconds. Runtime Base register offset:00h Register type:Read-Only Default value: 0000 0000h Table 6-40. HC Runtime Register (Runtime Base + 00h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-41. Microframe Index Register Description Bit 88 Field Name Access Description 31:14 RSVD r Reserved. Returns zeros when read. 13:0 MICROFRAME_IDX r Microframe Index. xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 6.4.2 Interrupter Management Register The TUSB73X0 implements 8 Interrupter Management Registers, one for each Interrupter implemented. Runtime Base register offset:20h + (20h*Interrupter), where Interrupter = 0 through 7 Register type:Read-Only,Read/Write Default value: 0000 0000h Table 6-42. HC Runtime Register (Runtime Base + 20h + (20h*Interrupter)), where Interrupter = 0 through 7 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-43. Interrupter Management Register Description Bit Field Name Access 31:2 RSVD r 1 IE rw Interrupt Enable. 0 IP rc Interrupt Pending. 6.4.3 Description Reserved. Returns zeros when read. Interrupter Moderation Register The TUSB73X0 implements 8 Interrupter Moderation Registers, one for each Interrupter implemented. Runtime Base register offset:24h + (20h*Interrupter), where Interrupter = 0 through 7 Register type:Read/Write Default value: 0000 0FA0h Table 6-44. HC Runtime Register (Runtime Base + 24h + (20h*Interrupter)), where Interrupter = 0 through 7 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State X X X X X X X X X X X X X X X X Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 Table 6-45. Interrupter Management Register Description Bit Field Name Access 31:16 IMODC rw Interrupt Moderation Counter. 15:0 IMODI rw Interrupt Moderation Interval. Copyright (c) 2011, Texas Instruments Incorporated Description xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 89 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 6.4.4 www.ti.com Event Ring Segment Table Size Register The TUSB73X0 implements 8 Event Ring Segment Table Size Registers, one for each Interrupter implemented. Runtime Base register offset:28h + (20h*Interrupter), where Interrupter = 0 through 7 Register type:Read-Only,Read/Write Default value: 0000 0000h Table 6-46. HC Runtime Register (Runtime Base + 28h + (20h*Interrupter)), where Interrupter = 0 through 7 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-47. Event Ring Segment Table Size Register Description Bit Field Name Access 31:16 RSVD r 15:0 ERSTS rw 6.4.5 Description Reserved. Returns zeros when read. Event Ring Segment Table Size. Event Ring Segment Table Base Address Register The TUSB73X0 implements 8 Event Ring Segment Table Base Address Registers, one for each Interrupter implemented. Runtime Base register offset:30h + (20h*Interrupter), where Interrupter = 0 through 7 Register type:Read-Only,Read/Write Default value: 0000 0000 0000 0000h Table 6-48. HC Runtime Register (Runtime Base + 30h + (20h*Interrupter)), where Interrupter = 0 through 7 Bit No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-49. Event Ring Segment Table Base Address Register Description Bit Field Name Access 63:4 ERST_BASE rw 3:0 RSVD r 6.4.6 Description Event Ring Segment Table Base Address. Reserved. Returns zeros when read. Event Ring Dequeue Pointer Register The TUSB73X0 implements 8 Event Ring Dequeue Pointer Registers, one for each Interrupter implemented. Runtime Base register offset:38h + (20h*Interrupter), where Interrupter = 0 through 7 Register type:Read/Write, Read/Clear Default value: 0000 0000 0000 0000h Table 6-50. HC Runtime Register (Runtime Base + 38h + (20h*Interrupter)), where Interrupter = 0 through 7 Bit No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-51. Event Ring Dequeue Pointer Register Description Bit Field Name Access 64:4 ERDP rw Event Ring Dequeue Pointer. 3 EHB rc Event Handler Busy. 2:0 DESI rw Dequeue ERST Segment Index. Copyright (c) 2011, Texas Instruments Incorporated Description xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 91 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 6.5 www.ti.com Host Controller Doorbell Registers The TUSB73X0 supports an array of 65 Doorbell Registers, one for the host controller plus one for each Device Slot supported. The address of the first Doorbell Register is the address programmed into the Base Address Register 0 plus the value programmed into the Doorbell Offset (see Section 6.2.7). Doorbell Base register offset:00h + (04h*Device Slot), where Device Slot = 0 through 64 Register type:Read-Only, Read/Write Default value: 0000 0000h Table 6-52. HC Doorbell Register (Doorbell Base + (04h*Device Slot)), where Device Slot = 0 through 64 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-53. Interrupter Management Register Description Bit Field Name Access 31:16 DB_STREAM_ID rw 15:8 RSVD r 7:0 DB_TARGET rw 6.6 Description Doorbell Stream ID. This field returns zeros when read. Reserved. Returns zeros when read. Doorbell Target. This field returns zeros when read. xHCI Extended Capabilities Registers These registers are used for the xHCI Extended Capabilities in the TUSB73X0. The offset in Table 6-54 is from the xHCI Extended Capabilities Base, which is the address programmed into the Base Address Register 0 plus the value programmed into the xHCI Extended Capabilities Pointer field in the Host Controller Capability Parameters (see Section 6.2.6). Table 6-54. xHCI Extended Capabilities Register Map 6.6.1 Register Name Offset Legacy Support Capability 00h-07h Reserved 08h-0Fh xHCI Supported Protocol Capability (USB 2.0) 10h-1Bh Reserved 1Ch-1Fh xHCI Supported Protocol Capability (USB 3.0) 20h-2Bh USB Legacy Support Capability Register This register is used to coordinate the ownership of the host controller between BIOS and the operating system. xHCI Extended Capabilities Base register offset:00h Register type:Read-Only, Read/Write Default value: 0000 0201h 92 xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-55. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 00h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 Table 6-56. USB Legacy Support Capability Register Description Bit Field Name Access Description 31:25 RSVD r 24 HC_OS_SEMA rw 23:17 RSVD r 16 HC_BIOS_SEMA rw 15:8 NEXT_CAP r Next Capability Pointer. This field is 04h, indicating that the xHCI Supported Protocol Capability for USB 2.0 starts at offset 10h from the xHCI Extended Capabilities Base. 7:0 CAPABILITY_ID r Capability ID. This field is 01h, identifying this capability as a USB Legacy Support Capability. 6.6.2 Reserved. Returns zeros when read. HC OS Owned Semaphore. Reserved. Returns zeros when read. HC BIOS Owned Semaphore. USB Legacy Support Control/Status Register This register is used by BIOS software to enable System Management Interrupts. xHCI Extended Capabilities Base register offset:04h Register type:Read-Only, Read/Clear Default value: 0000 0000h Table 6-57. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 04h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6-58. USB Legacy Support Control/Status Register Description Bit Field Name Access 31 SMI_BAR rc SMI on BAR. 30 SMI_PCI_COM rc SMI on PCI Command. 29 SMI_OS_CHANGE rc SMI on OS Ownership Change. 28:21 RSVD r Reserved. Returns zeros when read. 20 SMI_HOST_SYS_ERR r SMI on Host System Error. 19:17 RSVD r Reserved. Returns zeros when read. 16 SMI_EVENT_INT r SMI on Event Interrupt. 15 SMI_BAR_EN rw SMI on BAR Enable. 14 SMI_PCI_COM_EN rw SMI on PCI Command Enable. Copyright (c) 2011, Texas Instruments Incorporated Description xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 93 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-58. USB Legacy Support Control/Status Register Description (continued) 13 SMI_OS_EN rw 12:5 RSVD r 4 SMI_HOST_SYS_ERR_EN rw 3:1 RSVD r 0 USB_SMI_EN rw 6.6.3 SMI on OS Ownership Enable. Reserved. Returns zeros when read. SMI on Host System Error Enable. Reserved. Returns zeros when read. USB SMI Enable. xHCI Supported Protocol Capability Register (USB 2.0) This register indicates that the Supported Protocol Capability is for USB 2.0. xHCI Extended Capabilities Base register offset:10h Register type:Read-Only Default value: 0200 0402h Table 6-59. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 10h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Table 6-60. xHCI Supported Protocol Capability Register (USB 2.0) Description Bit Field Name Access Description 31:24 MAJOR_REV r Major Revision. This field is 02h, since this Supported Protocol Capability is for release 2.0 of the USB specification. 23:16 MINOR_REV r Minor Revision. This field is 00h, since this Supported Protocol Capability is for release 2.0 of the USB specification. 15:8 NEXT_CAP r Next Capability Pointer. This field is 04h, indicating that the xHCI Supported Protocol Capability for USB 3.0 starts at offset 20h from the xHCI Extended Capabilities Base. 7:0 CAPABILITY_ID r Capability ID. This field is 02h, identifying this capability as a Supported Protocol Capability. 6.6.4 xHCI Supported Protocol Name String Register (USB 2.0) This read only register is set to 2042 5355h, indicating that the Supported Protocol Capability is for USB 2.0. xHCI Extended Capabilities Base register offset:14h Register type:Read-Only Default value: 2042 5355h 94 xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-61. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 14h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 6.6.5 xHCI Supported Protocol Port Register (USB 2.0) This register indicates how many USB 2.0 ports are supported and what their port numbers are. xHCI Extended Capabilities Base register offset:18h Register type:Read-Only Default value: 0001 0X01h Table 6-62. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 18h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 1 Table 6-63. xHCI Supported Protocol Capability Register (USB 2.0) Description Bit Field Name Access 31:19 RSVD r Reserved. Returns zeros when read. 18 IHI r Integrated Hub Implemented. This field is `0' to indicate that the root hub to external port mapping adheres to the default mapping in the xHCI Specification. 17 HSO r High-speed Only. This field is `0' to indicate that the USB 2.0 ports are Low-, Full-, and High-speed capable. 16 L1C r L1 Capability. This field is `1' to indicate that the TUSB73X0 supports the USB 2.0 Link Power Management L1 state. 15:8 COMPATIBLE_PORT_CNT r Compatible Port Count. For the TUSB7340 , this field is 04h to indicate that four USB 2.0 ports are supported. For the TUSB7320, this field is 02h to indicate that two USB 2.0 ports are supported. 7:0 COMPATIBLE_PORT_OFF r Compatible Port Offset. This field is 01h to indicate that the first USB 2.0 port is port 1. 6.6.6 Description xHCI Supported Protocol Capability Register (USB 3.0) This register indicates that the Supported Protocol Capability is for USB 3.0. xHCI Extended Capabilities Base register offset:20h Register type:Read-Only Default value: 0300 0002h Copyright (c) 2011, Texas Instruments Incorporated xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 95 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-64. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 20h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 6-65. xHCI Supported Protocol Capability Register (USB 3.0) Description Bit Field Name Access Description 31:24 MAJOR_REV r Major Revision. This field is 03h, since this Supported Protocol Capability is for release 3.0 of the USB specification. 23:16 MINOR_REV r Minor Revision. This field is 00h, since this Supported Protocol Capability is for release 3.0 of the USB specification. 15:8 NEXT_CAP r Next Capability Pointer. This field is 00h, indicating that this is the last capability. 7:0 CAPABILITY_ID r Capability ID. This field is 02h, identifying this capability as a Supported Protocol Capability. 6.6.7 xHCI Supported Protocol Name String Register (USB 3.0) This read only register is set to 2042 5355h, indicating that the Supported Protocol Capability is for USB 3.0. xHCI Extended Capabilities Base register offset:24h Register type:Read-Only Default value: 2042 5355h Table 6-66. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 24h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 6.6.8 xHCI Supported Protocol Port Register (USB 3.0) This register indicates how many USB 3.0 ports are supported and what their port numbers are. xHCI Extended Capabilities Base register offset:28h Register type:Read-Only Default value: 0000 0X0Xh 96 xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com Table 6-67. xHCI Extended Capabilities Register (xHCI Extended Capabilities Base + 28h) Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 x x 0 0 0 0 0 0 x x 1 Table 6-68. xHCI Supported Protocol Capability Register (USB 3.0) Description Bit Field Name Access 31:19 RSVD r Reserved. Returns zeros when read. 18 IHI r Integrated Hub Implemented. This field is `0' to indicate that the root hub to external port mapping adheres to the default mapping in the xHCI Specification. 17 HSO r High-speed Only. This field is not applicable to USB 3.0 and is `0'. 16 L1C r L1 Capability. This field is not applicable to USB 3.0 and is `0'. 15:8 COMPATIBLE_PORT_CNT r Compatible Port Count. For the TUSB7340 , this field is 04h to indicate that four USB 3.0 ports are supported. For the TUSB7320, this field is 02h to indicate that two USB 3.0 ports are supported. 7:0 COMPATIBLE_PORT_OFF r Compatible Port Offset. For the TUSB7340 , this field is 05h to indicate that the first USB 3.0 port is port 5. For the TUSB7320, this field is 03h to indicate that the first USB 3.0 port is port 3. Copyright (c) 2011, Texas Instruments Incorporated Description xHCI MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 97 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 7 MSI-X MEMORY MAPPED REGISTER SPACE 7.1 The MSI-X Table and PBA in Memory Mapped Register Space The TUSB73X0 includes the MSI-X Table and PBA in memory mapped register space. These registers are accessible via the address programmed into the Base Address Register 2/3. Table 7-1. MSI-X Table and PBA Register Map Register Name Offset Entry 0 Message Address 0000h Entry 0 Message Upper Address 0004h Entry 0 Message Data 0008h Entry 0 Vector Control 000Ch Entry 1 Message Address 0010h Entry 1 Message Upper Address 0014h Entry 1 Message Data 0018h Entry 1 Vector Control 001Ch Entry 2 Message Address 0020h Entry 2 Message Upper Address 0024h Entry 2 Message Data 0028h Entry 2 Vector Control 002Ch Entry 3 Message Address 0030h Entry 3 Message Upper Address 0034h Entry 3 Message Data 0038h Entry 3 Vector Control 003Ch Entry 4 Message Address 0040h Entry 4 Message Upper Address 0044h Entry 4 Message Data 0048h Entry 4 Vector Control 004Ch Entry 5 Message Address 0050h Entry 5 Message Upper Address 0054h Entry 5 Message Data 0058h Entry 5 Vector Control 005Ch Entry 6 Message Address 0060h Entry 6 Message Upper Address 0064h Entry 6 Message Data 0068h Entry 6 Vector Control 006Ch Entry 7 Message Address 0070h Entry 7 Message Upper Address 0074h Entry 7 Message Data 0078h Entry 7 Vector Control 007Ch Reserved 0080h-0FFFh Pending Bits 7 through 0 1000h Reserved 1001h-1FFFh Refer to the PCI Local Bus Specification, Revision 3.0 for descriptions of these registers. 98 MSI-X MEMORY MAPPED REGISTER SPACE Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 8 PHY CONTROL 8.1 Output Voltage Swing Control The output swing of each transmitter can be independently set to one of a number of settings via the SWING bits in the De-Emphasis and Swing Control Register, see Section 4.65. Reducing the output amplitude decreases the current drawn in direct proportion to the reduction in swing, thereby saving power. Table 8-1. Differential Output Swing Swing Value AC-Coupled Amplitude 0000 2.7 0001 147 0010 222 0011 298 0100 373 0101 449 0110 525 0111 600 1000 702 1001 777 1010 853 1011 928 1100 1050 1101 1082 1110 1164 1111 1253 PHY CONTROL Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 99 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 8.2 www.ti.com De-Emphasis Control De-emphasis provides a means to compensate for high frequency attenuation in the attached media. It causes the output amplitude to be smaller for bits which are not preceded by a transition than for bits which are. Fifteen different de-emphasis settings are provided via the PORTx_DE bits in the De-Emphasis and Swing Control Register, see Section 4.65. Table 8-2. Differential Output De-Emphasis Value 8.3 Amplitude Reduction % dB 0000 0 0 0001 5.33 -0.48 0010 9.52 -0.87 0011 13.8 -1.29 0100 18.1 -1.73 0101 22.5 -2.21 0110 27.0 -2.73 0111 31.4 -3.28 1000 36.2 -3.9 1001 40.8 -4.55 1010 45.4 -5.26 1011 50.2 -6.05 1100 55.0 -6.93 1101 59.7 -7.90 1110 64.5 -8.99 1111 69.3 -10.27 Adaptive Equalizer All receive channels in this macro family incorporate an adaptive equalizer, which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal, thereby reducing inter-symbol interference. The equalizer can be configured via the Portx_EQ bits of the Equalizer Control Register, Section 4.66. Table 8-3 summarizes the options, which are: * No adaptive equalization. The equalizer provides a flat response at the maximum gain. This setting may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss. * Fully adaptive equalization. Both the low frequency gain and zero position of the equalizer are determined algorithmically by analyzing the data patterns and transition positions in the received data. FTC refers to the algorithm that controls the zero position. In the FTC normal mode, the zero is decreased in frequency when more equalization is needed; in the FTC reversed mode, the zero is increased in frequency when more equalization is needed. The fully adaptive with FTC reversed setting should be used for most applications. * Hold. The equalizer state is held at its current gain level and zero point. * Initialize. The equalizer is initialized to a mid-point gain level, with the zero set to a frequency appropriate for the receiver data rate. * Partially adaptive equalization. The low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and transition positions in the received data. The zero position is fixed in one of eight zero positions. For any given application, the optimal setting is a function of the loss characteristics of the channel and the spectral density of the signal as well as the data rate, which means it is not possible to identify the best setting by data rate alone, although generally speaking, the lower the line rate, the lower the zero frequency that will be required. 100 PHY CONTROL Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain of the equalizer should be increased or decreased. For the fully adaptive setting (EQ = 0001), if the low frequency gain reaches the minimum value, the zero frequency is then reduced. Likewise, if it reaches the maximum value, the zero frequency is then increased. The decision logic is implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable response of the channel. Table 8-3. Receiver Equalizer Configuration EQ Value 0000 Amplitude Reduction Low Frequency Gain Zero Frequency Maximum - 0001 Fully Adaptive, FTC Normal 0010 Fully Adaptive, FTC Reversed 0011 Hold 0100 0101 Initialize 0110 0111 1000 365 MHz 1001 275 MHz 1010 195 MHz 1011 1100 Partially Adaptive 140 MHz 105 MHz 1101 75 MHz 1110 55 MHz 1111 50 MHz PHY CONTROL Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 101 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 9 INPUT CLOCK 9.1 Clock Source Requirements The TUSB73x0 supports an external oscillator source or a crystal unit. The frequency of the clock source may be 20 MHz - 50 MHz. The FREQSEL pin is used to indicate the oscillator input frequency. If the FREQSEL pin is pulled low, the oscillator input frequency is 48 MHz. If the FREQSEL pin is pulled high, the value in the PLL_FREQ_SEL field controls the selected frequency. After the PLL_FREQ_SEL field is set appropriately the FREQ_SEL_EN bit should be set. When the FREQ_SEL_EN bit is set high, the oscillator is restarted with the PLL multiplier value and the oscillator frequency controls set according to the value specified in the PLL_FREQ_SEL field. The register values may be programmed via EEPROM or PCI Express access; refer to Table 4-100. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance between XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a crystal. Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value of the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2. Figure 9-1. Oscillation Circuit 102 INPUT CLOCK Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 9.2 External clock When using an external clock source, the reference clock should have a 100 PPM or better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the clock source and XO should be left floating. The input clock must be 1.8-V LVCMOS; this input is not 3.3-V tolerant. When AUX_DET is high and the TUSB73x0 is in D3cold the TUSB73x0 utilizes an internal ring oscillator to support wake from D3cold eliminating the need to keep the external clock active while in D3cold. Table 9-1. Input Clock Specification PARAMETER CONDITION Frequency Tolerance MAX UNIT Operational Temperature 50 ppm 1 year aging 100 ppm 20% - 80% 6 ns Frequency Stability Rise / Fall Time MIN TYP Reference Clock RJ with JTF (1 sigma) (1) (2) 0.8 ps Reference Clock TJ with JTF (total p-p) (2) (3) 25 ps Reference Clock Jitter (absolute p-p) (4) 50 ps (1) (2) (3) (4) Sigma value assuming Gaussian distribution. After application of JTF. Calculated as 14.1 x RJ+DJ Absolute phase jitter (p-p) Table 9-2. Input Clock 1.8-V DC Characteristics PARAMETER CONDITION MIN VIH High-level input voltage 0.65 VDDS VIL Low-level input voltage VOH VOL 9.3 TYP MAX UNIT V 0.35 VDDS IO = -2 mA, VDDS = 1.62 to 1.98 V, driver enabled, pullup or pulldown disabled VDDS-0.45 IO = -2 mA, VDDS = 1.4 to 1.6 V, driver enabled, pullup or pulldown disabled 0.75 VDDS V V IO = 2 mA, driver enabled, VDDS = 1.62 to 1.98 V, pullup or pulldown disabled 0.45 IO = 2 mA, VDDS = 1.4 to 1.6 V, driver enabled, pullup or pulldown disabled 0.25 VDDS V External crystal An external 1-M feedback resistor is required between XI and XO when using a crystal. See the table below for additional crystal specifications. Table 9-3. Crystal Specification PARAMETER Frequency Tolerance CONDITION MIN Operational Temperature Frequency Stability Load Capacitance 1 year aging 12 ESR TYP MAX UNIT 50 ppm 100 ppm 24 pF 50 INPUT CLOCK Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 103 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 10 www.ti.com PCI EXPRESS POWER MANAGEMENT 10.1 Power Management PCI power management (PM) features include active-state link PM, PME mechanisms, and all conventional PCI D states. If the active-state link PM is enabled, the link automatically saves power when idle using the L0s and L1 states. 10.2 PCI Express Link Power Management States PCI Express defines Link power management states, replacing the bus power management states that were defined by the PCI Bus Power Management Interface Specification. Link states are not visible to PCI-PM legacy compatible software, and are either derived from the power management D-states of the corresponding components connected to that Link or by ASPM protocols. Table 10-1. PCI Express Link Power Management States Link States Description L0 Active state. All PCI Express transactions and other operations are enabled. L0s A low resume latency, energy saving "standby" state. L1 Higher latency, lower power "standby" state. L2 Auxiliary-powered Link, deep-energy-saving state. L3 Link Off state. When no power is present, the component is in the L3 state. Link States Description L0 Fully active L0s Standby L1 Low power standby PM SW Directed Ref Clk Vaux Yes (D0) On On/Off No On On/Off Yes (D1-D3hot) On On/Off Staging for power removal Yes On On/Off L2 Low power sleep Yes Off On L3 No power N/A Off Off L2/L3 Ready 10.3 PCI Express Power Management D-States PCI Express supports all PCI-PM device power management states. The TUSB73x0 supports the D0, D1, D2, and D3 states (both D3hot and D3cold). Table 10-2. PCI Express Power Management D-States 104 Power Management States Description D0 Normal operation state. The device is completely active and responsive in this state. The link may be L0 or L0s. D1 Light sleep state. I Configuration and message requests are accepted. Intermediate state intended to provide some power savings but yields a quicker restore time. The link state is L1. D2 Deep sleep state. Configuration and message requests are accepted. Intermediate state intended to provide some power savings but yields a quicker restore time. The link state is L1. D3hot Disabled State. Configuration and message requests are accepted. Link state should be L1, PERST# is deasserted, and reference clock active depending on state of CLKREQ#. D3cold Power-off state. Link state should be L2. PERST# is active and no reference clock is present. PCI EXPRESS POWER MANAGEMENT Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 Copyright (c) 2011, Texas Instruments Incorporated TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 10.4 Power Management Event (PME) Power Management Events are generated by Functions as a means of requesting a PM state change. Power Management Events are typically utilized to revive the system or an individual Function from a low power state. Before using any wakeup mechanism, a Function must be enabled by software to do so by setting the PME_EN bit in the PMCSR, see Section 4.25. The PME_Status bit is sticky, and the value of the PME_Status bit is maintained through reset if aux power is available and the device is enabled for wakeup events. 10.4.1 PME Support The 5-bit PME_support field in the PMC (Power Management Capabilities) register, Section 4.24, indicates the power states in which the TUSB73X0 may send a PME Message. A value of 0b for any bit indicates that it is not capable of sending PME Message while in that power state. Note that the default value of the Bit15 of the PME_support for D3cold is "HwInit" and depends on the AUX_DET pin strapping. If the AUX_DET is pulled high, bit 15 set to 1b. Table 10-3. PME Support Pin Name Support Wake from D3cold/D3hot 3.3V 1.1V Power rails must be maintained to support D3cold and D3hot states. AUX_DET Support Wake from D3hot only Power rails must be maintained to support D3hot states, but may be removed for D3cold. Pulled high.When AUXDET is pulled high, bit 15 of the Pulled low. When AUXDET is pulled low, bit 15 of the Power Management Capabilities register is set to 1b. Power Management Capabilities register is cleared, or 0b. GRST# Must not be asserted during D3cold and D3hot states for WAKE# to function correctly. Should be asserted if power rails fall below specified operating conditions. Must not be asserted during D3hot state, but should assert if power rails fall below specified operating conditions. WAKE# Connected to WAKE# of the system chipset and is pulled high on the system board. WAKE# is used for wakeup from D3cold. In band PME message is used for wakeup from D3hot. WAKE# is not used. In band PME message is used for wakeup from D3hot. CLKREQ# Connected to CLKREQ# of the system chipset and is pulled high. Connected to CLKREQ# of the system chipset and is pulled high. OVERCUR(X:1)# Must remain pulled high during D3cold and D3hot states. Should not be pulled high if power is removed. Must remain pulled high during D3hot state. Should not be pulled high if power is removed. If an EEPROM is used for configuration, power should also be maintained during D3cold and D3hot states. The assertion of PERST# transitions the TUSB7340 from D3hot to D3cold. PERST# must be asserted if the power rails fall below the specified operation conditions. Copyright (c) 2011, Texas Instruments Incorporated PCI EXPRESS POWER MANAGEMENT Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 105 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 11 www.ti.com ELECTRICAL CHARACTERISTICS See the PCIe and USB specifications refered to in Section 2.2 for the electrical characteristics of those interfaces. 11.1 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT -0.5 to 3.6 V -0.5 to 3.6 V -0.3 to 1.4 V PCI Express (RX) 0 to 1.2 V PCI Express REFCLK (single-ended) -0.5 to VDD33 + 0.5 V VDD33 VDDA_3P3 Supply voltage range VDD11 VI Input voltage range VO Output voltage range HBM Human-Body ESD Rating VESD -0.3 to 1.15 V -0.5 to VDD33 + 0.5 V PCI Express (TX) 0.8 to 1.2 V Miscellaneous 3.3 V IO -0.5 to VDD33 + 0.5 V R = 1.5 k, C = 100 pF 2000 Charged-Device Model ESD Rating Tstg (1) REFCLK (differential) Miscellaneous 3.3 V IO V 500 Storage temperature range C -65 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 11.2 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD33 VDDA_3P3 Supply voltage range VDD11 (1) MIN NOM MAX 3 3.3 3.6 3 3.3 3.6 0.99 1.1 UNIT V 1.21 V TA Operating free-air temperature range 0 70 C TJ Operating junction temperature range -40 105 C (1) 106 A 1.05-V supply may be used as long as minimum supply conditions are met. ELECTRICAL CHARACTERISTICS Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 11.3 THERMAL INFORMATION RKM THERMAL METRIC JA Junction-to-ambient thermal resistance (1) JCtop Junction-to-case (top) thermal resistance (2) 9.5 JB Junction-to-board thermal resistance (3) 15.2 JT Junction-to-top characterization parameter (4) 0.1 JB Junction-to-board characterization parameter (5) 7.5 JCbot Junction-to-case (bottom) thermal resistance (6) 0.4 (1) (2) (3) (4) (5) (6) UNITS 100 PINS 25.6 C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 11.4 3.3-V I/O ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) VIH PARAMETER OPERATION High-level input voltage (1) VDD33 TEST CONDITIONS MIN MAX UNIT 2 VDD33 V 0 0.8 0 0.55 VIL Low-level input voltage (1) VI Input voltage 0 VDD33 V VO Output voltage (2) 0 VDD33 V tt Input transition time (trise and tfall) 0 25 ns Vhys Input hysteresis (3) 0.13 VDD33 V VOH High-level output voltage VDD33 VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V IOZ High-impedance, output current (2) VDD33 VI = 0 to VDD33 20 A IOZP High-impedance, output current with internal pullup or pulldown resistor (4) VDD33 VI = 0 to VDD33 225 A II Input current (5) VDD33 VI = 0 to VDD33 15 A (1) (2) (3) (4) (5) VDD33 JTAG pins only IOH = -4 mA 2.4 V V Applies to external inputs and bidirectional buffers. Applies to external outputs and bidirectional buffers. Applies to PERST, GRST, and PME. Applies to GRST (pullup) and most GPIO (pullup). Applies to external input buffers. ELECTRICAL CHARACTERISTICS Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 107 TUSB7320, TUSB7340 SLLSE76E - MARCH 2011 - REVISED JULY 2011 www.ti.com 11.5 POWER CONSUMPTION FOR TUSB7320 (1) (2) over operating free-air temperature range (unless otherwise noted) PARAMETER VDD11 VDD33 UNIT P2SS 2 Devices connected SuperSpeed transfer 507 112 mA P1SS 1 Device connected SuperSpeed transfer 392 112 mA PD0 PCI D0 - No device connnected 156 40 mA PD3 PCI D3 - No device connnected 56 3.5 mA (1) (2) All 1.1-V power rails connected together. All 3.3-V power rails connected together. 11.6 POWER CONSUMPTION FOR TUSB7340 (1) (2) over operating free-air temperature range (unless otherwise noted) VDD11 VDD33 UNIT P4SS 4 Devices connected SuperSpeed transfer PARAMETER 880 115 mA P3SS 3 Devices connected SuperSpeed transfer 740 115 mA P2SS 2 Devices connected SuperSpeed transfer 597 115 mA P1SS 1 Device connected SuperSpeed transfer 420 115 mA PD0 PCI D0 - No device connnected 168 42 mA PD3 PCI D3 - No device connnected 63 13.2 mA (1) (2) 108 All 1.1-V power rails connected together. All 3.3-V power rails connected together. ELECTRICAL CHARACTERISTICS Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TUSB7320RKMR ACTIVE WQFN RKM 100 3000 Green (RoHS & no Sb/Br) TUSB7320RKMT ACTIVE WQFN RKM 100 250 Green (RoHS & no Sb/Br) TUSB7340RKMR ACTIVE WQFN RKM 100 3000 Green (RoHS & no Sb/Br) TUSB7340RKMT ACTIVE WQFN RKM 100 250 Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR Call TI Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR Call TI Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TUSB7320RKMR WQFN RKM 100 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 TUSB7320RKMT WQFN RKM 100 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 TUSB7340RKMR WQFN RKM 100 3000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 TUSB7340RKMT WQFN RKM 100 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB7320RKMR WQFN RKM 100 3000 346.0 346.0 33.0 TUSB7320RKMT WQFN RKM 100 250 190.5 212.7 31.8 TUSB7340RKMR WQFN RKM 100 3000 346.0 346.0 33.0 TUSB7340RKMT WQFN RKM 100 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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