Preliminary Data Sheet V2.2 - Infineon Technologies

ICs for Communications

PC I I nt er face f or Telephony/Data Appl icat i on s

PITA-2

PSB 4610 Ver sion 2.2

Prel im i nar y Dat a Sheet 01.00 DS 1

For questions on technology, deliv ery and prices please contact the Infineon Technologies Offices

in Germany or the Infi neon Technologies Companies and Representatives worldwide:

see our webpage at http://www.infineon.com

PSB 4610

Revision History: Current Version: 01.00

Previous V ersion: PSB 4610 Version 2.1 (12.99)

Page

(i n previous

Version)

Page

(i n current

Version)

Subjects (major changes since last revision)

181 default value (40h) 1221 0001 changed to 1222 0001

ABM®, AO P®, A RCO FI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EP IC®-1, EPI C ®-S, ELIC®, FAL C®54,

FALC®56, F ALC ®-E1, F ALC ®-LH, IDEC®, IOM®, IO M®-1, IOM®-2, I PAT ®-2 , ISA C®-P, I SAC ®-S, ISAC®-S TE,

ISAC®-P TE , ITAC®, IWE®, M U SAC®-A, OC T AT ®-P, QUAT®-S, SI C AT ®, SICO FI®, SICOFI®-2, SICOFI®-4,

SICOFI®-4µC, SLI C OF I® are regis t ered t radem ark s of I nf ineon T ec hnologies AG.

ACE™, ASM™, ASP™, PO TSWIRE™, QuadF ALC™, SCO UT ™ are t rademark s of Inf ineon T echnologies AG.

dition 0 1.00

P ublis hed by Inf ineon Tec hnologies AG

TR,

B al anstr aß e 73,

81541 M ü n ch en

A ll Rig hts Re ser ve d.

At t ent ion plea se !

As f ar as pat ents or ot her rights of t hird part ies are c onc erned, liabilit y is only as sum ed for c om ponent s , not f or

applicat ions, proc es s es and c ircuit s im plem ent ed w it hin c om ponents or as s em blies .

T he inf ormat ion des c ribes t he t y pe of com ponent and s hall not be c ons idered as ass ured charac t erist ic s .

T erm s of deliv ery and right s t o c hange des ign res erv ed.

Due to technical requirements components may contain dangerous substances. For information on the types in

ques t ion pleas e c ont ac t y our neares t I nfineon T ec hnologies Of f ic e.

I nf ineon T ec hnologies AG is an approved C EC C manuf ac t urer.

Packing

Pleas e us e t he rec y c ling operators k now n to you. W e c an als o help y ou – get in t ouc h with your neares t s ales

of f ic e. By agreem ent w e w ill t ak e pac k ing mat erial bac k , if it is s orted. You m us t bear t he c os ts of t rans port.

For pac king material that is returned t o us unsorted or which we are not obliged to accept , we shall have t o invoic e

you for an y co sts incu rre d.

Com ponents us ed in life- support dev ic es or sy st em s m ust be e xpres sly aut horized for suc h purpos e!

Critical components 1 of t he I nf ineon Tec hnologies AG, may only be used in lif e-support devices or sy stems2 wi th

t he expres s w ritt en approv al of t he I nf ineon T ec hnologies AG.

1 A critica l co mpo ne nt is a co mpo ne nt used i n a life- supp or t de vice or system wh ose fail ure ca n re ason ab ly b e

ex pec t ed t o c aus e t he f ailure of t hat lif e-s upport dev ic e or sy s t em, or to aff ect its s af et y or eff ec tiv eness of t hat

de vice or system.

2 Life su ppo rt devi ce s o r syste ms a re i nten ded (a) to b e imp lan te d in the human b ody, or (b ) to sup por t a nd/o r

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-

dangered.

PSB 4610

Preliminary Data Sheet III 01.00

Organizat ion of thi s Data Sheet

•Chap ter 1, Feat ures

Descr ibes t he general feat ures of the PIT A- 2.

•Chap ter 2, Typical Applications with the PITA-2

Des c ribes ty pic al applic ations that c an be r ealiz ed with the PITA -2.

•Chap ter 3, Con stru c ti on of th e PIT A-2

S hows a block diagr am and des c ribes the interfac es and their func tions .

•Chap ter 4, Communicatio n w ith the P IT A-2

Des c ribes the P CI bus inter face of the P ITA- 2.

•Chap ter 5, Communicatio n w ith Ext ern al Co mponen ts

Giv es a general des cription of the loc al bus interfaces of the PITA -2.

•Chapter 6, Power Management

Descr ibes t he power managem ent functions ( inc luding D3cold) of the PIT A- 2.

•Chapt er 7, Reset and Int errupt s

Des c ribes the r equir ement s for r eset and the behaviour of the PIT A-2.

•C ha pt e r 8 , Pi nning

Descr ibes t he pins, types of pins and the charac teristics of the interfaces.

•Chap ter 9, Electrical Characterist ics

Des c ribes elec tr ic al maxim um ratings and elec tr ic al c haracteristic s.

•Chap ter 10, Package O utlines

Des c ribes the pac kage outlines.

•Chapt er 11, Co nfigu rat ion S pace Register of the P IT A- 2

Contains descr iptions of the C onfiguration Space Registers of the PIT A -2.

•Chap ter 12, Internal Register of th e P ITA

Contains descr iptions of the I nternal Registers of the P ITA- 2.

•Chap ter 13, Abbreviatio ns

Des c ribes abbr eviations occur ing in this dat a s heet.

•Chap ter 14, Index

PSB 4610

Preliminary Data Sheet IV 01.00

Im portant Notes about this Data Sheet

________________________________________

Wha t’s New?

The organization of the struc tur e follows the guidelines of Inform ation Mapping®.

________________________________________

What is Information Mapping®?

This is a res ear c h bas ed method for the

– analysis

– structure

– presentation

of us er -orientated manuals.

________________________________________

Major Changes

Instead of the used chapter s with mono caus al desc riptions you now get

– all inform ation

– for a s cope

– under the corres ponding heading.

________________________________________

The Intention

This Data Sheet is intended to be

– easily survey ed

– increas ingly readable

– c ustomized applic able

– practice-orientated

– offering the quic kest poss ible way to the required informat ion.

________________________________________

PSB 4610
Table of  Content s Page
Semiconductor Group  V Preliminary Data Sheet 01.00
1F eatu res   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2Ty pic a l A pplic a tions with t he  PITA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3C ons truc tion of  the PITA-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4Co mmu n ica t io n w ith  the PI T A-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0
.1 PC I C o n fi g u r a t i o n  Sp a ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1
1.1 Inform ation about t he P CI Configur ation Spac e   .  . . .  . . . . . . . . . . . . . . .12
.1 .2 Access  to  th e  PCI C o n fi g u rati o n  Spa ce . . . . . . . . . . . . . . . . . . . . . . . . . .15
.1 .3 Ba s e  Ad d r e ss R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6
1.4 Other  Regis ters  of t he P CI Configur ation Spac e .  . . .  . . . . . . . . . . . . . . .20
.2 PC I M a ste r/Ta rg e t C o n tr o l l e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2
2.1 S upported PCI Commands   . . . . . . . . . . . . . . . . . . . . . .  .  . . . . . . . . .  . . .23
2.2 Trans action Ty pe Bur st Read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
.2 .3 Tr a n sa cti o n  Typ e  Bu rst Wr i te   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7
2.4 Transaction Type Fast Back to Back . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3 Interr upt Contr ol Register - Retry  Counter  . . .  . .  . .  . .  . . .  . . . . . . . . . . . . . .31
5Communicat ion with  External Component s . . . . . . . . . . . . . . . . . . . . . .3 3
.1 Se r i a l D MA In te rfa c e   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .3 4
.1 .1 D MA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
1.2 Infor mation about the DMA  Cont roller . . . . . . . . . . . . . . . . . . . . . . . . .  . .37
.1 .3 In te rn a l Re g i ste rs o f th e  DMA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . .4 1
1.4 IOM-2 Mode 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
1.5 IOM-2 Mode 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.6 IOM-2 Mode 3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
1.7 IOM - 2 M odes -  S upplem entar y  Des cr iption . .  . .  . . .  . .  . . . . . . . . . . . . . .56
1.8 S ingle Modem  M ode V 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
1.9 S ingle Modem  M ode A LIS  V3.X  . . . . . . . . . . . . . . . . . .  .  . . . . . . . . . . . .65
1.10 Dual Modem /M odem+V oice M ode  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .73
1.11 Loop Bac k M ode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .76
.2 Pa r a l le l  In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 8
.2 .1 AL E  a ft e r  Syste m R e se t  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1
2.2 ALE after internal Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3 ALE  after  set ting t he P ar allel Interface M ode Bit .  . .  . .  . . . . . . . . . . . . . .83
2.4 Non Multiplexed Mode ( Write Trans action)  .  . .  . .  . .  . . . . . . . . . . . . . . . .84
2.5 Non Multiplexed Mode ( Read Trans ac tion) . . .  . .  . .  . . . . . . . . . . . . . . . .86
2.6 Multiplexed Mode (Wr ite Transaction) .  . . .  . .  . .  . . .  . .  . . . . . . . . . . . . . .87
2.7 Multiplexed Mode (Read Tr ans act ion)  . .  . . .  . .  . .  . .  . . . . . . . . . . . . . . . .88
2.8 Tr ansaction Disc onnec t with Tar get A bort . .  . .  . . .  . .  . . . . . . . . . . . . . . .89
2.9 Transaction Termination with Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
.2 .1 0 Ti m i n g  o f th e  Pa r a l l e l  I n te r fa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4
3 General Purpose I/O I nterf ace . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .97

PSB 4610
Table of  Content s Page
Semiconductor Group  VI Preliminary Data Sheet 01.00
3.1 Infor mation about the GP I /O  Int erfac e  . . . . . . . . . . . . .  . . . . . .  . . . . . . .98
.3 .2 Ti m i n g  o f th e  GP I/O In t e r fa ce  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0 0
.3 .3 In te rn a l Re g i ste rs o f th e  GP I/O In te rfa ce  . . . . . . . . . . . . . . . . . . . . . . .10 1
3.4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3.5 Output Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .109
3.6 Inter rupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .111
3.7 Usage of the GP  I /O Inter fac e as ALIS V2. 1 Control Inter face  . . . . . . .113
.4 SP I  EEP R O M In te r f a c e  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 5
4.1 Inform ation about t he S PI E E PROM Inter face   . .  . . .  . . . . . . . . . . . . . .116
.4 .2 Ti m i n g  o f th e  SP I  EEPR OM In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 9
.4 .3 In te rn a l Re g i ste rs fo r th e  SP I EE PROM Inte rfa ce  . . . . . . . . . . . . . . . . .12 1
6Powe r  M a n a ge me nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 3
1 Infor mation about the Power Supply Concept  . . . . . . . . . .  .  . . . . . . . . . . .124
1.1 Inform ation about t he P ower  Management  S tates   .  . .  . . . . . . . . . . . . .126
1.2 Considerations about Power  Cons umpt ion and Repor ting  . . . . . . . . . .128
1.3 Configur ation Spac e Regis ters of the Power  M anagement . . . . . . . . . .131
.1 .4 El e c trica l C h a ra c t e r i stics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 6
.1 .5 D e si g n  H i n ts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 7
1.6 Com patibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .148
7Reset and  Int errupt s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.1 R e se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.2 In te rru p ts   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 2
8Pinning  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 6
9E lectrical Ch aract eristi cs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 6
.1 Ab s o l u te  Ma ximu m R a ti n g s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 7
.2 D C C h a r a cte ri sti cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 8
P ackage O ut lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 2
Conf iguration Sp ace Regist er o f the PITA- 2 . . . . . . . . . . . . . . . . . . . . .1 7 3
1 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 4
1 .2 C o n fi g u r a ti o n  Sp a c e  R e g i ste rs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .185
Int ernal Regist er of  th e P ITA   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 3
2 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 4
2 .2 In te rn a l R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .202
Ab b reviatio ns  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 5
I n dex  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 6

PSB 4610

Preliminary Data Sheet 1 01.00

Introduction

________________________________________

What is the PITA-2?

The PITA-2 is a cost-effective PCI bridge for industrial and communication

applications. I t support s dual cards and D3cold power m anagement.

________________________________________

The PITA-2 can b e used in

•PCI ISDN cards.

•P CI hardware modem s.

•P CI software m odem s.

•Industrial PCI bridge applicat ions.

________________________________________

Inter faces of t he PITA-2

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

P CI Mast er/Tar get Controller see chapter 4. 2 on page 22

Ser ial DM A Int erf ac e s ee chapter 5.1 on page 34

P arallel Int erfac e see chapter 5. 2 on page 78

PSB 4610

Preliminary Data Sheet 2 01.00

Gener al Purpos e I/O Interfac e s ee chapter 5.3 on page 97

SP I EEP ROM Int er face s ee chapter 5.4 on page 115

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

PSB 4610

Features

Preliminary Data Sheet 3 01.00

1 Features

________________________________________

Comp lia nt with

•P C 99 (P CI r equir ement s)

•PCI B us Specific ation Version 2.2

•PCI P ower Managem ent Specific ation V ersion 1.1

________________________________________

Highlights

•Dual Car d suppor t (3.3V and 5V signaling environment )

•E xtensive Power Management Feat ures ( including D3c old)

•Automatic Configuration with Customer Specific V alues

________________________________________

Interfaces

•P CI Master Target Interface

–PCI 2.2 compliant

–32 bit

–33 MHz

•Ser ial Int erfac e

–Suppor ts IO M -2 M odes

–S upports s er ial inter face to the ALIS chip- set fam ily

–DMA Control le r for seri al communica ti on

–16 word F IF Os for each dir ection

•Para llel Inte rface

with chip select logic s upport ing up to t hree ex ter nal com ponents

•General P urpose I/ O Interface

with interr upt capability

•SPITM Interface

for optional E EP ROM

________________________________________

PSB 4610

Features

Preliminary Data Sheet 4 01.00

________________________________________

Compatibility

•ALI S V2.1 P SB 4596

•ALI S V3.X PSB 4596

•IS DN IOM -2 Component s , e.g.:

–IEC-Q famil y

–S BCX, SB CX- X

•Com ponents consis ting of a parallel multiplexed or non m ultiplex ed Intel/

Infineon Inter fac e, e.g:

–IPA C , IPAC -X

–ISAC-S, I SAC-SX, ISAC-SX TE

________________________________________

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 5 01.00

2 Typical Applications with the PITA-2

________________________________________

Overview

Besides all the applications that require only a simple PCI interface there are

s ome applic ations which the PITA -2 is es pec ially suited for.

Simple applications benefit from the easy configuration of the PITA-2, the

ext ensive power managem ent support and the st andar d interfaces on the loc al

bus side.

Telecommunication applications (e.g modems) benefit from the integrated

mas ter DMA controller as well as the IOM- 2/GCI bus interface.

This allows for easy connection of most telecommunications transceivers and

subs tant ially reduces t he CPU work load.

Fur therm or e the PIT A-2 fully suppor ts D3c old state.

This allows the PC to enter a deep sleep state and still be able to react to an

inc oming c all at the same time.

________________________________________

ISDN-S Inte rf ace Ap plicatio n with the IPAC

PSB 2115

IPAC

PSB 4610

PTA-2

EEPROM

S0-Interface

PC I B u s

u C In terface

SPI

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 6 01.00

________________________________________

IS DN-U Int erface App lication with th e 3PAC and IE C-Q TE

________________________________________

PSB 2113

3PAC

PSB 4610

PTA-2

PC I B u s

uC Interface

EEPROM

SPI

U-Interface

PSB21911

IE C- Q TE

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 7 01.00

3 Construction of the PITA-2

________________________________________

Overview

The PITA-2 provides a Peripheral Component Interconnect (PCI) bus interface

which acts as a bridge between the PCI bus and the different controllers and

interfaces:

•The Parallel Inter face Contr ol s upport s up to three ex ternal devic es .

•The S erial Int erface is cont rolled by the internal DMA Controller; s erial

c omm unic ation uses tr ans mit and r ec eiv e FI FOs .

•The EEP ROM for conf igur ation of the PITA - 2 and cust omer spec ific dat a

storage.

•The Gener al Purpos e I/O Int er face.

________________________________________

Block Diagram of the PITA-2

________________________________________

PITA-2

PCI

Controller

EEPROM

Control

Parallel

Interface

Control

Serial

Interface

Control

DMA

Controller

TX FIFO

RX FI FO

SPI-

Interface

Parallel

Microcontroller

Interface

General

Purpose

Interface

Serial

Interface

PCI-Bus

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 8 01.00

________________________________________

Descrip tion of t he single Blocks

Name provides supports Notes

PCI Bus

Control •a 32 bit inter fac e

at speeds up to

33 MHz

•Bus Master D MA

capabi lity for data

pass ing through

the Serial

Interface

•Tar get c apability

for data passing

thr ough the

Pa ral le l Int e rfa c e

•D0

•D1

•D2

•D3hot and D3c old

•5V environm ent

•3.3V environm ent

•V aux supply

Parallel

Interface

Control

Chips with a Infineon/

Intel Standard Parallel

Interface, including:

•ISDN devices

•Modem s DSP s

•Industrial devices

Three pr ede-

coded chip s el-

ec t lines

Can be used

for pinst rap-

ping the subsy -

stem/

subsyst em

vendor ID

Serial

Interface

Control

Chips with a serial

interfac e, including:

•Analog v oic e

codecs

•Analog modem

codecs

•IOM-2 devices .

Transmit and

receive data

are held in

separate 16

word FIFOs.

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 9 01.00

________________________________________

EEPROM

Control •additional

informati on, such

–the Subsystem

Vendor ID

–extensiv e pow-

er manage-

ment

information

Al l EEPRO Ms wi th

SPI in te rface This is an

optional

feature that

can be used to

customize the

PITA-2

configuration

at s tar t up.

General

Purpose

I/O

Interface

•GP output s

•GP inputs

•GP interrupt

inputs

It can be

configured to

ac t as

•Input pins

•Output pins

•I nterr upt

pins.

Can be used

for

pinst rapping

the s ubsys tem

Descrip tion of t he single Blocks (cont’d)

Name provides supports Notes

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 10 01.00

4 Communication with the PITA- 2

________________________________________

For communication with the PITA-2 the followin g blocks are u sed:

Components Page

P CI Configuration S pace 11

P CI Mas ter/T arget Controller 22

Inter rupt Contr ol Register - Retr y Counter 31

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 11 01.00

4. 1 PCI Configur at ion Space

________________________________________

Overview

Overview Page

Infor mat ion about the PCI Conf iguration Space 12

Ac c ess to the PCI Configur ation Space 15

B ase Address Register 16

Other Regist er s of the P CI Configuration S pac e 20

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 12 01.00

4.1.1 Inf ormat ion abo ut th e PCI Con f igu ratio n Space

________________________________________

Description

The PCI Configuration Space c ontains infor m ation about

•the P CI device

•the r eques ted address s pac e in the mem or y s pace of the P CI system.

The address s pac e includes 64 32-bit r egis ters where the firs t 16 r egis ter s build

the c onfigur ation s pac e header ( 00h- 3Ch, refer to “Conf igur ation Space Register

of the P ITA- 2” on page 173)

________________________________________

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 13 01.00

________________________________________

Construction of the PCI C onfiguration Space

De vice ID

31 23 15 7

Vendor ID

Status Command

Class Code Revision ID

BIST H eader Ty pe Latency Timer Cac h Line Size

Bas e Address R egi s ter 0 (Int er nal R egist ers)

Bas e Address R egister 1 (Paral lel Interface)

Bas e Address R egi s ter 2 (unused)

Bas e Address R egi s ter 3 (unused)

Bas e Address R egi s ter 4 (unused)

Bas e Address R egi s ter 5 (unused)

C ardBus CIS Pointer

Subsystem ID Subsys tem Vendor ID

Ex pansion R OM Bas e Address

Reserved Cap_Ptr

Reserved

Max_Lat Min_Gnt Interrupt Pin In te r r up t Lin e

Pow er M anagem ent Capabili ties Ca pab il ity IDNe xt Ite m P o i nt er

PMCSRBridge SupportData

P ower Data Register 1

P ower Data Register 2

P ower Data Register 3

U nused C onfigurat i on Spac e Regist er s

shaded fields l oaded duri ng

init ializ at ion if EEPROM is connec t ed

58h

54h

50h

4Ch

48h

44h

40h

3Ch

38h

34h

30h

2Ch

28h

24h

20h

1Ch

18h

14h

10h

0Ch

08h

04h

00h

081624

CardB us CI S

5Ch

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 14 01.00

________________________________________

Descrip tion of Register Types

Type Description

PE •r ead only via P CI

•thes e bits ar e initialized by pins trapping dur ing PCI r eset

or by the optional E EPROM

H•r ead only via P CI

•hardwired

RC •read clear via P CI

•thes e bits are set by the internal logic

•thes e bits c an be r ead out and r eset by writing logical “1”

to th e m

•wri ting logical “0” does n’t influence the stat es of these bits

RW •read write via PCI

•these bits can be read out and written via t he P CI bus

E•r ead only via P CI

•thes e bits are initialized to a default value dur ing PCI

r eset or by the optional E E PROM

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 15 01.00

4.1.2 Access to th e PCI Configu ration Space

________________________________________

Description

The PITA-2 supports single 32 bit data transactions for the access to the PCI

Configurat ion Space.

________________________________________

Spe c ial Qualities

Name Description

Subsystem ID •lower 4 bit s c an be set via pins tr apping if no

EEPR O M is u sed

•with external E EPROM the c omplet e 16 bit

v alue can be loaded for the Subsyst em ID

Subs y stem Vendor ID •16 bit ID of the car d manuf ac turer

•has to be applied for at the PCI Spec ial Interes t

Group

•c an be set via pins tr apping dur ing r es et if no

EEPR O M is u sed

•c an be loaded fr om ex ternal EEPROM

CardBus CIS Pointer is not supported by the PITA-2, although it is

implemented in the PCI Configuration Space

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 16 01.00

4.1.3 Base Addr ess Register

________________________________________

Base Add ress Reg isters 0 - 5

Base Ad dress Reg ister Description

B ase Address Register 0 •the lower 12 bits are hardwired t o “0”

•occ upies an address space of 4K

•allows acc es s to the internal r egis ter s of

the PIT A-2

B ase Address Register 1 •the lower 12 bits are hardwired t o “0”

•allows continuous r ead and write

oper ations for acces s to the par allel

interface

•occ upies an address space of 4K

•addr es s s pace is logically s egmented in

4x 1K addr ess blocks

B ase Address Register 2 - 5 not used

Structure of the Add ress Space o f Base Add ress Register 1

Ad dress Space Access to

3FFh - 000h device 1 on the parallel interface ( CS0)

7FFh - 400h device 2 on the parallel interface ( CS1)

BFF h - 800h device 3 on the parallel interface ( CS2)

FFFh - C00h not us ed

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 17 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 1 Memory_Access_Enable

Type RW

Defau lt Val ue 0b

Description Only if thi s bit is set to ‘1’, the PCI interface will react on

trans ac tions to the bas e addres s r egis ter s BAR ( all Bas e

Addres s Registers are defined as m emor y m apped).

Co nfig urat io n Sp ace Register: 10h

Bit 31:12 B ase A ddres s Regis ter 0

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 0

Type H

Value 000h

Description BAR0 c ontains the base addr es s of an addr es s s pac e in the

P CI m ain m emory through whic h the inter nal r egis ter s of t he

PI TA -2 can be acces sed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 18 01.00

________________________________________

Co nfig urat io n Sp ace Register: 14h

Bit 31:12 B ase A ddres s Regis ter 1

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 1

Type H

Value 000h

Description BA R1 c ontains the base addr ess of a 4-k ilobyte addr ess

s pac e in the PCI main mem ory through which the parallel

m ic ro c ontroller interface of the P ITA- 2 c an be acces s ed.

Co nfig urat io n Sp ace Register: 18h

Bit 31:0 B ase A ddres s Regis ter 2

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 2 is not support ed.

Co nfig urat io n Sp ace Register: 1Ch

Bit 31:0 B ase A ddres s Regis ter 3

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 3 is not support ed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 19 01.00

________________________________________

Co nfig urat io n Sp ace Register: 20h

Bit 31:0 B ase A ddres s Regis ter 4

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 4 is not support ed.

Co nfig urat io n Sp ace Register: 24h

Bit 31:0 B ase A ddres s Regis ter 5

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 5 is not support ed.