Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MCF5307 ColdFire(R) Integrated Microprocessor User's Manual MCF5307UM/D Rev. 2.0, 08/2000 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Document Comments: FAX (512) 895-2638, Attn: RISC Applications Engineering World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/NetComm http://www.motorola.com/ColdFire (c) Motorola Inc., 2000. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Overview Part I: MCF5307 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Freescale Semiconductor, Inc... 1 Part II SIM Overview 6 Phase-Locked Loop (PLL) 7 2 I C Module 8 Interrupt Controller 9 Chip-Select Module 10 Synchronous/Asynchronous DRAM Controller Module 11 Part III: Peripheral Module Part III DMA Controller Module 12 Timer Module 13 UART Modules 14 Parallel Port (General-Purpose I/O) 15 Part IV: Hardware Interface Part IV Mechanical Data 16 Signal Descriptions 17 Bus Operation 18 IEEE 1149.1 Test Access Port (JTAG) 19 Electrical Specifications 20 Appendix: Memory Map A Glossary of Terms and Abbreviations GLO Index IND For More Information On This Product, Go to: www.freescale.com IND B GLO IND Freescale Semiconductor, Inc. 1 Part I Part I: MCF5307 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Freescale Semiconductor, Inc... Overview Part II: System Integration Module (SIM) 6 SIM Overview 7 Phase-Locked Loop (PLL) 8 I2C Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III Part III: Peripheral Module 12 DMA Controller Module 13 Timer Module 14 UART Modules 15 Parallel Port (General-Purpose I/O) Part IV Part IV: Hardware Interface 16 Mechanical Data 17 Signal Descriptions 18 Bus Operation 19 IEEE 1149.1 Test Access Port (JTAG) 20 Electrical Specifications A Appendix B: Memory Map GLO Glossary of Terms and Abbreviations IND Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... About This Book Chapter 1 Overview 1.1 1.2 1.2.1 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.7.1 1.3.7.2 1.3.7.3 1.3.7.4 1.3.7.5 1.3.8 1.3.9 1.4 1.4.1 1.4.2 1.4.3 1.4.4 Features ............................................................................................................... 1-1 MCF5307 Features.............................................................................................. 1-4 Process ............................................................................................................ 1-6 ColdFire Module Description ............................................................................. 1-7 ColdFire Core ................................................................................................. 1-7 Instruction Fetch Pipeline (IFP).................................................................. 1-7 Operand Execution Pipeline (OEP) ............................................................ 1-7 MAC Module.............................................................................................. 1-7 Integer Divide Module................................................................................ 1-7 8-Kbyte Unified Cache ............................................................................... 1-8 Internal 4-Kbyte SRAM ............................................................................. 1-8 DRAM Controller ........................................................................................... 1-8 DMA Controller.............................................................................................. 1-8 UART Modules............................................................................................... 1-8 Timer Module ................................................................................................. 1-9 I2C Module ..................................................................................................... 1-9 System Interface ........................................................................................... 1-10 External Bus Interface .............................................................................. 1-10 Chip Selects .............................................................................................. 1-10 16-Bit Parallel Port Interface .................................................................... 1-10 Interrupt Controller ................................................................................... 1-10 JTAG......................................................................................................... 1-11 System Debug Interface................................................................................ 1-11 PLL Module.................................................................................................. 1-11 Programming Model, Addressing Modes, and Instruction Set......................... 1-12 Programming Model ..................................................................................... 1-13 User Registers ............................................................................................... 1-14 Supervisor Registers ..................................................................................... 1-14 Instruction Set ............................................................................................... 1-15 Contents For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Part I MCF5407 Processor Core Freescale Semiconductor, Inc... Chapter 2 ColdFire Core 2.1 2.1.1 2.1.2 2.1.2.1 2.1.2.1.1 2.1.2.2 2.1.2.2.1 2.1.2.2.2 2.1.2.2.3 2.1.3 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.6.1 2.7 2.7.1 2.7.2 2.7.3 2.7.4 vi Features and Enhancements.............................................................................. Clock-Multiplied Microprocessor Core........................................................ Enhanced Pipelines ....................................................................................... Instruction Fetch Pipeline (IFP)................................................................ Branch Acceleration ............................................................................. Operand Execution Pipeline (OEP) .......................................................... Illegal Opcode Handling....................................................................... Hardware Multiply/Accumulate (MAC) Unit ...................................... Hardware Divide Unit .......................................................................... Debug Module Enhancements ...................................................................... Programming Model ......................................................................................... User Programming Model ............................................................................ Data Registers (D0-D7) ........................................................................... Address Registers (A0-A6) ...................................................................... Stack Pointer (A7, SP).............................................................................. Program Counter (PC) .............................................................................. Condition Code Register (CCR)............................................................... Supervisor Programming Model................................................................... Status Register (SR).................................................................................. Vector Base Register (VBR) .................................................................... Cache Control Register (CACR) .............................................................. Access Control Registers (ACR0-ACR1)................................................ RAM Base Address Register (RAMBAR) ............................................... Module Base Address Register (MBAR) ................................................. Integer Data Formats......................................................................................... Organization of Data in Registers..................................................................... Organization of Integer Data Formats in Registers ...................................... Organization of Integer Data Formats in Memory ....................................... Addressing Mode Summary ............................................................................. Instruction Set Summary................................................................................... Instruction Set Summary .............................................................................. Instruction Timing ............................................................................................ MOVE Instruction Execution Times ............................................................ Execution Timings--One-Operand Instructions .......................................... Execution Timings--Two-Operand Instructions.......................................... Miscellaneous Instruction Execution Times................................................. MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com 2-21 2-22 2-22 2-23 2-23 2-24 2-24 2-24 2-25 2-25 2-26 2-27 2-27 2-27 2-28 2-28 2-28 2-29 2-29 2-30 2-30 2-31 2-31 2-31 2-31 2-31 2-31 2-32 2-33 2-34 2-37 2-40 2-41 2-43 2-43 2-45 Freescale Semiconductor, Inc. CONTENTS Paragraph Number 2.7.5 2.8 2.8.1 2.8.2 Title Page Number Branch Instruction Execution Times ............................................................ Exception Processing Overview ....................................................................... Exception Stack Frame Definition................................................................ Processor Exceptions .................................................................................... 2-46 2-47 2-49 2-50 Freescale Semiconductor, Inc... Chapter 3 Hardware Multiply/Accumulate (MAC) Unit 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 Overview............................................................................................................. MAC Programming Model............................................................................. General Operation........................................................................................... MAC Instruction Set Summary ...................................................................... Data Representation........................................................................................ MAC Instruction Execution Timings.................................................................. 3-1 3-2 3-3 3-4 3-4 3-5 Chapter 4 Local Memory 4.1 4.2 4.3 4.4 4.4.1 4.5 4.5.1 4.6 4.7 4.8 4.8.1 4.8.2 4.9 4.9.1 4.9.1.1 4.9.1.2 4.9.1.3 4.9.2 4.9.3 4.9.3.1 4.9.3.2 4.9.3.3 4.9.3.4 4.9.4 Interactions between Local Memory Modules ................................................... 4-1 SRAM Overview ................................................................................................ 4-1 SRAM Operation ................................................................................................ 4-2 SRAM Programming Model............................................................................... 4-3 SRAM Base Address Register (RAMBAR)................................................... 4-3 SRAM Initialization............................................................................................ 4-4 SRAM Initialization Code .............................................................................. 4-5 Power Management ............................................................................................ 4-6 Cache Overview.................................................................................................. 4-6 Cache Organization............................................................................................. 4-7 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8 The Cache at Start-Up..................................................................................... 4-9 Cache Operation................................................................................................ 4-11 Caching Modes ............................................................................................. 4-13 Cacheable Accesses .................................................................................. 4-13 Write-Through Mode ............................................................................... 4-14 Copyback Mode ....................................................................................... 4-14 Cache-Inhibited Accesses ............................................................................. 4-14 Cache Protocol.............................................................................................. 4-15 Read Miss ................................................................................................. 4-15 Write Miss ............................................................................................... 4-16 Read Hit .................................................................................................... 4-16 Write Hit .................................................................................................. 4-16 Cache Coherency ......................................................................................... 4-17 Contents For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 4.9.5 4.9.5.1 4.9.5.2 4.9.5.2.1 4.9.5.2.2 4.9.6 4.10 4.10.1 4.10.2 4.11 4.12 4.12.1 4.13 Title Page Number Memory Accesses for Cache Maintenance................................................... Cache Filling............................................................................................. Cache Pushes ............................................................................................ Push and Store Buffers ......................................................................... Push and Store Buffer Bus Operation................................................... Cache Locking .............................................................................................. Cache Registers................................................................................................. Cache Control Register (CACR) .................................................................. Access Control Registers (ACR0-ACR1).................................................... Cache Management........................................................................................... Cache Operation Summary ............................................................................... Cache State Transitions ................................................................................ Cache Initialization Code.................................................................................. 4-17 4-17 4-18 4-18 4-18 4-19 4-21 4-21 4-22 4-24 4-25 4-25 4-29 Chapter 5 Debug Support 5.1 5.2 5.3 5.3.1 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.5 5.5.1 5.5.2 5.5.2.1 5.5.2.2 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.2 5.5.3.3 5.5.3.3.1 5.5.3.3.2 5.5.3.3.3 viii Overview............................................................................................................. 5-1 Signal Description............................................................................................... 5-2 Real-Time Trace Support.................................................................................... 5-3 Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-4 Programming Model ........................................................................................... 5-5 Address Attribute Trigger Register (AATR) .................................................. 5-7 Address Breakpoint Registers (ABLR, ABHR) ............................................ 5-8 BDM Address Attribute Register (BAAR)..................................................... 5-9 Configuration/Status Register (CSR)............................................................ 5-10 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-12 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-13 Trigger Definition Register (TDR) ............................................................... 5-14 Background Debug Mode (BDM) .................................................................... 5-16 CPU Halt....................................................................................................... 5-16 BDM Serial Interface.................................................................................... 5-17 Receive Packet Format ............................................................................. 5-19 Transmit Packet Format............................................................................ 5-19 BDM Command Set...................................................................................... 5-19 ColdFire BDM Command Format............................................................ 5-20 Extension Words as Required............................................................... 5-21 Command Sequence Diagrams................................................................. 5-21 Command Set Descriptions ...................................................................... 5-23 Read A/D Register (RAREG/RDREG) ..................................................... 5-24 Write A/D Register (WAREG/WDREG)................................................... 5-25 Read Memory Location (READ)............................................................ 5-26 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.5.3.3.13 5.6 5.6.1 5.6.1.1 5.6.2 5.7 5.8 5.8.1 5.8.2 Title Page Number Write Memory Location (WRITE) ......................................................... Dump Memory Block (DUMP) .............................................................. Fill Memory Block (FILL) ..................................................................... Resume Execution (GO)........................................................................ No Operation (NOP) .............................................................................. Synchronize PC to the PST/DDATA Lines (SYNC_PC) ....................... Read Control Register (RCREG) ............................................................ Write Control Register (WCREG) .......................................................... Read Debug Module Register (RDMREG) ............................................. Write Debug Module Register (WDMREG) ........................................... Real-Time Debug Support ................................................................................ Theory of Operation...................................................................................... Emulator Mode ......................................................................................... Concurrent BDM and Processor Operation .................................................. Motorola-Recommended BDM Pinout............................................................. Processor Status, DDATA Definition............................................................... User Instruction Set ...................................................................................... Supervisor Instruction Set............................................................................. 5-27 5-29 5-31 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-39 5-40 5-41 5-41 5-42 5-42 5-43 5-46 Part II System Integration Module (SIM) Chapter 6 SIM Overview 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.10.1 6.2.10.1.1 6.2.10.1.2 Features ............................................................................................................... 6-1 Programming Model ........................................................................................... 6-3 SIM Register Memory Map............................................................................ 6-3 Module Base Address Register (MBAR) ....................................................... 6-4 Reset Status Register (RSR) ........................................................................... 6-5 Software Watchdog Timer.............................................................................. 6-6 System Protection Control Register (SYPCR) ............................................... 6-8 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9 Software Watchdog Service Register (SWSR)............................................... 6-9 PLL Clock Control for CPU STOP Instruction ............................................ 6-10 Pin Assignment Register (PAR) ................................................................... 6-10 Bus Arbitration Control ................................................................................ 6-11 Default Bus Master Park Register (MPARK) .......................................... 6-11 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12 Arbitration between Internal and External Masters for Accessing Internal Resources ......................................................... 6-14 Contents For More Information On This Product, Go to: www.freescale.com ix Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Chapter 7 Phase-Locked Loop (PLL) 7.1 7.1.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 7.4.1 7.4.2 7.5 Overview............................................................................................................. PLL:PCLK Ratios........................................................................................... PLL Operation .................................................................................................... Reset/Initialization .......................................................................................... Normal Mode.................................................................................................. Reduced-Power Mode..................................................................................... PLL Control Register (PLLCR)...................................................................... PLL Port List ...................................................................................................... Timing Relationships .......................................................................................... PCLK, PSTCLK, and BCLKO ....................................................................... RSTI Timing ................................................................................................... PLL Power Supply Filter Circuit ........................................................................ 7-1 7-2 7-2 7-2 7-2 7-2 7-3 7-3 7-4 7-4 7-5 7-6 Chapter 8 I2C Module 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 x Overview............................................................................................................. 8-1 Interface Features................................................................................................ 8-1 I2C System Configuration................................................................................... 8-3 I2C Protocol ........................................................................................................ 8-3 Arbitration Procedure ..................................................................................... 8-4 Clock Synchronization.................................................................................... 8-5 Handshaking ................................................................................................... 8-5 Clock Stretching ............................................................................................. 8-5 Programming Model ........................................................................................... 8-6 I2C Address Register (IADR) ......................................................................... 8-6 I2C Frequency Divider Register (IFDR)......................................................... 8-7 I2C Control Register (I2CR) ........................................................................... 8-8 I2C Status Register (I2SR).............................................................................. 8-9 I2C Data I/O Register (I2DR) ....................................................................... 8-10 2C Programming Examples ............................................................................. 8-10 I Initialization Sequence.................................................................................. 8-10 Generation of START................................................................................... 8-10 Post-Transfer Software Response................................................................. 8-11 Generation of STOP...................................................................................... 8-12 Generation of Repeated START................................................................... 8-12 Slave Mode ................................................................................................... 8-13 Arbitration Lost............................................................................................. 8-13 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Chapter 9 Interrupt Controller Freescale Semiconductor, Inc... 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 Overview............................................................................................................. Interrupt Controller Registers ............................................................................. Interrupt Control Registers (ICR0-ICR9) ...................................................... Autovector Register (AVR) ............................................................................ Interrupt Pending and Mask Registers (IPR and IMR)................................... Interrupt Port Assignment Register (IRQPAR) .............................................. 9-1 9-2 9-3 9-5 9-6 9-7 Chapter 10 Chip-Select Module 10.1 10.2 10.3 10.3.1 10.3.1.1 10.3.1.2 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.1.4 Overview........................................................................................................... Chip-Select Module Signals ............................................................................. Chip-Select Operation....................................................................................... General Chip-Select Operation..................................................................... 8-, 16-, and 32-Bit Port Sizing.................................................................. Global Chip-Select Operation................................................................... Chip-Select Registers........................................................................................ Chip-Select Module Registers ...................................................................... Chip-Select Address Registers (CSAR0-CSAR7)................................... Chip-Select Mask Registers (CSMR0-CSMR7)...................................... Chip-Select Control Registers (CSCR0-CSCR7) .................................... Code Example........................................................................................... 10-1 10-1 10-2 10-3 10-4 10-4 10-5 10-6 10-6 10-6 10-8 10-9 Chapter 11 Synchronous/Asynchronous DRAM Controller Module 11.1 11.1.1 11.1.2 11.2 11.2.1 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 Overview........................................................................................................... 11-1 Definitions .................................................................................................... 11-2 Block Diagram and Major Components ....................................................... 11-2 DRAM Controller Operation ............................................................................ 11-3 DRAM Controller Registers ......................................................................... 11-3 Asynchronous Operation .................................................................................. 11-4 DRAM Controller Signals in Asynchronous Mode...................................... 11-4 Asynchronous Register Set........................................................................... 11-4 DRAM Control Register (DCR) in Asynchronous Mode ........................ 11-4 DRAM Address and Control Registers (DACR0/DACR1) ..................... 11-5 DRAM Controller Mask Registers (DMR0/DMR1) ................................ 11-7 General Asynchronous Operation Guidelines .............................................. 11-8 Non-Page-Mode Operation..................................................................... 11-11 Contents For More Information On This Product, Go to: www.freescale.com xi Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.4 11.4.4.1 11.4.4.2 11.4.4.3 11.4.4.4 11.4.4.5 11.4.4.6 11.4.5 11.4.5.1 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 Title Page Number Burst Page-Mode Operation ................................................................... 11-12 Continuous Page Mode........................................................................... 11-13 Extended Data Out (EDO) Operation..................................................... 11-15 Refresh Operation ................................................................................... 11-16 Synchronous Operation................................................................................... 11-16 DRAM Controller Signals in Synchronous Mode...................................... 11-17 Using Edge Select (EDGESEL) ................................................................. 11-18 Synchronous Register Set ........................................................................... 11-19 DRAM Control Register (DCR) in Synchronous Mode.......................... 11-19 DRAM Address and Control Registers (DACR0/DACR1) in Synchronous Mode ......................................................................... 11-20 DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22 General Synchronous Operation Guidelines............................................... 11-23 Address Multiplexing ............................................................................. 11-23 Interfacing Example................................................................................ 11-27 Burst Page Mode..................................................................................... 11-27 Continuous Page Mode........................................................................... 11-29 Auto-Refresh Operation.......................................................................... 11-31 Self-Refresh Operation ........................................................................... 11-32 Initialization Sequence................................................................................ 11-33 Mode Register Settings........................................................................... 11-33 SDRAM Example ........................................................................................... 11-34 SDRAM Interface Configuration................................................................ 11-35 DCR Initialization....................................................................................... 11-35 DACR Initialization.................................................................................... 11-35 DMR Initialization...................................................................................... 11-37 Mode Register Initialization ....................................................................... 11-38 Initialization Code....................................................................................... 11-39 Part III Peripheral Module Chapter 12 DMA Controller Module 12.1 12.1.1 12.2 12.3 12.4 12.4.1 12.4.2 xii Overview........................................................................................................... DMA Module Features ................................................................................. DMA Signal Description .................................................................................. DMA Transfer Overview.................................................................................. DMA Controller Module Programming Model................................................ Source Address Registers (SAR0-SAR3) .................................................... Destination Address Registers (DAR0-DAR3) ........................................... MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com 12-1 12-2 12-2 12-3 12-4 12-6 12-7 Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.3 12.5.3.1 12.5.3.2 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.5 Title Page Number Byte Count Registers (BCR0-BCR3)........................................................... 12-7 DMA Control Registers (DCR0-DCR3)...................................................... 12-8 DMA Status Registers (DSR0-DSR3) ....................................................... 12-10 DMA Interrupt Vector Registers (DIVR0-DIVR3) ................................... 12-11 DMA Controller Module Functional Description........................................... 12-11 Transfer Requests (Cycle-Steal and Continuous Modes) ........................... 12-12 Data Transfer Modes .................................................................................. 12-12 Dual-Address Transfers .......................................................................... 12-12 Single-Address Transfers........................................................................ 12-13 Channel Initialization and Startup .............................................................. 12-13 Channel Prioritization ............................................................................. 12-13 Programming the DMA Controller Module ........................................... 12-13 Data Transfer .............................................................................................. 12-14 External Request and Acknowledge Operation ...................................... 12-14 Auto-Alignment...................................................................................... 12-17 Bandwidth Control.................................................................................. 12-18 Termination................................................................................................. 12-18 Chapter 13 Timer Module 13.1 13.1.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4 13.5 Overview........................................................................................................... Key Features ................................................................................................. General-Purpose Timer Units ........................................................................... General-Purpose Timer Programming Model .................................................. Timer Mode Registers (TMR0/TMR1) ........................................................ Timer Reference Registers (TRR0/TRR1) ................................................... Timer Capture Registers (TCR0/TCR1)....................................................... Timer Counters (TCN0/TCN1) .................................................................... Timer Event Registers (TER0/TER1)........................................................... Code Example................................................................................................... Calculating Time-Out Values ........................................................................... 13-1 13-2 13-2 13-2 13-3 13-4 13-4 13-5 13-5 13-6 13-7 Chapter 14 UART Modules 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 Overview........................................................................................................... Serial Module Overview ................................................................................... Register Descriptions ........................................................................................ UART Mode Registers 1 (UMR1n).............................................................. UART Mode Register 2 (UMR2n) ............................................................... UART Status Registers (USRn) ................................................................... Contents For More Information On This Product, Go to: www.freescale.com 14-1 14-2 14-2 14-4 14-6 14-7 xiii Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.12 14.3.13 14.3.14 14.4 14.5 14.5.1 14.5.1.1 14.5.1.2 14.5.1.2.1 14.5.1.2.2 14.5.2 14.5.2.1 14.5.2.2 14.5.2.3 14.5.3 14.5.3.1 14.5.3.2 14.5.3.3 14.5.4 14.5.5 14.5.5.1 14.5.5.2 14.5.5.3 14.5.6 14.5.6.1 Title Page Number UART Clock-Select Registers (UCSRn)...................................................... 14-8 UART Command Registers (UCRn) ............................................................ 14-9 UART Receiver Buffers (URBn) ............................................................... 14-11 UART Transmitter Buffers (UTBn) ........................................................... 14-11 UART Input Port Change Registers (UIPCRn).......................................... 14-12 UART Auxiliary Control Register (UACRn)............................................. 14-12 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-13 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................ 14-14 UART Interrupt Vector Register (UIVRn)................................................. 14-15 UART Input Port Register (UIPn) .............................................................. 14-15 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 14-15 UART Module Signal Definitions .................................................................. 14-16 Operation......................................................................................................... 14-18 Transmitter/Receiver Clock Source............................................................ 14-18 Programmable Divider............................................................................ 14-18 Calculating Baud Rates........................................................................... 14-19 BCLKO Baud Rates ........................................................................... 14-19 External Clock .................................................................................... 14-19 Transmitter and Receiver Operating Modes............................................... 14-19 Transmitting ........................................................................................... 14-21 Receiver .................................................................................................. 14-22 FIFO Stack ............................................................................................. 14-24 Looping Modes ........................................................................................... 14-25 Automatic Echo Mode ............................................................................ 14-25 Local Loop-Back Mode .......................................................................... 14-25 Remote Loop-Back Mode....................................................................... 14-26 Multidrop Mode.......................................................................................... 14-26 Bus Operation ............................................................................................. 14-28 Read Cycles ............................................................................................ 14-28 Write Cycles ........................................................................................... 14-28 Interrupt Acknowledge Cycles ............................................................... 14-28 Programming .............................................................................................. 14-28 UART Module Initialization Sequence .................................................. 14-29 Chapter 15 Parallel Port (General-Purpose I/O) 15.1 15.1.1 15.1.2 15.1.3 15.1.4 xiv Parallel Port Operation...................................................................................... Pin Assignment Register (PAR) ................................................................... Port A Data Direction Register (PADDR).................................................... Port A Data Register (PADAT) .................................................................... Code Example............................................................................................... MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com 15-1 15-1 15-2 15-2 15-3 Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Part IV Hardware Interface Freescale Semiconductor, Inc... Chapter 16 Mechanical Data 16.1 16.2 16.3 16.4 Package ............................................................................................................. Pinout ................................................................................................................ Mechanical Diagram......................................................................................... Case Drawing.................................................................................................... 16-1 16-1 16-8 16-9 Chapter 17 Signal Descriptions 17.1 17.2 17.2.1 17.2.1.1 17.2.1.2 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.3 17.3.1 17.4 17.4.1 17.4.2 17.4.3 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.5.1 17.5.5.2 Overview........................................................................................................... 17-1 MCF5307 Bus Signals ...................................................................................... 17-7 Address Bus .................................................................................................. 17-7 Address Bus (A[23:0]).............................................................................. 17-7 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7 Data Bus (D[31:0]) ....................................................................................... 17-8 Read/Write (R/W)......................................................................................... 17-8 Size (SIZ[1:0]) .............................................................................................. 17-8 Transfer Start (TS) ........................................................................................ 17-9 Address Strobe (AS) ..................................................................................... 17-9 Transfer Acknowledge (TA) ......................................................................... 17-9 Transfer In Progress (TIP/PP7)................................................................... 17-10 Transfer Type (TT[1:0]/PP[1:0]) ................................................................ 17-10 Transfer Modifier (TM[2:0]/PP[4:2])......................................................... 17-10 Interrupt Control Signals................................................................................. 17-12 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12 Bus Arbitration Signals................................................................................... 17-12 Bus Request (BR) ....................................................................................... 17-12 Bus Grant (BG).......................................................................................... 17-12 Bus Driven (BD)......................................................................................... 17-13 Clock and Reset Signals.................................................................................. 17-13 Reset In (RSTI)........................................................................................... 17-13 Clock Input (CLKIN).................................................................................. 17-13 Bus Clock Output (BCLKO) ...................................................................... 17-13 Reset Out (RSTO)....................................................................................... 17-13 Data/Configuration Pins (D[7:0]) ............................................................... 17-13 D[7:5Boot Chip-Select (CS0) Configuration ......................................... 17-14 D7--Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14 Contents For More Information On This Product, Go to: www.freescale.com xv Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 17.5.5.3 17.5.6 17.5.7 17.5.8 17.6 17.6.1 17.6.2 17.6.3 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1 17.9 17.9.1 17.9.2 17.9.3 17.9.4 17.10 17.10.1 17.10.2 17.11 17.12 17.12.1 17.12.2 17.13 17.13.1 17.13.2 17.13.3 17.13.4 17.13.5 17.14 17.14.1 17.14.2 17.14.3 17.14.4 17.14.5 xvi Title Page Number D[6:5]--Port Size Configuration (PS_CONFIG[1:0]) ........................... 17-14 D4--Address Configuration (ADDR_CONFIG) ....................................... 17-14 D[3:2]--Frequency Control PLL (FREQ[1:0] ..........................................) 17-15 D[1:0]--Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15 Chip-Select Module Signals ........................................................................... 17-15 Chip-Select (CS[7:0]) ................................................................................. 17-16 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16 Output Enable (OE) .................................................................................... 17-16 DRAM Controller Signals .............................................................................. 17-16 Row Address Strobes (RAS[1:0])............................................................... 17-16 Column Address Strobes (CAS[3:0]) ......................................................... 17-16 DRAM Write (DRAMW)........................................................................... 17-17 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17 Synchronous DRAM Clock Enable (SCKE) .............................................. 17-17 Synchronous Edge Select (EDGESEL) ...................................................... 17-17 DMA Controller Module Signals.................................................................... 17-17 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-18 Serial Module Signals ..................................................................................... 17-18 Transmitter Serial Data Output (TxD)........................................................ 17-18 Receiver Serial Data Input (RxD)............................................................... 17-18 Clear to Send (CTS).................................................................................... 17-18 Request to Send (RTS) ............................................................................... 17-18 Timer Module Signals..................................................................................... 17-18 Timer Inputs (TIN[1:0]).............................................................................. 17-19 Timer Outputs (TOUT1, TOUT0) .............................................................. 17-19 Parallel I/O Port (PP[15:0]) ............................................................................ 17-19 I2C Module Signals ........................................................................................ 17-19 I2C Serial Clock (SCL)............................................................................... 17-19 I2C Serial Data (SDA)................................................................................ 17-19 Debug and Test Signals .................................................................................. 17-20 Test Mode (MTMOD[3:0]) ........................................................................ 17-20 High Impedance (HIZ)................................................................................ 17-20 Processor Clock Output (PSTCLK)............................................................ 17-20 Debug Data (DDATA[3:0])........................................................................ 17-20 Processor Status (PST[3:0])........................................................................ 17-20 Debug Module/JTAG Signals......................................................................... 17-21 Test Reset/Development Serial Clock (TRST/DSCLK) ............................ 17-21 Test Mode Select/Breakpoint (TMS/BKPT) .............................................. 17-22 Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22 Test Clock (TCK) ....................................................................................... 17-23 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Chapter 18 Bus Operation 18.1 18.2 18.3 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.7.1 18.4.7.2 18.4.7.3 18.4.7.4 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.8.1 18.9 18.9.1 18.9.2 18.10 18.10.1 18.10.2 Features ............................................................................................................. 18-1 Bus and Control Signals ................................................................................... 18-1 Bus Characteristics............................................................................................ 18-2 Data Transfer Operation ................................................................................... 18-3 Bus Cycle Execution..................................................................................... 18-4 Data Transfer Cycle States ........................................................................... 18-5 Read Cycle.................................................................................................... 18-7 Write Cycle ................................................................................................... 18-8 Fast-Termination Cycles............................................................................... 18-9 Back-to-Back Bus Cycles ........................................................................... 18-10 Burst Cycles................................................................................................ 18-11 Line Transfers ......................................................................................... 18-12 Line Read Bus Cycles............................................................................. 18-12 Line Write Bus Cycles............................................................................ 18-14 Transfers Using Mixed Port Sizes .......................................................... 18-15 Misaligned Operands ...................................................................................... 18-16 Bus Errors ....................................................................................................... 18-17 Interrupt Exceptions........................................................................................ 18-17 Level 7 Interrupts........................................................................................ 18-18 Interrupt-Acknowledge Cycle..................................................................... 18-19 Bus Arbitration................................................................................................ 18-20 Bus Arbitration Signals............................................................................... 18-21 General Operation of External Master Transfers............................................ 18-21 Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... 18-25 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29 Reset Operation............................................................................................... 18-33 Master Reset ............................................................................................... 18-34 Software Watchdog Reset........................................................................... 18-35 Chapter 19 IEEE 1149.1 Test Access Port (JTAG) 19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 Overview........................................................................................................... JTAG Signal Descriptions ............................................................................... TAP Controller.................................................................................................. JTAG Register Descriptions ............................................................................. JTAG Instruction Shift Register .................................................................. IDCODE Register ......................................................................................... JTAG Boundary-Scan Register .................................................................... Contents For More Information On This Product, Go to: www.freescale.com 19-1 19-2 19-3 19-4 19-5 19-6 19-7 xvii Freescale Semiconductor, Inc. CONTENTS Paragraph Number 19.4.4 19.5 19.6 19.7 Title Page Number JTAG Bypass Register................................................................................ Restrictions ..................................................................................................... Disabling IEEE Standard 1149.1 Operation ................................................... Obtaining the IEEE Standard 1149.1.............................................................. 19-10 19-10 19-11 19-12 Freescale Semiconductor, Inc... Chapter 20 Electrical Specifications 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 20.11 xviii General Parameters ........................................................................................... 20-1 Clock Timing Specifications............................................................................. 20-2 Input/Output AC Timing Specifications........................................................... 20-3 Reset Timing Specifications ........................................................................... 20-12 Debug AC Timing Specifications................................................................... 20-12 Timer Module AC Timing Specifications ...................................................... 20-14 I2C Input/Output Timing Specifications......................................................... 20-15 UART Module AC Timing Specifications ..................................................... 20-16 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-18 DMA Timing Specifications........................................................................... 20-19 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-20 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 Title Page Number MCF5307 Block Diagram............................................................................................. 1-2 UART Module Block Diagram..................................................................................... 1-9 PLL Module ................................................................................................................ 1-12 ColdFire MCF5307 Programming Model .................................................................. 1-13 ColdFire Enhanced Pipeline ....................................................................................... 2-23 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25 ColdFire Programming Model.................................................................................... 2-27 Status Register (SR).................................................................................................... 2-30 Vector Base Register (VBR)....................................................................................... 2-30 Organization of Integer Data Formats in Data Registers............................................ 2-32 Organization of Integer Data Formats in Address Registers ...................................... 2-32 Memory Operand Addressing..................................................................................... 2-33 Exception Stack Frame Form...................................................................................... 2-49 ColdFire MAC Multiplication and Accumulation........................................................ 3-2 MAC Programming Model ........................................................................................... 3-2 SRAM Base Address Register (RAMBAR) ................................................................. 4-3 Unified Cache Organization ......................................................................................... 4-7 Cache Organization and Line Format ........................................................................... 4-8 Cache--A: at Reset, B: after Invalidation, C and D: Loading Pattern ....................... 4-10 Caching Operation ...................................................................................................... 4-11 Write-Miss in Copyback Mode................................................................................... 4-16 Cache Locking ............................................................................................................ 4-20 Cache Control Register (CACR) ................................................................................ 4-21 Access Control Register Format (ACRn) ................................................................... 4-23 An Format .................................................................................................................. 4-24 Cache Line State Diagram--Copyback Mode............................................................ 4-26 Cache Line State Diagram--Write-Through Mode.................................................... 4-26 Processor/Debug Module Interface............................................................................... 5-1 PSTCLK Timing........................................................................................................... 5-3 Example JMP Instruction Output on PST/DDATA...................................................... 5-5 Debug Programming Model ......................................................................................... 5-6 Address Attribute Trigger Register (AATR) ................................................................ 5-7 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9 BDM Address Attribute Register (BAAR)................................................................... 5-9 Configuration/Status Register (CSR).......................................................................... 5-10 Data Breakpoint/Mask Registers (DBR and DBMR)................................................. 5-12 Illustrations For More Information On This Product, Go to: www.freescale.com xix Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 5-10 Program Counter Breakpoint Register (PBR)............................................................. 5-14 5-11 Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-14 5-12 Trigger Definition Register (TDR) ............................................................................. 5-15 5-13 BDM Serial Interface Timing ..................................................................................... 5-18 5-14 Receive BDM Packet.................................................................................................. 5-19 5-15 Transmit BDM Packet ................................................................................................ 5-19 5-16 BDM Command Format ............................................................................................. 5-21 5-17 Command Sequence Diagram..................................................................................... 5-22 RAREG/RDREG Command Sequence............................................................................ 5-24 5-19 RAREG/RDREG Command Format ............................................................................... 5-24 5-18 WAREG/WDREG Command Sequence .......................................................................... 5-25 5-21 WAREG/WDREG Command Format.............................................................................. 5-25 5-20 READ Command Sequence.......................................................................................... 5-26 5-23 READ Command/Result Formats................................................................................. 5-26 5-22 WRITE Command Format ............................................................................................ 5-27 5-24 WRITE Command Sequence ........................................................................................ 5-28 5-25 DUMP Command/Result Formats ................................................................................ 5-29 5-26 DUMP Command Sequence ......................................................................................... 5-30 5-27 FILL Command Format................................................................................................ 5-31 5-28 FILL Command Sequence............................................................................................ 5-32 5-29 GO Command Sequence.............................................................................................. 5-33 5-31 GO Command Format.................................................................................................. 5-33 5-30 NOP Command Sequence ............................................................................................ 5-34 5-33 NOP Command Format................................................................................................ 5-34 5-32 SYNC_PC Command Sequence .................................................................................... 5-35 5-35 SYNC_PC Command Format........................................................................................ 5-35 5-34 RCREG Command Sequence........................................................................................ 5-36 5-37 RCREG Command/Result Formats............................................................................... 5-36 5-36 WCREG Command Sequence ....................................................................................... 5-37 5-39 WCREG Command/Result Formats.............................................................................. 5-37 5-38 RDMREG Command Sequence..................................................................................... 5-38 5-41 RDMREG bdm Command/Result Formats.................................................................... 5-38 5-40 WDMREG Command Sequence .................................................................................... 5-39 5-43 WDMREG BDM Command Format.............................................................................. 5-39 5-42 5-44 Recommended BDM Connector................................................................................. 5-42 6-1 SIM Block Diagram...................................................................................................... 6-1 6-2 Module Base Address Register (MBAR) ..................................................................... 6-4 6-3 Reset Status Register (RSR) ......................................................................................... 6-5 6-4 MCF5307 Embedded System Recovery from Unterminated Access........................... 6-7 6-5 System Protection Control Register (SYPCR) ............................................................. 6-8 6-6 Software Watchdog Interrupt Vector Register (SWIVR)............................................. 6-9 6-7 Software Watchdog Service Register (SWSR)............................................................. 6-9 6-8 Pin Assignment Register (PAR) ................................................................................. 6-10 xx MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 Title Page Number Default Bus Master Register (MPARK) ..................................................................... 6-11 Round Robin Arbitration (PARK = 00)...................................................................... 6-12 Park on Master Core Priority (PARK = 01) ............................................................... 6-13 Park on DMA Module Priority (PARK = 10)............................................................. 6-13 Park on Current Master Priority (PARK = 01) ........................................................... 6-14 PLL Module Block Diagram ........................................................................................ 7-1 PLL Control Register (PLLCR).................................................................................... 7-3 CLKIN, PCLK, PSTCLK, and BCLKO Timing .......................................................... 7-5 Reset and Initialization Timing..................................................................................... 7-6 PLL Power Supply Filter Circuit .................................................................................. 7-6 I2C Module Block Diagram .......................................................................................... 8-2 I2C Standard Communication Protocol ........................................................................ 8-3 Repeated START .......................................................................................................... 8-4 Synchronized Clock SCL.............................................................................................. 8-5 I2C Address Register (IADR) ....................................................................................... 8-6 I2C Frequency Divider Register (IFDR)....................................................................... 8-7 I2C Control Register (I2CR) ......................................................................................... 8-8 I2CR Status Register (I2SR) ......................................................................................... 8-9 I2C Data I/O Register (I2DR) ..................................................................................... 8-10 Flow-Chart of Typical I2C Interrupt Routine ............................................................. 8-14 Interrupt Controller Block Diagram.............................................................................. 9-1 Interrupt Control Registers (ICR0-ICR9) .................................................................... 9-3 Autovector Register (AVR) .......................................................................................... 9-5 Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR) ......................... 9-7 Interrupt Port Assignment Register (IRQPAR) ............................................................ 9-7 Connections for External Memory Port Sizes ............................................................ 10-4 Chip Select Address Registers (CSAR0-CSAR7) ..................................................... 10-6 Chip Select Mask Registers (CSMRn) ....................................................................... 10-7 Chip-Select Control Registers (CSCR0-CSCR7) ...................................................... 10-8 Asynchronous/Synchronous DRAM Controller Block Diagram ............................... 11-2 DRAM Control Register (DCR) (Asynchronous Mode) ............................................ 11-5 DRAM Address and Control Registers (DACR0/DACR1)........................................ 11-6 DRAM Controller Mask Registers (DMR0 and DMR1)............................................ 11-7 Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) .......................... 11-11 Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) .......................... 11-12 Burst Page-Mode Read Operation (4-3-3-3)............................................................. 11-13 Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13 Continuous Page-Mode Operation............................................................................ 11-14 Write Hit in Continuous Page Mode......................................................................... 11-15 EDO Read Operation (3-2-2-2) ................................................................................ 11-15 DRAM Access Delayed by Refresh ......................................................................... 11-16 MCF5307 SDRAM Interface.................................................................................... 11-18 Using EDGESEL to Change Signal Timing............................................................. 11-19 Illustrations For More Information On This Product, Go to: www.freescale.com xxi Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 11-15 DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19 11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20 11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22 11-18 Burst Read SDRAM Access ..................................................................................... 11-28 11-19 Burst Write SDRAM Access .................................................................................... 11-29 11-20 Synchronous, Continuous Page-Mode Access--Consecutive Reads....................... 11-30 11-21 Synchronous, Continuous Page-Mode Access--Read after Write........................... 11-31 11-22 Auto-Refresh Operation............................................................................................ 11-32 11-23 Self-Refresh Operation ............................................................................................. 11-32 11-24 Mode Register Set (mrs) Command ......................................................................... 11-34 11-25 Initialization Values for DCR ................................................................................... 11-35 11-26 SDRAM Configuration............................................................................................. 11-36 11-27 DACR Register Configuration.................................................................................. 11-36 11-28 DMR0 Register ......................................................................................................... 11-37 11-29 Mode Register Mapping to MCF5307 A[31:0] ........................................................ 11-38 12-1 DMA Signal Diagram ................................................................................................. 12-1 12-2 Dual-Address Transfer................................................................................................ 12-3 12-3 Single-Address Transfers............................................................................................ 12-4 12-4 Source Address Registers (SARn) .............................................................................. 12-6 12-5 Destination Address Registers (DARn) ...................................................................... 12-7 12-6 Byte Count Registers (BCRn)--BCR24BIT = 1 ........................................................ 12-7 12-7 BCRn--BCR24BIT = 0.............................................................................................. 12-8 12-8 DMA Control Registers (DCRn) ............................................................................... 12-8 12-9 DMA Status Registers (DSRn) ................................................................................ 12-10 12-10 DMA Interrupt Vector Registers (DIVRn) ............................................................... 12-11 12-11 DREQ Timing Constraints, Dual-Address DMA Transfer....................................... 12-15 12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer ................... 12-16 12-13 Single-Address DMA Transfer ................................................................................. 12-17 13-1 Timer Block Diagram ................................................................................................. 13-1 13-2 Timer Mode Registers (TMR0/TMR1) ...................................................................... 13-3 13-3 Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4 13-4 Timer Capture Register (TCR0/TCR1) ...................................................................... 13-5 13-5 Timer Counters (TCN0/TCN1)................................................................................... 13-5 13-6 Timer Event Registers (TER0/TER1)......................................................................... 13-5 14-1 Simplified Block Diagram .......................................................................................... 14-1 14-2 UART Mode Registers 1 (UMR1n)............................................................................ 14-5 14-3 UART Mode Register 2 (UMR2n) ............................................................................. 14-6 14-4 UART Status Register (USRn) ................................................................................... 14-7 14-5 UART Clock-Select Register (UCSRn)...................................................................... 14-8 14-6 UART Command Register (UCRn)............................................................................ 14-9 14-7 UART Receiver Buffer (URB0) ............................................................................... 14-11 14-8 UART Transmitter Buffer (UTB0)........................................................................... 14-12 14-9 UART Input Port Change Register (UIPCRn).......................................................... 14-12 xxii MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 14-10 14-11 14-12 14-13 14-14 14-15 14-17 14-16 14-18 14-19 14-20 14-21 14-22 14-23 14-24 14-25 14-26 14-27 15-1 15-2 15-3 16-1 16-2 16-3 17-1 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 Title Page Number UART Auxiliary Control Register (UACRn) ........................................................... 14-13 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13 UART Divider Upper Register (UDUn)................................................................... 14-14 UART Divider Lower Register (UDLn)................................................................... 14-14 UART Interrupt Vector Register (UIVRn) ............................................................... 14-15 UART Input Port Register (UIPn) ............................................................................ 14-15 UART Block Diagram Showing External and Internal Interface Signals ................ 14-16 UART Output Port Command Register (UOP1/UOP0) ........................................... 14-16 UART/RS-232 Interface ........................................................................................... 14-17 Clocking Source Diagram......................................................................................... 14-18 Transmitter and Receiver Functional Diagram......................................................... 14-20 Transmitter Timing Diagram .................................................................................... 14-22 Receiver Timing........................................................................................................ 14-23 Automatic Echo ........................................................................................................ 14-25 Local Loop-Back ...................................................................................................... 14-26 Remote Loop-Back ................................................................................................... 14-26 Multidrop Mode Timing Diagram ............................................................................ 14-27 UART Mode Programming Flowchart ..................................................................... 14-30 Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1 Port A Data Direction Register (PADDR).................................................................. 15-2 Port A Data Register (PADAT) .................................................................................. 15-3 Mechanical Diagram................................................................................................... 16-9 MCF5307 Case Drawing (General View) ................................................................ 16-10 Case Drawing (Details)............................................................................................. 16-11 MCF5307 Block Diagram with Signal Interfaces ...................................................... 17-2 Signal Relationship to BCLKO for Non-DRAM Access ........................................... 18-2 Connections for External Memory Port Sizes ............................................................ 18-4 Chip-Select Module Output Timing Diagram ............................................................ 18-4 Data Transfer State Transition Diagram ..................................................................... 18-6 Read Cycle Flowchart................................................................................................. 18-7 Basic Read Bus Cycle................................................................................................. 18-8 Write Cycle Flowchart................................................................................................ 18-9 Basic Write Bus Cycle ................................................................................................ 18-9 Read Cycle with Fast Termination ........................................................................... 18-10 Write Cycle with Fast Termination........................................................................... 18-10 Back-to-Back Bus Cycles ......................................................................................... 18-11 Line Read Burst (2-1-1-1), External Termination .................................................... 18-12 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13 Line Read Burst (3-2-2-2), External Termination .................................................... 18-13 Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination ................... 18-15 Line Write Burst-Inhibited, Internal Termination .................................................... 18-15 Illustrations For More Information On This Product, Go to: www.freescale.com xxiii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16 18-20 Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16 18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17 18-22 Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17 18-23 Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20 18-24 Basic No-Wait-State External Master Access .......................................................... 18-22 18-25 External Master Burst Line Access to 32-Bit Port.................................................... 18-24 18-26 MCF5307 Two-Wire Mode Bus Arbitration Interface............................................. 18-25 18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26 18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27 18-29 MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28 18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30 18-31 Three-Wire Bus Arbitration...................................................................................... 18-31 18-32 Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32 18-33 Master Reset Timing................................................................................................. 18-34 18-34 Software Watchdog Reset Timing ............................................................................ 18-36 19-1 JTAG Test Logic Block Diagram ............................................................................... 19-2 19-2 JTAG TAP Controller State Machine......................................................................... 19-4 19-4 Disabling JTAG in JTAG Mode ............................................................................... 19-11 19-5 Disabling JTAG in Debug Mode .............................................................................. 19-11 20-1 Clock Timing .............................................................................................................. 20-3 20-2 PSTCLK Timing......................................................................................................... 20-3 20-3 AC Timings--Normal Read and Write Bus Cycles ................................................... 20-5 20-4 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6 20-5 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7 20-6 SDRAM Read Cycle with EDGESEL Tied High....................................................... 20-8 20-7 SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9 20-8 SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-10 20-9 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11 20-10 AC Output Timing--High Impedance...................................................................... 20-11 20-11 Reset Timing............................................................................................................. 20-12 20-12 Real-Time Trace AC Timing .................................................................................... 20-13 20-13 BDM Serial Port AC Timing .................................................................................... 20-13 20-14 Timer Module AC Timing ........................................................................................ 20-14 20-15 I2C Input/Output Timings......................................................................................... 20-16 20-16 UART0/1 Module AC Timing--UART Mode......................................................... 20-17 20-17 General-Purpose I/O Timing..................................................................................... 20-18 20-18 DMA Timing ............................................................................................................ 20-19 20-19 IEEE 1149.1 (JTAG) AC Timing ............................................................................. 20-21 xxiv MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 Title Page Number User-Level Registers................................................................................................... 1-14 Supervisor-Level Registers......................................................................................... 1-14 CCR Field Descriptions ............................................................................................. 2-28 MOVEC Register Map ............................................................................................... 2-29 Status Field Descriptions ............................................................................................ 2-30 Integer Data Formats................................................................................................... 2-31 ColdFire Effective Addressing Modes........................................................................ 2-34 Notational Conventions .............................................................................................. 2-34 User-Mode Instruction Set Summary ......................................................................... 2-37 Supervisor-Mode Instruction Set Summary................................................................ 2-40 Misaligned Operand References ................................................................................. 2-41 Move Byte and Word Execution Times...................................................................... 2-42 Move Long Execution Times...................................................................................... 2-42 MAC Move Execution Times..................................................................................... 2-43 One-Operand Instruction Execution Times ................................................................ 2-43 Two-Operand Instruction Execution Times................................................................ 2-44 Miscellaneous Instruction Execution Times............................................................... 2-45 General Branch Instruction Execution Times............................................................. 2-46 Bcc Instruction Execution Times................................................................................ 2-47 Exception Vector Assignments................................................................................... 2-48 Format Field Encoding ............................................................................................... 2-49 Fault Status Encodings................................................................................................ 2-50 MCF5307 Exceptions ................................................................................................. 2-50 MAC Instruction Summary........................................................................................... 3-4 Two-Operand MAC Instruction Execution Times ....................................................... 3-5 MAC Move Instruction Execution Times..................................................................... 3-6 RAMBAR Field Description ........................................................................................ 4-3 Examples of Typical RAMBAR Settings ..................................................................... 4-6 Valid and Modified Bit Settings ................................................................................... 4-8 CACR Field Descriptions ........................................................................................... 4-21 ACRn Field Descriptions............................................................................................ 4-23 Cache Line State Transitions ...................................................................................... 4-27 Cache Line State Transitions (Current State Invalid) ................................................. 4-28 Cache Line State Transitions (Current State Valid) ................................................... 4-28 Cache Line State Transitions (Current State Modified) ............................................. 4-29 Debug Module Signals.................................................................................................. 5-2 Tables For More Information On This Product, Go to: www.freescale.com xxv Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 xxvi Title Page Number Processor Status Encoding............................................................................................ 5-4 BDM/Breakpoint Registers........................................................................................... 5-7 AATR Field Descriptions ............................................................................................. 5-8 ABLR Field Description ............................................................................................... 5-9 ABHR Field Description............................................................................................... 5-9 BAAR Field Descriptions ........................................................................................... 5-10 CSR Field Descriptions .............................................................................................. 5-11 DBR Field Descriptions.............................................................................................. 5-13 DBMR Field Descriptions .......................................................................................... 5-13 Access Size and Operand Data Location .................................................................... 5-13 PBR Field Descriptions .............................................................................................. 5-14 PBMR Field Descriptions ........................................................................................... 5-14 TDR Field Descriptions .............................................................................................. 5-15 Receive BDM Packet Field Description ..................................................................... 5-19 Transmit BDM Packet Field Description ................................................................... 5-19 BDM Command Summary ......................................................................................... 5-20 BDM Field Descriptions ............................................................................................. 5-21 Control Register Map.................................................................................................. 5-36 Definition of DRc Encoding--Read........................................................................... 5-38 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................... 5-40 PST/DDATA Specification for User-Mode Instructions............................................ 5-43 PST/DDATA Specification for Supervisor-Mode Instructions.................................. 5-46 SIM Registers .............................................................................................................. 6-3 MBAR Field Descriptions ............................................................................................ 6-5 RSR Field Descriptions ................................................................................................ 6-6 SYPCR Field Descriptions ........................................................................................... 6-8 PLLIPL Settings ......................................................................................................... 6-10 MPARK Field Descriptions........................................................................................ 6-11 PLLCR Field Descriptions............................................................................................ 7-3 PLL Module Input SIgnals............................................................................................ 7-3 PLL Module Output Signals ......................................................................................... 7-4 I2C Interface Memory Map........................................................................................... 8-6 I2C Address Register Field Descriptions ...................................................................... 8-6 IFDR Field Descriptions ............................................................................................... 8-7 I2CR Field Descriptions................................................................................................ 8-8 I2SR Field Descriptions ................................................................................................ 8-9 Interrupt Controller Registers ....................................................................................... 9-2 Interrupt Control Registers ........................................................................................... 9-2 ICRn Field Descriptions ............................................................................................... 9-3 Interrupt Priority Scheme.............................................................................................. 9-4 AVR Field Descriptions................................................................................................ 9-6 Autovector Register Bit Assignments........................................................................... 9-6 IPR and IMR Field Descriptions................................................................................... 9-7 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 Title Page Number IRQPAR Field Descriptions ......................................................................................... 9-8 Chip-Select Module Signals ....................................................................................... 10-1 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2 Accesses by Matches in CSCRs and DACRs ............................................................. 10-3 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4 D[6:5]/PS[1:0], Port Size of Boot CS0 ....................................................................... 10-4 Chip-Select Registers.................................................................................................. 10-5 CSARn Field Description ........................................................................................... 10-6 CSMRn Field Descriptions ......................................................................................... 10-7 CSCRn Field Descriptions.......................................................................................... 10-8 DRAM Controller Registers ....................................................................................... 11-3 SDRAM Signal Summary ......................................................................................... 11-4 DCR Field Descriptions (Asynchronous Mode)......................................................... 11-5 DACR0/DACR1 Field Description ............................................................................ 11-6 DMR0/DMR1 Field Descriptions............................................................................... 11-7 Generic Address Multiplexing Scheme ...................................................................... 11-8 DRAM Addressing for Byte-Wide Memories.......................................................... 11-10 DRAM Addressing for 16-Bit Wide Memories........................................................ 11-10 DRAM Addressing for 32-Bit Wide Memories........................................................ 11-11 SDRAM Commands ................................................................................................. 11-17 Synchronous DRAM Signal Connections ................................................................ 11-17 DCR Field Descriptions (Synchronous Mode) ......................................................... 11-19 DACR0/DACR1 Field Descriptions (Synchronous Mode)...................................... 11-21 DMR0/DMR1 Field Descriptions............................................................................. 11-23 MCF5307 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 11-24 MCF5307 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 11-24 MCF5307 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................. 11-24 MCF5307 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................. 11-24 MCF5307 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 11-25 MCF5307 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 11-25 MCF5307 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)................ 11-25 MCF5307 to SDRAM Interface (16-Bit Port, 10-Column Address Lines).............. 11-25 MCF5307 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25 MCF5307 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26 MCF5307to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) .............. 11-26 MCF5307 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26 MCF5307 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26 MCF5307 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26 MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 11-27 MCF5307 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 11-27 SDRAM Hardware Connections............................................................................... 11-27 SDRAM Example Specifications ............................................................................. 11-34 SDRAM Hardware Connections............................................................................... 11-35 Tables For More Information On This Product, Go to: www.freescale.com xxvii Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 11-34 11-35 11-36 11-37 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-5 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 15-1 15-2 15-3 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 xxviii Title Page Number DCR Initialization Values......................................................................................... 11-35 DACR Initialization Values...................................................................................... 11-36 DMR0 Initialization Values...................................................................................... 11-37 Mode Register Initialization ..................................................................................... 11-38 DMA Signals .............................................................................................................. 12-2 Memory Map for DMA Controller Module Registers................................................ 12-5 DCRn Field Descriptions............................................................................................ 12-8 DSRn Field Descriptions .......................................................................................... 12-10 General-Purpose Timer Module Memory Map .......................................................... 13-3 TMRn Field Descriptions ........................................................................................... 13-4 TERn Field Descriptions............................................................................................. 13-6 Calculated Time-out Values (90-MHz Processor Clock) ........................................... 13-7 UART Module Programming Model.......................................................................... 14-3 UMR1n Field Descriptions ......................................................................................... 14-5 UMR2n Field Descriptions ......................................................................................... 14-6 USRn Field Descriptions ............................................................................................ 14-7 UCSRn Field Descriptions.......................................................................................... 14-9 UCRn Field Descriptions............................................................................................ 14-9 UIPCRn Field Descriptions ...................................................................................... 14-12 UACRn Field Descriptions ....................................................................................... 14-13 UISRn/UIMRn Field Descriptions ........................................................................... 14-14 UIVRn Field Descriptions ........................................................................................ 14-15 UIPn Field Descriptions............................................................................................ 14-15 UOP1/UOP0 Field Descriptions ............................................................................... 14-16 UART Module Signals ............................................................................................. 14-17 UART Module Initialization Sequence .................................................................... 14-29 Parallel Port Pin Descriptions ..................................................................................... 15-2 PADDR Field Description .......................................................................................... 15-2 Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3 Pins 1-52 (Left, Top-to-Bottom) ................................................................................ 16-1 Pins 53-104 (Bottom, Left-to-Right).......................................................................... 16-3 Pins 105-156 (Right, Bottom-to-Top)........................................................................ 16-4 Pins 157-208 (Top, Right-to-Left) ............................................................................. 16-6 Dimensions ............................................................................................................... 16-11 MCF5307 Signal Index............................................................................................... 17-3 Data Pin Configuration ............................................................................................... 17-6 Bus Cycle Size Encoding............................................................................................ 17-7 Bus Cycle Transfer Type Encoding............................................................................ 17-9 TM[2:0] Encodings for TT = 00 (Normal Access)..................................................... 17-9 TM0 Encoding for DMA as Master (TT = 01) ........................................................... 17-9 TM[2:1] Encoding for DMA as Master (TT = 01) ................................................... 17-10 TM[2:0] Encodings for TT = 10 (Emulator Access) ................................................ 17-10 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-10 MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 17-10 17-11 17-12 17-13 17-14 17-15 17-16 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 A-1 A-2 A-3 A-4 A-5 Title Page Number Data Pin Configuration ............................................................................................. 17-12 D7 Selection of CS0 Automatic Acknowledge ........................................................ 17-13 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13 CLKIN Frequency .................................................................................................... 17-13 BCLKO/PSTCLK Divide Ratios.............................................................................. 17-14 Processor Status Signal Encodings ........................................................................... 17-19 ColdFire Bus Signal Summary ................................................................................... 18-1 Bus Cycle Size Encoding............................................................................................ 18-3 Accesses by Matches in CSCRs and DACRs ............................................................. 18-5 Bus Cycle States ......................................................................................................... 18-6 Allowable Line Access Patterns ............................................................................... 18-12 MCF5307 Arbitration Protocol States ...................................................................... 18-20 ColdFire Bus Arbitration Signal Summary............................................................... 18-21 Cycles for Basic No-Wait-State External Master Access......................................... 18-23 Cycles for External Master Burst Line Access to 32-Bit Port .................................. 18-24 MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32 Data Pin Configuration ............................................................................................. 18-35 JTAG Pin Descriptions ............................................................................................... 19-3 JTAG Instructions....................................................................................................... 19-5 IDCODE Bit Assignments.......................................................................................... 19-6 Boundary-Scan Bit Definitions................................................................................... 19-7 Absolute Maximum Ratings ....................................................................................... 20-1 Operating Temperatures.............................................................................................. 20-1 DC Electrical Specifications ....................................................................................... 20-2 Clock Timing Specification ........................................................................................ 20-2 Input AC Timing Specification................................................................................... 20-3 Output AC Timing Specification ................................................................................ 20-4 Reset Timing Specification....................................................................................... 20-12 Debug AC Timing Specification .............................................................................. 20-12 Timer Module AC Timing Specification.................................................................. 20-14 I2C Input Timing Specifications between SCL and SDA......................................... 20-15 I2C Output Timing Specifications between SCL and SDA ...................................... 20-15 UART Module AC Timing Specifications ............................................................... 20-16 General-Purpose I/O Port AC Timing Specifications............................................... 20-18 DMA AC Timing Specifications .............................................................................. 20-19 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 20-20 SIM Registers............................................................................................................... A-1 Interrupt Controller Registers ...................................................................................... A-1 Chip-Select Registers................................................................................................... A-2 DRAM Controller Registers ........................................................................................ A-3 General-Purpose Timer Registers ................................................................................ A-4 Tables For More Information On This Product, Go to: www.freescale.com xxix Freescale Semiconductor, Inc. TABLES Table Number xxx Page Number UART0 Control Registers............................................................................................ A-4 UART1 Control Registers............................................................................................ A-6 Parallel Port Memory Map........................................................................................... A-7 I2C Interface Memory Map.......................................................................................... A-8 DMA Controller Registers........................................................................................... A-8 Freescale Semiconductor, Inc... A-6 A-7 A-8 A-9 A-10 Title MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. About This Book Freescale Semiconductor, Inc... The primary objective of this user's manual is to define the functionality of the MCF5307 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure they are using the most recent version of the documentation. To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MCF5307. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire architecture. Organization Following is a summary and a brief description of the major sections of this manual: * Chapter 1, "Overview," includes general descriptions of the modules and features incorporated in the MCF5307, focussing in particular on new features. * Part I is intended for system designers who need to understand the operation of the MCF5307 ColdFire core. -- Chapter 2, "ColdFire Core," provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the V2 ColdFire core, and then fully describes the V3 programming model as it is implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. -- Chapter 3, "Hardware Multiply/Accumulate (MAC) Unit," describes the MCF5307 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). About This Book For More Information On This Product, Go to: www.freescale.com xxxi Organization Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... -- Chapter 4, "Local Memory." This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification. It consists of the two following major sections. * - Section 4.2, "SRAM Overview," describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. - Section 4.7, "Cache Overview," describes the MCF5307 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. -- Chapter 5, "Debug Support," describes the Revision C enhanced hardware debug support in the MCF5307. This revision of the ColdFire debug architecture encompasses earlier revisions. Part II, "System Integration Module (SIM)," describes the system integration module, which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices. It includes a general description of the SIM and individual chapters that describe components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt controller for peripherals, configuration and operation of chip selects, and the SDRAM controller. -- Chapter 6, "SIM Overview," describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5307. -- Chapter 7, "Phase-Locked Loop (PLL)," describes configuration and operation of the PLL module. It describes in detail the registers and signals that support the PLL implementation. -- Chapter 8, "I2C Module," describes the MCF5307 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. -- Chapter 9, "Interrupt Controller," describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. -- Chapter 10, "Chip-Select Module," describes the MCF5307 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. -- Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes configuration and operation of the synchronous/asynchronous DRAM controller component of the SIM. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. xxxii MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. * Organization Part III, "Peripheral Module," describes the operation and configuration of the MCF5307 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. Freescale Semiconductor, Inc... -- Chapter 12, "DMA Controller Module," provides an overview of the DMA controller module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. * -- Chapter 13, "Timer Module," describes configuration and operation of the two general-purpose timer modules, timer 0 and timer 1. It includes programming examples. -- Chapter 14, "UART Modules," describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5307 and includes programming examples. -- Chapter 15, "Parallel Port (General-Purpose I/O)," describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. Part IV, "Hardware Interface," provides a pinout and both electrical and functional descriptions of the MCF5307 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams. -- Chapter 16, "Mechanical Data," provides a functional pin listing and package diagram for the MCF5307. -- Chapter 17, "Signal Descriptions," provides an alphabetical listing of MCF5307 signals. This chapter describes the MCF5307 signals. In particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. -- Chapter 18, "Bus Operation," describes data transfers, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Note that Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes DRAM cycles. -- Chapter 19, "IEEE 1149.1 Test Access Port (JTAG)," describes configuration and operation of the MCF5307 JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. -- Chapter 20, "Electrical Specifications," describes AC and DC electrical specifications and thermal characteristics for the MCF5307. Because additional speeds may have become available since the publication of this book, consult Motorola's ColdFire web page, http://www.motorola.com/coldfire, to confirm that this is the latest information. About This Book For More Information On This Product, Go to: www.freescale.com xxxiii Suggested Reading Freescale Semiconductor, Inc. This manual includes the following appendix: * Appendix A, "List of Memory Maps," lists the entire address-map for MCF5307 memory-mapped registers. This manual also includes a glossary and an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. Freescale Semiconductor, Inc... General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general: ColdFire Documentation The ColdFire documentation is available from the sources listed on the back cover of this manual. Document order numbers are included in parentheses for ease in ordering. * ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) * User's manuals--These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These include the following: * * -- ColdFire MCF5102 User's Manual (MCF5102UM/AD) -- ColdFire MCF5202 User's Manual (MCF5202UM/AD) -- ColdFire MCF5204 User's Manual (MCF5204UM/AD) -- ColdFire MCF5206 User's Manual (MCF5206EUM/AD) -- ColdFire MCF5206E User's Manual (MCF5206EUM/AD) ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase. xxxiv MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Acronyms and Abbreviations Freescale Semiconductor, Inc... italics 0x0 Italics indicate variable command parameters. Book titles in text are set in italics. Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don't care. n Used to express an undefined numerical value NOT logical operator & AND logical operator | OR logical operator Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion ALU Arithmetic logic unit AVEC Autovector BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address EDO Extended data output (DRAM) FIFO First-in, first-out About This Book For More Information On This Product, Go to: www.freescale.com xxxv Freescale Semiconductor, Inc. Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Freescale Semiconductor, Inc... Term Meaning GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter xxxvi MCF5307 User's Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Terminology and Notational Conventions Terminology and Notational Conventions Table ii shows notational conventions used throughout this document. Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) An Any address register n (example: A3 is address register 3) Register Specifications Freescale Semiconductor, Inc... Ay,Ax Source and destination address registers, respectively Dn Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) Rm MAC registers (ACC, MAC, MASK) Rn Any address or data register Rw Destination register w (used for MAC instructions only) Ry,Rx Any source and destination registers, respectively Xi index register i (can be an address or data register: Ai, Di) Register Names ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands # I Immediate data following the 16-bit operation word of the instruction Effective address y,x