Quick Start Procedure
DESCRIPTION
The EPC9017 development board features the 100 V EPC2001 en-
hancement mode (eGaN®) eld eect transistor (FET) operating
up to a 20 A maximum output current in a half bridge congura-
tion with onboard gate drives. The purpose of this development
board is to simplify the evaluation process of the EPC2001 eGaN
FET by including all the critical components on a single board that
can be easily connected into any existing converter.
The EPC9017 development board is 2” x 1.5” and features three
EPC2001 eGaN FETs in a half bridge conguration using the Texas
Instruments LM5113 gate driver. The half bridge conguration
Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9017 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter
CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM)
Figure 1: Block Diagram of EPC9017 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – VSW
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe
tip on probe
pad at OUT
Ground probe
against TP3
Minimize loop
contains a single top side device and two parallel bottom devices
and is recommended for high current, lower duty cycle applica-
tions. The board contains all critical components and the printed
circuit board (PCB) layout is designed for optimal switching per-
formance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET eciency. A com-
plete block diagram of the circuit is given in Figure 1.
For more information on the EPC2001s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Development Board EPC9017
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2001
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 70* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 20* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width V
PWM
rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width V
PWM
rise and fall time < 10ns 200 #ns
* Assumes lower duty cycle inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Quick Start Procedure
DESCRIPTION
The EPC9017 development board features the 100 V EPC2001 en-
hancement mode (eGaN®) eld eect transistor (FET) operating
up to a 20 A maximum output current in a half bridge congura-
tion with onboard gate drives. The purpose of this development
board is to simplify the evaluation process of the EPC2001 eGaN
FET by including all the critical components on a single board that
can be easily connected into any existing converter.
The EPC9017 development board is 2” x 1.5” and features three
EPC2001 eGaN FETs in a half bridge conguration using the Texas
Instruments LM5113 gate driver. The half bridge conguration
Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9017 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter
CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM)
Figure 1: Block Diagram of EPC9017 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – VSW
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe
tip on probe
pad at OUT
Ground probe
against TP3
Minimize loop
contains a single top side device and two parallel bottom devices
and is recommended for high current, lower duty cycle applica-
tions. The board contains all critical components and the printed
circuit board (PCB) layout is designed for optimal switching per-
formance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET eciency. A com-
plete block diagram of the circuit is given in Figure 1.
For more information on the EPC2001s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Development Board EPC9017
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2001
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 70* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 20* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width V
PWM
rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width V
PWM
rise and fall time < 10ns 200 #ns
* Assumes lower duty cycle inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Quick Start Procedure
DESCRIPTION
The EPC9017 development board features the 100 V EPC2001 en-
hancement mode (eGaN®) eld eect transistor (FET) operating
up to a 20 A maximum output current in a half bridge congura-
tion with onboard gate drives. The purpose of this development
board is to simplify the evaluation process of the EPC2001 eGaN
FET by including all the critical components on a single board that
can be easily connected into any existing converter.
The EPC9017 development board is 2” x 1.5” and features three
EPC2001 eGaN FETs in a half bridge conguration using the Texas
Instruments LM5113 gate driver. The half bridge conguration
Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9017 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter
CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM)
Figure 1: Block Diagram of EPC9017 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – VSW
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe
tip on probe
pad at OUT
Ground probe
against TP3
Minimize loop
contains a single top side device and two parallel bottom devices
and is recommended for high current, lower duty cycle applica-
tions. The board contains all critical components and the printed
circuit board (PCB) layout is designed for optimal switching per-
formance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET eciency. A com-
plete block diagram of the circuit is given in Figure 1.
For more information on the EPC2001s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Development Board EPC9017
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2001
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 70* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 20* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width V
PWM
rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width V
PWM
rise and fall time < 10ns 200 #ns
* Assumes lower duty cycle inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Quick Start Procedure
DESCRIPTION
The EPC9017 development board features the 100 V EPC2001 en-
hancement mode (eGaN®) eld eect transistor (FET) operating
up to a 20 A maximum output current in a half bridge congura-
tion with onboard gate drives. The purpose of this development
board is to simplify the evaluation process of the EPC2001 eGaN
FET by including all the critical components on a single board that
can be easily connected into any existing converter.
The EPC9017 development board is 2” x 1.5” and features three
EPC2001 eGaN FETs in a half bridge conguration using the Texas
Instruments LM5113 gate driver. The half bridge conguration
Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9017 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter
CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM)
Figure 1: Block Diagram of EPC9017 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – VSW
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe
tip on probe
pad at OUT
Ground probe
against TP3
Minimize loop
contains a single top side device and two parallel bottom devices
and is recommended for high current, lower duty cycle applica-
tions. The board contains all critical components and the printed
circuit board (PCB) layout is designed for optimal switching per-
formance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET eciency. A com-
plete block diagram of the circuit is given in Figure 1.
For more information on the EPC2001s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Development Board EPC9017
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2001
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 70* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 20* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width V
PWM
rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width V
PWM
rise and fall time < 10ns 200 #ns
* Assumes lower duty cycle inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
Figure 5: Development Board EPC9017 Schematic
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
A
B
Y
VDD
U1
NC7SZ00L6X
70V Max
SW OUT
GND
(Optional)
1
TP3
CON1
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
1
TP1
Keystone 5015
R2
Zero
R14
Optional
R15
Zero
R5
47.0
D2
SDM03U40
R4
22.0
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3 MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
C9
0.1uF, 25V
R19
Zero
R20
Zero
R23
Zero
R24
Zero
Q2
EPC2001
Q1
EPC2001
C22 C23
C21
1.0uF, 100V
U2
LM5113TME
C19
0.1uF, 25V
C17
100pF
C16
100pF
D3
Optional
Q3
EPC2001
R21
Zero
R22
Zero
Table 2 : Bill of Material
Item Qty Reference Part Description Manufacturer / Part #
1 3 C4, C10, C11, Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C16, C17 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU
3 2 C9, C19 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K
4 3 C21, C22, C23 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125AE
5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0
7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
8 3 Q1, Q2, Q3 eGaN® FET EPC, EPC2001
9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0
12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0
13 6 R19, R20, R21, R22, R23, R24 Resistor, 0 Ohm, 1/16W Stackpole, RMCF0402ZT0R00
14 2 TP1, TP2 Test Point Keystone Elect, 5015
15 1 TP3 Connector 1/40th of Tyco, 4-103185-0
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113TME
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 R14 Optional Resistor
21 0 D3 Optional Diode
22 0 P1, P2 Optional Potentiometer
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
Figure 5: Development Board EPC9017 Schematic
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
A
B
Y
VDD
U1
NC7SZ00L6X
70V Max
SW OUT
GND
(Optional)
1
TP3
CON1
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
1
TP1
Keystone 5015
R2
Zero
R14
Optional
R15
Zero
R5
47.0
D2
SDM03U40
R4
22.0
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3 MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
C9
0.1uF, 25V
R19
Zero
R20
Zero
R23
Zero
R24
Zero
Q2
EPC2001
Q1
EPC2001
C22 C23
C21
1.0uF, 100V
U2
LM5113TME
C19
0.1uF, 25V
C17
100pF
C16
100pF
D3
Optional
Q3
EPC2001
R21
Zero
R22
Zero
Table 2 : Bill of Material
Item Qty Reference Part Description Manufacturer / Part #
1 3 C4, C10, C11, Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C16, C17 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU
3 2 C9, C19 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K
4 3 C21, C22, C23 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125AE
5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0
7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
8 3 Q1, Q2, Q3 eGaN® FET EPC, EPC2001
9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0
12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0
13 6 R19, R20, R21, R22, R23, R24 Resistor, 0 Ohm, 1/16W Stackpole, RMCF0402ZT0R00
14 2 TP1, TP2 Test Point Keystone Elect, 5015
15 1 TP3 Connector 1/40th of Tyco, 4-103185-0
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113TME
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 R14 Optional Resistor
21 0 D3 Optional Diode
22 0 P1, P2 Optional Potentiometer
Quick Start Procedure
DESCRIPTION
The EPC9017 development board features the 100 V EPC2001 en-
hancement mode (eGaN®) eld eect transistor (FET) operating
up to a 20 A maximum output current in a half bridge congura-
tion with onboard gate drives. The purpose of this development
board is to simplify the evaluation process of the EPC2001 eGaN
FET by including all the critical components on a single board that
can be easily connected into any existing converter.
The EPC9017 development board is 2” x 1.5” and features three
EPC2001 eGaN FETs in a half bridge conguration using the Texas
Instruments LM5113 gate driver. The half bridge conguration
Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9017 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter
CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM)
Figure 1: Block Diagram of EPC9017 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – VSW
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe
tip on probe
pad at OUT
Ground probe
against TP3
Minimize loop
contains a single top side device and two parallel bottom devices
and is recommended for high current, lower duty cycle applica-
tions. The board contains all critical components and the printed
circuit board (PCB) layout is designed for optimal switching per-
formance. There are also various probe points to facilitate simple
waveform measurement and evaluate eGaN FET eciency. A com-
plete block diagram of the circuit is given in Figure 1.
For more information on the EPC2001s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Development Board EPC9017
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2001
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 70* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 20* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width V
PWM
rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width V
PWM
rise and fall time < 10ns 200 #ns
* Assumes lower duty cycle inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
