Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM) NOTE. The EPC9017 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - VSW EFFICIENT POWER CONVERSION EPC The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Minimize loop Place probe tip on probe pad at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of EPC9017 Development Board - (For Efficiency Measurement) PWM Input VDD Quick Start Procedure PWM Input Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Contact us: www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Development Board EPC9017 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2001 DESCRIPTION www.epc-co.com The EPC9017 development board features the 100 V EPC2001 enhancement mode (eGaN(R)) field effect transistor (FET) operating up to a 20 A maximum output current in a half bridge configuration with onboard gate drives. The purpose of this development board is to simplify the evaluation process of the EPC2001 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. contains a single top side device and two parallel bottom devices and is recommended for high current, lower duty cycle applications. The board contains all critical components and the printed circuit board (PCB) layout is designed for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and evaluate eGaN FET efficiency. A complete block diagram of the circuit is given in Figure 1. The EPC9017 development board is 2" x 1.5" and features three EPC2001 eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate driver. The half bridge configuration For more information on the EPC2001s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 VDD Gate Drive Input Supply Range 12 V VIN Bus Input Voltage Range 70* V VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 20* A VPWM PWM Logic Input Voltage Threshold Input `High' 3.5 6 V Input `Low' 0 1.5 V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200 # ns * Assumes lower duty cycle inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM) NOTE. The EPC9017 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - VSW EFFICIENT POWER CONVERSION EPC The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Minimize loop Place probe tip on probe pad at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of EPC9017 Development Board - (For Efficiency Measurement) PWM Input VDD Quick Start Procedure PWM Input Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Contact us: www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Development Board EPC9017 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2001 DESCRIPTION www.epc-co.com The EPC9017 development board features the 100 V EPC2001 enhancement mode (eGaN(R)) field effect transistor (FET) operating up to a 20 A maximum output current in a half bridge configuration with onboard gate drives. The purpose of this development board is to simplify the evaluation process of the EPC2001 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. contains a single top side device and two parallel bottom devices and is recommended for high current, lower duty cycle applications. The board contains all critical components and the printed circuit board (PCB) layout is designed for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and evaluate eGaN FET efficiency. A complete block diagram of the circuit is given in Figure 1. The EPC9017 development board is 2" x 1.5" and features three EPC2001 eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate driver. The half bridge configuration For more information on the EPC2001s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 VDD Gate Drive Input Supply Range 12 V VIN Bus Input Voltage Range 70* V VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 20* A VPWM PWM Logic Input Voltage Threshold Input `High' 3.5 6 V Input `Low' 0 1.5 V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200 # ns * Assumes lower duty cycle inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. NOTE. The EPC9017 development board does not have any current or thermal protection on board. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM) Figure 3: Proper Measurement of Switch Node - VSW EFFICIENT POWER CONVERSION EPC The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Minimize loop Ground probe against TP3 Place probe tip on probe pad at OUT THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of EPC9017 Development Board PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V VIN Supply Switch Node + + IIN <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Development Board EPC9017 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). Turn on the controller / PWM input source and probe switching node to see switching operation. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 1. 2. 3. 4. 5. 6. 7. 8. Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Quick Start Procedure 100 V Half-Bridge with Gate Drive, Using EPC2001 www.epc-co.com For more information on the EPC2001s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. The EPC9017 development board is 2" x 1.5" and features three EPC2001 eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate driver. The half bridge configuration contains a single top side device and two parallel bottom devices and is recommended for high current, lower duty cycle applications. The board contains all critical components and the printed circuit board (PCB) layout is designed for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and evaluate eGaN FET efficiency. A complete block diagram of the circuit is given in Figure 1. The EPC9017 development board features the 100 V EPC2001 enhancement mode (eGaN(R)) field effect transistor (FET) operating up to a 20 A maximum output current in a half bridge configuration with onboard gate drives. The purpose of this development board is to simplify the evaluation process of the EPC2001 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER VDD V EPC Products are distributed exclusively through Digi-Key. www.digikey.com IN CONDITIONS Gate Drive Input Supply Range MIN 7 Bus Input Voltage Range PWM Logic Input Voltage Threshold VPWM Switch Node Output Current IOUT Switch Node Output Voltage OUT V Development Board / Demonstration Board Notification The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. MAX 12 70* 100 20* 0 Input `Low' 3.5 Input `High' VPWM rise and fall time < 10ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns Minimum `High' State Input Pulse Width 6 1.5 60 UNITS V V V A V V ns ns 200 # * Assumes lower duty cycle inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. EPC reserves the right at any time, without notice, to change said circuitry and specifications. NOTE. The EPC9017 development board does not have any current or thermal protection on board. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM) Figure 3: Proper Measurement of Switch Node - VSW EFFICIENT POWER CONVERSION EPC The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Minimize loop Ground probe against TP3 Place probe tip on probe pad at OUT THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of EPC9017 Development Board PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V VIN Supply Switch Node + + IIN <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Development Board EPC9017 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). Turn on the controller / PWM input source and probe switching node to see switching operation. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 1. 2. 3. 4. 5. 6. 7. 8. Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Quick Start Procedure 100 V Half-Bridge with Gate Drive, Using EPC2001 www.epc-co.com For more information on the EPC2001s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. The EPC9017 development board is 2" x 1.5" and features three EPC2001 eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate driver. The half bridge configuration contains a single top side device and two parallel bottom devices and is recommended for high current, lower duty cycle applications. The board contains all critical components and the printed circuit board (PCB) layout is designed for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and evaluate eGaN FET efficiency. A complete block diagram of the circuit is given in Figure 1. The EPC9017 development board features the 100 V EPC2001 enhancement mode (eGaN(R)) field effect transistor (FET) operating up to a 20 A maximum output current in a half bridge configuration with onboard gate drives. The purpose of this development board is to simplify the evaluation process of the EPC2001 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER VDD V EPC Products are distributed exclusively through Digi-Key. www.digikey.com IN CONDITIONS Gate Drive Input Supply Range MIN 7 Bus Input Voltage Range PWM Logic Input Voltage Threshold VPWM Switch Node Output Current IOUT Switch Node Output Voltage OUT V Development Board / Demonstration Board Notification The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. MAX 12 70* 100 20* 0 Input `Low' 3.5 Input `High' VPWM rise and fall time < 10ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns Minimum `High' State Input Pulse Width 6 1.5 60 UNITS V V V A V V ns ns 200 # * Assumes lower duty cycle inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Table 2 : Bill of Material Item Qty Reference Part Description Manufacturer / Part # 1 3 C4, C10, C11, Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D 2 2 C16, C17 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU 3 2 C9, C19 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K 4 3 C21, C22, C23 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125AE 5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7 6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0 7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF 8 3 Q1, Q2, Q3 eGaN(R) FET EPC, EPC2001 9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0 10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0 12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0 13 6 R19, R20, R21, R22, R23, R24 Resistor, 0 Ohm, 1/16W Stackpole, RMCF0402ZT0R00 14 2 TP1, TP2 Test Point Keystone Elect, 5015 15 1 TP3 Connector 1/40th of Tyco, 4-103185-0 16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X 17 1 U2 I.C., Gate driver Texas Instruments, LM5113TME 18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC 19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X 20 0 R14 Optional Resistor 21 0 D3 Optional Diode 22 0 P1, P2 Optional Potentiometer 1 2 4 3 5 6 7 - 12 Vdc A J1 1 2 CON2 C10 1uF, 25V 8 U3 IN 7 NC MCP1703 OUT 1 NC 2 6 NC NC 3 NC GND 4 C11 1uF, 25V C4 1uF, 25V GND Q1 EPC2001 Y NC7SZ00L6X R2 Zero U4 A P1 Optional 2 J6 CON4 NC7SZ08L6X P2 Optional J3 CON4 D1 Y GND PWM2 B VDD B C 1 2 3 4 70V Max B 4 3 2 1 R1 10k U2 SDM03U40 R4 22.0 2 D2 SW OUT 0.1uF, 25V C9 R19 Zero R22 Zero J4 CON4 (Optional) SDM03U40 R5 Optional 47.0 100pF C17 R23 100pF R15 Zero 0.1uF, 25V C19 LM5113TME Q2 EPC2001 Zero R20 Zero R21 Zero R24 Zero C TP3 1 C16 R14 C21 C22 C23 1.0uF, 100V CON1 Q3 EPC2001 D3 Optional J7 CON4 1 2 3 4 CON2 J9 1 2 CON2 VCC VDD 1 2 3 4 B 1 2 J5 CON4 4 3 2 1 U1 A J2 TP2 Keystone 5015 1 PWM1 9 GND 5 A VCC 1 4 3 2 1 GND TP1 Keystone 5015 J8 CON4 D D Figure 5: Development Board EPC9017 Schematic 1 2 3 4 5 6 Table 2 : Bill of Material Item Qty Reference Part Description Manufacturer / Part # 1 3 C4, C10, C11, Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D 2 2 C16, C17 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU 3 2 C9, C19 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K 4 3 C21, C22, C23 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125AE 5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7 6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0 7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF 8 3 Q1, Q2, Q3 eGaN(R) FET EPC, EPC2001 9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0 10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0 12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0 13 6 R19, R20, R21, R22, R23, R24 Resistor, 0 Ohm, 1/16W Stackpole, RMCF0402ZT0R00 14 2 TP1, TP2 Test Point Keystone Elect, 5015 15 1 TP3 Connector 1/40th of Tyco, 4-103185-0 16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X 17 1 U2 I.C., Gate driver Texas Instruments, LM5113TME 18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC 19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X 20 0 R14 Optional Resistor 21 0 D3 Optional Diode 22 0 P1, P2 Optional Potentiometer 1 2 4 3 5 6 7 - 12 Vdc A J1 1 2 CON2 C10 1uF, 25V 8 U3 IN 7 NC MCP1703 OUT 1 NC 2 6 NC NC 3 NC GND 4 C11 1uF, 25V C4 1uF, 25V GND Q1 EPC2001 Y NC7SZ00L6X R2 Zero U4 A P1 Optional 2 J6 CON4 NC7SZ08L6X P2 Optional J3 CON4 D1 Y GND PWM2 B VDD B C 1 2 3 4 70V Max B 4 3 2 1 R1 10k U2 SDM03U40 R4 22.0 2 D2 SW OUT 0.1uF, 25V C9 R19 Zero R22 Zero J4 CON4 (Optional) SDM03U40 R5 Optional 47.0 100pF C17 R23 100pF R15 Zero 0.1uF, 25V C19 LM5113TME Q2 EPC2001 Zero R20 Zero R21 Zero R24 Zero C TP3 1 C16 R14 C21 C22 C23 1.0uF, 100V CON1 Q3 EPC2001 D3 Optional J7 CON4 1 2 3 4 CON2 J9 1 2 CON2 VCC VDD 1 2 3 4 B 1 2 J5 CON4 4 3 2 1 U1 A J2 TP2 Keystone 5015 1 PWM1 9 GND 5 A VCC 1 4 3 2 1 GND TP1 Keystone 5015 J8 CON4 D D Figure 5: Development Board EPC9017 Schematic 1 2 3 4 5 6 Figure 4: Typical Waveforms for VIN = 48 V to 5 V/14 A (500 kHz) Buck converter CH1: Switch node voltage (VSW) - CH2: PWM input voltage (VPWM) NOTE. The EPC9017 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - VSW EFFICIENT POWER CONVERSION EPC The EPC9017 development board showcases the EPC2001 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9017 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Minimize loop Place probe tip on probe pad at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Development board EPC9017 is easy to set up to evaluate the performance of the EPC2001 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of EPC9017 Development Board - (For Efficiency Measurement) PWM Input VDD Quick Start Procedure PWM Input Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Contact us: www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Development Board EPC9017 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2001 DESCRIPTION www.epc-co.com The EPC9017 development board features the 100 V EPC2001 enhancement mode (eGaN(R)) field effect transistor (FET) operating up to a 20 A maximum output current in a half bridge configuration with onboard gate drives. The purpose of this development board is to simplify the evaluation process of the EPC2001 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. contains a single top side device and two parallel bottom devices and is recommended for high current, lower duty cycle applications. The board contains all critical components and the printed circuit board (PCB) layout is designed for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and evaluate eGaN FET efficiency. A complete block diagram of the circuit is given in Figure 1. The EPC9017 development board is 2" x 1.5" and features three EPC2001 eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate driver. The half bridge configuration For more information on the EPC2001s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9017 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 VDD Gate Drive Input Supply Range 12 V VIN Bus Input Voltage Range 70* V VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 20* A VPWM PWM Logic Input Voltage Threshold Input `High' 3.5 6 V Input `Low' 0 1.5 V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200 # ns * Assumes lower duty cycle inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage.