64K x 4 Static RAM
CY7C194
CY7C195
CY7C196
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Decembe r 1987 - Revis ed December 1994
Features
• High speed
—12 ns
• Output enable (OE) f eature (7C195 and 7C196)
• CMOS for optimum speed/power
• Low active power
—880 mW
• Low sta n dby pow er
—220 mW
• TTL-compatibl e inputs and outputs
• A utomatic power-down when deselected
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-perfor-
mance CMOS static RAMs organized as 65,536 by 4 bits.
Easy mem or y expansion is provided by active LOW chip en-
able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and three-state drivers. They have an automatic
power -do wn f eat ure, reduc ing the po wer consumpt ion by 75%
when deselected.
Writing t o th e d e vice i s accom plish ed when the chi p enabl e(s)
(CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and writ e enable (WE) inputs are both LOW. Data
on the four input pins (I/O0 through I/O3) is written into the
memory location, specified on the address pins (A0 through
A15).
Reading the device is accomplished by taking the chip en-
able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) LOW, while write enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
A die coat is used to ensure alpha immunity.
Shaded area contains prelimin ary inform ation.
CE
28
Logic Block Diagram Pin Configurations
1024 x 64 x 4
ARRAY
A1
A2
A3
A4
A5
A6
A7
A8
A0
A11
A13
A12
A14
A15
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
WE
(OE)
(7C195 and
7C196 ONLY)
I/O3
CE2(7C196 only)
I/O2
I/O1
I/O0
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11 14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C194
A5
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O3
I/O2
I/O1
I/O0
A0
GND 12 13
11
12 19
18
A7
NC
VCC
A8
A9
A10
A11
A12
A13
CE1
NC
A4
A3
A2
A1
A0
I/O2
I/O3
I/O0
GND
OE
WE
Top View
LCC
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
18
A7
NC
NC
VCC
NC
I/O0
GND
WE
7C194
Top View
LCC
A8
A9
A10
A11
A12
A13
A14
A15
CE
A4
A3
A2
A1
A0
I/O3
I/O2
I/O1
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C195
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O3
I/O2
I/O1
I/O0
A0
CE1
A14
A15
A5
A14
A15
OE
NC
NC CE2
(7C196)
A6
A5
A14
A15
I/O1
A6
A5
INPUT BUFFER
CE1
A9
A10
7C196
7C196
C194-1
C194-2 C194-3
C194-4 C194-5
NC
(7C195)
CE2
NC
Sele c tio n G uide 7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35 7C194-45
7C196-45
Maximum Access Time (ns) 12 15 20 25 35 45
Maximum Operating
Current (mA) Commercial 155 145 135 115 115
Military 160 150 125 125 125
Maximum Standby Current (mA) 30 30 30 30 30 30
CY7C194
CY7C195
CY7C196
2
Maximum Ratings
(Above which the usefu l l ife may be impaired. For user guide-
li nes, not tes ted.)
Storage Temperature .............................. ...–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to G round Potential. ....... .......–0.5V to +7.0V
DC Voltag e Appli ed to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage [1].................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ...... .. ....... .. ...... .. ....... .. ...... .. >2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Current............ ........... ....... .. ....... ....... ...... >200 mA
]
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Military[2] –55°C to +125°C 5V ± 10%
Electrical Characte ristics Over the Operating Range[3]
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0.3V 2.2 VCC
+ 0.3V V
VIL[1] Input LOW Voltage −0.5 0.8 −0.5 0.8 V
IIX Input Load Current GND < VI < VCC −5+5 −5+5 µA
IOZ Output Leakage
Current GND < VO < VCC,
Output Di sabled −5+5 −5+5 µA
IOS Output Short
Circ uit Current[4] VCC = Max.,
VOUT = GN D −300 −300 mA
ICC VCC Operating
Supply C u rren t VCC=Max., IOUT=0 mA,
f=fMAX=1/tRC Com’l 155 145 mA
Mil 160
ISB1 Autom a tic C E
Power-Do wn Curr ent
—TT L In puts[5]
Max. VCC, CE 1,2 > VIH,
VIN > VIH or VIN < VIL, f = fMAX 30 30 mA
ISB2 Autom a tic C E
Power-Do wn Curr ent
—CMOS Input s[5]
Max. VCC, CE1,2 > VCC - 0.3V,
VIN > VCC - 0.3V or
VIN < 0.3V, f = 0
Com’l 10 10 mA
Mil 15
Shaded area contains preliminary information.
Notes:
1. Minimum v oltage is equal to -2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. A pull-up resistor to VCC on the CE input is required to keep the device deselec ted during VCC power-up, otherwise I SB will ex ceed v alues given.
CY7C194
CY7C195
CY7C196
3
)
Electrical Characte ristics O v er t he O perating Ra ng e[3] (continued)
7C194-20
7C195-20
7C196-20
7C194- 25, 35, 45
7C195-25, 35
7C196- 25, 35, 45
Parameter Description Test Conditi ons Min. Max. Min. Max. Unit
VOH Output H IGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8. 0 mA 0.4 0.4 V
VIH Input HIGH Vol ta ge 2.2 VCC
+ 0.3V 2.2 VCC
+0.3V V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –5 +5 –5 +5 µA
IOZ Outpu t Leakage
Current GND < V O < VCC,
Output Disabled –5 +5 –5 +5 µA
IOS Outpu t Short
Circuit Cur rent[4] VCC = Max.,
VOUT = GN D –300 –300 mA
ICC VCC Operatin g
Supply Current VCC=Max., IOUT=0 m A ,
f=fMAX=1/tRC Com’l 135 115 mA
Mil 150 125
ISB1 A uto mati c C E
P ower-Down Current
—TTL Inputs[5]
Max. VCC, CE1,2 > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
30 30 mA
ISB2 A uto mati c C E
P ower-Down Current
—C MOS Inputs[5]
Max. VCC, CE1,2 > VCC - 0.3V,
VIN > VCC - 0.3V or
VIN < 0.3V, f = 0
15 15 mA
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0 V 8pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms[7]
Notes:
6. Tested initially and after any design or process changes that may affect these parameters.
7. tr = < 3 ns for the -12 and -15 speeds. tr = < 5 ns f or the -20 and slower speeds .
3.0V
5V
OUTPUT
R1 48 1Ω
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<t
r<t
r
5V
OUTPUT
R1 48 1Ω
R2
255Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.73V
Equivalent to: THÉ EVENIN EQUIVALENT
ALL INPUT PULSES
C194-6 C194-7
167Ω
CY7C194
CY7C195
CY7C196
4
:
Switching Charac teris t ics Ov er t he Op er at ing Ran ge [3, 8 ]
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35 7C194-45
7C196-45
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 45 ns
tAA Address to Data
Valid 12 15 20 25 35 45 ns
tOHA Output Hold from
Address Change 3 33333ns
tACE1,
tACE2 CE LOW to
Data Valid 12 15 20 25 35 45 ns
tDOE OE LOW to
Data Valid 7C195,
7C196 5 7 9 10 16 16 ns
tLZOE OE LOW to
Low Z 7C195,
7C196 0 00333ns
tHZOE OE HIGH to
High Z[10] 7C195,
7C196 5 7 9 11 15 15 ns
tLZCE1,
tLZCE2 CE LO W to
Low Z[9] 3 33333ns
tHZCE1,
tHZCE2 CE HIGH to
High Z[9,10] 5 7 9 11 15 15 ns
tPU CE LOW to
Power-Up 0 00000ns
tPD CE HIGH to
Power-Down 12 15 20 25 35 45 ns
WRITE CYCLE[11]
tWC Write Cycle Time 12 15 20 25 35 45 ns
tSCE CE LOW to Write End 910 15 18 22 22 ns
tAW Address Set-Up to
Writ e End 910 15 20 25 35 ns
tHA Add ress Hol d from
Writ e End 0 00000ns
tSA Address Set-Up to
Writ e Start 0 00000ns
tPWE WE Pulse Width 8 9 15 18 22 22 ns
tSD Data Set- Up to
Writ e End 8 9 10 10 15 15 ns
tHD Data Hold from
Writ e End 0 00000ns
tLZWE WE HIGH to
Low Z[9] 3 33333ns
tHZWE WE LOW to
High Z[9,8] 7 7 10 013 015 020 ns
Shaded area contains preliminary information.
Notes:
8. Test conditions assume signal transi tion time of 3 ns or less f or -12 and - 15 speeds and 5 ns or l ess f or -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load c apacitance.
9. At any given temperature and vol tage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE f or any given de vice.
10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of A C Test Loads. Transiti on is measured ±500 mV from steady-state voltage.
11. The internal write time of the memory i s defined by the overlap of CE1 LOW, CE2 LO W, and WE LOW . All signals mus t be LOW to i nitiate a write and any si gnal can
terminate a write by going HIGH. T he data input set-up and hold timi ng should be referenced to the rising edge of the signal that terminates the write.
CY7C194
CY7C195
CY7C196
5
Swi tch i ng Waveform s
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected: CE1 = VIL, CE2 = VIL (7C196), and OE = VIL (7C195 and 7C196).
14. Address valid prior to or coincident with CE1 and CE2 transition LO W.
15. Data I/O will be high impedance if OE = VIH (7C195 and 7C196).
16. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Read Cycle No. 1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C194-8
[12,13]
[12,14]
Read Cycle No. 2
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
C194-9
ICC
ISB
IMPEDANCE
CE1,CE
2
OE
(7C195and
7C196)
DATA OUT
VCC
SUPPLY
CURRENT
C194-10
WriteCycleNo.1(CEControlled)
tWC
DATA VALID
tAW
tSA tHA
tHD
tSD
tSCE
[11,15,16]
WE
DATA I/O
ADDRESS
CE1
CE2
(7C196)
CY7C194
CY7C195
CY7C196
6
Note:
17. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Swi tch i ng Waveform s (continued )
Write Cycle No. 2 (WE Controlled, OEHIGHDuringWrite for 7C195and 7C196only)
DATA VALI D
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATA I/O
ADDRESS
WE
OE
CE1
CE2(7C196)
C194-12
[11,15,16]
WriteCycleNo.3(WEControlled, OE LOW)
DATA VALID
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
WE
tHZWE C194-11
CE1
CE2(7C196)
[16,17]
Typical DC and AC Characteristi cs
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.0
0.8
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.6
0.4
0.2
0.0
NORMALIZED I , I
CC SB
NORMALIZED I , I
CC SB
ISB
ICC
ICC
VCC =5.0V
TA=25°C
ISB 0
VIN =5.0V
TA=25°C
1.4
VCC =5.0V
VIN =5.0V
CY7C194
CY7C195
CY7C196
7
Typical DC and AC Characteristi cs (conti nued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED IPO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUTLOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLE TIME
0.0 5.0 0.0 1000 0.50
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VIN =0.5V
1.6
1.4
1.2
1.0
0.8
−55 25 125
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.4
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SI NK CURRENT (mA)
0
80
OUTPUT VO LTAGE (V )
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
VCC =5.0V VCC =5.0V
TA=25°C
TA=25°C
0.6
0.8
AA
1.3
1.2
7C194 Truth Table
CE WE Data I/O Mode Power
H X High Z Deselect/Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L Data In Write Active (I CC)
7C195 Truth Table
CE1WE OE Data I/ O Mode Power
H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Da ta In Write Activ e (ICC)
L H H High Z Deselect Activ e (ICC)
7C196 Truth Table
CE1CE2WE OE Data I/O Mode Power
H X X X High Z Deselect/Power-Down S t andby (ISB)
X H X X
L L H L Data Out Read Activ e (ICC)
L L L X Data In Write Active (ICC)
L L H H High Z Deselect Active (ICC)
CY7C194
CY7C195
CY7C196
8
Sh aded areas contain pr elimin ary inform ation.
Ordering Information
Speed
(ns) Or dering Code Package
Name Package Type Operating
Range
12 CY7C194-12PC P13 24-Lead (300-Mil ) Molded DIP Commercial
CY7C194-12VC V13 24-Lead Molded SOJ
15 CY7C194-15PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C194-15VC V13 24-Lead Molded SOJ
CY7C194-15DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C194-15LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier
20 CY7C194-20PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C194-20VC V13 24-Lead Molded SOJ
CY7C194-20DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C194-20LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier
25 CY7C194-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C194-25VC V13 24-Lead Molded SOJ
CY7C194-25DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C194-25LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier
35 CY7C194-35PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C194-35VC V13 24-Lead Molded SOJ
CY7C194-35DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C194-35LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier
45 CY7C194-45DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C194-45LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier
Speed
(ns) Or dering Code Package
Name Package Type Operating
Range
12 CY7C195-12PC P21 28-Lead (300-Mil ) Molded DIP Commercial
CY7C195-12VC V21 28-Lead Molded SOJ
15 CY7C195-15PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C195-15VC V21 28-Lead Molded SOJ
20 CY7C195-20PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C195-20VC V21 28-Lead Molded SOJ
25 CY7C195-25PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C195-25VC V21 28-Lead Molded SOJ
35 CY7C195-35PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C195-35VC V21 28-Lead Molded SOJ
CY7C194
CY7C195
CY7C196
9
)
Sh aded area cont ains prelimin ary inform ation.
Ordering Information (continued
Speed
(ns) Or dering Code Package
Name Package Type Operating
Range
12 CY7C196-12PC P21 28-Lead (300-Mil ) Molded DIP Commercial
CY7C196-12VC V21 28-Lead Molded SOJ
15 CY7C196-15PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C196-15VC V21 28-Lead Molded SOJ
CY7C196-15LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier Military
20 CY7C196-20PC P21 28-Lead (300-Mil ) Molded DIP Commercial
CY7C196-20VC V21 28-Lead Molded SOJ
CY7C196-20LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier Military
25 CY7C196-25PC P21 28-Lead (300-Mil ) Molded DIP Commercial
CY7C196-25VC V21 28-Lead Molded SOJ
CY7C196-25LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier Military
35 CY7C196-35PC P21 28-Lead (300-Mil ) Molded DIP Commercial
CY7C196-35VC V21 28-Lead Molded SOJ
CY7C196-35LMB L54 28-Pin Rect ang ular L eadless Chi p Carrier Military
45 CY7C196-45LMB L54 28-Pin Rect angula r L eadless Chip Car rier Military
MILITAR Y SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
IOS 1, 2, 3
ICC 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3
Switching Characteristics
Parameter Subgroups
READ CYCLE
tRC 7, 8, 9, 10, 11
tAA 7, 8, 9, 10, 11
tOHA 7, 8, 9, 10, 11
tACE, ACE2 7, 8, 9, 10, 11
tDOE[18] 7, 8, 9, 10, 11
WRITE CYCLE
tWC 7, 8, 9, 10, 11
tSCE 7, 8, 9, 10, 11
tAW 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tSA 7, 8, 9, 10, 11
tPWE 7, 8, 9, 10, 11
tSD 7, 8, 9, 10, 11
tHD 7, 8, 9, 10, 11
Note:
18. 7C195 and 7C196 only.
Docume nt #: 38-00081- J
CY7C194
CY7C195
CY7C196
10
Package Di ag r ams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D-9 C on fig . A 28-Pin Rectangular Leadless Chip Carrier L54
M IL-ST D-1835 C-11A
24-Lead (300-Mil) Molded DIP P13/P13A
CY7C194
CY7C195
CY7C196
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no res ponsibility for the use
of any circuit ry other tha n circu itry emb odied i n a Cyp res s Sem iconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semi condu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cy press Semiconductor against all charges.
Package Di ag r ams (continued)
24-Lead Molded SOJ V13
28-Lead Molded SOJ V21
28-Lead (300-Mil) Molded DIP P21
