CY7C194 CY7C195 CY7C196 64K x 4 Static RAM Features able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected. * High speed -- 12 ns * Output enable (OE) feature (7C195 and 7C196) * CMOS for optimum speed/power * Low active power -- 880 mW * Low standby power -- 220 mW * TTL-compatible inputs and outputs * Automatic power-down when deselected Writing to the device is accomplished when the chip enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and write enable (WE) inputs are both LOW. Data on the four input pins (I/O0 through I/O 3) is written into the memory location, specified on the address pins (A0 through A15). Reading the device is accomplished by taking the chip enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) LOW, while write enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. Functional Description The CY7C194, CY7C195, and CY7C196 are high-performance CMOS static RAMs organized as 65,536 by 4 bits. Easy memory expansion is provided by active LOW chip en- A die coat is used to ensure alpha immunity. Pin Configurations DIP/SOJ Top View DIP/SOJ Top View A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I/O2 WE (OE) (7C195 and 7C196 ONLY) A15 A0 A11 A12 A13 A14 CE2 (7C196 only) CE1 1 2 3 4 5 6 7C195 7 7C196 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE CE2 (7C196) NC (7C195) C194-2 I/O1 POWER DOWN NC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE1 OE GND LCC Top View I/O0 COLUMN DECODER VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE LCC Top View A7 A6 NC VCC NC 1024 x 64 x 4 ARRAY CE GND 24 23 22 21 20 19 18 17 16 15 14 13 3 2 1 28 27 4 26 5 25 6 24 7 23 8 22 7C194 9 21 10 20 11 19 12 18 1314151617 A8 A9 A10 A11 A12 A13 A14 A15 CE NC GND NC WE I/O0 C194-1 C194-3 A7 A6 NC VCC A5 I/O3 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 ROW DECODER INPUT BUFFER 1 2 3 4 5 6 7C194 7 8 9 10 11 12 A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 A8 A9 A10 A11 A12 A13 A14 A15 CE1 C194-4 3 2 1 28 27 4 26 A4 5 25 A3 6 24 A2 7 23 A1 8 22 A0 7C196 9 21 NC 10 20 CE2 11 19 I/O3 12 18 I/O2 1314151617 OE GND WE I/O0 I/O1 Logic Block Diagram C194-5 Selection Guide Maximum Access Time (ns) Maximum Operating Commercial Current (mA) Military 7C194-12 7C195-12 7C196-12 12 155 Maximum Standby Current (mA) 30 7C194-15 7C195-15 7C196-15 15 145 160 30 7C194-20 7C195-20 7C196-20 20 135 150 30 7C194-25 7C195-25 7C196-25 25 115 125 30 7C194-35 7C195-35 7C196-35 35 115 125 30 7C194-45 7C196-45 45 125 30 Shaded area contains preliminary information. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 December 1987 - Revised December 1994 CY7C194 CY7C195 CY7C196 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Operating Range Range Ambient Temperature VCC Commercial 0C to +70C 5V 10% -55C to +125C 5V 10% Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Military DC Input Voltage[1].................................-0.5V to VCC + 0.5V [2] ] Electrical Characteristics Over the Operating Range[3] 7C194-12 7C195-12 7C196-12 Parameter Description Test Conditions Min. Max. 7C194-15 7C195-15 7C196-15 Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3V VIL[1] Input LOW Voltage -0.5 IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC =Max., IOUT =0 mA, f =fMAX =1/tRC ISB1 Automatic CE Power-Down Current --TTL Inputs[5] Max. VCC, CE1,2 > VIH, VIN > VIH or VIN < V IL, f = fMAX 30 30 mA ISB2 Automatic CE Power-Down Current --CMOS Inputs[5] Max. VCC, CE1,2 > VCC - 0.3V, Com'l VIN > VCC - 0.3V or Mil VIN < 0.3V, f = 0 10 10 mA 2.4 2.4 0.4 Com'l 0.4 V 2.2 VCC + 0.3V V 0.8 -0.5 0.8 V -5 +5 -5 +5 A -5 +5 -5 +5 A -300 -300 mA 155 145 mA Mil 160 Shaded area contains preliminary information. Notes: 1. Minimum voltage is equal to -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2 V 15 CY7C194 CY7C195 CY7C196 ) Electrical Characteristics Over the Operating Range[3] (continued) 7C194-20 7C195-20 7C196-20 Parameter Description Test Conditions Min. 7C194-25, 35, 45 7C195-25, 35 7C196-25, 35, 45 Max. Min. VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3V VIL Input LOW Voltage -0.5 IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC=Max., IOUT=0 mA, f=fMAX=1/tRC ISB1 Automatic CE Power-Down Current --TTL Inputs[5] Max. VCC, CE1,2 > VIH, VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-Down Current --CMOS Inputs[5] Max. VCC, CE1,2 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0 2.4 Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC +0.3V V 0.8 -0.5 0.8 V -5 +5 -5 +5 A -5 +5 -5 +5 A -300 -300 mA Com'l 135 115 mA Mil 150 125 30 30 mA 15 15 mA Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 10 pF AC Test Loads and Waveforms[7] R1 481 5V OUTPUT R1 481 5V ALL INPUT PULSES OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE (a) 3.0V 5 pF R2 255 INCLUDING JIG AND SCOPE (b) GND < tr C194-6 Equivalent to: THE EVENIN EQUIVALENT 167 OUTPUT 1.73V Notes: 6. Tested initially and after any design or process changes that may affect these parameters. 7. tr = < 3 ns for the -12 and -15 speeds. tr = < 5 ns for the -20 and slower speeds. 3 90% 10% 90% 10% < tr C194-7 CY7C194 CY7C195 CY7C196 : Switching Characteristics Over the Operating Range[3, 8] 7C194-12 7C195-12 7C196-12 Parameter Description Min. Max. 7C194-15 7C195-15 7C196-15 7C194-20 7C195-20 7C196-20 7C194-25 7C195-25 7C196-25 7C194-35 7C195-35 7C196-35 Min. Max. Min. Max. Min. Max. Min. Max. 7C194-45 7C196-45 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold from Address Change tACE1, tACE2 CE LOW to Data Valid tDOE OE LOW to Data Valid 7C195, 7C196 tLZOE OE LOW to Low Z 7C195, 7C196 tHZOE OE HIGH to High Z[10] 7C195, 7C196 tLZCE1, tLZCE2 CE LOW to Low Z[9] tHZCE1, tHZCE2 CE HIGH to High Z[9,10] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 12 15 12 3 20 15 25 20 3 3 35 25 3 45 35 3 ns 45 3 ns ns 12 15 20 25 35 45 ns 5 7 9 10 16 16 ns 0 0 5 3 0 7 9 3 5 0 3 7 3 0 15 3 11 9 0 12 3 15 3 11 0 20 3 15 3 15 0 25 ns ns 15 0 35 ns ns ns 45 ns WRITE CYCLE[11] tWC Write Cycle Time 12 15 20 25 35 45 ns tSCE CE LOW to Write End 9 10 15 18 22 22 ns tAW Address Set-Up to Write End 9 10 15 20 25 35 ns tHA Address Hold from Write End 0 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 0 ns tPWE WE Pulse Width 8 9 15 18 22 22 ns tSD Data Set-Up to Write End 8 9 10 10 15 15 ns tHD Data Hold from Write End 0 0 0 0 0 0 ns tLZWE WE HIGH to Low Z[9] 3 3 3 3 3 3 ns tHZWE WE LOW to High Z[9,8] 7 7 10 0 13 0 15 0 20 ns Shaded area contains preliminary information. Notes: 8. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 10. t HZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 4 CY7C194 CY7C195 CY7C196 Switching Waveforms Read Cycle No. 1 [12,13] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C194-8 Read Cycle No. 2 [12,14] t RC CE1, CE2 tACE OE (7C195and 7C196) DATA OUT t HZOE t HZCE tDOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID t LZCE VCC SUPPLY CURRENT tPD t PU ICC 50% 50% ISB C194-9 Write Cycle No. 1 (CE Controlled) [11,15,16] tWC ADDRESS CE1 CE2 (7C196) tSCE tSA tHA tAW WE tSD DATA I/O tHD DATA VALID C194-10 Notes: 12. WE is HIGH for read cycle. 13. Device is continuously selected: CE1 = VIL, CE2 = VIL (7C196), and OE = VIL (7C195 and 7C196). 14. Address valid prior to or coincident with CE1 and CE2 transition LOW. 15. Data I/O will be high impedance if OE = VIH (7C195 and 7C196). 16. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 5 CY7C194 CY7C195 CY7C196 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write for 7C195 and 7C196only) [11,15,16] tWC ADDRESS CE1 CE2 (7C196) tAW tHA tSA WE tPWE OE tSD DATA I/O tHD DATA VALID C194-12 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW) [16,17] tWC ADDRESS CE1 CE2 (7C196) tAW tHA tSA WE tHD tSD DATA I/O DATA VALID tLZWE tHZWE C194-11 Note: 17. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB NORMALIZED ICC, I SB 1.4 1.2 ICC 1.0 0.8 0.6 VIN =5.0V TA =25C 0.4 0.2 0.0 4.0 1.2 1.0 0.8 0.6 4.5 5.0 5.5 SUPPLY VOLTAGE(V) 6.0 VCC =5.0V VIN =5.0V 0.4 0.2 ISB ICC 0.0 -55 ISB 25 125 AMBIENT TEMPERATURE(C) 6 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC =5.0V TA =25C 60 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE(V) 4.0 CY7C194 CY7C195 CY7C196 Typical DC and AC Characteristics (continued) 1.6 1.4 NORMALIZED t AA 1.2 1.1 TA =25C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 -55 6.0 25 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 DELTA tAA (ns) 3.0 2.0 1.5 1.0 0.0 0.0 140 120 100 80 60 VCC =5.0V TA =25C 40 20 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED I CC vs.CYCLE TIME 1.25 20.0 15.0 VCC =4.5V TA =25C 10.0 0.5 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 0 0.0 125 NORMALIZED I CC NORMALIZED t AA 1.3 NORMALIZED IPO OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.00 VCC =5.0V TA =25C VIN =0.5V 0.75 5.0 1.0 2.0 3.0 4.0 0.0 5.0 0 SUPPLY VOLTAGE (V) 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 CYCLE FREQUENCY (MHz) 7C194 Truth Table CE H WE X L L H L High Z Data I/O Mode Deselect/Power-Down Power Standby (ISB) Data Out Data In Read Write Active (ICC) Active (ICC) 7C195 Truth Table CE1 H L WE X H OE X L L L L H X H High Z Data Out Data I/O Mode Deselect/Power-Down Read Power Standby (ISB) Active (ICC) Data In High Z Write Deselect Active (ICC) Active (ICC) 7C196 Truth Table CE1 CE2 WE OE Data I/O Mode H X X H X X X X High Z Deselect/Power-Down Standby (ISB) L L L L H L L X Data Out Data In Read Write Active (ICC) Active (ICC) L L H H High Z Deselect Active (ICC) 7 Power 40 CY7C194 CY7C195 CY7C196 Ordering Information Speed (ns) 12 15 20 25 35 45 Speed (ns) 12 15 20 25 35 Ordering Code Package Name Package Type CY7C194-12PC P13 24-Lead (300-Mil) Molded DIP CY7C194-12VC V13 24-Lead Molded SOJ CY7C194-15PC P13 24-Lead (300-Mil) Molded DIP CY7C194-15VC V13 24-Lead Molded SOJ CY7C194-15DMB D14 24-Lead (300-Mil) CerDIP CY7C194-15LMB L54 28-Pin Rectangular Leadless Chip Carrier CY7C194-20PC P13 24-Lead (300-Mil) Molded DIP CY7C194-20VC V13 24-Lead Molded SOJ CY7C194-20DMB D14 24-Lead (300-Mil) CerDIP CY7C194-20LMB L54 28-Pin Rectangular Leadless Chip Carrier CY7C194-25PC P13 24-Lead (300-Mil) Molded DIP CY7C194-25VC V13 24-Lead Molded SOJ CY7C194-25DMB D14 24-Lead (300-Mil) CerDIP CY7C194-25LMB L54 28-Pin Rectangular Leadless Chip Carrier CY7C194-35PC P13 24-Lead (300-Mil) Molded DIP CY7C194-35VC V13 24-Lead Molded SOJ CY7C194-35DMB D14 24-Lead (300-Mil) CerDIP CY7C194-35LMB L54 28-Pin Rectangular Leadless Chip Carrier CY7C194-45DMB D14 24-Lead (300-Mil) CerDIP CY7C194-45LMB L54 28-Pin Rectangular Leadless Chip Carrier Package Name Package Type Ordering Code CY7C195-12PC P21 28-Lead (300-Mil) Molded DIP CY7C195-12VC V21 28-Lead Molded SOJ CY7C195-15PC P21 28-Lead (300-Mil) Molded DIP CY7C195-15VC V21 28-Lead Molded SOJ CY7C195-20PC P21 28-Lead (300-Mil) Molded DIP CY7C195-20VC V21 28-Lead Molded SOJ CY7C195-25PC P21 28-Lead (300-Mil) Molded DIP CY7C195-25VC V21 28-Lead Molded SOJ CY7C195-35PC P21 28-Lead (300-Mil) Molded DIP CY7C195-35VC V21 28-Lead Molded SOJ Shaded areas contain preliminary information. 8 Operating Range Commercial Commercial Military Commercial Military Commercial Military Commercial Military Military Operating Range Commercial Commercial Commercial Commercial Commercial CY7C194 CY7C195 CY7C196 ) Ordering Information (continued Speed (ns) 12 15 20 25 35 45 Ordering Code Package Name Operating Range Package Type CY7C196-12PC P21 28-Lead (300-Mil) Molded DIP CY7C196-12VC V21 28-Lead Molded SOJ Commercial CY7C196-15PC P21 28-Lead (300-Mil) Molded DIP CY7C196-15VC V21 28-Lead Molded SOJ CY7C196-15LMB L54 28-Pin Rectangular Leadless Chip Carrier Military CY7C196-20PC P21 28-Lead (300-Mil) Molded DIP CY7C196-20VC V21 28-Lead Molded SOJ CY7C196-20LMB L54 28-Pin Rectangular Leadless Chip Carrier Military CY7C196-25PC P21 28-Lead (300-Mil) Molded DIP CY7C196-25VC V21 28-Lead Molded SOJ CY7C196-25LMB L54 28-Pin Rectangular Leadless Chip Carrier Military CY7C196-35PC P21 28-Lead (300-Mil) Molded DIP CY7C196-35VC V21 28-Lead Molded SOJ CY7C196-35LMB L54 28-Pin Rectangular Leadless Chip Carrier Military CY7C196-45LMB L54 28-Pin Rectangular Leadless Chip Carrier Military Commercial Commercial Commercial Commercial Shaded area contains preliminary information. Switching Characteristics MILITARY SPECIFICATIONS Group A Subgroup Testing Parameter READ CYCLE DC Characteristics Parameter Subgroups Subgroups tRC 7, 8, 9, 10, 11 tAA 7, 8, 9, 10, 11 VOH 1, 2, 3 tOHA 7, 8, 9, 10, 11 VOL 1, 2, 3 tACE, ACE2 7, 8, 9, 10, 11 VIH 1, 2, 3 tDOE[18] 7, 8, 9, 10, 11 VIL Max. 1, 2, 3 WRITE CYCLE IIX 1, 2, 3 tWC 7, 8, 9, 10, 11 IOZ 1, 2, 3 tSCE 7, 8, 9, 10, 11 IOS 1, 2, 3 tAW 7, 8, 9, 10, 11 ICC 1, 2, 3 tHA 7, 8, 9, 10, 11 ISB1 1, 2, 3 tSA 7, 8, 9, 10, 11 ISB2 1, 2, 3 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 Note: 18. 7C195 and 7C196 only. Document #: 38-00081-J 9 CY7C194 CY7C195 CY7C196 Package Diagrams 28-Pin Rectangular Leadless Chip Carrier L54 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 MIL-STD-1835 C-11A D- 9 Config.A 24-Lead (300-Mil) Molded DIP P13/P13A 10 CY7C194 CY7C195 CY7C196 Package Diagrams (continued) 24-Lead Molded SOJ V13 28-Lead Molded SOJ V21 28-Lead (300-Mil) Molded DIP P21 (c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.