1/14November 2004
■HIGH SPE ED:
■fMAX = 180 MHz (TYP.) at VCC = 5V
■LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
■HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
■POWER DOWN PROTEC TION ON INPUTS
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
■BALANCED PRO PAGATION DELAYS :
tPLH ≅ tPHL
■OPERATING VO LTAGE RANGE:
VCC(OPR) = 2V to 5.5V
■PIN AND FUNCTION COMPATIBLE WITH
74 SERIE S 574
■IMPROVED L ATCH-UP I MMU NI T Y
■LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHC574 is an advanced high-speed
CMOS OC TA L D -TYP E FLI P FLO P wi t h 3 S TA TE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS techn ology.
These 8 bit D-T ype flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic states that were
setup at the D inputs.
While the ( OE) input is low, the 8 output s will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impe dance s tate.
The Output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC574
OC TAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERT ING
Fi gure 1: Pin Connect ion An d I E C Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74VHC574MTR
TSSOP 74VHC574TTR
TSSOPSOP
Rev. 4