SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. * * * * OCTAL D FLIP-FLOP WITH CLEAR 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 20 19 D7 18 D6 17 Q6 Q5 16 15 D5 14 D4 13 Q4 CP 12 11 J SUFFIX CERAMIC CASE 732-03 20 1 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 PIN NAMES 10 GND N SUFFIX PLASTIC CASE 738-03 20 LOADING (Note a) 1 CP D0 - D7 MR Q0 - Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b) HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 20 1 NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. ORDERING INFORMATION TRUTH TABLE MR CP Dx Qx L H H X X H L L H L DW SUFFIX SOIC CASE 751D-03 SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 CP 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS FAST AND LS TTL DATA 5-1 SN54/74LS273 FUNCTIONAL DESCRIPTION independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 - 55 0 25 25 125 70 C IOH Output Current -- High 54, 74 - 0.4 mA IOL Output Current -- Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max U i Unit 2.0 54 0.7 74 0.8 - 0.65 - 1.5 T Test C Conditions di i V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input p LOW Voltage g for All Inputs V VCC = MIN, IIN = - 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 A VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V - 0.4 mA VCC = MAX, VIN = 0.4 V - 100 mA VCC = MAX 27 mA VCC = MAX - 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits S b l Symbol P Parameter Min Typ 30 40 Max U i Unit T Test C Conditions di i MHz Figure 1 fMAX Maximum Input Clock Frequency tPHL Propagation Delay, MR to Q Output 18 27 ns Figure 2 tPLH tPHL Propagation Delay, Clock to Output 17 18 27 27 ns Figure 1 FAST AND LS TTL DATA 5-2 SN54/74LS273 AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits U i Unit T Test C Conditions di i tw S b l Symbol Pulse Width, Clock or Clear P Parameter 20 ns Figure 1 ts Data Setup Time 20 ns Figure 1 th Hold Time 5.0 ns Figure 1 trec Recovery Time 25 ns Figure 2 Min Typ Max AC WAVEFORMS 1/f max tW CP 1.3 V 1.3 V ts(H) D * Qn ts(L) trec 1.3 V tPLH tPHL 1.3 V 1.3 V tPHL tPLH 1.3 V CP th(L) 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V th(H) tW MR Qn tPHL 1.3 V 1.3 V 1.3 V 1.3 V tPLH Qn *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued FAST AND LS TTL DATA 5-3