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FEATURES
10 years minimu m data retention in the
absence o f exter na l po wer
Dat a is aut omatical l y p r ot ected during power
loss
Unlim ited write cycles
Low-pow er CMO S operation
Read and wr it e acces s times of 70 ns
Lithium energy sour ce is elect rically
d iscon nect ed to retain freshness until power is
applied for the first time
Full ± 10% VCC o perating r ange (DS1249Y)
Optional ± 5% VCC o perating range
(DS1249AB)
Optional indust r ial temperatur e range of
-40°C to +85°C, des ignated I N D
JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A17 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip E na ble
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
NC - No Connect
DESCRIPTION
The DS1249 2048k Nonvo lat ile SRAMs are 2,097,152-bit , fully stat ic, no nvo lat ile SR AMs organized as
262,144 words by 8 bits. E ach NV SRAM ha s a self-contained lithiu m energ y source and co nt ro l cir cuit ry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
a d dition al s up port circuit ry is required for micro pr ocessor interfacing.
DS1249Y/AB
2048k Nonvolatile SRAM
19-5631; Rev 11/10
www.maxim-ic.com
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2
3
4
5
6
7
8
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31
740-mil EXTENDED
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
DS1249Y/AB
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READ MODE
The DS1249 devices execut e a read cyc le w he ne ver
WE
(Writ e Enable) is inact ive (high) and
CE
(Chip
Ena ble ) and
OE
(Output Enable) are active (lo w). The unique address specified by the 18 address input s
(A0 - A17) define s w hich of the 262,144 bytes of data is accessed. Valid data will be available to the eig ht
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that
CE
and
OE
access t imes ar e a lso sat isfied . I f
OE
and
CE
acces s t ime s are not sat isf ied, t hen data acce ss
must be measured fro m t he later-o cc ur r ing s igna l (
CE
or
OE
) and t he l imit ing par amet er is e ither t CO for
CE
or tOE for
OE
r athe r than tACC.
WRITE MODE
The DS1249 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stab le. T he later -occurr ing fa lling edge of
CE
or WE w ill det ermine t he start o f the wr ite c yc le.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during writ e
c yc le s t o avo id bus c ont ent io n. H oweve r, if t he o ut p ut drivers a re e nabled (
CE
and
OE
ac tive) t hen
WE
will disab le the outp uts in tODW from it s fa lling edg e.
DATA RETENTION MODE
The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1249Y provides full-functional capability for VCC greater than 4.5 volts and write
prot ect s by 4. 25 vo lt s. Dat a is maint ained in the abse nce of VCC wit ho ut any add it io nal support c ircu it ry.
The nonvolatile static RAMs constantly mo nitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
t he po wer sw itching c ircuit connect s exter na l V CC to t he RAM and d iscon nect s the lithiu m e ner gy so ur ce.
No rma l RAM oper at io n can re su me after VCC exceeds 4.75 vo lt s fo r the DS1249AB and 4. 5 volts fo r t he
DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is
enabled for bat ter y backup operation.
DS1249Y/AB
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6. 0V
Operating T emperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e Range -40°C to +85°C
Lead Temperature (soldering, 10s) +260°C
Note: EDIP is wave or ha nd soldered o nly.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1249AB Power S upply Voltage VCC 4.75 5.0 5.25 V
DS1249Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1249AB)
(TA: See Note 10) (VCC = 5V ±10 % for DS 1249Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -2.0 +2.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -2.0 +2.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Curr ent
CE
=2.2V ICCS1 1.0 1.5 mA
St andby Curr ent
CE
=VCC-0.5V ICCS2 100 150 µA
Operating Cur r ent ICCO1 85 mA
Writ e Pr otection Voltage (DS1249AB) VTP 4.50 4.62 4.75 V
Writ e Pr otection Voltage (DS1249Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 10 20 pF
I nput/O utput C apa cita nce CI/O 10 20 pF
DS1249Y/AB
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AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1249AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1249Y)
PARAMETER SYMBOL DS1249AB-70
DS1249Y-70 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE
to O utput Va lid tOE 35 ns
CE
to O utput Va lid tCO 70 ns
OE
or
CE
to O utput Ac tive tCOE 5 ns 5
Out put High-Z from D es election tOD 25 ns 5
Output Hold fro m Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
A ddress Setup Time tAW 0 ns
Write Reco ver y Ti me tWR1
tWR2
5
15
ns
ns 12
13
Out put High-Z f r om
WE
tODW 25 ns 5
Output Active from
WE
tOEW 5 ns 5
Da ta Setup Time tDS 30 ns 4
Da ta Hold Time tDH1
tDH2
0
10
ns
ns 12
13
DS1249Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1249Y/AB
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WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
DS1249Y/AB
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POWER-DOWN/POWER-UP TIMING (TA: See N ot e 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC sl ew f rom VTP t o 0V tF 150 µs
VCC slew from 0 V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Protection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Retent ion T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH during write cycle, t he o ut put buffers remain in a high impedan ce state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
going lo w to the earlier of
CE
or
WE
go ing h igh.
4. tDS is measur ed from the ear lier o f
CE
or
WE
going high.
5. T hese para met er s ar e sampled with a 5 pF load an d ar e not 100 % tested .
6. If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition in Write
Cycle 1, the outp ut buf fers remain in a high-impedance state during this per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h-impeda nce st ate during this period.
8. If
WE
is low or th e
WE
lo w t ra ns ition o cc ur s p r io r to or s imu lt a neo us ly w it h t he
CE
lo w t ra ns ition ,
the output bu f f e rs remain in a high-impedance state during this period.
9. Each DS1249 has a bu ilt -in sw it c h that d isco nnect s the lithiu m source u nt il the user fir st app lies VCC.
The e xpected tDR is defined as accumulative time in t he a bse nce of VCC starting fro m the t ime power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production test ing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For indust ria l pro ducts (IND), this range is -40°C t o
+85°C.
11. I n a po wer-dow n conditio n the volt age on an y pin may no t exc ee d the volt age on VCC.
12. tWR1 and tDH1 are mea sur ed fro m
WE
go ing h ig h.
13. tWR2 and tDH2 are mea sur ed from
CE
go ing h ig h.
14. DS1249 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DS1249Y/AB
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DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating curr ent I nput Pulse Levels: 0 - 3.0V
All voltages ar e r eferenced to ground Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1. 5V
Input puls e R ise and Fall Times: 5 ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1249AB-70#
0°C to +70°C
5V ± 5%
32 740 EDIP
70
DS1249AB-70IND#
-40°C to +85°C
5V ± 5%
32 740 EDIP
70
DS1249Y-70#
0°C to +70°C
5V
±
10%
32 740 EDIP
70
DS1249Y-70IND#
-40°C to +85°C
5V ± 10%
32 740 EDIP
70
#Denotes a RoHS-compliant devi ce that may include l e ad(Pb) that is exem pt under the R oHS requirem ents.
PACKAGE INFORMATION
For the latest package outline informa ti on a nd land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr aw ing pertains to the p ackag e regard less of RoHS s tatus.
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT32#7 21-0245 —
DS1249Y/AB
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
11/10
Updated the storage information, soldering temperature, and lead
t emperat ur e info rmation in t he Absolute Maximum Ratings section;
r emove d the -100 M IN/ M A X i n form a tion fr om th e AC Electrical
Characteristics table; updated the Ordering Inf ormation table (removed -
100 parts and leaded -70 parts); updated the Package Information table
1, 3, 4, 8