General Description
The MAX4691–MAX4694 are low-voltage CMOS analog
ICs configured as an 8-channel multiplexer (MAX4691),
two 4-channel multiplexers (MAX4692), three single-
pole/double-throw (SPDT) switches (MAX4693), and
four SPDT switches (MAX4694).
The MAX4691/MAX4692/MAX4693 operate from either
a single +2V to +11V power supply or dual ±2V to
±5.5V power supplies. When operating from ±5V sup-
plies they offer 25Ωon-resistance (RON), 3.5Ω(max)
RON flatness, and 3Ω(max) matching between chan-
nels. The MAX4694 operates from a single +2V to +11V
supply. Each switch has rail-to-rail signal handling and
a low 1nA leakage current.
All digital inputs are 1.8V logic-compatible when oper-
ating from a +3V supply and TTL compatible when
operating from a +5V supply.
The MAX4691–MAX4694 are available in 16-pin,
4mm 4mm QFN and TQFN and 16-bump UCSP pack-
ages. The chip-scale package (UCSP™) occupies a
2mm 2mm area, significantly reducing the required
PC board area.
Applications
Audio and Video Signal Routing
Cellular Phones
Battery-Operated Equipment
Communications Circuits
Modems
Features
o16 Bump, 0.5mm-Pitch UCSP (2mm x 2mm)
o1.8V Logic Compatibility
oGuaranteed On-Resistance
70Ω(max) with +2.7V Supply
35Ω(max) with +5V Supply
25Ω(max) with ±4.5V Dual Supplies
oGuaranteed Match Between Channels
5Ω(max) with +2.7V Supply
3Ω(max) with ±4.5V Dual Supplies
oGuaranteed Flatness Over Signal Range
3.5Ω(max) with ±4.5V Dual Supplies
oLow Leakage Currents Over Temperature
20nA (max) at +85°C
oFast 90ns Transition Time
oGuaranteed Break-Before-Make
oSingle-Supply Operation from +2V to +11V
oDual-Supply Operation from ±2V to ±5.5V
(MAX4691/MAX4692/MAX4693)
oV+ to V- Signal Handling
oLow Crosstalk: -90dB (100kHz)
oHigh Off-Isolation: -88dB (100kHz)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
________________________________________________________________
Maxim Integrated Products
1
Functional Diagrams
19-1945; Rev 6; 1/12
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
PART
TEMP RANGE
PIN-PACKAGE
MAX4691EBE+T
-40°C to +85°C
16-Bump UCSP*
MAX4691EGE+
-40°C to +85°C
16 QFN-EP†
MAX4691ETE+T
-40°C to +85°C
16 TQFN-EP†
MAX4692EBE+T
-40°C to +85°C
16-Bump UCSP*
MAX4692EGE+
-40°C to +85°C
16 QFN-EP†
MAX4692ETE+T
-40°C to +85°C
16 TQFN-EP†
MAX4693EBE+T
-40°C to +85°C
16-Bump UCSP*
MAX4693EGE+
-40°C to +85°C
16 QFN-EP†
MAX4693ETE+T
-40°C to +85°C
16 TQFN-EP†
MAX4694EBE+T
-40°C to +85°C
16-Bump UCSP*
MAX4694EGE+
-40°C to +85°C
16 QFN-EP†
MAX4694ETE+T
-40°C to +85°C
16 TQFN-EP†
Ordering Information
*UCSP reliability is integrally linked to the user’s assembly meth-
ods, circuit board, and environment. See the UCSP Reliability
section for more information.
†
EP = Exposed pad.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
MAX4691
X0
X1
X2
X3
X4
X5
X6
X7
LOGIC
CBA
EN
X
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +2.7V to +3.6V, V- = 0V, VIH = +1.4V, VIL = +0.4V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Notes 2, 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND ..............................................................-0.3V to +12V
V+ to V- (MAX4691/MAX4692/MAX4693) ..............-0.3V to +12V
Voltage into any Terminal (Note 1) ...... (V- - 0.3V) to (V+ + 0.3V)
Continuous Current into any Terminal ............................. ±20mA
Peak Current W_, X_, Y_, Z_ (pulsed at 1ms,
10% duty cycle)...........................................................±40mA
ESD per Method 3015.7......................................................> 2kV
Continuous Power Dissipation (TA= +70°C)
16-Bump UCSP (derate 8.2mW/°C above +70°C) .... 659mW
16-Pin QFN (derate 18.5mW/°C above +70°C) ....... 1481mW
16-Pin TQFN (derate 16.9mW/°C above +70°C) ..... 1349mW
Operating Temperature Range .......................... -40°C to +85°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (TQFN, QFN only, soldering, 10s).... +300°C
Soldering Temperature (reflow) ...................................... +260°C
Note 1: Voltages exceeding V+ or V- on any signal terminal are clamped by internal diodes. Limit forward-diode current to maxi-
mum current rating.
PARAMETER
SYMBOL
CONDITIONS TA
MIN TYP MAX
UNITS
ANALOG SWITCH
Analog Signal Range
V
W, V
X
, V
Y
,
V
Z
,
V
W_,
V
X
_, V
Y
_,
V
Z
_
- 40°C to + 85°C
0V+V
+ 25°C 45 70
On-Resistance (Note 5) RON V+ = 2.7V; IW, IX, IY, IZ = 1mA
VW_, VX_, VY_, VZ_ = 1.5V
- 40°C to + 85°C
80 Ω
+ 25°C 2 5
On-Resistance Match
Between Channels
(Notes 5, 6)
∆RON
V+ = 2.7V; IW, IX, IY, IZ = 1mA
VW_, VX_, VY_, VZ_ = 1.5V
- 40°C to + 85°C
6
Ω
+ 25°C -1 +1
W_, X_, Y_, Z_ Off-
Leakage Current (Note 7)
IW_, IX_,
IY_, IZ_
V+ = 3.6V; VW,
VX, VY, VZ = 3V,
0.6V; VW_, VX_, VY_, VZ_ = 0.6V,
3V
- 40°C to + 85°C -10
+10
nA
+ 25°C -2 +2
W, X, Y, Z Off-Leakage
Current (Note 7)
IW(OFF),
IX(OFF),
IY(OFF),
IZ
(
OFF
)
V+ = 3.6V; VW,
VX, VY, VZ = 3V,
0.6V; VW_, VX_, VY_, VZ_ = 0.6V,
3V
- 40°C to + 85°C -20
+20
nA
+ 25°C -2 +2
W, X, Y, Z On-Leakage
Current (Note 7)
IW(ON),
IX(ON),
IY(ON),
IZ
(
ON
)
V+ = 3.6V; VW,
VX, VY, VZ = 0.6V,
3V; VW_, VX_, VY_, VZ_ = 0.6V, 3V,
or unconnected
- 40°C to + 85°C -20
+20
nA
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, V- = 0V, VIH = +1.4V, VIL = +0.4V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Notes 2, 3, 4)
PARAMETER
SYMBOL
CONDITIONS TA
MIN TYP MAX UNITS
Input Off-Capacitance
CW_
(
OFF
)
,
CX_
(
OFF
)
,
CY_
(
OFF
)
,
CZ_
(
OFF
)
f = 1MHz, Figure 7 + 25°C 9 pF
MAX4691 68
MAX4692 36
Output Off-Capacitance
CX
(
OFF
)
,
CY
(
OFF
)
,
CZ
(
OFF
)
f = 1MHz,
Figure 7 MAX4693
+ 25°C
20
pF
MAX4691 78
MAX4692 46
On-Capacitance
CW
(
ON
)
,
CX
(
ON
)
,
CY
(
ON
)
,
CZ
(
ON
)
f = 1MHz,
Figure 7
MAX4693
+ 25°C
30
pF
DYNAMIC
+ 25°C 180 300
Enable Turn-On Time
( M AX 4691/M AX 4692/
M AX 4693)
tON VW_, VX_, VY_, VZ_ = 1.5V;
RL = 300Ω,CL = 35pF, Figure 2 - 40°C to + 85°C
350
ns
+ 25°C 70 100
Enable Turn-Off Time
( M AX 4691/M AX 4692/
M AX 4693)
tOFF VW_, VX_, VY_, VZ_ = 1.5V;
RL = 300Ω,CL = 35pF, Figure 2 - 40°C to + 85°C
120
ns
+ 25°C 200 350
Address Transition Time
tTRANS
VW_, VX_, VY_, VZ_ = 0V, 1.5V;
RL = 300Ω, CL = 35pF, Figure 3 - 40°C to + 85°C
400 ns
+ 25°C 2 90
Break-Before-Make tBBM VW_, VX_, VY_, VZ_ = 1.5V;
RL = 300Ω, CL = 35pF, Figure 4 - 40°C to + 85°C
2ns
Charge Injection Q V
GE N
= 0V ; RGE N
= 0Ω; C
L = 1nF,
Fi g ur e 5 + 25°C 0.1
pC
Off-Isolation (Note 8) VISO
f = 0.1MHz, RL = 50Ω, CL = 5pF,
Figure 6 + 25°C -70
dB
Crosstalk (Note 9) VCT
f = 0.1MHz, RL = 50Ω, CL = 5pF,
Figure 6 + 25°C -75
dB
DIGITAL I/O
Input Logic-High VIH
1.4
V
Input Logic-Low VIL 0.4 V
Input Leakage Current IIN VA, VB, VC, V EN = 0V or V+ -1 +1
µA
SUPPLY
+ 25°C 0.1
Positive Supply Current I+
V+ = 3.6V, VA, VB, VC, VEN = 0V
or V+
- 40°C to + 85°C
1
µA
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.5V to +5.5V, V- = 0V, VIH = +2V, VIL = +0.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Notes 2, 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
ANALOG SWITCH
Analog Signal Range
VW, VX, VY,
VZ, VW_, VX_,
VY_, VZ__
- 40°C to + 85°C 0 V+ V
+ 25°C 25 35
On-Resistance (Note 5) RON V+ = 4.5V; IW, IX, IY, IZ = 1mA;
V
W_, V
X
_, V
Y
_, V
Z
_ = 3.5V - 40°C to + 85°C 40 Ω
+ 25°C 2 4
On-Resistance Match
Between Channels
(Notes 5, 6)
∆RON V+ = 4.5V; IW, IX, IY, IZ = 1mA;
V
W_, V
X
_, V
Y
_, V
Z
_ = 3.5V - 40°C to + 85°C 5
Ω
+ 25°C 2 6
On-Resistance Flatness
(Note 10) RFLAT
(
ON
)
V+ = 4.5V; IW, IX, IY, IZ = 1mA;
V
W_, V
X
_, V
Y
_, V
Z
_ = 1V, 2.25V,
3.5V - 40°C to + 85°C 8
Ω
+ 25°C -1 +1
W_, X_ , Y_, Z_ Off-Leakage
Current (Note 7)
IW_, IX _,
IY _, IZ _
V+ = 5.5V; VW, VX, VY,
VZ = 4.5V, 1V_; V
W_, V
X
_, V
Y
_,
V
Z
_ = 1V, 4.5V - 40°C to + 85°C -10 +10
nA
+ 25°C -2 +2
W, X, Y, Z Off-Leakage
Current (Note 7)
IW(OFF),
IX (OFF),
IY(OFF),
IZ(OFF)
V+ = 5.5V; VW, VX, VY,
VZ = 4.5V, 1V_; V
W_, V
X
_, V
Y
_,
V
Z
_ = 1V, 4.5V - 40°C to + 85°C -20 +20
nA
+ 25°C -2 +2
W, X, Y, Z On-Leakage
Current (Note 7)
IW(ON),
IX(ON),
IY(ON),
IZ(ON)
V + = 5.5V ; V
W, V
X
, VY
, VZ
= 1V ,
4.5V _; V
W_, V
X
_, V
Y
_, V
Z
_ = 1V,
4.5V , or unconnected - 40°C to + 85°C -20 +20
nA
DYNAMIC
+ 25°C 90 130
Enable Turn-On Time
( M AX 4691/M AX 4692/M AX 4693) tON V
W_, V
X
_, V
Y
_, V
Z
_ = 3V; RL =
300Ω, CL = 35pF, Figure 2 - 40°C to + 85°C 150 ns
+ 25°C 45 60
Enable Turn-Off Time
( M AX 4691/M AX 4692/M AX 4693) tOFF V
W_, V
X
_, V
Y
_, V
Z
_ = 3V; RL =
300Ω, CL = 35pF, Figure 2 - 40°C to + 85°C 70 ns
+ 25°C 100 140
Ad d r ess Tr ansi ti on Ti m et
TRANS
V
W_, V
X
_, V
Y
_, V
Z
_ = 0V, 3V;
RL = 300Ω, CL = 35pF,
Fi
g
ure 3 - 40°C to + 85°C 160 ns
+ 25°C 2 35
Break-Before-Make tBBM V
W_, V
X
_, V
Y
_, V
Z
_ = 3V; RL =
300Ω, CL = 35pF, Figure 4 - 40°C to + 85°C 2 ns
Charge Injection Q V
GE N = 0V ; RGE N = 0Ω; CL = 1nF,
Fi gur e 5 + 25°C 0.2 pC
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies
(MAX4691/MAX4692/MAX4693 only)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, VIH = +2V, VIL = +0.8V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
ANALOG SWITCH
Analog Signal Range V
X
, VY
, VZ
,
V
X
_, VY
_, VZ
_- 40°C to + 85°C V- V+ V
+ 25°C 18 25
On-Resistance (Note 5) RON V+ = 4.5V; IX, IY, IZ = 10mA;
V- = -4.5V; VX_, VY_, VZ_ = 3.5V - 40°C to + 85°C 30 Ω
+ 25°C 2 3
On-Resistance Match
Between Channels
(Notes 5, 6)
∆RON V+ = 4.5V; V- = -4.5V; IX, IY, IZ =
10mA; VX_, VY_, VZ_ = 3.5V - 40°C to + 85°C 4
Ω
+ 25°C 2.5 3.5
On-Resistance Flatness
(Note 10) RFLAT
(
ON
)
V+ = 4.5V; V- = -4.5V; IX, IY, IZ =
10mA; VX, VY, VZ = 3.5V, 0V,
-3.5V - 40°C to + 85°C 4
Ω
+ 25°C -1 +1
X_ , Y_, Z_ Off-Leakage
Current (Note 7)
IX
_,
IY
_, IZ
_
V+ = 5.5V; V- = -5.5V; VX, VY, VZ
= +4.5V; VX_, VY_, VZ_ = ±4.5V
- 40°C to + 85°C -10 +10
nA
+ 25°C -2 +2
X, Y, Z Off-Leakage Current
(Note 7)
IX
(
OFF
)
,
IY(OFF),
IZ(OFF)
V+ = 5.5V; V- = -5.5V; VX, VY,
VZ = +4.5V; VX_, VY_, VZ_ =
±4.5V - 40°C to + 85°C -20 +20 nA
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.5V to +5.5V, V- = 0V, VIH = +2V, VIL = +0.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Notes 2, 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
Off-Isolation (Note 8) VISO f = 0.1MHz, RL = 50Ω,
CL = 5pF Figure 6 + 25°C -80 dB
Crosstalk (Note 9) VCT f = 0.1MHz, RL = 50Ω,
CL = 5pF Figure 6 + 25°C -87 dB
DIGITAL I/O
Input Logic-High VIH 2V
Input Logic-Low VIL 0.8 V
Input Leakage Current ILEAKAGE VIN_ = 0V or V+ -1 +1 µA
SUPPLY
+ 25°C 0.1
Positive Supply Current I+ V+ = 5.5V; VIN_ = 0V or V+ - 40°C to + 85°C -1 1 µA
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
6 _______________________________________________________________________________________
Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value is a maximum, is used
in this data sheet.
Note 3: UCSP parts are 100% tested at TA= +25°C. Limits across the full temperature range are guaranteed by correlation.
Note 4: QFN and TQFN parts are 100% tested at TA= +85°C. Limits across the full temperature range are guaranteed by correlation.
Note 5: UCSP RON and RON match are guaranteed by design.
Note 6: ∆RON = RON(MAX) - RON(MIN).
Note 7: Leakage parameters are guaranteed by design.
Note 8: Off-isolation = 20log10 (VW,X,Y,Z / VW_,X_,Y_,Z_), VW,X,Y,Z = output, VW_,X_,Y_,Z_ = input to off switch.
Note 9: Between any two switches.
Note 10: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)
(MAX4691/MAX4692/MAX4693 only)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, VIH = +2V, VIL = +0.8V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 2, 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
+ 25°C -2 2
X, Y, Z On-Leakage Current
(Note 7)
IX(ON),
IY(ON),
IZ(ON)
V+ = 5.5V; V- = -5.5V;
VX, VY, VZ = ±4.5V;
VX_, VY_, VZ_ = ±4.5V,
or unconnected - 40°C to + 85°C -20 20
nA
DYNAMIC
+ 25°C 55 80
Enable Turn-On Time tON VX_, VY_, VZ_ = 3V; RL = 300Ω,
CL = 35pF, Figure 2 - 40°C to + 85°C 90 ns
+ 25°C 35 50
Enable Turn-Off Time tOFF VX_, VY_, VZ_ = 3V; RL = 300Ω,
CL = 35pF, Figure 2 - 40°C to + 85°C 60 ns
+ 25°C 60 90
Ad d r ess Tr ansi ti on Ti m et
TRANS
V
X
_, V
Y
_, V
Z
_ = 0V, 3V;
RL = 300Ω, CL = 35pF,
Figure 3 - 40°C to + 85°C 100
ns
+ 25°C 2 20
Break-Before-Make tBBM V
X
_, V
Y
_, V
Z
_ = 3V; RL = 300Ω,
CL = 35pF, Figure 4 - 40°C to + 85°C 2 ns
Charge Injection Q VGEN = 0V; R GEN = 0Ω;
CL = 1nF, Figure 5 + 25°C 1.8 pC
Off-Isolation (Note 8) VISO f = 0.1MHz, RL = 50Ω,
CL = 5pF, Figure 6 + 25°C -82 dB
Crosstalk (Note 9) VCT f = 0.1MHz, RL = 50Ω,
CL = 5pF, Figure 7 + 25°C -84 dB
Total Harmonic Distortion THD f = 20Hz to 20kHz, V
X
, V
Y
, V
Z
=
5Vp-p; RL = 600Ω,+ 25°C 0.02 %
DIGITAL I/O
Input Logic-High VIH 2V
Input Logic-Low VIL 0.8 V
Input Leakage Current IIN V
A
, V
B
, V
C
, V E N = 0V or V+ -1 +1 µA
SUPPLY
+ 25°C 0.1
Positive Supply Current I+ V+ = 5.5V; V- = 5.5V;
V
A
, V
B
, V
C
, V E N = 0V or V+ - 40°C to + 85°C 1 µA
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
_______________________________________________________________________________________ 7
40
30
20
10
0
-6 0-4 -2 2 4 6
ON-RESISTANCE vs. VX, VY, VZ
(DUAL SUPPLIES)
MAX4691 toc01
VX, VY, VZ (V)
RON (Ω)
V+ = +2.7V
V- = -2.7V
V+ = +5V
V- = -5V
V+ = +3.3V
V- = -3.3V
V+ = +2V
V- = -2V
6
10
8
16
14
12
22
20
18
24
-5 -1-3 135
ON-RESISTANCE vs. VX, VY, VZ AND
TEMPERATURE (DUAL SUPPLIES)
MAX4691 toc02
VX, VY, VZ (V)
RON (Ω)
V+ = +5V
V- = -5V
TA = +85°C
TA = -40°C
TA = +25°C
0
30
20
10
40
50
60
70
80
90
100
042681012
ON-RESISTANCE vs. VW, VX, VY, VZ
(SINGLE SUPPLY)
MAX4691 toc03
VW, VX, VY, VZ (V)
RON (Ω)
V+ = +2V
V+ = +7.5V
V+ = +5V
V+ = +3.3V
V+ = +2.7V
V+ = +10V
10
14
12
16
18
20
22
24
26
28
30
32
34
012345
MAX4691 toc04
ON-RESISTANCE vs. VW, VX, VY, VZ AND
TEMPERATURE (SINGLE SUPPLY)
VW, VX, VY, VZ (V)
RON (Ω)
V+ = +5V
TA = +85°C
TA = +25°C
TA = -40°C
10
20
30
40
50
0 0.6 0.90.3 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
MAX4691 toc05
ON-RESISTANCE vs. VW, VX, VY, VZ AND
TEMPERATURE (SINGLE SUPPLY)
VW, VX, VY, VZ (V)
RON (Ω)
V+ = +3.3V
TA = +85°C
TA = +25°C
TA = -40°C
10
1
0.1
0.01
0.001
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(DUAL SUPPLIES)
MAX4691 toc06
TEMPERATURE (°C)
I+, I- (nA)
V+ = +5V
V- = -5V
VA, VB, VC, VEN = 0V, +5V
I+
I-
10
1
0.1
0.01
0.001
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(SINGLE SUPPLY)
MAX4691 toc07
TEMPERATURE (°C)
I+, I- (nA)
V+ = +5V
VA, VB, VC, VEN = 0V, +5V
1pA
0.1nA
0.01nA
1nA
0.01µA
0.1µA
1µA
0.01mA
0.1mA
1mA
0.01A
0.1A
1A
012345
I+ vs. LOGIC LEVEL
MAX4691 toc08
VA, VB, VC, VENB (V)
I+
0
0.4
0.2
0.8
0.6
1.2
1.0
1.4
1.8
1.6
2.0
2 4563 7891011
LOGIC-LEVEL THRESHOLD vs. V+
MAX4691 toc09
V+ (V)
VA, VB, VC, VEN (V)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
FREQUENCY RESPONSE
vs. ±5V SUPPLIES
FREQUENCY (MHz)
0.001 100
LOSS (dB)
MAX4691 toc16
-140
0
-100
-120
-60
-80
-20
-40
0.01 0.1 1 10
OFF-ISOLATION
CROSSTALK
ON-RESPONSE
FREQUENCY RESPONSE
vs. +3V SUPPLIES
FREQUENCY (MHz)
0.001 100
LOSS (dB)
MAX4691 toc17
-140
0
-100
-120
-60
-80
-20
-40
0.01 0.1 1 10
OFF-ISOLATION
CROSSTALK
ON-RESPONSE
10 1k100 10k 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX4691 toc18
FREQUENCY (Hz)
THD+N (%)
0.1
0.001
0.01
V+ = +5V
V- = -5V
V+ = +3V
V- = 0V
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0.0001
0.001
0.1
0.01
1
10
-40 10-15 35 60 85
ON-LEAKAGE CURRENT vs. TEMPERATURE
MAX4691 toc10
TEMPERATURE (°C)
ON-LEAKAGE (nA)
V+ = +5.5V
V- = -5.5V
0.0001
0.001
0.1
0.01
1
10
-40 10-15 35 60 85
OFF-LEAKAGE CURRENT vs. TEMPERATURE
MAX4691 toc11
TEMPERATURE (°C)
OFF-LEAKAGE (nA)
V+ = +5.5V
V- = -5.5V
W, X, Y, Z
W_, X_, Y_, Z_
30
40
35
50
45
60
55
65
-40 10-15 35 60 85
TURN-ON/TURN-OFF TIME
vs. TEMPERATURE (DUAL SUPPLY)
MAX4691 toc12
TURN-ON/TURN-OFF TIME (ns)
TEMPERATURE (°C)
V+ = +5.5V
V- = -5.5V
TURN-ON
TURN-OFF
30
50
40
70
60
80
90
-40 10-15 35 60 85
TURN-ON/TURN-OFF TIME
vs. TEMPERATURE (SINGLE SUPPLY)
MAX4691 toc13
TURN-ON/TURN-OFF TIME (ns)
TEMPERATURE (°C)
V+ = +5.5V
TURN-ON
TURN-OFF
30
130
80
230
180
330
280
380
MAX4691 toc14
SUPPLY VOLTAGE V+, V- (V)
TURN-ON/TURN-OFF TIME (ns)
±2±3±4±5±6
TURN-ON/TURN-OFF TIME
vs. SUPPLY VOLTAGE
TURN-ON
TURN-OFF
0
1.0
0.5
2.0
1.5
3.0
2.5
3.5
-5 -1-3 1 3-4 0-2 2 4 5
CHARGE INJECTION vs. VW, VX, VY, VZ
MAX4691 toc15
VW, VX, VY, VZ (V)
Q (pC)
V+ = +5V
V- = -5V
V+ = +5V
V- = 0V
V+ = +3V
V- = 0V
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
_______________________________________________________________________________________ 9
Pin Description
PIN
UCSP QFN-EP/
TQFN-EP
NAME FUNCTION
A4, B4, C 4,
D 4, A1, B1,
C 1, D 1
16, 1, 3, 4,
12, 11, 9, 8
X0–X7 Analog Switch Inputs 0–7
A2 13 X Analog Switch Common
D 3, D 2, A3
5, 7, 15 A, B, C Digital Address Inputs
B2 14 V- Negative Analog Supply Voltage Input. Connect V- to GND for single-supply operation.
B3 2 GND Ground. Connect to digital ground. (Analog signals have no ground reference; they are
limited to V+ and V-.)
C2 10 EN Digital Enable Input. Normally connect EN to GND. EN can be driven to logic high to
set all switches off.
C3 6 V+ Positive Analog and Digital Supply Voltage Input
— — EP Exposed Pad (QFN and TQFN only). Connect EP to V+.
MAX4691
PIN
UCSP QFN-EP/
TQFN-EP
NAME FUNCTION
A1, B1, C 1,
D 1
12, 11, 9, 8
X0–X3 Analog Switch “X” Inputs 0–3
A4, B4, C 4,
D 4
16, 1, 3, 4
Y0–Y3 Analog Switch “Y” Inputs 0–3
A2 13 X Analog Switch “X” Common
A3 15 Y Analog Switch “Y” Common
D 3, D 2 5, 7 A, B Digital Address Inputs for both “X” and “Y” Analog Switches
B2 14 V- Negative Analog Supply Voltage Input. Connect V- to GND for single-supply
B3 2 GND Ground. Connect to digital ground. (Analog signals have no ground reference;
they are limited to V+ and V-.)
C2 10 EN Digital Enable Input. Normally connect EN to GND. EN can be driven to logic high to
set all switches off.
C3 6 V+ Positive Analog and Digital Supply Voltage Input
— — EP Exposed Pad (QFN and TQFN only). Connect EP to V+.
MAX4692
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
10 ______________________________________________________________________________________
PIN
UCSP QFN-EP/
TQFN-EP
NAME FUNCTION
A1 12 X0 Analog Switch “X” Normally Closed Input
B1 11 X1 Analog Switch “X” Normally Open Input
A4 16 Y0 Analog Switch “Y” Normally Closed Input
B4 1 Y1 Analog Switch “Y” Normally Open Input
D 1 8 Z0 Analog Switch “Z” Normally Closed Input
C1 9 Z1 Analog Switch “Z” Normally Open Input
A2 13 X Analog Switch “X” Common
A3 15 Y Analog Switch “Y” Common
D2 7 Z Analog Switch “Z” Common
C4 3 A Analog Switch “X” Digital Control Input
D4 4 B Analog Switch “Y” Digital Control Input
D3 5 C Analog Switch “Z” Digital Control Input
B2 14 V- Negative Analog Supply Voltage Input. Connect V- to GND for single-supply operation.
B3 2 GND Ground. Connect GND to digital ground. (Analog signals have no ground reference; they
are limited to V+ and V-.)
C2 10 EN Digital Enable Input. Normally connect EN to GND. EN can be driven to logic high to set
all switches off.
C3 6 V+ Positive Analog and Digital Supply Voltage Input
— — EP Exposed Pad (QFN and TQFN only). Connect EP to V+.
MAX4693
Pin Description (continued)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
______________________________________________________________________________________ 11
PIN
USCP QFN-EP/
TQFN-EP
NAME FUNCTION
D4 4 W0 Analog Switch “W” Normally Closed Input
C4 3 W1 Analog Switch “W” Normally Open Input
A1 12 X0 Analog Switch “X” Normally Closed Input
B1 11 X1 Analog Switch “X” Normally Open Input
A4 16 Y0 Analog Switch “Y” Normally Closed Input
B4 1 Y1 Analog Switch “Y” Normally Open Input
D1 8 Z0 Analog Switch “Z” Normally Closed Input
C1 9 Z1 Analog Switch “Z” Normally Open Input
D3 5 W Analog Switch “W” Common
A2 13 X Analog Switch “X” Common
A3 15 Y Analog Switch “Y” Common
D2 7 Z Analog Switch “Z” Common
B2 14 GND Ground
B3 2 A Analog Switch “W” and “Y” Digital Control Input
C2 10 B Analog Switch “X” and “Z” Digital Control Input
C3 6 V+ Positive Analog and Digital Supply Voltage Input
— — EP Exposed Pad (QFN and TQFN only). Connect EP to V+.
MAX4694
Pin Description (continued)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
12 ______________________________________________________________________________________
Detailed Description
The MAX4691–MAX4694 are low-voltage CMOS analog
ICs configured as an 8-channel multiplexer (MAX4691),
two 4-channel multiplexers (MAX4692), three SPDT
switches (MAX4693), and four SPDT switches
(MAX4694). All switches are bidirectional.
The MAX4691/MAX4692/MAX4693 operate from either
a single +2V to +11V power supply or dual ±2V to
±5.5V power supplies. When operating from ±5V sup-
plies they offer 25Ωon-resistance (RON), 3.5Ωmax
RON flatness, and 3Ωmax matching between channels.
The MAX4694 operates from a single +2V to +11V sup-
ply. Each switch has rail-to-rail signal handling, fast
switching times of tON = 80ns, tOFF = 50ns, and a low
1nA leakage current.
All digital inputs are 1.8V logic-compatible when oper-
ating from a +3V supply and TTL-compatible when
operating from a +5V supply.
Digital Inputs
The MAX4691 and MAX4692 include address pins that
allow control of the multiplexers. For the MAX4691, pins
A, B, C determine which switch is closed. The two 4-1
muxes in the MAX4692 are controlled by the same
address pins (A and B). (Table 1)
The MAX4693 and MAX4694 offer SPDT switches in
triple and quadruple packages. In the MAX4693, each
switch has a unique control input. The MAX4694 has
two digital control inputs: A (for switches “W” and “Y”)
and B (for switches “X” and “Z”). (Table 1)
Applications Information
Power-Supply Considerations
Overview
The MAX4691–MAX4694 construction is typical of most
CMOS analog switches. V+ and V-* are used to drive
the internal CMOS switches and set the limits of the
analog voltage on any switch. Reverse ESD-protection
diodes are internally connected between each analog
signal pin and both V+ and V-. If any analog signal
exceeds V+ or V-, one of these diodes will conduct.
*
V- is found only on the MAX4691/MAX4692/MAX4693.
ADDRESS BITS ON SWITCHES
EN
1
C2
B A MAX4691 MAX4692 MAX4693 MAX4694
1XXX
All switches open
All switches open All switches open —
0 0 0 0 X-X0 X-X0, Y-Y0 X-X0, Y-Y0, Z-Z0 W-W0, X-X0,
Y-Y0, Z-Z0
0 0 0 1 X-X1 X-X1, Y-Y1 X-X1, Y-Y0, Z-Z0 W-W1, X-X0,
Y-Y1, Z-Z0
0 0 1 0 X-X2 X-X2, Y-Y2 X-X0, Y-Y1, Z-Z0 W-W0, X-X1,
Y-Y0, Z-Z1
0 0 1 1 X-X3 X-X3, Y-Y3 X-X1, Y-Y1, Z-Z0 W-W1, X-X1,
Y-Y1, Z-Z1
0 1 0 0 X-X4 X-X0, Y-Y0 X-X0, Y-Y0, Z-Z1 W-W0, X-X0,
Y-Y0, Z-Z0
0 1 0 1 X-X5 X-X1, Y-Y1 X-X1, Y-Y0, Z-Z1 W-W1, X-X0,
Y-Y1, Z-Z0
0 1 1 0 X-X6 X-X2, Y-Y2 X-X0, Y-Y1, Z-Z1 W-W0, X-X1,
Y-Y0, Z-Z1
0 1 1 1 X-X7 X-X3, Y-Y3 X-X1, Y-Y1, Z-Z1 W-W1, X-X1,
Y-Y1, Z-Z1
Table 1. Truth Table/Switch Programming
X = Don’t care
1. EN is not present on the MAX4694.
2. C is not present on the MAX4692 and MAX4694.
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
______________________________________________________________________________________ 13
During normal operation, these (and other) reverse-
biased ESD diodes leak, forming the only current drawn
from V+ or V-.
Virtually all the analog leakage current comes from the
ESD diodes. Although the ESD diodes on a given signal
pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages will vary as the signal varies. The
difference
in
the two diode leakages to the V+ and V- pins consti-
tutes the analog signal path leakage current. All analog
leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is
why both sides of a given switch can show leakage cur-
rents of either the same or opposite polarity.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels
into switched V+ and V- signals to drive the gates of the
analog signals. This drive signal is the only connection
between the logic supplies (and signals) and the ana-
log supplies. V+ and V- have ESD-protection diodes on
GND.
Bipolar Supplies
The MAX4691/MAX4692/MAX4693 operate with bipolar
supplies between ±2V and ±5.5V. The V+ and V- sup-
plies need not be symmetrical, but their difference can-
not exceed the absolute maximum rating of +12V.
Single Supply
These devices operate from a single supply between +2V
and +11V when V- is connected to GND. All of the bipolar
precautions must be observed. At room temperature,
they operate with a single supply at near or below +2V,
although as supply voltage decreases, switch on-resis-
tance and switching times become very high.
Always bypass supplies with a 0.1µF capacitor.
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, then V-, followed by the
logic inputs and by W, X, Y, Z. If power-supply
sequencing is not possible, add two small signal
diodes (D1, D2) in series with the supply pins for over-
voltage protection (Figure 1).
Adding diodes reduces the analog signal range to one
diode drop below V+ and one diode drop above V-, but
does not affect the devices’ low switch resistance and
low leakage characteristics. Device operation is
unchanged, and the difference between V+ and V-
should not exceed 12V. These protection diodes are
not recommended when using a single supply if signal
levels must extend to ground.
UCSP Reliability
The chip-scale package (UCSP) represents a unique
package that greatly reduces board space compared to
other packages. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review these
areas when considering a UCSP. Performance through
Operating Life Test and Moisture Resistance is equal to
conventional package technology as it is primarily deter-
mined by the wafer-fabrication process. However, this
form factor may not perform equally to a packaged prod-
uct through traditional mechanical reliability tests.
Mechanical stress performance is a greater considera-
tion for a UCSP. UCSP solder joint contact integrity
must be considered since the package is attached
through direct solder contact to the user’s PC board.
Testing done to characterize the UCSP reliability per-
formance shows that it is capable of performing reli-
ably through environmental stresses. Results of
environmental stress tests and additional usage data
and recommendations are detailed in the UCSP appli-
cation note, which can be found on Maxim’s website,
at www.maxim-ic.com.
( ) ARE FOR THE MAX4694 ONLY, REPLACE V- WITH GND.
MAX4691
MAX4692
MAX4693
MAX4694
COM NO
V- (GND)
V+
*INTERNAL PROTECTION DIODES
D2
D1EXTERNAL BLOCKING DIODE
EXTERNAL BLOCKING DIODE
V- (GND )
V+
*
*
*
*
Figure 1. Overvoltage Protection
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
14 ______________________________________________________________________________________
Figure 2. Enable Transition Time
50%
tON
V+
0
VX0
VOUT
0
90%
90%
tOFF
50%
tON
V+
0
VX0,
VY0
VOUT
0
90%
90%
tOFF
50%
tON
V+
0
VW0,
VX0,
VY0,
VZ0
VOUT
VEN
VW1,
VX1,
VY1,
VZ1
90%
90%
tOFF
VOUT
V-
GND
B
V-
A
C
X0
X1–X7
X
V+
MAX4691
300Ω
50Ω35pF
V+
VOUT
V-
GND
V+
B
V-
AX0, Y0
X1, X2, X3, Y1, Y2, Y3
X, Y
V+
MAX4692
300Ω
50Ω35pF
V+
VOUT
V-
GND
V+
V-
A
B
C
X1, Y1, Z1
X0, Y0, Z0
X, Y, Z
V+
V-
MAX4693
300Ω
35pF
50Ω
V- = 0 FOR SINGLE-SUPPLY OPERATION.
TEST EACH SECTION INDIVIDUALLY.
VEN
VEN
VEN
VEN
EN
EN
VEN
EN
V+
V+
Test Circuits/Timing Diagrams
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
______________________________________________________________________________________ 15
Figure 3. Address Transition Time
50%
tTRANS
V+
0
VX0
VOUT
VA, VB, VC
0
VX7
90%
90%
tTRANS
50%
tTRANS
V+
0
VX0,
VY0
VOUT
VA, VB
0
VX3,
VY3
90%
90%
tTRANS
50%
tTRANS
V+
0
VW0,
VX0,
VY0,
VZ0
VOUT
VA, VB, VC
0
VW1,
VX1,
VY1,
VZ1
90%
90%
tTRANS
V+
VOUT
VA, VB, VC
VA, VB
V-
GND
V+
B
V-
A
C
X0
X1–X6
X7
X
V+
V-
MAX4691
300Ω
50Ω
35pF
V+
VOUT
V-
GND
V+
B
V-
AX0, Y0
X1, X2, Y1, Y2
X3, Y3
X, Y
V+
V-
MAX4692
300Ω
50Ω
35pF
V+
VOUT
V-
GND
V+
V-
A, B, C
VA, VB, VCW1, X1, Y1, Z1
W0, X2, Y2, Z2,
X0, Y0, Z0
X, Y, Z
V-
V+
MAX4693
MAX4694
300Ω
50Ω
35pF
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY.
EN
EN
EN
Test Circuits/Timing Diagrams (continued)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
16 ______________________________________________________________________________________
50%
V+
0
VW, VX, VY, VZ
VOUT
VA, VB, VC
0
90%
tBBM
V+
VOUT
VA, VB, VCVA, VB
VA, VB, VC
V-
GND
V+
B
V-
A
C
EN
X0–X7
X
V+
MAX4691
300Ω
50Ω
35pF
V+
VOUT
V-
GND
V+
B
V-
AX0–X3,
Y0–Y3
X, Y
V+
MAX4692
300Ω
35pF
V+
VOUT
V-
GND
V+
V-
A, B, C W0, W1, X0, X1,
Y0, Y1, Z0, Z1
W, X, Y, Z
V+
MAX4693
MAX4694
300Ω
35pF
50Ω
50Ω
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY.
tR < 20ns
tF < 20ns
EN
EN
0
V+
∆ VOUT IS THE MEASURED VOLTAGE DUE TO CHARGE
TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.
∆ VOUT
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY. Q = ∆ VOUT X CL
VOUT
V+
VOUT
VEN
V-
GND
V+
B
V-
A
CHANNEL
SELECT
C
W_, X_, Y_, Z_
W, X, Y, Z
MAX4691–
MAX4694
50ΩCL = 1000pF
EN
VEN
Figure 4. Break-Before-Make Interval
Figure 5. Charge Injection
Test Circuits/Timing Diagrams (continued)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
______________________________________________________________________________________ 17
MEASUREMENTS ARE STANDARDIZED AGAINST SHORT AT SOCKET TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM AND “OFF” NO TERMINAL ON EACH SWITCH.
ON LOSS IS MEASURED BETWEEN COM AND “ON” NO TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL (A, B, C) TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
V- IS NOT PRESENT ON THE MAX4694.
V+
VOUT
VIN
V-
GND
V+ VIN
VOUT MEAS.
NETWORK
ANALYZER
50Ω50Ω
50ΩOFF-ISOLATION = 20log
ON-LOSS = 20log
CROSSTALK = 20log
50Ω
REF.
B
V-
VOUT
VIN
VOUT
VIN
A
CHANNEL
SELECT
C
W_, X_, Y_, Z_
W, X, Y, Z
10nF
10nF
MAX4691–
MAX4694
VEN
EN
Figure 6. Off-Isolation, On-Loss, and Crosstalk
V+
V-
GND
V+
B
V-
A
CHANNEL
SELECT
1MHz
CAPACITANCE
ANALYZER
C
W_, X_, Y_, Z_
W, X, Y, Z
EN
MAX4691–
MAX4694
V- IS NOT PRESENT ON THE MAX4694.
Figure 7. Capacitance
Test Circuits/Timing Diagrams (continued)
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
18 ______________________________________________________________________________________
Functional Diagrams (continued)
MAX4694
W0
W
W1
Y0
Y
Y1
Z0
Z
Z1
X0
X
X1
AB
MAX4693
Z0
Z
Z1
Y0
Y
Y1
X0
AB C
X
X1
EN
MAX4692
X0
X1
X2
X3
Y0
Y1
Y2
Y3
LOGIC
BA
EN
X
Y
Chip Information
PROCESS: BiCMOS
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
______________________________________________________________________________________ 19
TOP VIEW
A
B
C
D
12 3 4
X4 X C X0
X5 V- GND X1
X1
GND
X2
X3
X6 V+ X2
X7 B A X3
MAX4691
MAX4691
1
16
2
3
4
12
11
10
9
X4
X5
EN
X6
15 14 13
X0 C V- X
5 6 7 8
AV+BX7
A
B
C
D
12 3 4
X0 X Y Y0
X1 V- GND Y1
Y1
GND
Y2
Y3
X2 V+ Y2
X3 B A Y3
MAX4692
MAX4692
1
16
2
3
4
12
11
10
9
X0
X1
EN
X2
15 14 13
Y0YV-X
5 6 7 8
AV+BX3
EN
EN
EP*
QFN
*EXPOSED PAD.
CONNECT EP TO V+.
UCSP TQFN
*EXPOSED PAD.
CONNECT EP TO V+.
QFN
*EXPOSED PAD.
CONNECT EP TO V+.
UCSP TQFN
*EXPOSED PAD.
CONNECT EP TO V+.
EP*
MAX4691
*EP 9
10
11
12
4
3
2
1
X6
EN
X5
X4
X3
X2
GND
X1
13
14
15
16
8
7
6
5
X
V-
C
X0
X7
B
V+
A
MAX4692
*EP 9
10
11
12
4
3
2
1
X2
EN
X1
X0
Y3
Y2
GND
Y1
13
14
15
16
8
7
6
5
X
V-
Y
Y0
X3
B
V+
A
+
+
+
+
+
+
Pin Configurations
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
20 ______________________________________________________________________________________
Pin Configurations (continued)
A
B
C
D
12 3 4
X0 X Y Y0
X1 V- GND Y1
Y1
GND
A
B
Z1 V+ A
Z0 Z C B
MAX4693
MAX4693
1
16
2
3
4
12
11
10
9
X0
X1
EN
Z1
15 14 13
Y0YV-X
5 6 7 8
CV+Z Z0
A
B
C
D
12 3 4
X0 X Y Y0
X1 GND A Y1
Y1
A
W1
W0
Z1 V+ W1
Z0 Z W W0
B
MAX4694
MAX4694
1
16
2
3
4
12
11
10
9
X0
X1
B
Z1
15 14 13
Y0 Y GND X
5 6 7 8
WV+ Z Z0
EN
TOP VIEW
EP*
EP*
CONNECT EP TO V+. CONNECT EP TO V+.
QFN
*EXPOSED PAD.
CONNECT EP TO V+.
UCSP TQFN
*EXPOSED PAD.
CONNECT EP TO V+.
+
+
+
+
+
+
QFN
*EXPOSED PAD.
CONNECT EP TO V+.
UCSP TQFN
*EXPOSED PAD.
CONNECT EP TO V+..
MAX4693
*EP 9
10
11
12
4
3
2
1
Z1
EN
X1
X0
B
A
GND
Y1
13
14
15
16
8
7
6
5
X
V-
Y
Y0
Z0
Z
V+
C
MAX4694
*EP 9
10
11
12
4
3
2
1
Z1
B
X1
X0
W0
W1
A
Y1
13
14
15
16
8
7
6
5
X
GND
Y
Y0
Z0
Z
V+
W
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
16 UCSP B16+1 21-0101 Refer to Application Note 1891
16 QFN-EP G1644+1 21-0106 90-0216
16 TQFN-EP T1644+4 21-0139 90-0070
MAX4691–MAX4694
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
21
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/01 Initial release —
1 7/01 Added UCSP Package —
2 2/03 Removed statement in Features section with UCSP now qualified —
3 12/06 Exposed Paddle Connection information edited, style changes 1, 9, 10, 11, 19, 21, 22
4 8/08 Added part numbers, package diagram, and TQFN packaging 1–26
5 3/09 Added lead-free packaging, edited Pin Description, revised Chip Information,
changed “floating” to “unconnected,” style changes 1–6, 9, 10, 11, 18–21
6 1/12 Updated Absolute Maximum Ratings and Pin Description sections 2, 9, 10
