LM4937 www.ti.com LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Audio Sub-System with OCL Stereo Headphone Output and RF Suppression Check for Samples: LM4937 FEATURES DESCRIPTION * * * * * * * The LM4937 is an integrated audio sub-system designed for mono voice, stereo music cell phones connecting to base band processors with mono differential analog voice paths. Operating on a 3.3V supply, it combines a mono speaker amplifier delivering 520mW into an 8 load, a stereo headphone amplifier delivering 36mW per channel into a 32 load, and a mono earpiece amplifier delivering 55mW into a 32 load. It integrates the audio amplifiers, volume control, mixer, and power management control all into a single package. In addition, the LM4937 routes and mixes the singleended stereo and differential mono inputs into multiple distinct output modes. The LM4937 features an I2S serial interface for full range audio and an I2C TMor SPI compatible interface for control. The full range music path features an SNR of 85dB with a 192kHz playback. 1 234 * * * 18-Bit Stereo DAC Multiple Distinct Output Modes Mono Speaker Amplifier Stereo Headphone Amplifier Mono Earpiece Amplifier Differential Mono Analog Input Independent Loudspeaker, Headphone and Mono Earpiece Volume Controls I2C/SPI (Selectable) Compatible Interface Ultra Low Shutdown Current Click and Pop Suppression Circuit APPLICATIONS * * Cell Phones PDAs KEY SPECIFICATIONS * * * * * BoomerTM audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. POUT, BTL, 8, 3.3V, 1%: 520 mW (typ) POUT H/P, 32, 3.3V, 1%: 36 mW (typ) POUT Mono Earpiece, 32, 1%: 55 mW (typ) Shutdown current: 0.6A (typ) SNR (DAC + Amplifier): 85 dB (typ) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. 2 I C is a trademark of NXP. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2013, Texas Instruments Incorporated LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com Block Diagram PLL MCLK Ci Differential + Ci Differential - + Volume 5 ~ - 56 dB Volume Volume 5 ~ - 56 dB Mixer Ci RIN AMP -12 ~ + 9 dB - Ci LIN Speaker Volume and -6 ~ + 15 dB Output HP AMP Mode Select I2S CLK DAC Gain -3 ~ 6 dB STEREO DAC I2S SDI I2S WS Volume 5 ~ - 56 dB 2 I C Vdd SDA/SDI SCL/SCK ADDR/ENB MODE Volume 5 ~ - 56 dB 2 I C/SPI Interface Mono Earpiece (Receiver) Figure 1. Audio Sub-System Block Diagram with OCL HP Outputs (HP outputs may also be configured as cap-coupled) Connection Diagram F E D C B A 1 2 3 4 5 6 Figure 2. 36-Bump DSBGA Top View (Bump Side Down) See YPG0036 Package 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 PIN DESCRIPTIONS Pin Pin Name Digital/An I/O, Power alog Description A1 DGND D P DIGITAL GND A2 MCLK D I MASTER CLOCK A3 I2S_WS D I/O I2S WORD SELECT A4 SDA/SDI D I/O I2C SDA OR SPI SDI A5 DVDD D P DIGITAL SUPPLY VOLTAGE A6 VDD_IO D P I/O SUPPLY VOLTAGE B1 PLL_VDD D P PLL SUPPLY VOLTAGE B2 I2S_SDATA D I I2S SERIAL DATA INPUT B3 I2S_CLK D I/O I2S CLOCK SIGNAL B4 GPIO D O TEST PIN (MUST BE LEFT FLOATING) B5 I2C_VDD D P I2C SUPPLY VOLTAGE B6 SDL/SCK D I I2C_SCL OR SPI_SCK C1 PLL_GND D P PLL GND C2 PLL_OUT D O PLL FILTER OUTPUT C3 PLL_IN D I PLL FILTER INPUT C4 ADDR/ENB D I I2C ADDRESS OR SPI ENB DEPENDING ON MODE C5 BYPASS A I HALF-SUPPLY BYPASS C6 AVDD A P ANALOG SUPPLY VOLTAGE D1 AGND A P ANALOG GND D2 AGND A P D3 NC D4 MODE D I SELECTS BETWEEN I2C OR SPI CONTROL D5 RHP A O RIGHT HEADPHONE OUTPUT D6 CHP A O HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND) E1 DIFF_ A I ANALOG NEGATIVE DIFFERENTIAL INPUT E2 LIN A I ANALOG LEFT CHANNEL INPUT E3 RIN A I ANALOG RIGHT CHANNEL INPUT E4 NC E5 LHP A O LEFT HEADPHONE OUTPUT E6 AGND A P ANALOG GND F1 DIFF+ A I ANALOG POSITIVE DIFFERENTIAL INPUT F2 EP_ A O MONO EARPIECE- F3 EP+ A O MONO EARPIECE+ F4 LS- A O LOUDSPEAKER OUT- F5 AVDD A P ANALOG SUPPLY VOLTAGE F6 LS+ A O LOUD SPEAKER OUT+ ANALOG GND NO CONNECT NO CONNECT These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 3 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Analog Supply Voltage 6.0V Digital Supply Voltage 6.0V Storage Temperature -65C to +150C Input Voltage -0.3V to VDD +0.3V (4) Internally Limited ESD Susceptibility (5) 2000V ESD Susceptibility (6) 200V Power Dissipation Junction Temperature 150C Thermal Resistance: JA 100C/W See AN-1279 (1) (2) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4937 typical application with VDD = 3.3V, RL = 8 stereo operation, the total power dissipation is TBDW. JA = TBDC/W. Human body model: 100pF discharged through a 1.5k resistor. Machine model: 220pF - 240pF discharged through all pins. (3) (4) (5) (6) OPERATING RATINGS Temperature Range (TMIN TA TMAX) -40C TA +85C 2.7V AVDD 5.5V Supply Voltage 2.7V DVDD 4.0V 1.7V I2CVDD 4.0V 1.7V VDD_IO 4.0V AUDIO AMPLIFIER ELECTRICAL CHARACTERISTICS AVDD = 3.0V, DVDD = 3.0V (1) (2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical VIN = 0, No Load All Amps On + DAC, OCL (6) Headphone Mode Only, OCL IDD Supply Current Mono Loudspeaker Mode Only (6) Mono Earpiece Speaker Mode Only D_6 = 0 (register 01h) D_6 = 1 DAC Off, All Amps On (OCL) (6) ISD (1) (2) (3) (4) (5) (6) 4 Shutdown Current (3) Limits (4) (5) Units (Limits) 14 19 mA (max) 4.6 6.25 mA (max) 7 11.5 mA (max) 3.7 3.3 5 mA (max) mA 10 15.5 mA (max) 0.6 2 A (max) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Enabling mono bit (D_6 in Output Control Register 01h) will save 400A (typ) from specified current. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 AUDIO AMPLIFIER ELECTRICAL CHARACTERISTICS AVDD = 3.0V, DVDD = 3.0V(1)(2) (continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol PO VFS Parameter Output Power DAC THD+N VOS Conditions LM4937 Limits (4) (5) Speaker; THD = 1%; f = 1kHz, 8 BTL 420 370 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 27 24 mW (min) Earpiece; THD = 1%; f = 1kHz, 32 BTL 45 40 mW (min) Full Scale DAC Output Total Harmonic Distortion Offset Voltage Units (Limits) Typical (3) 2.4 Vpp Speaker; PO = 200mW; f = 1kHz, 8 BTL 0.04 % Headphone; PO = 10mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 20mW; f = 1kHz, 32 BTL 0.04 % Speaker 10 55 mV (max) Earpiece 8 50 mV (max) Headphone (OCL) 8 40 mV (max) O Output Noise A = weighted; 0dB gain; See Table 1 Table 1 PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 2 Table 2 Xtalk Crosstalk Headphone; PO= 10mW f = 1kHz; OCL -60 dB TWU Wake-Up Time CB = 2.2F, CD6 = 0 35 ms (max) CB = 2.2F, CD6 = 1 85 ms (max) f = 217Hz, VRMS = 200mVpp 56 dB CMRR Common-Mode Rejection Ratio AUDIO AMPLIFIER ELECTRICAL CHARACTERISTICS AVDD = 5.0V, DVDD = 3.3V (1) (2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (3) VIN = 0, No Load All Amps On + DAC, OCL (6) IDD Supply Current mA (max) Headphone Mode Only (OCL) 5.8 mA (max) Mono Loudspeaker Mode Only (6) 11.6 mA (max) (6) 5 mA (max) 12.9 mA (max) 1.6 A (max) 1.25 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 80 mW (min) Earpiece; THD = 1%; f = 1kHz, 32 BTL 175 mW (min) DAC Off, All Amps On (OCL) (6) Shutdown Current Speaker; THD = 1%; f = 1kHz, 8 BTL PO (1) (2) (3) (4) (5) (6) Output Power Units (Limits) 17.5 Mono Earpiece Mode Only ISD Limits (4) (5) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Enabling mono bit (D_6 in Output Control Register 01h) will save 400A (typ) from specified current. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 5 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com AUDIO AMPLIFIER ELECTRICAL CHARACTERISTICS AVDD = 5.0V, DVDD = 3.3V(1)(2) (continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (3) VFS DAC THD+N Full Scale DAC Output Total Harmonic Distortion VOS Offset Voltage O PSRR 2.4 Vpp 0.03 % Headphone; PO = 30mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 40mW; f = 1kHz, 32 BTL; CD4 = 0 0.04 % Speaker 10 mV Earpiece 8 mV HP (OCL) 8 mV A = weighted; 0dB gain; See Table 1 Table 1 Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 3 Table 3 Headphone; PO= 15mW f = 1kHz; OCL Crosstalk TWU Wake-Up Time Units (Limits) Speaker; PO = 500mW; f = 1kHz, 8 BTL Output Noise Xtalk Limits (4) (5) -56 dB CB = 2.2F, CD6 = 0 45 ms CB = 2.2F, CD6 = 1 130 ms VOLUME CONTROL ELECTRICAL CHARACTERISTICS (1) (2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (3) minimum gain setting -6 Stereo Analog Inputs PreAmp Gain Setting Range maximum gain setting 15 minimum gain setting -12 maximum gain setting 9 minimum gain setting -56 maximum gain setting +5 PGR Differential Mono Analog Input PreAmp Gain Setting Range Output Volume Control for Loudspeaker, Headphone Output, or Earpiece Output VCR ACH-CH AMUTE Stereo Channel to Channel Gain Mismatch Mute Attenuation (3) (4) (5) 6 Units (Limits) -7 dB (min) -5 dB (max) 15.5 dB (max) 14.5 dB (min) -13 dB (min) -11 dB (max) 9.5 dB (max) 8.5 dB (min) -59 dB (min) -53 dB (max) 4.5 dB (min) 5.5 dB (max) 0.3 dB <-90 dB (min) Vin = 1Vrms, Gain = 0dB with load Headphone (1) (2) Limits (4) (5) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 VOLUME CONTROL ELECTRICAL CHARACTERISTICS(1)(2) (continued) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (3) RINPUT DIFF+, DIFF-, LIN and RIN Input Impedance 23 Limits (4) (5) Units (Limits) 18 k (min) 28 k (max) DIGITAL SECTION ELECTRICAL CHARACTERISTICS (1) (2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical DISD Digital Shutdown Current (3) Limits (4) (5) Units (Limits) Mode 0, DVDD = 3.0V A No MCLK 0.01 5.3 6.5 mA (max) 4.8 6 mA (max) DIDD Digital Power Supply Current fMCLK = 12MHz, DVDD = 3.0V ALL MODES EXCEPT 0 PLLIDD PLL Quiescent Current fMCLK = 12MHz, DVDD = 3.0V Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency RDAC Audio DAC Ripple 20Hz - 20kHz through headphone output PBDAC Audio DAC Passband width -3dB point SBADAC Audio DAC Stop band Attenuation Above 24kHz Audio DAC Dynamic Range DC - 20kHz, -60dBFS; AES17 Standard See Table 4 Audio DAC-AMP Signal to Noise Ratio A-Weighted, Signal = VO at 0dBFS, f = 1kHz Noise = digital zero, A-weighted, See Table 4 Internal DAC SNR A-weighted (6) DRDAC SNR SNRDAC +/-0.1 dB 22.6 kHz 76 dB Table 4 dB Table 4 dB 95 dB PLL fIN Input Frequency on MCLK pin 12 10 26 MHz SPI/I2C (1.7V I2CVDD 2.2V) fSPI Maximum SPI Frequency 1000 kHz (max) tSPISETD SPI Data Setup Time 250 ns (max) tSPISETENB SPI ENB Setup Time 250 ns (max) tSPIHOLDD SPI Data Hold Time 250 ns (max) tSPIHOLDENB SPI ENB Hold Time 250 ns (max) tSPICL SPI Clock Low Time 500 ns (max) tSPICH SPI Clock High Time 500 ns (max) 2 fCLKI2C I C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 250 ns (max) tI2CSET I2C_DATA Setup Time 250 ns (max) (1) (2) (3) (4) (5) (6) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Internal DAC only with DAC modes 00 and 01. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 7 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com DIGITAL SECTION ELECTRICAL CHARACTERISTICS(1)(2) (continued) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (3) Limits (4) (5) 0.7 x I2CVDD VIH I2C/SPI Input High Voltage I2CVDD VIL I2C/SPI Input Low Voltage 0 0.25 x I2CVDD Units (Limits) V (min) V (max) SPI/I2C (2.2V I2CVDD 4.0V) fSPI Maximum SPI Frequency 4000 kHz (max) tSPISETD SPI Data Setup Time 100 ns (max) tSPISETENB SPI ENB Setup Time 100 ns (max) tSPIHOLDD SPI Data Hold Time 100 ns (max) tSPIHOLENB SPI ENB Hold Time 100 ns (max) tSPICL SPI Clock Low Time 125 ns (max) tSPICH SPI Clock High Time 125 ns (max) fCLKI2C I2C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 100 ns (max) tI2CSET 2 I C_DATA Setup Time 100 ns (max) V (min) VIH I C/SPI Input High Voltage I CVDD 0.7 x I2CVDD VIL I2C/SPI Input Low Voltage- 0 0.3 x I2CVDD V (ax) 1536 3072 6144 12288 kHz (ax) kHz (max) 50 40 60 % % 2 2 2 I S(1.7V VDD_IO 2.7V) I2S_CLK Frequency fCLKI2S I2S_RES = 1 I2S_RES = 0 I2S_WS Duty Cycle VIH Digital Input High Voltage 0.75 x VDD_IO V (min) VIL Digital Input Low Voltage 0.25 x VDD_IO V (max) I2S(2.7V VDD_IO 4.0V) I2S_CLK Frequency I2S_RES = 0 1536 3072 6144 12288 kHz (max) kHz (max) I2S_WS Duty Cycle I2S_RES = 1 50 40 60 % % fCLKI S 2 VIH Digital Input High Voltage 0.7 x VDD_IO V (min) VIL Digital Input Low Voltage 0.3x VDD_IO V (max) 8 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Table 1. Output Noise (1) (1) MODE EP LS HP OCL Units 1 22 22 8 V 2 22 22 8 V 3 22 22 8 V 4 68 88 46 V 5 38 48 24 V 6 29 34 18 V 7 38 48 24 V Output Noise AVDD = 5.0V and AVDD = 3.0V. All gains set to 0dB. Units in V. A - weighted Table 2. PSRR AVDD = 3.0V (1) (1) MODE EP(Typ) LS (Typ) 1 69 76 LS (Limit) HP (Typ) HP (Limit) Units 2 69 76 3 69 76 72 dB 4 63 62 55 dB 5 69 68 61 dB 6 69 70 64 dB 7 69 68 61 dB 72 67 dB 72 68 dB PSRR AVDD = 3.0V, f = 217Hz; Vripple = 200mVp-p; CB = 2.2F. Table 3. PSRR AVDD = 5.0V (1) (1) MODE EP (Typ) LS (Typ) HP (Typ) Units 1 68 72 71 dB 2 68 72 71 dB 3 68 72 71 dB 4 68 66 69 dB 5 68 69 70 dB 6 69 72 71 dB 7 68 69 70 dB PSRR AVDD = 5.0V. All gains set to 0dB. f = 217Hz; Vripple = 200mVp-p; CB = 2.2F Table 4. Dynamic Range and SNR (1) (1) DR (Typ) SNR (Typ) Units LS 95 85 dB HP 95 85 dB EP 97 85 dB Dynamic Range and SNR. 3.0V AVDD 5.0V. All programmable gain set to 0dB. Units in dB. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 9 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com SYSTEM CONTROL The LM4937 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM4937 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction ENB SCK SDI 7 0 7 0 Register Address Data Three Wire Mode Write Bus Timing TSPISETENB TSPIHOLDENB ENB TSPICL TSPIT SCK TSPICH SDI TSPISETD TSPIHOLDD Figure 3. Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Figure 4. Two Wire Mode Write Bus Transaction SDA SCL 6-0 S Start Condition Host Address 7-1 W ACK Register Address 0 7-1 ACK 0 Data P ACK Stop Condition Figure 5. Two Wire Mode Write Bus Timing SDA TI2CSET TI2CSET TI2CHOLD TI2CSET SCL Start Condition Data ACK Stop Condition Figure 6. Two Wire Mode Write Bus 10 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 When the part is configured as an I2C device then the LM4937 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. Table 5. Chip Address A6 A5 A4 A3 A2 A1 A0 Chip Address A7 0 EC (1) EC (1) 1 0 0 0 0 ADR = 0 0 0 0 1 0 0 0 0 ADR = 1 0 1 1 1 0 0 0 0 (1) EC -- Externally configured by ADR pin Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 11 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com Table 6. Control Registers (1) Address Register D7 D6 D5 D4 D3 D2 D1 D0 00h Mode Control 0 CD_6 0 OCL CD_3 CD_2 CD_1 CD_0 01h Output Control 0 D_6 0 0 HP_R_ OUTPUT HP_L_ OUTPUT LS_ OUTPUT MONO_ OUTPUT 02h Mono Volume Control 0 0 0 EP_VOL_4 EP_VOL_3 EP_VOL_2 EP_VOL_1 EP_VOL_0 03h Loud Speaker Volume Control 0 0 0 LS_VOL_4 LS_VOL_3 LS_VOL_2 LS_VOL_1 LS_VOL_0 04h RESERVED 0 0 0 0 0 0 0 0 05h Headphone Left Volume Control 0 0 0 HP_L_VOL_4 HP_L_VOL_3 HP_L_VOL_2 HP_L_VOL_1 HP_L_VOL_0 06h Headphone Right Volume Control 0 0 0 HP_R_VOL_4 HP_R_VOL_3 HP_R_VOL_2 HP_R_VOL_1 HP_R_VOL_0 07h Analog R & L Input Gain Control 0 0 ANA_R_ GAIN_2 ANA_R_ GAIN_1 ANA_R_ GAIN_0 ANA_L_ GAIN_2 ANA_L _GAIN_1 ANA_L _GAIN_0 08h Analog Mono & DAC Input Gain Control 0 DIG_R_ GAIN_1 DIG_R_ GAIN_0 DIG_L_ GAIN_1 DIG_L_ GAIN_0 MONO_IN_ GAIN_2 MONO_IN_ GAIN_1 MONO_IN_ GAIN_0 09h Clock Configu ration R_DIV_3 R_DIV_2 R_DIV_1 R_DIV_0 PLL_ ENABLE AUDIO _CLK_SEL PLL_INPUT FAST_ CLOCK 0Ah PLL M Divider 0 PLL_M_6 PLL_M_5 PLL_M_4 PLL_M_3 PLL_M_2 PLL_M_1 PLL_M_0 0Bh PLL N Divider PLL_N_7 PLL_N_6 PLL_N_5 PLL_N_4 PLL_N_3 PLL_N_2 PLL_N_1 PLL_N_0 0Ch PLL N_MOD Divider and Dither Level VCO_FAST PLL_DITH_LEV_1 PLL_DITH_LEV_0 PLL_N_MOD_4 PLL_N_MOD_3 PLL_N_MOD_2 PLL_N_MOD_1 PLL_N_MOD_0 0Dh PLL_P Divider 0 0 0 0 PLL_P_3 PLL_P_2 PLL_P_1 PLL_P_0 0Eh DAC Setup 0 CUST_COMP DITHER_ALW_ON DITHER_OFF MUTE_R MUTE_L DAC_MODE_1 DAC_MODE_0 0Fh Interface 0 0 0 0 I2C_FAST I2S_MODE I2S_RESOL I2S_M/S 10h COMPENSATION _C OEFF0_LSB COMP0_7 COMP0_6 COMP0_5 COMP0_4 COMP0_3 COMP0_2 COMP0_1 COMP0_0 11h COMPENSATION _C OEFF0_MSB COMP0_15 COMP0_14 COMP0_13 COMP0_12 COMP0_11 COMP0_10 COMP0_9 COMP0_8 12h COMPENSATION _C OEFF1_LSB COMP1_7 COMP1_6 COMP1_5 COMP1_4 COMP1_3 COMP1_2 COMP1_1 COMP1_0 13h COMPENSATION _C OEFF1_MSB COMP1_15 COMP1_14 COMP1_13 COMP1_12 COMP1_11 COMP1_10 COMP1_9 COMP1_8 14h COMPENSATION _C OEFF2_LSB COMP2_7 COMP2_6 COMP2_5 COMP2_4 COMP2_3 COMP2_2 COMP2_1 COMP2_0 15h COMPENSATION _C OEFF2_MSB COMP2_15 COMP2_14 COMP2_13 COMP2_12 COMP2_11 COMP2_10 COMP2_9 COMP2_8 16h TEST_ REGISTER RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED (1) 12 Note: All registers default to 0 on initial power-up. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 SYSTEM CONTROLS Table 7. Loudspeaker, Earpiece, HP Left or Right Volume Control EP_VOL_4, LS_VOL_4, HP_L_VOL_4, HP_R_VOL_4 EP_VOL_3, LS_VOL_3, HP_L_VOL_3, HP_R_VOL_3 EP_VOL_2, LS_VOL_2, HP_L_VOL_2, HP_R_VOL_2 EP_VOL_1, LS_VOL_1, HP_L_VOL_1, HP_R_VOL_1 EP_VOL_0, LS_VOL_0, HP_L_VOL_0, HP_R_VOL_0 Gain (dB) 0 0 0 0 0 <-90 (MUTE) 0 0 0 0 1 -56 0 0 0 1 0 -52 0 0 0 1 1 -48 0 0 1 0 0 -45 0 0 1 0 1 -42 0 0 1 1 0 -39 0 0 1 1 1 -36 0 1 0 0 0 -33 0 1 0 0 1 -30 0 1 0 1 0 -28 0 1 0 1 1 -26 0 1 1 0 0 -24 0 1 1 0 1 -22 0 1 1 1 0 -20 0 1 1 1 1 -18 1 0 0 0 0 -16 1 0 0 0 1 -14 1 0 0 1 0 -12 1 0 0 1 1 -10 1 0 1 0 0 -8 1 0 1 0 1 -6 1 0 1 1 0 -4 1 0 1 1 1 -3 1 1 0 0 0 -2 1 1 0 0 1 -1 1 1 0 1 0 0 1 1 0 1 1 +1 1 1 1 0 0 +2 1 1 1 0 1 +3 1 1 1 1 0 +4 1 1 1 1 1 +5 Table 8. Mixer Code Control (1) (1) Mode CD3 CD2 CD1 CD0 Mono Earpiece Loudspeaker Headphone L Headphone R 0 0 0 0 0 SD SD SD SD 1 1 0 0 1 M M M M 2 1 0 1 0 AL+AR AL+AR AL AR 3 1 0 1 1 M+AL+AR M+AL+AR M+AL M+AR SD -- Shutdown, M -- Mono Differential Input AL -- Analog Left Channel, AR -- Analog Right Channel DL -- I2S DAC Left Channel, DR -- I2S DAC Right Channel, MUTE -- Mute Note: Power-On Default Mode is Mode 0 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 13 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com Table 8. Mixer Code Control(1) (continued) 4 1 1 0 0 DL+DR DL+DR DL DR 5 1 1 0 1 DL+DR+ AL+AR DL+AL AL+AR DL+AL DR+AR 6 1 1 1 0 M+DL+AL+ DR+AR M+DL+AL+ DR+AR M+DL+AL M+DR+AR 7 1 1 1 1 M+DL+DR M+DL+DR M+DL M+DR Table 9. Output Control (01h) LS_OUTPUT = 1 Loudspeaker Headphone Left Channel LS_OUTPUT = 0 Output On Output Off HP_L_OUTPUT = 1 HP_L_OUTPUT = 0 Output On Output Off (OCL = 0) HP_R_OUTPUT = 1 Headphone Right Channel Output On Earpiece All Outputs Output Mute (OCL = 1) HP_R_OUTPUT = 0 Output Off (OCL = 0) Output Mute (OCL = 1) EP_OUTPUT = 1 EP_OUTPUT = 0 Output On Output Off CD3 = 1 CD3 = 0 Outputs Toggled Via Register Control All Outputs Off Table 10. Mono Differential Amplifier Input Gain Select (08h) 14 MONO_IN_GAIN_2 MONO_IN_GAIN_1 MONO_IN_GAIN_0 Input Gain Setting 0 0 0 -12dB 0 0 1 -9dB 0 1 0 -6dB 0 1 1 -3dB 1 0 0 0dB 1 0 1 3dB 1 1 0 6dB 1 1 1 9dB Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Table 11. Analog Single-Ended Input Amplifier Gain Select (07h) ANA_L_GAIN_2 ANA_R_GAIN_2 ANA_L_GAIN_1 ANA_R_GAIN_1 ANA_L_GAIN_0 ANA_R_GAIN_0 Input Gain Setting 0 0 0 -6dB 0 0 1 -3dB 0 1 0 0dB 0 1 1 3dB 1 0 0 6dB 1 0 1 9dB 1 1 0 12dB 1 1 1 15dB Table 12. DAC Gain Select (08h) DIG_L_GAIN_1 DIG_R_GAIN_1 DIG_L_GAIN_0 DIG_R_GAIN_0 Input Gain Setting 0 0 -3dB 0 1 0dB 1 0 3dB 1 1 6dB PLL CONFIGURATION REGISTERS PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. Table 13. PLL_M (0Ah) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 6:0 PLL_M Programs the PLL input divider to select: (1) PLL_M Divide Ratio 0 Divider Off 1 1 2 1.5 3 2 4 2.5 ... 3 126 63.5 NOTES: The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The division of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 15 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. Table 14. PLL_N (0Bh) (Set = logic 1, Clear = logic 0) (1) (1) Bits Register Description 7:0 PLL_N Programs the PLL feedback divider: PLL_N Divide Ratio 0 Divider Off 1 10 10 11 11 12 12 ... ... 248 248 249 249 NOTES: The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used. PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL's P divider. Table 15. PLL_P (0Dh) (Set = logic 1, Clear = logic 0) (1) (1) 16 Bits Register Description 3:0 PLL_P Programs the PLL input divider to select: 0 Divider Off 1 1 2 1.5 3 2 ... -> 2.5 13 7 14 7.5 15 8 NOTES: The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes. The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. Table 16. PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 4:0 PLL_N_MOD This programs the PLL N Modulator's fractional component: 6:5 DITHER_LEVEL 7 (1) PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 30 2/32 30/32 Allows control over the dither used by the N Modulator FAST_VCO DITHER_LEVEL DAC Sub-system Input Source 00 Medium (32) 01 Small (16) 10 Large (48) If set the VCO maximum and minimum frequencies are raised: FAST_VCO Maximum FVCO 0 40-55MHz NOTES: The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. PLL_P 0.5 - 26 MHz 4 64 Phase Comparator and Charge Pump M = 0, 1 + 0/2 %M VCO 0 256 x FS OR 250 x FS 40 to 80 MHz %P 0.5 < 5 MHz P = 0, 1 + 0/2 8 External Loop Filter 7 %N 6'M 8 N = 0, 1, 2, .., 255 PLL_M 8 5 PLL_N PLL_N_MOD Table 17. Example Of PLL Settings For 48Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P f_out (MHz) 11 48 11 60 5 21 60 0 9 12 12 48 5 25 5 9 25 0 9 12 12.288 48 4 19.53125 5 7 19 17 9 12 13 48 13 60 5 25 60 0 9 12 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 17 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com Table 17. Example Of PLL Settings For 48Khz Sample Rates (continued) f_in (MHz) fsamp (kHz) M N P PLL_M 14.4 16.2 PLL_N PLL_N_MO D PLL_P f_out (MHz) 48 9 37.5 5 48 27 100 5 17 37 16 9 12 53 100 0 9 16.8 48 14 50 12 5 27 50 0 9 12 19.2 48 13 40.625 5 25 40 20 9 12 19.44 48 27 100 6 53 100 0 11 12 19.68 48 20.5 62.5 5 40 62 16 9 12 19.8 48 16.5 50 5 32 50 0 9 12 PLL_P f_out (MHz) Table 18. Example PLL Settings For 44.1Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MO D 11 44.1 11 55.125 5 21 55 4 9 11.025000 11.2896 44.1 8 39.0625 5 15 39 2 9 11.025000 12 44.1 5 22.96875 5 9 22 31 9 11.025000 13 44.1 13 55.125 5 25 55 4 9 11.025000 14.4 44.1 12 45.9375 5 23 45 30 9 11.025000 16.2 44.1 9 30.625 5 17 30 20 9 11.025000 16.8 44.1 17 55.78125 5 33 55 25 9 11.025000 19.2 44.1 16 45.9375 5 31 45 30 9 11.025000 19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025000 19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025000 19.8 44.1 11 30.625 5 21 30 20 9 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 7.0 sweep the M inputs from 2.5 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) (1) (2) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM4937 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM4937 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. 18 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 CLOCK CONFIGURATION REGISTER This register is used to control the multiplexers and clock R divider in the clock module. Table 19. CLOCK (09h) (Set = logic 1, Clear = logic 0) Bits Register Description 0 FAST_CLOCK If set master clock is divided by two. FAST_CLOCK 1 PLL_INPUT 0 Normal 1 Divided by 2 Programs the PLL input multiplexer to select: PLL_INPUT 2 AUDIO_CLK_SEL 3 PLL_ENABLE 7:4 R_DIV MCLK Frequency PLL Input Source 0 MCLK 1 I2S Input Clock Selects which clock is passed to the audio sub-system DAC_CLK_SEL DAC Sub-system Input Source 0 PLL Input 1 PLL Output If set enables the PLL. (MODES 4-7 only) Programs the R divider R_DIV Divide Value 0000 1 0001 1 0010 1.5 0011 2 0100 2.5 0101 3 0110 3.5 0111 4 1000 4.5 1001 5 1010 5.5 1011 6 1100 6.5 1101 7 1110 7.5 1111 8 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 19 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com fast_clock %2 MCLK 1 0 audio_dk_sel pll_input 0 1 PLL input clock PLL output clock I2S Interface R Div input clock %R Clock Gen input clock DAC Clock Gen I2S_INT_CLK I2S_INPUT_CLK I2S_CLK 0 1 PLL Stereo DAC 125/128 DSP CLK I2S_OUTPUT_CLK By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. Common Clock Settings for the DAC The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: DAC MODE Over sampling Ratio Used 00 125 01 128 10 64 11 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: 20 Fs (kHz) DAC Oversampling Ratio Required CLock at DAC Clock Generator Input (MHz) 8 125 2 8 128 2.048 11.025 125 2.75625 11.025 128 2.8224 12 125 3 12 128 3.072 16 125 4 16 128 4.096 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Fs (kHz) DAC Oversampling Ratio Required CLock at DAC Clock Generator Input (MHz) 22.05 125 5.5125 22.05 128 5.6448 24 125 6 24 128 6.144 32 125 8 32 128 8.192 44.1 125 11.025 44.1 128 11.2896 48 125 12 48 128 12.288 88.2 64 11.2896 96 64 12.288 176.4 32 22.5792 192 32 24.576 Methods for producing these clock frequencies are described in the PLL CONFIGURATION REGISTERS section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. R_DIV Divide Value DAC Clock Generator Input Frequency <MHz> Sample Rate Supported <KHz> 11 6 2 8 9 5 2.4 9.6 7 4 3 12 5 3 4 16 4 2.5 4.8 19.2 3 2 6 24 2 1.5 8 32 0 1 12 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. DAC SETUP REGISTER This register is used to configure the basic operation of the stereo DAC. Table 20. DAC_SETUP (0Eh) (Set = logic 1, Clear = logic 0) Bits Register Description 1:0 DAC_MODE The DAC used in the LM4937 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE Oversampling Rate Typical FS Clock Required 00 125 48KHz 12.000MHz (USB Mode) 01 128 44.1KHz 48KHz 11.2896MHz 12.288MHz 10 64 96KHz 12.288MHz 11 32 192KHz 24.576MHz 2 MUTE_L Mutes the left DAC channel on the next zero crossing. 3 MUTE_R Mutes the right DAC channel on the next zero crossing. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 21 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com Table 20. DAC_SETUP (0Eh) (Set = logic 1, Clear = logic 0) (continued) Bits Register Description 4 DITHER_OFF If set the dither in DAC is disabled. 5 DITHER ALWAYS_ON If set the dither in DAC is enabled all the time. 6 CUST_COMP If set the DAC frequency response can be programmed manually via a 5 tap FIR "compensation" filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. INTERFACE CONTROL REGISTER This register is used to control the I2S and I2C compatible interface on the chip. Table 21. INTERFACE (0Fh) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 0 I2S_MASTER_SLAVE If set the LM4937 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. If cleared the LM4937 acts as a slave where both I2S clock and word select are configured as inputs. 1 I2S_RESOLUTION If set the I2S resolution is set to 32 bits. If clear, resolution is set to 16 bits. This bit only affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. 2 I2S_MODE If set the I2S is configured in left justified mode timing. If clear, the I2S interface is configured in normal I2S mode timing. 3 I2C_FAST If set enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. If clear the I2C speed gets its default value of a maximum of 400kHz (1) NOTES: The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. LEFT CHANNEL RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 I S_SDO 1 MSB 2 3 n-1 n 1 LSB MSB 2 3 n-1 n LSB Figure 7. I2S Mode Timing 22 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 LEFT CHANNEL RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 1 I S_SDO 2 3 n-1 MSB n 1 2 LSB MSB 3 n-1 n LSB Figure 8. Left Justified Mode Timing FIR Compensation Filter Configuration Registers These registers are used to configure the DAC's FIR compensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: Table 22. COMP_COEFF (10h 15h) (Set = logic 1, Clear = logic 0) (1) (1) Address Register Description 10h COMP_COEFF0_LSB Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) 11h COMP_COEFF0_MSB Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) 12h COMP_COEFF1_LSB Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) 13h COMP_COEFF1_MSB Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) 14h COMP_COEFF2_LSB Bits [7:0] of the 3rd FIR tap (C2) 15h COMP_COEFF2_MSB Bits [15:8] of the 3rd FIR tap (C2) NOTES: The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. -1 -1 Z C0 -1 Z C1 -1 Z C2 Z C3 C4 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR C0, C4 C1, C3 C2 00 434 -2291 26984 01, 10, 11 61 -371 25699 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2's complement. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 23 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS 10 THD+N vs Frequency 3.0V EP Out, RL = 32, PO = 20mW 10 1 THD+N (%) THD+N (%) 1 THD+N vs Frequency 3.0V HP Out, RL = 16, PO = 20mW 0.1 0.01 0.1 0.01 0.001 20 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) Figure 9. 10 THD+N vs Frequency 3.0V LS Out, RL = 8, PO = 200mW 1 THD+N (%) THD+N (%) THD+N vs Frequency 5.0V EP, RL = 32, PO = 40mW 10 0.1 0.01 0.1 0.01 0.001 20 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) 10k 20k Figure 11. Figure 12. THD+N vs Frequency 5.0V HP Out, RL = 16, PO = 60mW THD+N vs Frequency 5.0V HP Out, RL = 32, PO = 30mW 10 1 THD+N (%) THD+N (%) 1k FREQUENCY (Hz) 1 0.1 0.01 0.001 20 0.1 0.01 100 1k 10k 20k 0.001 20 FREQUENCY (Hz) 100 1k 10k 20k FREQUENCY (Hz) Figure 13. 24 10k 20k Figure 10. 1 10 1k FREQUENCY (Hz) Figure 14. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 THD+N vs Frequency 5.0V LS Out, RL = 8, PO = 500mW THD+N vs Output Power 3.0V EP Out, RL = 16, f = 1kHz 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 20 0.1 0.01 100 1k 0.001 1m 10k 20k 10m OUTPUT POWER (W) Figure 16. THD+N vs Output Power 3.0V EP Out, RL = 32, f = 1kHz THD+N vs Output Power 3.0V HP Out, RL = 16, f = 1kHz 10 10 1 1 0.1 0.01 0.001 1m 0.1 0.01 10m 0.001 1m 50m 100m 10m 50m 100m OUTPUT POWER (W) Figure 17. Figure 18. THD+N vs Output Power 3.0V HP Out, RL = 32, f = 1kHz THD+N vs Output Power 3.0V LS Out, RL = 8, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.1 0.01 0.01 0.001 1m 50m 100m Figure 15. THD+N (%) THD+N (%) FREQUENCY (Hz) 10m 50m 100m 0.001 10m 100m 500m OUTPUT POWER (W) OUTPUT POWER (W) Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 25 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Output Power 5.0V EP Out, RL = 32, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Power 5.0V EP Out, RL = 16, f = 1kHz 0.1 0.01 0.1 0.01 0.001 1m 10m 0.001 1m 100m 200m 10m OUTPUT POWER (W) Figure 21. Figure 22. THD+N vs Output Power 5.0V HP Out, RL = 16, f = 1kHz THD+N vs Output Power 5.0V HP Out, RL = 32, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.01 0.001 1m 0.1 0.01 10m 0.001 1m 100m 200m 10m Figure 23. Figure 24. THD+N vs Output Power 5.0V LS Out, RL = 8, f = 1kHz THD+N vs I2S Level EP Out 10 10 1 1 0.1 0.01 0.001 10m 100m 200m OUTPUT POWER (W) THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.01 100m 2 0.001 1m OUTPUT POWER (W) 10m 100m 1 I2S INPUT LEVEL (FFS) Figure 25. 26 100m 200m Figure 26. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs I2S Level LS Out 10 10 1 1 THD+N (%) THD+N (%) THD+N vs I2S Level HP Out 0.1 0.1 0.01 0.01 0.001 1m 10m 100m 0.001 1m 1 PSRR vs Frequency 3.0V EP Out Mode 1 PSRR vs Frequency 3.0V EP Out Mode 4 0 0 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Figure 28. -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 1k 10k Figure 30. PSRR vs Frequency 3.0V HP Out Mode 2 PSRR vs Frequency 3.0V HP Out Mode 4 0 -10 -10 -20 -20 -30 -30 PSRR (dB) 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 1k 10k 100k FREQUENCY (Hz) Figure 29. 100 1 -40 FREQUENCY (Hz) PSRR (dB) 100m Figure 27. -10 -100 20 10m I2S INPUT LEVEL (FFS) I2S INPUT LEVEL (FFS) 100k FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 31. Figure 32. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 27 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) PSRR vs Frequency 3.0V LS Out Mode 4 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) PSRR vs Frequency 3.0V LS Out Mode 2 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 100 1k 10k 100k 100 Figure 34. PSRR vs Frequency 5.0V HP Out Mode 2 PSRR vs Frequency 5.0V HP Out Mode 4 0 0 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 10k Figure 35. Figure 36. PSRR vs Frequency 5.0V LS Out Mode 4 PSRR vs Frequency 5.0V LS Out Mode 2 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 1k 10k 100k -40 100k -100 20 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 37. 28 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) 100 100k -40 -70 -100 20 10k Figure 33. -10 -100 20 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) Figure 38. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Output Power vs Supply Voltage HP Out , RL = 32, 1% THD+N 280 150 240 130 OUTPUT POWER (mW) OUTPUT POWER (mW) Output Power vs Supply Voltage EP Out , RL = 32, 1% THD+N 200 160 120 80 40 0 2.7 110 90 70 50 30 3 3.5 4 4.5 5 10 2.7 5.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 39. Figure 40. Output Power vs Supply Voltage LS Out , RL = 8, 1% THD+N 2 1.8 OUTPUT POWER (W) 1.6 1.4 1.2 1 800m 600m 400m 200m 0 2.7 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 41. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 29 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com APPLICATION INFORMATION I2S The LM4937 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: MONO ONLY SETTING The LM4937 may be restricted to mono amplification only by setting D-6 in Output Control register 0x01h to 1. This may save an additional 400A from IDD. LM4937 DEMOBOARD OPERATION BOARD LAYOUT DIGITAL SUPPLIES * * * * * JP14 -- JP10 -- JP13 -- JP16 -- JP15 -- Digital Power DVDD I/O Power IOVDD PLL Supply PLLVDD USB Board Supply BBVDD I2C VDD All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. * S9 - connects VDD_PLL to VDD_D * S10 - connects VDD_D to VDD_IO * S11 - connects VDD_IO to VDD_I2C * S12 - connects VDD_I2C to Analog VDD * S17 - connects BB_VDD to USB3.3V (from USB board) * S19 - connects VDD_D to USB3.3V (from USB board) * S20 - connects VDD_D to SPDIF receiver chip ANALOG SUPPLY * * * * JP11 -- Analog Supply S12 -- connects Analog VDD with Digital VDD (I2C_VDD) S16 -- connects Analog Ground with Digital Ground S21 -- connects Analog VDD to SPDIF receiver chip INPUTS Analog Inputs * JP2 -- Mono Differential Input * JP6 -- Left Input * JP7 -- Right Input 30 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Digital Inputs * JP19 -- Digital Interface - Pin 1 -- MCLK - Pin 2 -- I2S_CLK - Pin 3 -- I2S_SDI - Pin 4 -- I2S_WS * JP20 -- Toslink SPDIF Input * JP21 -- Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. OUTPUTS * * * * * JP5 -- BTL Loudspeaker Output JP1 -- Left Headphone Output (Single-Ended or OCL) JP3 -- Right Headphone Output (Single-Ended or OCL) P1 -- Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL) JP12 -- Mono BTL Earpiece Output CONTROL INTERFACE * * * X1, X2 - USB Control Bus for I2C/SPI X1 - Pin 9 - Mode Select (SPI or I2C) X2 - Pin 1 - SDA - Pin 3 - SCL - Pin 15 - ADDR/END - Pin 14 - USB5V - Pin 16 - USB3.3V - Pin 16 - USB GND MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 - I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM4937 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode is required. S2 connects the center amplifer HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: * OCL (CD_6 = 1) - S1 = ON - S2 = ON - S3 = ON - S4 = OFF Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 31 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 * www.ti.com Cap-Coupled (CD_6 = 0) - S1 = OFF - S2 = OFF - S3 = OFF - S4 = ON PLL FILTER CONFIGURATION The LM4937 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM4937 demo board allows quick demonstration of the capabilities of the LM4937 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3.0V and analog supplies of less than 4V. This means low analog supply voltage testing of the LM4937 must be done on the external digital bus. The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up.. A quick short across S29 should clear this condition. LM4937 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM4937. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Software is available from www.ti.com and is compatible with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft. 32 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 Demonstration Board Schematic VDD_D C1 1 uF C2 VDD_A 0.1 uF C3 VDD_I2C 0.1 uF C4 1 uF 0.1 uF 1 uF VDD_PLL C5 C9 C8 1 uF JP1 0.22 uF 1 2 L IN BBVDD S17 VDD_A E2 E3 C14 1 2 0.22 uF B3 B2 A3 S18 2 1 A4 B6 C4 D4 USB_5V BB_VDD USB_3.3V S19 L1 VDD_A GND 2 S7 S23 C22 0.1 uF RXP 0.01 uF 5 R4 75 47k R5 C25 0.01 uF 24 3 28 R7 47k 14 AVDD 4 RXN H/S EMPH ORIG CHS C13 P1 220 uF JP12 F3 F2 Stereo Headphone Jack 1 2 S4 JP9 GPIO VDD_I/O B4 A6 1 2 VDD_IO C16 1uF NC NC D3 E4 C18 150 nF C19 10 nF R3 422 C27 0.33 uF X1 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 X2 1 3 5 7 9 11 13 15 S26 10 17 16 18 S27 I2S CLK R6 AUDIO C U NVERR PRO RCBL RERR COPY 19 26 25 15 13 12 11 1 47k S9 S11 S10 S12 3 2 S28 VDD_PLL JP13 1 1 2 VDD_D JP14 VDD_IO JP10 1 2 1 2 VDD_I2C JP15 VDD_A JP11 1 2 1 2 BBVDD DGND R11 7 R9 1.6k C26 4.7 nF AGND S29 RESET SPDIF RST FILT 22 DGND 21 DGND 20 DGND 9 8 MCLK I2S_WS I2S_CLK I2S_DOUT U2 CS8415A R8 47k USB_CS C12 220 uF S2 I2S WS 6 C24 2 23 DVDD 27 DVDD 2 DVDD S25 3 USB_SDA USB_SCL EPOUTP EPOUTM D5 D6 E5 C23 1 JP21 USB_SPI_M 1 2 S24 TOSLINK RECEIVER S/PDIF IN S8 MCLK BP C17 2.2 uF PLL FILTER I2S DATA R2 DIGITAL INTERFACE C21 0.1 uF F4 F6 S3 SDA/SDI SCL/SCK ADDR/ENBL MODE C1 OUTPUT S21 I2S_CLK I2S_DATA I2S_WS A1 47 uH C20 0.1 uF S5 S6 HPROUT HPCOUT HPLOUT U1 LM4937TL E6 AGRND D2 AGRND S20 3 1 7 6 5 4 3 2 1 L_IN R_IN DGND VDD_D JP20 VCC C5 JP19 14 13 12 11 10 9 8 LSLOUTM LSOUTP PLL_GND VDD_D M_IN+ M_IN- 0.22 uF JP7 JP16 1 2 S1 JP5 F1 E1 C11 R IN JP3 C30 0.22 uF JP6 1 2 AVDD AVDD 1 2 F5 C10 Diiferential Mono Input MCLK PLL_IN PLL_OUT C6 A2 C3 C2 A5 DVDD B5 I2C_VDD B1 PLL_VDD JP2 5k R10 5k R12 5k S16 USB_SPIDO USB_SCL USB_SDA USB_CS USB_SPI_M S22 2 4 6 8 10 12 14 16 USB_5V USB_SPIDO USB_3.3V USB INTERFACE Figure 42. Complete Board Schematic Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 33 LM4937 SNAS369J - OCTOBER 2006 - REVISED MAY 2013 www.ti.com JP2 C10 Diiferential Mono Input 1 2 0.22 uF C30 0.22 uF JP6 C11 1 2 L IN 0.22 uF JP7 C14 1 2 R IN JP16 BBVDD S17 VDD_A 0.22 uF S18 2 1 USB_5V BB_VDD USB_3.3V VDD_D S19 JP19 VDD_D S20 L1 14 13 12 11 10 9 8 VDD_A 47 uH JP20 VCC OUTPUT GND 3 C20 0.1 uF 1 S21 2 7 6 5 4 3 2 1 S23 MCLK DIGITAL INTERFACE C21 C22 0.1 uF 0.1 uF I2S DATA S24 TOSLINK RECEIVER 3 4 0.01 uF 5 S/PDIF IN RXP R4 75 47k R5 C25 0.01 uF 24 3 28 R7 47k 14 H/S EMPH ORIG I2S_WS I2S_CLK I2S_DOUT U2 CS8415A CHS C27 0.33 uF X1 USB_SPI_M 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 X2 USB_SDA USB_SCL USB_CS 1 3 5 7 9 11 13 15 S26 10 17 16 18 S27 I2S CLK R6 AUDIO C U NVERR PRO RCBL RERR COPY 19 26 25 15 13 12 11 1 47k 3 2 S28 1 BBVDD R11 7 4.7 nF AGND R9 1.6k C26 RST FILT 22 DGND 21 DGND 20 DGND S29 RESET SPDIF MCLK RXN R8 47k 9 8 I2S WS AVDD C24 2 6 S25 23 DVDD 27 DVDD 2 DVDD 1 JP21 5k R10 5k R12 5k USB_SPIDO USB_SCL USB_SDA USB_CS USB_SPI_M S22 2 4 6 8 10 12 14 16 USB_5V USB_SPIDO USB_3.3V USB INTERFACE Figure 43. Enlarged Board Schematic Part 1 of 2 34 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 LM4937 www.ti.com SNAS369J - OCTOBER 2006 - REVISED MAY 2013 VDD_D C1 1 uF C2 VDD_A 0.1 uF C3 VDD_I2C 0.1 uF C4 1 uF VDD_PLL C5 1 uF C9 C8 0.1 uF 1 uF JP1 1 2 F5 C6 AVDD AVDD MCLK PLL_IN PLL_OUT A5 DVDD B5 I2C_VDD B1 PLL_VDD A2 C3 C2 JP3 1 2 S1 JP5 F1 E1 E2 E3 B3 B2 A3 A4 B6 C4 D4 L_IN R_IN LM4937TL I2S_CLK I2S_DATA I2S_WS 1 2 D5 D6 E5 C12 P1 220 uF S2 C13 220 uF JP12 F3 F2 Stereo Headphone Jack 1 2 S4 JP9 GPIO VDD_I/O B4 A6 1 2 VDD_IO C16 1uF C1 E6 AGRND D2 AGRND BP F4 F6 S3 A1 PLL FILTER EPOUTP EPOUTM SDA/SDI SCL/SCK ADDR/ENBL MODE C17 2.2 uF S8 HPROUT HPCOUT HPLOUT U1 DGND S7 LSLOUTM LSOUTP PLL_GND C5 S5 S6 M_IN+ M_IN- NC NC D3 E4 C18 150 nF C19 10 nF R2 R3 422 C23 S9 S11 S10 VDD_PLL JP13 1 2 VDD_D JP14 VDD_IO JP10 1 2 S12 VDD_I2C JP15 1 2 VDD_A JP11 1 2 1 2 DGND S16 Figure 44. Enlarged Board Schematic Part 2 of 2 REVISION HISTORY Rev Date Description 1.0 10/04/06 Initial release. 1.1 10/13/06 Text edits. 1.2 12/15/06 Changed the datasheet title from RF Resistant Topology to RF Suppression. 1.3 02/09/07 Replaced curve (THD+N vs Output Power, 3V LS Out) with the curve 20166975 from LM4934. These 2 curves have identical performance). 1.4 07/23/07 Changed the datasheet I2C Vdd & VDD_IO to 1.7V. 1.5 07/30/07 Added more tables (SPI/I2S). 1.6 08/03/07 Text edits. 1.7 10/12/07 Edited 20202001 and 58 and input some text edits. 1.8 10/31/07 Added the RL package. J 05/03/13 Changed layout of National Data Sheet to TI format. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4937 35 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) LM4937RL/NOPB ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YPG 36 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 85 GJ3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM4937RL/NOPB Package Package Pins Type Drawing SPQ DSBGA 250 YPG 36 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 12.4 Pack Materials-Page 1 3.43 B0 (mm) K0 (mm) P1 (mm) 3.59 0.76 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4937RL/NOPB DSBGA YPG 36 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPG0036xxx D 0.6500.075 E RLA36XXX (Rev A) D: Max = 3.525 mm, Min =3.465 mm E: Max = 3.268 mm, Min =3.208 mm 4214895/A NOTES: A. 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