ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 ADC0820-N 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function Check for Samples: ADC0820-N FEATURES KEY SPECIFICATIONS * * * * * * * 1 2 * * * * * * * * * Built-In Track-and-Hold Function No Missing Codes No External Clocking Single Supply--5 VDC Easy Interface to All Microprocessors, or Operates Stand-Alone Latched TRI-STATE Output Logic Inputs and Outputs Meet Both MOS and T2L Voltage Level Specifications Operates Ratiometrically or with any Reference Value Equal to or Less than VCC 0V to 5V Analog Input Voltage Range with Single 5V Supply No Zero or Full-Scale Adjust Required Overflow Output Available for Cascading 0.3 in. Standard Width 20-Pin PDIP 20-Pin PLCC 20-Pin SOIC * * Resolution: 8 Bits Conversion Time - 2.5 s Max (RD Mode) - 1.5 s Max (WR-RD Mode) Low Power: 75 mW Max Total Unadjusted Error: 1/2 LSB and 1 LSB DESCRIPTION By using a half-flash conversion technique, the 8-bit ADC0820-N CMOS A/D offers a 1.5 s conversion time and dissipates only 75 mW of power. The halfflash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the ADC0820-N is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/s. For ease of interface to microprocessors, the ADC0820-N has been designed to appear as a memory location or I/O port without the need for external interfacing logic. Connection and Functional Diagrams Figure 1. CDIP, PDIP, and SOIC Packages (Top View) Figure 2. PLCC Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Figure 3. Functional Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VCC) 10V Logic Control Inputs -0.2V to VCC +0.2V Voltage at Other Inputs and Output -0.2V to VCC +0.2V -65C to +150C Storage Temperature Range Package Dissipation at TA = 25C 875 mW Input Current at Any Pin (4) 1 mA Package Input Current (4) 4 mA ESD Susceptibility (5) Lead Temp. (Soldering, 10 sec.) 900V PDIP Package 260C CDIP Package 300C SOIC Package (1) (2) (3) (4) (5) Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. All voltages are measured with respect to the GND pin, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V-or VIN > V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four. Human body model, 100 pF discharged through a 1.5 k resistor. Operating Ratings (1) (2) -40CTA+85C ADC0820CCJ, ADC0820CIWM Temperature Range (TMINTATMAX) ADC0820BCN, ADC0820CCN, ADC0820BCV, ADC0820BCWM, ADC0820CCWM VCC Range (1) (2) 2 0CTA70C 4.5V to 8V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. All voltages are measured with respect to the GND pin, unless otherwise specified. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Converter Characteristics The following specifications apply for RD mode (pin 7 = 0), VCC = 5V, VREF(+) = 5V,and VREF(-) = GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25C. ADC0820CCJ Parameter Conditions Design Limit (3) 8 8 Bits 1/2 1/2 LSB ADC0820CCN, CCWM, CIWM 1 1 LSB ADC0820CCMSA 1 1 LSB Resolution Design Limit (3) Typ (1) 8 ADC0820BCN, BCWM Total Unadjusted Error (4) Limit Units Tested Limit (2) Typ (1) Tested Limit (2) ADC0820BCN, ADC0820CCN, ADC0820BCV, ADC0820BCWM, ADC0820CCWM, ADC0820CIWM ADC0820CCJ 1 LSB Minimum Reference Resistance 2.3 1.00 2.3 1.2 Maximum Reference Resistance 2.3 6 2.3 5.3 6 k k Maximum VREF(+) Input Voltage VCC VCC VCC V Minimum VREF(-) Input Voltage GND GND GND V Minimum VREF(+) Input Voltage VREF(-) VREF(-) VREF(-) V Maximum VREF(-) Input Voltage VREF(+) VREF(+) VREF(+) V Maximum VIN Input Voltage VCC+0.1 VCC+0.1 VCC+0.1 V Minimum VIN Input Voltage GND-0.1 GND-0.1 GND-0.1 V Maximum Analog Input Leakage Current Power Supply Sensitivity (1) (2) (3) (4) CS =VCC VIN=VCC 3 0.3 3 A VIN=GND -3 -0.3 -3 A 1/4 1/4 LSB VCC=5V5% 1/16 1/4 1/16 Typicals are at 25C and represent most likely parametric norm. Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. Total unadjusted error includes offset, full-scale, and linearity errors. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 3 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com DC Electrical Characteristics The following specifications apply for VCC = 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25C. ADC0820BCN, ADC0820CCN, ADC0820BCV, ADC0820BCWM, ADC0820CCWM, ADC0820CIWM ADC0820CCJ Parameter Conditions Typ (1) VIN(1), Logical "1" Input Voltage VIN(0), Logical "0" Input Voltage VCC=5.25V VCC=4.75V IIN(0), Logical "0" Input Current Design Limit (3) Typ (1) Tested Limit (2) Design Limit (3) CS , WR , RD 2.0 2.0 2.0 V Mode 3.5 3.5 3.5 V CS , WR , RD 0.8 0.8 0.8 V Mode 1.5 1.5 1.5 V VIN(1)=5V; CS , RD IIN(1), Logical "1" Input Current Tested Limit (2) Limit Units 0.005 1 0.005 1 A VIN(1)=5V; WR 0.1 3 0.1 0.3 3 A VIN(1)=5V; Mode 50 200 50 170 200 A -0.005 -1 -0.005 -1 A VIN(0)=0V; CS, RD, WR, Mode VCC=4.75V, IOUT=-360 A; DB0-DB7, OFL , INT 2.4 2.8 2.4 V VCC=4.75V, IOUT=-10 A; DB0-DB7, OFL , INT 4.5 4.6 4.5 V VOUT(0), Logical "0" Output Voltage VCC=4.75V, IOUT=1.6 mA; DB0-DB7, OFL , INT , RDY 0.4 0.34 0.4 V IOUT, TRI-STATE Output Current VOUT=5V; DB0-DB7, RDY 0.1 3 0.1 0.3 3 A VOUT=0V; DB0-DB7, RDY -0.1 -3 -0.1 -0.3 -3 A ISOURCE, Output Source Current VOUT=0V; DB0-DB7, OFL -12 -6 -12 -7.2 -6 mA INT -9 -4.0 -9 -5.3 -4.0 mA ISINK, Output Sink Current VOUT=5V; DB0-DB7, OFL , INT , RDY 14 7 14 8.4 7 mA ICC, Supply Current CS =WR =RD =0 7.5 15 7.5 13 15 mA VOUT(1), Logical "1" Output Voltage (1) (2) (3) 4 Typicals are at 25C and represent most likely parametric norm. Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 AC Electrical Characteristics The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(-) = 0V and TA = 25C unless otherwise specified. Parameter Conditions Tested Limit (2) Typ (1) Design Limit (3) Units tCRD, Conversion Time for RD Mode Pin 7 = 0 (Figure 4) 1.6 2.5 s tACC0, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = 0 (Figure 4) tCRD + 20 tCRD + 50 ns tCWR-RD, Conversion Time for WR-RD Mode Pin 7 = VCC; tWR = 600 ns, tRD=600 ns (Figure 5 & Figure 6) 1.52 s tWR, Write Time tRD, Read Time Min Pin 7 = VCC (Figure 5 & Figure 6) Max Figure 11 (4) Min Pin 7 = VCC (Figure 5 & Figure 6 & Figure 12) (4) 600 ns 50 s 600 ns tACC1, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = VCC, tRD < tI, CL = 15pF (Figure 5) 190 280 ns CL = 100 pF 210 320 ns tACC2, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = VCC, tRD > tI, CL = 15pF (Figure 6) 70 120 ns CL=100 pF 90 150 ns tACC3, Access Time (Delay from Rising Edge of RDY to Output Valid) RPULLUP = 1k and CL = 15 pF 30 tI, Internal Comparison Time Pin 7 = VCC, CL = 50pF (Figure 6 & Figure 7) 800 1300 ns t1H, t0H, TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) RL = 1k, CL = 10 pF 100 200 ns tI ns tRD+200 tRD+290 ns 125 225 ns tINTHWR, Delay from Rising Edge of WR to CL = 50pF (Figure 7) Rising Edge of INT 175 270 ns tRDY, Delay from CS to RDY CL = 50 pF, Pin 7 = 0 (Figure 4) 50 100 ns tID, Delay from INT to Output Valid See Figure 7 20 50 ns tRI, Delay from RD to INT Pin 7 = VCC, tRD<tI Figure 5 200 290 ns tP, Delay from End of Conversion to Next Conversion (Figure 4 & Figure 5 & Figure 6 & Figure 7 & Figure 13) (4) 500 ns tINTL, Delay from Rising Edge of WR to Falling Edge of INT Pin 7 = VCC, CL = 50 pF tRD > tI (Figure 6) tINTH, Delay from Rising Edge of RD to Rising Edge of INT CL = 50pF (Figure 4 & Figure 5 & Figure 6) tRD < tI (Figure 5) ns Slew Rate, Tracking 0.1 V/s CVIN, Analog Input Capacitance 45 pF COUT, Logic Output Capacitance 5 pF CIN, Logic Input Capacitance 5 pF (1) (2) (3) (4) Typicals are at 25C and represent most likely parametric norm. Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Figure 11 and Figure 12 graphs. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 5 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com TRI-STATE Test Circuits and Waveforms tr=20 ns t1H Circuit t1H Waveform t0H Circuit t0H Waveform tr=20 ns Timing Diagrams Note: On power-up the state of INT can be high or low. Figure 4. RD Mode (Pin 7 is Low) 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Figure 5. WR-RD Mode (Pin 7 is High and tRD<tI) Figure 6. WR-RD Mode (Pin 7 is High and tRD>tI) Figure 7. WR-RD Mode (Pin 7 is High) Stand-Alone Operation Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 7 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 8 Logic Input Threshold Voltage vs. Supply Voltage Conversion Time (RD Mode) vs. Temperature Figure 8. Figure 9. Power Supply Current vs. Temperature (not including reference ladder) Accuracy vs. tWR Figure 10. Figure 11. Accuracy vs. tRD Accuracy vs. tp Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF Accuracy vs. [VREF=VREF(+)-VREF(-)] tI, Internal Time Delay vs. Temperature Figure 14. Figure 15. Output Current vs. Temperature Figure 16. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 9 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin Name Function 1 VIN Analog input; range =GNDVINVCC 2 DB0 TRI-STATE data output--bit 0 (LSB) 3 DB1 TRI-STATE data output--bit 1 4 DB2 TRI-STATE data output--bit 2 5 DB3 TRI-STATE data output--bit 3 6 WR-RD Mode WR: With CS low, the conversion is started on the falling edge of WR. Approximately 800 ns (the preset internal time out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (See Figure 5 & Figure 6). RD Mode RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS; RDY will go TRI-STATE when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (See Figure 4). WR / RDY Mode: Mode selection input--it is internally tied to GND through a 50 A current source. 7 Mode RD Mode: When mode is low WR-RD Mode: When mode is high 8 9 WR-RD Mode With CS low, the TRI-STATE data outputs (DB0-DB7) will be activated when RD goes low (See Figure 7). RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (tI, 800 ns). If this is done, the data result transferred to output latch is latched after the falling edge of the RD (See Figure 5 & Figure 6). RD Mode With CS low, the conversion will start with RD going low, also RD will enable the TRI-STATE data outputs at the completion of the conversion. RDY going TRI-STATE and INT going low indicates the completion of the conversion (See Figure 4). WR-RD Mode INT going low indicates that the conversion is completed and the data result is in the output latch. INT will go low, 800 ns (the preset internal time out, tI) after the rising edge of WR (See Figure 6); or INT will go low after the falling edge of RD , if RD goes low prior to the 800 ns time out (See Figure 5). INT is reset by the rising edge of RD or CS (See Figure 5 & Figure 6). RD Mode INT going low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or CS (See Figure 4). RD INT 10 GND Ground 11 VREF(-) The bottom of resistor ladder, voltage range: GNDVREF(-)VREF(+) (1) 12 VREF(+) The top of resistor ladder, voltage range: VREF(-)VREF(+)VCC (1) 13 CS CS must be low in order for the RD or WR to be recognized by the converter. 14 DB4 TRI-STATE data output--bit 4 15 DB5 TRI-STATE data output--bit 5 16 DB6 TRI-STATE data output--bit 6 17 DB7 TRI-STATE data output--bit 7 (MSB) 18 OFL Overflow output--If the analog input is higher than the VREF(+), OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). This output is always active and does not go into TRI-STATE as DB0-DB7 do. 19 NC No connection 20 VCC Power supply voltage (1) 10 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V-or VIN > V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 FUNCTIONAL DESCRIPTION GENERAL OPERATION The ADC0820-N uses two 4-bit flash A/D converters to make an 8-bit measurement (Figure 3). Each flash ADC is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. To take a full 8-bit reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an analog approximation of the input voltage. This analog signal is then subtracted from the input, and the difference voltage is converted by a second 4-bit flash ADC (the LS ADC), providing the 4 least significant bits of the output data word. The internal DAC is actually a subsection of the MS flash converter. This is accomplished by using the same resistor ladder for the A/D as well as for generating the DAC signal. The DAC output is actually the tap on the resistor ladder which most closely approximates the analog input. In addition, the "sampled-data" comparators used in the ADC0820-N provide the ability to compare the magnitudes of several analog signals simultaneously, without using input summing amplifiers. This is especially useful in the LS flash ADC, where the signal to be converted is an analog difference. THE SAMPLED-DATA COMPARATOR Each comparator in the ADC0820-N consists of a CMOS inverter with a capacitively coupled input (Figure 17 Figure 18). Analog switches connect the two comparator inputs to the input capacitor (C) and also connect the inverter's input and output. This device in effect now has one differential input pair. A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison. In the first cycle, one input switch and the inverter's feedback switch (Figure 17) are closed. In this interval, C is charged to the connected input (V1) less the inverter's bias voltage (VB, approximately 1.2V). In the second cycle (Figure 18), these two switches are opened and the other (V2) input's switch is closed. The input capacitor now subtracts its stored voltage from the second input and the difference is amplified by the inverter's open loop gain. The inverter's input (VB) becomes (1) and the output will go high or low depending on the sign of VB-VB. The actual circuitry used in the ADC0820-N is a simple but important expansion of the basic comparator described above. By adding a second capacitor and another set of switches to the input (Figure 19), the scheme can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch on each capacitor (Z switches) are closed in the zeroing cycle. A comparison is then made by connecting the second input on each capacitor and opening all of the other switches (S switches). The change in voltage at the inverter's input, as a result of the change in charge on each input capacitor, will now depend on both input signal differences. * * * * VO = VB V on C = V1-VB CS = stray input node capacitor VB = inverter input bias voltage Zeroing Phase Figure 17. Sampled-Data Comparator Compare Phase Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 11 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Figure 18. Sampled-Data Comparator Figure 19. ADC0820-N Comparator (from MS Flash ADC) ARCHITECTURE In the ADC0820-N, one bank of 15 comparators is used in each 4-bit flash A/D converter (Figure 25). The MS (most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while the other is comparing. When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from zeroing to comparison mode (Figure 24). When WR is returned high after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600 ns later, the RD line may be pulled low to latch the lower 4 data bits and finish the 8-bit conversion. When RD goes low, the flash A/Ds change state once again in preparation for the next conversion. Figure 24 also outlines how the converter's interface timing relates to its analog input (VIN). In WR-RD mode, VIN is measured while WR is low. In RD mode, sampling occurs during the first 800 ns of RD. Because of the input connections to the ADC0820-N's LS and MS comparators, the converter has the ability to sample VIN at one instant (see Inherent Sample-Hold), despite the fact that two separate 4-bit conversions are being done. More specifically, when WR is low the MS flash is in compare mode (connected to VIN), and the LS flash is in zero mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time. DIGITAL INTERFACE The ADC0820-N has two basic interface modes which are selected by strapping the MODE pin high or low. RD Mode With the MODE pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is done by pulling RD low until output data appears. An INT line is provided which goes low at the end of the conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system Transfer Acknowledge signal. Figure 20. RD Mode (Pin 7 is Low) When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash converter goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns, data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800 ns, the lower 4 bits are recovered. 12 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 WR then RD Mode With the MODE pin tied high, the A/D will be set up for the WR-RD mode. Here, a conversion is started with the WR input; however, there are two options for reading the output data which relate to interface timing. If an interrupt driven scheme is desired, the user can wait for INT to go low before reading the conversion result (Figure 22). INT will typically go low 800 ns after WR's rising edge. However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a read after only 600 ns (Figure 21). If this is done, INT will immediately go low and data will appear at the outputs. Figure 21. WR-RD Mode (Pin 7 is High and tRD<tI) Figure 22. WR-RD Mode (Pin 7 is High and tRD>tI) Stand-Alone For stand-alone operation in WR-RD mode, CS and RD can be tied low and a conversion can be started with WR. Data will be valid approximately 800 ns following WR's rising edge. Figure 23. WR-RD Mode (Pin 7 is High) Stand-Alone Operation Note: MS means most significant LS means least significant Figure 24. Operating Sequence (WR-RD Mode) OTHER INTERFACE CONSIDERATIONS In order to maintain conversion accuracy, WR has a maximum width spec of 50 s. When the MS flash ADC's sampled-data comparators (see The Sampled-Data Comparator) are in comparison mode (WR is low), the input capacitors (C, Figure 19) must hold their charge. Switch leakage and inverter bias current can cause errors if the comparator is left in this phase for too long. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 13 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Since the MS flash ADC enters its zeroing phase at the end of a conversion (see Architecture), a new conversion cannot be started until this phase is complete. The minimum spec for this time (tP, see Figure 4 & Figure 5 & Figure 6 & Figure 7) is 500 ns. Detailed Block Diagram Figure 25. 14 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Analog Considerations REFERENCE AND INPUT The two VREF inputs of the ADC0820-N are fully differential and define the zero to full-scale input range of the A to D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN(+) and VIN(-). By reducing VREF(VREF = VREF(+) - VREF(-)) to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF = 2V then 1 LSB = 7.8 mV). The input/reference arrangement also facilitates ratiometric operation and in many cases the chip power supply can be used for transducer power as well as the VREF source. This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF(-) sets the input level which produces a digital output of all zeroes. Though VIN is not itself differential, the reference design affords nearly differential-input capability for most measurement applications. Figure 26 shows some of the configurations that are possible. INPUT CURRENT Due to the unique conversion techniques employed by the ADC0820-N, the analog input behaves somewhat differently than in conventional devices. The A/D's sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. The equivalent input circuit of the ADC0820-N is shown in Figure 27. When a conversion starts (WR low, WR-RD mode), all input switches close, connecting VIN to thirty-one 1 pF capacitors. Although the two 4-bit flash circuits are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because the MS flash converter is connected to the input during its compare interval and the LS flash is connected to the input during its zeroing phase (see Architecture). In other words, the LS ADC uses VIN as its zero-phase input. The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5 k to 10 k). In addition, about 12 pF of input stray capacitance must also be charged. For large source resistances, the analog input can be modeled as an RC network as shown in Figure 28. As RS increases, it will take longer for the input capacitance to charge. In RD mode, the input switches are closed for approximately 800 ns at the start of the conversion. In WR-RD mode, the time that the switches are closed to allow this charging is the time that WR is low. Since other factors force this time to be at least 600 ns, input time constants of 100 ns can be accommodated without special consideration. Typical total input capacitance values of 45 pF allow RS to be 1.5 k without lengthening WR to give VIN more time to settle. External Reference 2.5V Full-Scale Power Supply as Reference Input Not Referred to GND Figure 26. Analog Input Options Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 15 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Figure 27. ADC0820-N Input Circuit Figure 28. Analog Input, RC Network Model INPUT FILTERING It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/D's performance in most cases. In effect the ADC0820-n does not "look" at the input when these transients occur. The comparators' outputs are not latched while WR is low, so at least 600 ns will be provided to charge the ADC's input capacitance. It is therefore not necessary to filter out these transients by putting an external cap on the VIN terminal. INHERENT SAMPLE-HOLD Another benefit of the ADC0820-N's input mechanism is its ability to measure a variety of high speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain at least 1/2 LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled, and held stationary during the conversion. Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (see The Sampled Data Comparator). Although the conversion time for the ADC0820-N is 1.5 s, the time through which VIN must be 1/2 LSB stable is much smaller. Since the MS flash ADC uses VIN as its "compare" input and the LS ADC uses VIN as its "zero" input, the ADC0820-N only "samples" VIN when WR is low (see Architecture and Input Current). Even though the two flashes are not done simultaneously, the analog signal is measured at one instant. The value of VIN approximately 100 ns after the rising edge of WR (100 ns due to internal logic prop delay) will be the measured value. Input signals with slew rates typically below 100 mV/s can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the ADC0820-N's loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. An SAR type converter with a conversion time as fast as 1 s would still not be able to measure a 5V 1 kHz sine wave without the aid of an external sample-and-hold. The ADC0820-N, with no such help, can typically measure 5V, 7 kHz waveforms. 16 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Typical Applications Figure 29. 8-Bit Resolution Configuration Figure 30. 9-Bit Resolution Configuration * VIN=3 kHz max 4VP * No track-and-hold needed * Low power consumption Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 17 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Figure 31. Telecom A/D Converter Figure 32. Multiple Input Channels Figure 33. 8-Bit 2-Quadrant Analog Multiplier 18 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 Figure 34. Fast Infinite Sample-and-Hold Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 19 ADC0820-N SNAS529C - JUNE 1999 - REVISED MARCH 2013 www.ti.com Figure 35. Digital Waveform Recorder 20 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N ADC0820-N www.ti.com SNAS529C - JUNE 1999 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: ADC0820-N 21 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) ADC0820BCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820 BCWM ADC0820CCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0820CCN ADC0820CCN/PB NRND PDIP NFH 20 18 TBD Call TI Call TI ADC0820CCWM NRND SOIC DW 20 36 TBD Call TI Call TI -40 to 85 ADC0820 CCWM ADC0820CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820 CCWM ADC0820CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0820 CCWM ADC0820CCN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC0820BCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 ADC0820CCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0820BCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 ADC0820CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NFH0020A N0020A N20A (Rev G) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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