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LMH0387
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LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver
1 Features 3 Description
The LMH0387 3 Gbps HD/SD SDI Configurable I/O
1• ST 424, ST 292, ST 344, and ST 259 Compliant Adaptive Cable Equalizer / Cable Driver provides a(1) single chip interface to a BNC. The device can be
• Supports DVB-ASI at 270 Mbps configured either in the input mode as an equalizer to
• Data Rates: 125 Mbps to 2.97 Gbps when receive data over coaxial cable or in the output mode
as a cable driver to transmit data over coaxial cable.
Receiving (DC to 2.97 Gbps when Driving Cable) The same I/O pin is used both for the input and the
• Equalizes up to 120 Meters of Belden 1694A at output functions of the device, allowing the system
2.97 Gbps, up to 200 Meters of Belden 1694A at designer the flexibility to use a BNC attached to the
1.485 Gbps, or up to 400 Meters of Belden 1694A device as either an input or an output.
at 270 Mbps The device operates over a wide range of data rates
• Integrated Return Loss Network (No External from 125 Mbps to 2.97 Gbps (DC to 2.97 Gbps when
Components Required) driving cable) and supports ST 424, ST 292, ST 344,
• Power Saving Modes and ST 259. The return loss network is integrated
within the device so no external components are
• Cable Driver Selectable Slew Rate required to meet the SMPTE return loss specification.
• Internally Terminated 100-ΩLVDS Receiver The LMH0387 offers designers flexibility in system
Outputs With Programmable Common Mode design and quicker time to market.
Voltage and Swing In the input mode, the LMH0387 features include a
• Programmable Launch Amplitude Optimization for power-saving sleep mode, programmable output
Receiver common mode voltage and swing, cable length
• Cable Length Indication indication, launch amplitude optimization, input signal
• Single 3.3-V Supply Operation detection, and an SPI interface. In the output mode,
the LMH0387 features include two selectable slew
• 48-Pin Laminate TLGA Package rates for ST 424 / 292 and ST 259 compliance, and
• Industrial Temperature Range: −40°C to 85°C output driver power-down control.
The device is available in a 7-mm × 7-mm 48-pin
2 Applications laminate Thin Laminate Grid Array (TLGA) Package.
• ST 424 (SMPTE 424M), ST 292 (SMPTE 292M),
and ST 259 (SMPTE 259M) Serial Digital Device Information(1)
Interfaces (1) PART NUMBER PACKAGE BODY SIZE (NOM)
• Digital Video Servers and Modular Equipment LMH0387 TLGA (48) 7.00 mm × 7.00 mm
• Video Encoders and Decoders (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Distribution Amplifiers
Typical Application
(1) Due to SMPTE naming convention, all SMPTE Engineering
Documents will be numbered as a two-letter prefix and a
number. Documents and references with the same root
number and year are functionally identical; for example ST
424-2006 and SMPTE 424M-2006 refer to the same
document.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0387
SNLS315H –APRIL 2010–REVISED AUGUST 2015
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Table of Contents
1 Features.................................................................. 17 Detailed Description............................................ 11
7.1 Overview................................................................. 11
2 Applications ........................................................... 17.2 Functional Block Diagram....................................... 11
3 Description............................................................. 17.3 Feature Description................................................. 11
4 Revision History..................................................... 27.4 Device Functional Modes........................................ 14
5 Pin Configuration and Functions......................... 37.5 Programming........................................................... 14
6 Specifications......................................................... 57.6 Register Maps......................................................... 17
6.1 Absolute Maximum Ratings ...................................... 58 Application and Implementation ........................ 19
6.2 ESD Ratings.............................................................. 58.1 Application Information............................................ 19
6.3 Recommended Operating Conditions....................... 58.2 Typical Application ................................................. 19
6.4 Thermal Information.................................................. 59 Power Supply Recommendations...................... 21
6.5 Control Pin Electrical Characteristics........................ 610 Layout................................................................... 21
6.6 Input Mode (Equalizer) DC Electrical
Characteristics ........................................................... 610.1 Layout Guidelines ................................................. 21
6.7 Output Mode (Cable Driver) DC Electrical 10.2 Layout Example .................................................... 22
Characteristics ........................................................... 711 Device and Documentation Support................. 23
6.8 Input Mode (Equalizer) AC Electrical 11.1 Documentation Support ........................................ 23
Characteristics ........................................................... 711.2 Community Resources.......................................... 23
6.9 Output Mode (Cable Driver) AC Electrical 11.3 Trademarks........................................................... 23
Characteristics ........................................................... 811.4 Electrostatic Discharge Caution............................ 23
6.10 Input Mode (Equalizer) SPI Interface AC Electrical 11.5 Glossary................................................................ 23
Characteristics ........................................................... 812 Mechanical, Packaging, and Orderable
6.11 Typical Characteristics.......................................... 10 Information........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision F (April 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 18
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1
LMH0387
(Top View)
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
VEE
SD/HD
VCCTX
VCCTX
BNC_IO
SS
RSVD
RSVD
RSVD
RSVD
TERMRX
SPI_EN
AEC+
AEC-
CD
CDTHRESH
VEE
VEE
SDO
SDO
MISO
VCCRX
VEE
VEE
SDI
SDI
VEE
RREF
SCK
MOSI
TX_EN
VEE
VCCTX
RSVD
TERMTX
RSVD
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VEE
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5 Pin Configuration and Functions
NPD Package
48-Pin TLGA
Top View
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Pin Functions
PIN I/O, TYPE DESCRIPTION
NAME NO.
AEC loop filter external capacitor for equalizer (1 µF connected between AEC+ and
AEC+, AEC- 20, 21 I/O, Analog AEC-).
Serial digital interface input or output for connection to a BNC. Connect this pin to the
BNC_IO 8 I/O, Analog BNC through an AC coupling capacitor (nominally 4.7 μF).
Carrier detect for BNC_IO pin.
CD 22 O, LVCMOS H = No input signal detected on BNC_IO pin.
L = Input signal detected on BNC_IO pin.
Carrier detect threshold input. Sets the threshold for CD. CDTHRESH may be either
CDTHRESH 23 I, Analog unconnected or connected to ground for normal CD operation.
MISO (SPI) 29 O, LVCMOS SPI Master Input / Slave Output. LMH0387 control data transmit.
MOSI (SPI) 39 I, LVCMOS SPI Master Output / Slave Input. LMH0387 control data receive.
BNC_IO output driver level control. Connect a resistor (nominally 715 Ω) to VCC to set
RREF 36 I, Analog the output voltage swing for the BNC_IO pin.
1, 4-7, 9–16,
RSVD N/A Do not connect.
42, 46-48
SCK (SPI) 38 I, LVCMOS SPI serial clock input.
BNC_IO output slew rate control. SD/HD has an internal pulldown.
SD/HD 44 I, LVCMOS H = BNC_IO output rise/fall time complies with SMPTE 259M (SD).
L = BNC_IO output rise/fall time complies with SMPTE 424M / 292M (3G/HD).
SDI, SDI 33, 34 I, Analog Serial data differential input for transmitter (cable driver).
SDO, SDO 27, 28 O, LVDS Serial data differential output from receiver (equalizer).
SPI register access enable (equalizer). This pin should always be high; it must be pulled
SPI_EN 18 I, LVCMOS high while operating in the input mode and may optionally be pulled high while operating
in the output mode. This pin has an internal pulldown.
SS (SPI) 26 I, LVCMOS SPI slave select. This pin has an internal pullup.
Termination for unused receiver (equalizer) input. This network should consist of a 1-µF
TERMRX 17 I, Analog capacitor followed by a 220-Ωresistor to ground.
Termination for unused transmitter (cable driver) output. This network should consist of a
TERMTX 45 O, Analog 4.7-µF capacitor followed by a 75-Ωresistor to ground.
Transmitter output driver enable. TX_EN has an internal pullup.
H = BNC_IO output driver is enabled.
L = BNC_IO output driver is powered off.
TX_EN 40 I, LVCMOS To configure the LMH0387 as a receiver, the BNC_IO output driver must be disabled by
tying TX_EN low. To configure the LMH0387 as a transmitter, the output driver must be
enabled by tying TX_EN high and the receiver may be powered down using the sleep
mode setting through the SPI.
VCCTX 2, 3, 43 Power Positive power supply for transmitter (3.3 V).
19, 24, 25, 31,
VEE Power Negative power supply (ground).
32, 35, 37, 41
VCCRX 30 Power Positive power supply for receiver (3.3 V).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage 4 V
Input Voltage (all inputs) −0.3 VCC+0.3 V
Junction Temperature 125 °C
Storage Temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±6000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge ±2500 V
C101(2)
Machine model ±300
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
Supply Voltage (VCC – VEE) 3.14 3.3 3.46 V
BNC_IO Input / Output Coupling Capacitance 4.7 µF
AEC Capacitor (Connected between AEC+ and AEC-) 1 µF
Operating Free Air Temperature (TA)−40 85 °C
6.4 Thermal Information LMH0387
THERMAL METRIC(1) NPD (TLGA) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 64.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.8 °C/W
RθJB Junction-to-board thermal resistance 32.3 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 32 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Control Pin Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input Voltage High Level 2 VCC V
VIL Input Voltage Low Level VEE 0.8 V
VOH Output Voltage High Level IOH = –2 mA 2.4 V
VOL Output Voltage Low Level IOL = 2 mA 0.4 V
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3 V and TA= 25°C.
6.6 Input Mode (Equalizer) DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input Voltage Swing 0-m cable length(3) 720 800 950 mVP−P
VSSP-P Differential Output Voltage, P-P 500 700 900 mVP-P
VOD Differential Output Voltage 250 350 450 mV
Change in Magnitude of VOD for
ΔVOD 100-Ωload, default register settings, 50 mV
complementary Output States Figure 1(4)
VOS Offset Voltage 1.125 1.25 1.375 V
Change in Magnitude of VOS for
ΔVOS 50 mV
complementary Output States
IOS Output Short Circuit Current 30 mA
CDTHRESH CDTHRESH DC Voltage (floating) 1.3 V
CDTHRNG CDTHRESH Range 0.8 V
Equalizing cable > 120 m 91 113 mA
(Belden 1694A), TX_EN = 0
Equalizing cable ≤120 m
ICC Supply Current 71 mA
(Belden 1694A), TX_EN = 0(5)
Power save mode (equalizer in sleep 11 mA
mode, TX_EN = 0)
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3 V and TA= 25°C.
(3) The LMH0387 equalizer can be optimized for different launch amplitudes through the SPI.
(4) The differential output voltage and offset voltage are adjustable through the SPI.
(5) The equalizer automatically shifts equalization stages at cable lengths less than or equal to 120 m (Belden 1694A) to reduce power
consumption. This power saving is also achieved by setting Extended 3G Reach Mode = 1 through the SPI. (Note: Forcing the Extended
3G Reach Mode in this way increases the cable reach for 3G data rates but also limits the achievable cable lengths at HD and SD data
rates).
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6.7 Output Mode (Cable Driver) DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC –
VCMOUT BNC_IO Output Common Mode Voltage V
VOUT
VOUT BNC_IO Output Voltage Swing RREF = 715 Ω±1% 720 800 880 mVP-P
0.9 + VCC –
VCMIN SDI, SDI Input Common Mode Voltage V
VID/2 VID/2
VID SDI, SDI Input Voltage Swing Differential 100 2200 mVP-P
SD/HD = 0, equalizer in sleep mode 57 71 mA
SD/HD = 1, equalizer in sleep mode 50 mA
Power save mode (TX_EN = 0,
ICC Supply Current 11 mA
equalizer in sleep mode)
Loopback mode (Tx and Rx both 117 mA
enabled), SD/HD = 0
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3 V and TA= 25°C.
6.8 Input Mode (Equalizer) AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRMIN Minimum Input Data Rate 125 Mbps
DRMAX Maximum Input Data Rate 2970 Mbps
2.97 Gbps, Belden 1694A, 0.3 UI
0-100 meters(2)(3)
2.97 Gbps, Belden 1694A, 0.35 UI
100-120 meters(3)
1.485 Gbps, Belden 1694A, 0.25 UI
0-170 meters(2)(3)
Equalizer Jitter for Various Cable
tjit Lengths (SDO, SDO) 1.485 Gbps, Belden 1694A, 0.3 UI
170-200 meters(3)
270 Mbps, Belden 1694A, 0.2 UI
0-350 meters(2)(3)
270 Mbps, Belden 1694A, 0.2 UI
350-400 meters(3)
20% – 80%, 100 Ωload,
tr, tfOutput Rise Time, Fall Time 80 130 ps
Figure 1(4)
Δtr,ΔtfMismatch in Rise/Fall Time(4) 2 15 ps
.
tOS Output Overshoot(4) 1% 5%
5 MHz - 1.5 GHz(4)(5) 15 dB
RLIN BNC_IO Return Loss 1.5 GHz - 3 GHz(4)(5) 10 dB
(1) Typical values are stated for VCC = +3.3 V and TA= 25°C.
(2) Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in
accordance with ST RP 184, ST RP 192, and the applicable serial data transmission standard: ST 424, ST 292, or ST 259.
(3) LMH0387 equalizer launch amplitude fine tuning set to nominal through the SPI by writing 30h (“00110000 binary”) to SPI register 02h.
(4) Specification is ensured by characterization.
(5) Return loss is dependent on board design. The LMH0387 exceeds this specification on the SD387EVK evaluation board.
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6.9 Output Mode (Cable Driver) AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRMAX Maximum Input Data Rate 2970 Mbps
2.97 Gbps(2) 20 psP-P
tjit Additive Jitter 1.485 Gbps(2) 18 psP-P
270 Mbps(2) 15 psP-P
SD/HD = 0, 20% – 80% 65 130 ps
tr, tfOutput Rise Time, Fall Time SD/HD = 1, 20% – 80% 400 800 ps
SD/HD = 0 30 ps
Δtr,ΔtfMismatch in Rise/Fall Time SD/HD = 1 50 ps
SD/HD = 0(3) 30 ps
Duty Cycle Distortion SD/HD = 1(3) 100 ps
SD/HD = 0(3) 10%
tOS Output Overshoot SD/HD = 1(3) 8%
5 MHz - 1.5 GHz(3)(4) 15 dB
RLOUT BNC_IO Output Return Loss 1.5 GHz - 3 GHz(3)(4) 10 dB
(1) Typical values are stated for VCC = +3.3 V and TA= 25°C.
(2) Cable driver additive jitter is measured with the input AC coupled.
(3) Specification is ensured by characterization.
(4) Return loss is dependent on board design. The LMH0387 exceeds this specification on the SD387EVK evaluation board.
6.10 Input Mode (Equalizer) SPI Interface AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCK SCK Frequency 20 MHz
tPH SCK Pulse Width High 40% SCK period
Figure 2,Figure 3
tPL SCK Pulse Width Low 40% SCK period
tSU MOSI Setup Time 4 ns
Figure 2,Figure 3
tHMOSI Hold Time 4 ns
tSSSU SS Setup Time 4 ns
tSSH SS Hold Time Figure 2,Figure 3 4 ns
tSSOF SS Off Time 10 ns
tODZ MISO Driven-to-Tristate Time 15 ns
tOZD MISO Tristate-to-Driven Time Figure 3 15 ns
tOD MISO Output Delay Time 15 ns
(1) Typical values are stated for VCC = +3.3 V and TA= 25°C.
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A6 A5 A4 A3 A2 A1 A01
tOZD
tSSH tSSOF
tODZ
D7 D6 D5 D4 D3 D2 D1 D0
SS
(host)
SCK
(host)
MOSI
(host)
MISO
(device)
Hi-Z
Hi-Z Hi-Z
tSSSU
tSU tH
tPH tPL
tOD
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D00
tSSSU
tSU tH
tPH tPL tSSH tSSOF
SS
(host)
SCK
(host)
MOSI
(host)
MISO
(device) Hi-Z
LMH0387
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Figure 1. LVDS Output Voltage, Offset, and Timing Parameters
Figure 2. SPI Write Operation
Figure 3. SPI Read Operation
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6.11 Typical Characteristics
120m 0f B1694A at 2.97 Gbps, PRBS10 H: 100 ps / div, V: 50 mV
/ div (SDO Output Shown) H: 62.5 ps / div, V: 100 mV / div (BNC_IO Output Shown)
Figure 4. Differential Serial Data Output After Equalizing
Figure 5. Cable Driver Output at 2.97 Gbps, PRBS10
Figure 6. BNC_IO Return Loss
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Cable
Driver
Cable
Equalizer
TERMTX
RREF
TX_EN
SD/HD
SDI
SDI
SDO
SDO
BNC_IO
TERMTX
AEC+
AEC–
SPI_EN
CD
CDTHRESH
SS
MISO
MOSI
SCK
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7 Detailed Description
7.1 Overview
The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver provides a single
chip interface to a BNC. The same I/O pin is used both for the input and the output functions of the device,
allowing the system designer to use a BNC attached to the device as either an input or an output. The LMH0387
operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST
259, and DVB/ASI standards. The LMH0387 includes passive components for the return loss network –
simplifying board design and development time.
7.2 Functional Block Diagram
7.3 Feature Description
The LMH0387 can be configured either in the input mode as an equalizer to receive data over coaxial cable or in
the output mode as a cable driver to transmit data over coaxial cable. The LMH0387 requires register
programming to operate either in Input Mode (Equalizer) or Output Mode (Cable Driver).
7.3.1 Input Mode (Equalizer) Description
SPI register access is required while operating the LMH0387 in the input mode. The equalizer launch amplitude
fine tuning must be set to nominal through the SPI for correct equalizer operation. To do this, write 30h
(“00110000 binary”) to SPI register 02h. The SPI registers provide access to many other useful LMH0387
features while in the input mode. Refer to the Input Mode (Equalizer) SPI Register Access section for details.
7.3.1.1 Input Interfacing
The LMH0387 accepts a single-ended input at the BNC_IO pin. The input must be AC coupled as shown in
Figure 9 . The TERMRX input must be properly terminated with a 1-µF capacitor followed by a 220-Ωresistor to
ground.
The LMH0387 BNC_IO input can be optimized for different launch amplitudes through the SPI (see Launch
Amplitude Optimization (Register 02h) in the Input Mode (Equalizer) SPI Register Access section).
The LMH0387 correctly handles equalizer pathological signals for standard and high definition serial digital video,
as described in ST RP 178 and RP 198, respectively.
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Feature Description (continued)
7.3.1.2 Output Interfacing
The LMH0387 equalizer outputs, SDO and SDO, are internally terminated 100-ΩLVDS outputs. These outputs
can be DC coupled to most common differential receivers.
The default output common mode voltage (VOS) is 1.25 V. The output common mode voltage may be adjusted
through the SPI in 200 mV increments, from 1.05 V to 1.85 V (see Output Driver Adjustments (Register 01h) in
the Input Mode (Equalizer) SPI Register Access section). This adjustable output common mode voltage offers
flexibility for interfacing to many types of receivers.
The default differential output swing (VSSP-P) is 700 mVP-P. The differential output swing may be adjusted through
the SPI in 100 mV increments from 400 mVP-P to 800 mVP-P (see Output Driver Adjustments (Register 01h) in the
Input Mode (Equalizer) SPI Register Access section).
The LMH0387 equalizer output should be DC coupled to the input of the receiving device as long as the common
mode ranges of both devices are compatible. 100-Ωdifferential transmission lines should be used to connect
between the LMH0387 outputs and the input of the receiving device where possible.
The LMH0387 allows flexibility when interfacing to low voltage crosspoint switches (that is, 1.8 V) and other
devices with limited input ranges. The LMH0387 equalizer outputs can be DC coupled to these devices in most
cases.
The LMH0387 may be AC coupled to the receiving device when necessary. For example, the LMH0387
equalizer outputs are not strictly compatible with 3.3 V CML and thus should not be connected through 50-Ω
resistors to 3.3 V. If the input common mode range of the receiving device is not compatible with the output
common mode range of the LMH0387, then AC coupling is required. Following the AC coupling capacitors, the
signal may have to be biased at the input of the receiving device.
7.3.1.3 Carrier Detect (CD)
Carrier detect CD indicates if a valid signal is present at the LMH0387 BNC_IO pin. If CDTHRESH is used, the
carrier detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the
LMH0387 BNC_IO pin. CD is low when a valid input signal is detected.
7.3.1.4 Carrier Detect Threshold (CDTHRESH)
The CDTHRESH pin sets the threshold for the carrier detect. The carrier detect threshold is set by applying a
voltage inversely proportional to the length of cable to equalize before loss of carrier is triggered. The applied
voltage must be greater than the CDTHRESH floating voltage (typically 1.3 V) to change the CD threshold. As the
applied CDTHRESH voltage is increased, the amount of cable that will be equalized before carrier detect is
deasserted is decreased. CDTHRESH may be left unconnected or connected to ground for normal CD operation.
Figure 7 shows the minimum CDTHRESH input voltage required to force carrier detect to inactive vs. Belden 1694A
cable length. The results shown are valid for Belden 1694A cable lengths of 0 m to 120 m at 2.97 Gbps, 0 m
to200 m at 1.485 Gbps, and 0 m to 400 m at 270 Mbps.
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0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
2.0
2.2
2.4
2.6
2.8
3.0
3.2
CDTHRESH (V)
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Feature Description (continued)
Figure 7. CDTHRESH vs Belden 1694A Cable Length
7.3.1.5 Auto Sleep
The LMH0387 equalizer is set for auto sleep operation by default. The equalizer portion of the LMH0387 powers
down when no input signal is detected on the BNC_IO pin. The equalizer powers on again once an input signal
is detected. The auto sleep functionality can be changed to force sleep or turned off completely through the SPI
registers.
In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs
and should not have any impact on the system timing requirements. The equalizer will wake up automatically
once an input signal is detected, and the delay between signal detection and full functionality of the equalizer is
negligible. The overall system will be limited only by the settling time constant of the equalizer adaptation loop.
7.3.2 Output Mode (Cable Driver) Description
7.3.2.1 Input Interfacing
The LMH0387 cable driver accepts differential input signals which can be DC or AC coupled.
7.3.2.2 Output Interfacing
The LMH0387 cable driver uses 75-Ωinternally terminated current mode outputs. The output level is 800 mVP-P
with an RREF resistor of 715 Ω. The RREF resistor is connected between the RREF pin and VCC, and should be
placed as close as possible to the RREF pin.
The output should be AC coupled as shown in the Figure 9. The TERMTX output must be properly terminated
with a 4.7-µF capacitor followed by a 75-Ωresistor to ground as shown.
7.3.2.3 Output Slew Rate Control
The LMH0387 cable driver output rise and fall times are selectable for either ST 259 or ST 424 / 292 compliance
through the SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise
and fall times, or ST 424 and ST 292 compliance, SD/HD is set low. SD/HD has an internal pulldown.
7.3.2.4 Output Enable
The LMH0387 cable driver can be enabled or disabled with the TX_EN pin. When set low, the cable driver is
powered off. TX_EN has an internal pullup to enable the cable driver by default. When using the LMH0387 in the
input mode (as an equalizer), the cable driver must be disabled by setting the TX_EN pin low.
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7.4 Device Functional Modes
SPI register access is required while operating the LMH0387 in the input mode. The equalizer launch amplitude
fine tuning must be set to nominal through the SPI for correct equalizer operation. To do this, write 30h
(“00110000 binary”) to SPI register 02h. The SPI registers provide access to many other useful LMH0387
features while in the input mode.
To configure the LMH0387 in the output mode, the cable driver must be enabled. The equalizer may either be
disabled for power savings or enabled to provide a loopback path for the data being transmitted. For the normal
output mode (equalizer disabled for power savings) follow these steps:
1. Disable the equalizer by forcing it to sleep through the SPI. To do this, write “10” (force sleep) to bits [4:3] of
SPI register 00h.
2. Enable the cable driver by pulling the TX_EN pin high.
7.5 Programming
The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver is used at the input
or output port of digital video equipment. It is designed to allow the sharing of a single BNC connector for either
input or output. The LMH0387 must be configured in either the output mode as a cable driver, or the input mode
as an equalizer.
7.5.1 Output Mode (Cable Driver)
To configure the LMH0387 in the output mode, the cable driver must be enabled. The equalizer may either be
disabled for power savings or enabled to provide a loopback path for the data being transmitted. For the normal
output mode (equalizer disabled for power savings) follow these steps:
1. Disable the equalizer by forcing it to sleep through the SPI. To do this, write “10” (force sleep) to bits [4:3] of
SPI register 00h.
2. Enable the cable driver by pulling the TX_EN pin high.
To configure the LMH0387 for the output mode with the loopback path, the equalizer can be enabled in output
mode by writing either “01” (auto sleep – default) or “00” (never sleep) to bits [4:3] of SPI register 00h. In this
case, the LMH0387 input/output mode may be configured simply by toggling the TX_EN pin because the
equalizer remains active in either mode (TX_EN set low for input mode and high for output mode).
7.5.2 Input Mode (Equalizer)
To configure the LMH0387 in the input mode, the equalizer must be enabled and the cable driver must be
disabled as described in the following steps:
1. Disable the cable driver by pulling the TX_EN pin low.
2. Enable the equalizer by setting the sleep mode through the SPI to either auto sleep or disabled (never
sleep). To do this, write either “01” (auto sleep – default) or “00” (never sleep) to bits [4:3] of SPI register
00h.
3. Set the equalizer launch amplitude fine tuning to the nominal setting through the SPI. To do this, write 30h
(“00110000” binary) to SPI register 02h.
7.5.3 Input Mode (Equalizer) SPI Register Access
SPI register access is required for correct input mode (equalizer) operation. The SPI registers provide access to
all of the equalizer features along with a cable length indicator, programmable output common mode voltage and
swing, and launch amplitude optimization. There are four supported 8-bit registers in the device (see SPI
Registers).
Note: The SPI_EN pin must always be pulled high while using the LMH0387 in the input mode (equalizer), and
may optionally be pulled high while using the LMH0387 in the output mode (cable driver) as well.
7.5.3.1 SPI Write
The SPI write is shown in Figure 2. The MOSI payload consists of a “0” (write command), seven address bits,
and eight data bits. The SS signal is driven low, and the 16 bits are sent to the LMH0387's MOSI input. Data is
latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI
write, SS must return high.
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Programming (continued)
7.5.3.2 SPI Read
The SPI read is shown in Figure 3. The MOSI payload consists of a “1” (read command) and seven address bits.
The SS signal is driven low, and the eight bits are sent to the LMH0387's MOSI input. The addressed location is
accessed immediately after the rising edge of the 8th clock and the eight data bits are shifted out on MISO
starting with the falling edge of the 8th clock. MOSI must be tri-stated immediately after the rising edge of the 8th
clock. After the SPI read, SS must return high.
7.5.3.3 Output Driver Adjustments (Register 01h)
The equalizer output driver swing (amplitude) and offset voltage (common mode voltage) are adjustable through
SPI register 01h.
7.5.3.3.1 Output Swing
The output swing is adjustable through bits [7:5] of SPI register 01h. The default value for these register bits is
“011” for a peak-to-peak differential output voltage of 700 mVP-P. The output swing can be adjusted in 100 mV
increments from 400 mVP-P to 800 mVP-P.
7.5.3.3.2 Offset Voltage
The offset voltage is adjustable through bits [4:2] of SPI register 01h. The default value for these register bits is
“001” for an output offset of 1.25 V. The output common mode voltage may be adjusted in 200 mV increments,
from 1.05 V to 1.85 V. It can also be set to “101” for the maximum offset voltage. At this maximum offset voltage
setting, the outputs are referenced to the positive supply and the offset voltage is around 2.1 V.
7.5.3.4 Launch Amplitude Optimization (Register 02h)
The LMH0387 can compensate for attenuation of the input signal before the equalizer. This compensation is
useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and
is controlled by SPI register 02h.
NOTE
For correct equalizer operation with the default SMPTE 800 mVP-P launch amplitude and
no external attenuation, the equalizer launch amplitude fine tuning must be set to the
“nominal” setting through the SPI. To do this, write 30h (“00110000” binary) to SPI register
02h.
7.5.3.4.1 Coarse Control
Bit 7 of SPI register 02h is used for coarse control of the launch amplitude setting. At the default setting of “0”,
the equalizer operates normally and expects a launch amplitude of 800 mVP-P. Bit 7 may be set to “1” to optimize
the equalizer for input signals with 6 dB of attenuation (400 mVP-P).
7.5.3.4.2 Fine Control
Once the coarse control is set, the equalizer input compensation may be further fine tuned by bits [6:3] of SPI
register 02h. These bits may be used to tweak the input gain stage -2% to 60% around the coarse control
setting. For typical equalizer operation, bits [6:3] of SPI register 02h should be changed from the default setting
of “0000” to the nominal setting of “0110”.
7.5.3.5 Cable Length Indicator (CLI (Register 03h)
The Cable Length Indicator (CLI) provides an indication of the length of cable attached to the equalizer input. CLI
is accessible through bits [7:3] of SPI register 03h. The 5-bit CLI ranges in decimal value from 0 to 25 (“00000” to
“11001” binary) and increases as the cable length is increased. Figure 8 shows typical CLI values vs. Belden
1694A cable length. CLI is valid for Belden 1694A cable lengths of 0 m to 120 m at 2.97 Gbps, 0 m to 200 m at
1.485 Gbps, and 0 m to 400 m at 270 Mbps.
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0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
0
5
10
15
20
25
30
CLI (decimal value)
LMH0387
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Programming (continued)
Figure 8. CLI vs. Belden 1694A Cable Length
7.5.4 Input Mode (Equalizer) SPI Register Access
7.5.4.1 General Control (Register 00h)
SPI Register 00h, General Control, provides access to many basic features of the equalizer, including the carrier
detect status and the mute, sleep mode, and extended 3G reach mode controls.
7.5.4.1.1 Carrier Detect
This bit shows the status of the carrier detect for the BNC_IO pin.
7.5.4.1.2 Mute
The mute control can be used to manually mute or enable SDO and SDO. Setting this bit to “1” will mute the
equalizer outputs by forcing them to logic zero. Setting the mute bit to “0” will force the equalizer outputs to be
active.
7.5.4.1.3 Sleep Mode
The sleep mode is used to automatically or selectively power down the equalizer for power savings when it is not
needed. The auto sleep mode allows the equalizer to power down when no input signal is detected, and is
activated by default or by writing “01” to bits [4:3] of SPI register 00h. If the auto sleep mode is active, the
equalizer goes into a deep power save mode when no input signal is detected on the BNC_IO pin. The device
powers on again once an input signal is detected. The sleep functionality can be turned off completely (equalizer
will never sleep) by writing “00” to bits [4:3] of SPI register 00h. Additionally, the equalizer can be forced to power
down regardless of whether there is an input signal or not by writing “10” to bits [4:3] of SPI register 00h. The
sleep mode has precedence over the mute mode.
7.5.4.1.4 Extended 3G Reach Mode
The LMH0387 equalizer provides a mode to extend the 3G cable reach in systems that have margin in the jitter
budget. This allows for additional cable reach at 2.97 Gbps at the expense of slightly higher output jitter. The
extended 3G reach mode provides 10m of additional Belden 1694A cable reach, with an increase of output jitter
at this longer cable length of 0.05 to 0.1 UI. (Note: In Extended 3G Reach Mode, the maximum equalizable cable
lengths for HD and SD data rates will be limited to less than what can be achieved in normal mode).
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7.6 Register Maps
7.6.1 SPI Registers
Table 1. SPI Register Descriptions
ADDRESS R/W NAME BITS FIELD DEFAULT DESCRIPTION
Read only.
0: No carrier detected on
7 Carrier Detect BNC_IO pin.
1: Carrier detected on BNC_IO
pin.
0 0: Normal operation.
6 Mute 1: Equalizer outputs muted.
0 Reserved as 0. Always write 0
5 Reserved to this bit.
01 Equalizer sleep mode control.
Sleep has precedence over
Mute.
00: Never sleep. Disable sleep
mode (force equalizer to stay
enabled).
01: Auto sleep. Sleep mode
00h R/W General Control 4:3 Sleep Mode active when no input signal
detected.
10: Force sleep. Force
equalizer into sleep mode
(powered down) regardless of
whether there is an input signal
or not.
11: Reserved.
0 Extended 3G reach mode to
extend the equalizable cable
length for 2.97 Gbps
2 Extended 3G Reach Mode applications.
0: Normal operation.
1: Extended 3G reach mode.
00 Reserved as 00. Always write
1:0 Reserved 00 to these bits.
011 Equalizer output driver swing
(VSSP-P).
000: VSSP-P = 400 mVP-P.
001: VSSP-P = 500 mVP-P.
7:5 Output Swing 010: VSSP-P = 600 mVP-P.
011: VSSP-P = 700 mVP-P.
100: VSSP-P = 800 mVP-P.
101, 110, 111: Reserved.
001 Equalizer output driver offset
voltage (common mode
01h R/W Output Driver voltage).
000: VOS = 1.05V.
001: VOS = 1.25V.
4:2 Offset Voltage 010: VOS = 1.45V.
011: VOS = 1.65V.
100: VOS = 1.85V.
101: VOS referenced to positive
supply.
110, 111: Reserved.
00 Reserved as 00. Always write
1:0 Reserved 00 to these bits.
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Register Maps (continued)
Table 1. SPI Register Descriptions (continued)
ADDRESS R/W NAME BITS FIELD DEFAULT DESCRIPTION
0 Coarse launch amplitude
optimization for equalizer input.
0: Normal optimization with no
external attenuation (800 mVP-P
7 Coarse Control launch amplitude).
1: Optimized for -6 dB external
attenuation (400 mVP-P launch
amplitude).
0000 Launch amplitude optimization
fine tuning for equalizer input.
0000: +20% from nominal.
0001: +16% from nominal.
0010: +12% from nominal.
0011: +9% from nominal.
0100: +6% from nominal.
02h R/W Launch Amplitude 0101: +3% from nominal.
0110: Nominal. (The default
setting must be changed to this
6:3 Fine Control nominal setting for most
applications).
0111: -2% from nominal.
1001: +24% from nominal.
1010: +29% from nominal.
1011: +34% from nominal.
1100: +40% from nominal.
1101: +46% from nominal.
1110: +53% from nominal.
1111: +60% from nominal.
1000: Reserved.
000 Reserved as 000. Always write
2:0 Reserved 000 to these bits.
Cable Length Indicator.
Provides an indication of the
7:3 CLI length of cable attached to the
03h R CLI equalizer input. CLI increases
as the cable length increases.
2:0 Reserved 000 Reserved.
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SDI
SDO
SDI
SDO
BNC_IO
SD/HD
RREF
Cable
Equalizer
Cable
Driver
4.7 PF
220:
TX_EN
TERMTX
TERMRX
MOSI
MISO
SCK
SS
AEC+
AEC-
SPI_EN
CD
CDTHRESH
1.0 PF
75:
1.0 PF
4.7 PF715:
VCC
LMH0387
100:
4.7 PF
4.7 PF
4.7 PF
4.7 PF
CD
CDTHRESH
MISO
SS
SCK
MOSI
TX_EN
SD/HD
To FPGA
Configurable
SDI In/Out
VCC
LMH0387
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0387 is a single channel SDI cable driver and equalizer that supports different application spaces. The
following sections describe the typical use cases and common implementation practices.
8.1.1 General Guidance for Applications
The LMH0387 supports SPI interface for configuring the device. Registers must be programmed (see
Programming) for proper operation of the device. Attention must be paid to the PCB layout for the high speed
signals to facilitate the SMPTE specification compliance. SMPTE specifies requirements for the Serial Digital
Interface to transport digital video over coaxial cable. SMPTE specifies the use of AC coupling capacitors for
transporting uncompressed serial data with heavy low-frequency content. This specification requires the use of a
4.7-μF AC coupling capacitor to avoid low-frequency DC wander. The 75-Ωtrace impedance is required to meet
SMPTE specified rise/fall requirements to facilitate highest eye opening for the receiving device.
8.2 Typical Application
To meet SMPTE requirements, the optimal placement of the LMH0387 is to be as close to the BNC as possible.
Figure 9 shows the application circuit for the LMH0387.
Figure 9. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Table 2 lists the key design parameters of the LMH0387.
Table 2. Design Parameters
DESIGN PARAMETER REQUIREMENTS
Required. A common type of AC coupling capacitor
Input AC coupling capacitor is 4.7-µF ±10% X7R ceramic capacitor (0402 or
0201 size).
Trace or via under the device No trace or via under the device.
Keep this distance as short as possible to minimize
Distance from device to BNC the parasitic.
Design single-ended trace impedance with 75 Ω±
BNC_IO, TERMTX, TERMRX trace impedance 5%.
SDI, SDI and SDO, SDO differential trace Design differential trace impedance with 100 Ω± 5%.
impedance To minimize power supply noise, use 0.1-µF shunt
DC power supply coupling capacitors across 10-µF capacitors as close to the device as
possible.
8.2.2 Detailed Design Procedure
To begin the design process, determine the followings:
• Maximum power consumption for PCB regulator selection: Use maximum current consumption in the data
sheet to compute the maximum power consumption.
• Closely compare schematic against typical connection diagram in the data sheet.
• With layout guideline in mind (see Layout Guidelines ) plan out the PCB layout and component placement to
minimize parasitic.
• Consult the BNC vendor for optimum BNC landing pattern.
8.2.3 Application Curve
Figure 10. Differential Serial Data Output After Equalizing 200m of B1694A at 1.485 Gbps, PRBS10
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
• The power supply should be designed to provide the recommended operating conditions in terms of DC
voltage and maximum current consumption.
• The maximum current draw for the LMH0387 is provided in the data sheet. This number can be used to
calculate the maximum current the supply must provide.
• The LMH0387 does not require any special power supply filtering, provided the recommended operating
conditions are met. Use 0.1-µF capacitors as close to the device VCCRX and VCCTX pins as possible.
10 Layout
10.1 Layout Guidelines
For information on layout and soldering of the laminate TLGA package, refer to the following application note:
AN-1125 (SNAA002), Laminate CSP/FBGA.
NOTE
For a CSP package, it is a general requirement not to have any metal (traces or vias) on
the top layer in the area directly underneath the device, other than the footprint. This is
intended to provide a flat planar surface for the package.
The ST 424, 292, and 259 standards have stringent requirements for the input and output return loss of receivers
and transmitters, which essentially specify how closely they must resemble a 75-Ωnetwork. Any non-idealities in
the network between the BNC and the LMH0387 will degrade the return loss. Take care to minimize impedance
discontinuities both for the BNC footprint and for the trace between the BNC and the LMH0387 to ensure that the
characteristic impedance is 75 Ω. Best return loss performance is achieved with the LMH0387 placed closely to
the BNC to minimize the trace length between the BNC and the LMH0387's BNC_IO pin. Consider the following
PCB recommendations:
• Place the LMH0387 in close proximity to the BNC.
• Use surface mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the LMH0387.
• Select a board stack up that supports both 75-Ωsingle-ended traces and 100-Ωloosely-coupled differential
traces.
• Maintain symmetry on the complementary signals.
• Route 100-Ωtraces uniformly (keep trace widths and trace spacing uniform along the trace).
• Avoid sharp bends in the signal path; use 45° or radial bends.
• Place bypass capacitors close to each power pin, and use the shortest path to connect device power and
ground pins to the respective power or ground planes.
• Remove ground plane under input/output components to minimize parasitic capacitance.
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No metal (traces or vias) in this area
GND and V relief under BNC and component pad
CC
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10.2 Layout Example
Figure 11. Ground and VCC Relief Under Controlled Impedance Component Pads
Figure 12. Top Etch Routing Restriction
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•AN-1125 Laminate CSP/FBGA,SNAA002
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH0387SL/NOPB ACTIVE TLGA NPD 48 1000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 LMH0387SL
LMH0387SLE/NOPB ACTIVE TLGA NPD 48 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 LMH0387SL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH0387SL/NOPB TLGA NPD 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
LMH0387SLE/NOPB TLGA NPD 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH0387SL/NOPB TLGA NPD 48 1000 367.0 367.0 38.0
LMH0387SLE/NOPB TLGA NPD 48 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
MECHANICAL DATA
NPD0048A
www.ti.com
SLD48A (Rev B)
IMPORTANT NOTICE AND DISCLAIMER
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