PLL
Three
Audio Buses
I C/SPI Bus
2
DirectPath™
Headphone
ADC DAC
ADC DAC
Two
miniDSP
Engines
Mixer
Outputs
Microphone
(Analog or Digital)
8 SE /
4 Diff
Inputs
Level
Control
Mixer
PGA
SE Line-Ins
ASRC
CP
1.4 W
Stereo
Speaker
(Class-D)
Receiver
SAR
ADC
TLV320AIC3262
www.ti.com
SLAS679 –DECEMBER 2011
Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Stereo
Class-D Speaker Amplifier
Check for Samples: TLV320AIC3262
1FEATURES • Three Independent Digital Audio Serial
Interfaces
2• Stereo Audio DAC with 101dB SNR – TDM and mono PCM support on all Audio
• 2.7mW Stereo 48kHz DAC Playback Serial Interfaces
• Stereo Audio ADC with 93dB SNR – 8-channel Input and Output on Audio Serial
• 5.6mW Stereo 48kHz ADC Record Interface 1
• 8-192kHz Playback and Record • Programmable PLL, plus Low-Frequency
• 30mW DirectPathTM Headphone Driver Clocking
Eliminates Large Output DC-Blocking • Programmable 12-Bit SAR ADC
Capacitors • SPI and I2C Control Interfaces
• 128mW Differential Receiver Output Driver • 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP
• Stereo Class-D Speaker Drivers (YZF) Package
– 1.7 W (8Ω, 5.5V, 10% THDN) AIC3262
– 1.4 W (8Ω, 5.5V, 1% THDN) APPLICATIONS
• Stereo Line Outputs • Mobile Handsets
• PowerTune™ - Adjusts Power vs. SNR • Tablets/eBooks
• Extensive Signal Processing Options • Portable Navigation Devices (PND)
• Eight Single-Ended or 4 Fully-Differential • Portable Media Player (PMP)
Analog Inputs • Portable Gaming Systems
• Stereo Digital and Analog Microphone Inputs • Portable Computing
• Low Power Analog Bypass Mode • Acoustic Echo Cancellation (AEC)
• Asynchronous Sample Rate Conversion • Active Noise Cancellation (ANC)
• Fully-programmable Enhanced miniDSP with • Noise Suppression (NS)
PurePathTM Studio Support • Speaker Protection
– Extensive Algorithm Support for Voice and • Advanced DSP algorithms
Audio Applications
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerTune is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SPI_SELECT
IN1R/AUX2
IN2R
IN3R
IN3L
IN4L
IN2L
IN1L/AUX1
DRCAGC
DRC
t
PR
t
PL
AGC
Audio
Interface
Ref
MICBIAS
VREF_AUDIO
LOL
LOR
–36...0dB
–36...0dB
CPVDD_18
CPVSS
CPFCP
CPFCM
VNEG
MICBIAS_EXT
PLL
GPO1
GPI1
DIN3
GPIO1
GPIO2
DOUT3
DOUT2
WCLK2
BCLK2
WCLK1
BCLK1
VBAT
VREF_SAR
+
+
–
–
–12, –6, 0dB
–12, –6, 0dB
WCLK3
BCLK3
MICDET Detection
Mic
Bias Charge
Pump
Primary
Audio Interface
Secondary
Audio IF
Interrupt
Ctrl
Digital
Mic.
SPI / I C
Control Block
2
Low Freq
Clocking
B0395-04
-12, -6, 0dB
)
ADC
Signal
Proc.
DAC
Signal
Proc.
DAC
Signal
Proc.
ADC
Signal
Proc.
miniDSP
ASRC
Dig Mixer
Volume
miniDSP
Dig Mixer
Volume
Right
ADC
Left
ADC
SAR
ADC
Right
DAC
Left
DAC
0>47.5dB
(0.5-dB Steps)
0>47.5dB
(0.5-dB Steps)
)
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
–6 dB
GPI2
MCLK1
MCLK2
DOUT1
Tertiary
Audio IF
IN4R
–6 dB
Supplies
IOVDD
RECVDD_33
AVDD1_18
AVDD2_18
SRVDD
SPK_V
AVDD3_33
AVDD_18
AVDD4_18
DVDD
SRVSS
SLVDD
HVDD_18
SLVSS
RECVSS
IOVSS
AVSS1
AVSS2
AVSS3
AVSS
DVSS
AVSS4
LOL
LOR
-78...0dB
-78...0dB
MAL
MAR
-6dB
-6dB
LOL
-78...0dB
-78...0dB
-78...0dB
-78...0dB
RECP
RECM
-6...29dB
(1-dB Steps
-6...14dB
(1-dB Steps
HPL
HPR
-78...0dB
-78...0dB
HPVSS_SENSE
6...30dB
SPKLM
SPKLP
(6-dB Steps)
6...30dB
SPKRM
SPKRP
(6-dB Steps)
)
-6...14dB
(1-dB Steps
-12, -6, 0dB
TEMP
VBAT
IN1R/AUX2
IN1L/AUX1
TEMP
SENSOR
GPI3
GPI4
SCL
SDA
RESET
Vol. Ctrl.
LOR
Pin Muxing / Clock Routing
IN1L
IN1R
SPR_IN
SPR_IN
Vol. Ctrl.
Int.
Ref.
in Adj.Ga
in Adj.
Ga
DIN1
DIN2
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
DESCRIPTION
The TLV320AIC3262 (also referred to as the AIC3262) is a flexible, highly-integrated, low-power, low-voltage
stereo audio codec. The AIC3262 features digital microphone inputs and programmable outputs, PowerTune
capabilities, enhanced fully-programmable miniDSP, predefined and parameterizable signal processing blocks,
integrated PLL, and flexible audio interfaces. Extensive register-based control of power, input and output channel
configuration, gains, effects, pin-multiplexing and clocks are included, allowing the device to be precisely targeted
to its application.
Figure 1. Simplified Block Diagram
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SLAS679 –DECEMBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3262 features two fully-programmable miniDSP cores that support application-specific algorithms
in the record and/or the playback path of the device. The miniDSP cores are fully software programmable.
Targeted miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP
filtering are loaded into the device after power-up.
Combined with the advanced PowerTune technology, the device can execute operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3262 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations which cover single-ended and differential setups, as well as
floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise
that may be introduced by mechanical coupling, e.g. optical zooming in a digital camera. The record path can
also be configured as a stereo digital microphone Pulse Density Modulation (PDM) interface typically used at
64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D
speaker outputs; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The
playback path contains two high-power DirectPathTM headphone output drivers which eliminate the need for ac
coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone
drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In
addition, playback audio can be routed to integrated stereo Class-D speaker drivers or a differential receiver
amplifier.
The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-
off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used
in a mobile environment. When used in a docked environment power consumption typically is less of a concern
while lowest possible noise is important. With PowerTune the TLV320AIC3262 can address both cases.
The required internal clock of the TLV320AIC3262 can be derived from multiple sources, including the MCLK1
pin, the MCLK2 pin, the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal
PLL, where the input to the PLL again can be derived from similar pins. Although using the internal fractional PLL
ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is
highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. To enable even
lower clock frequencies, an integrated low-frequency clock multiplier can also be used as an input to the PLL.
The TLV320AIC3262 has a 12-bit SAR ADC converter that supports system voltage measurements. These
system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or
VBAT pins), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
The TLV320AIC3262 also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF,
LJF, and mono PCM formats. This enables three simultaneous digital playback and record paths to three
independent digital audio buses or chips. Additionally, the general purpose interrupt pins can be used to connect
to a fourth digital audio bus, allowing the end system to easily switch in this fourth audio bus to one of the three
Digital Audio Serial Interfaces.
The device is available in the 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP (YZF) Package.
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLV320AIC3262
J
H
G
F
E
D
C
B
ACPFCM VNEG
12
3
4
5
6
7
89
P0044-07
CPVDD_18
AVSS4SPKLP
SLVSS CPFCP CPVSS HPL HVDD_18 RECM RECP MICDET
IN4L
AVDD1_18
MICBIAS
_EXT
MICBIAS
AVDD2_18
LOL
AVDD4_18
SPKLMSPKRM
VREF
_AUDIO
VREF_SAR
IN1L/AUX1IN1R/AUX2IN4R
HPVSS
_SENSE
LOR
SRVSSSRVDD
IN3RIN3L
AVSSAVSS1
AVSS3
AVSS2DVSS
SPK_V
SPKRP
IN2LIN2R
AVDD_18
DVSS
GPI3
GPI2GPI4
IOVSS
VBAT
MCLK1BCLK2
DIN2
WCLK2
WCLK3
DIN3
SPI_SELECT
RESET
MCLK2
BCLK1
DOUT1IOVDD
SCLSDA
GPO1
BCLK3
GPIO2IOVDD
DIN1
WCLK1DVDD
IOVSS
GPI1
DOUT2
DOUT3
GPIO1
DVDD
HPR RECVDD_33 RECVSS AVDD3_33
SLVDD
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
Package and Signal Descriptions
Packaging/Ordering Information
OPERATING
PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT PACKAGE TEMPERATURE
DESIGNATOR NUMBER QUANTITY
RANGE
TLV320AIC3262IYZFT Tape and Reel, 250
TLV320AIC3262 WCSP-81 YZF –40°C to 85°C TLV320AIC3262IYZFR Tape and Reel, 3000
Pin Assignments
space
space
Figure 2. WCSP-81 (YZF) Package Ball Assignments, Top View
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SLAS679 –DECEMBER 2011
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
A1 AVDD3_33 P 3.3V Power Supply for Micbias
A2 RECVSS P Receiver Driver Ground
A3 RECVDD_33 P 3.3V Power Supply for Receiver Driver
A4 HPR O Right Headphone Output
A5 VNEG I/O Charge Pump Negative Supply
A6 CPFCM I/O Charge Pump Flying Capacitor M terminal
A7 CPVDD_18 P Power Supply Input for Charge Pump
A8 AVSS4 P Analog Ground for Class-D
A9 SPKLP O Left Channel P side Class-D Output
B1 MICDET I/O Headset Detection Pin
B2 RECP O Receiver Driver P side Output
B3 RECM O Receiver Driver M side Output
B4 HVDD_18 P Headphone Amp Power Supply
B5 HPL O Left Headphone Output
B6 CPVSS P Charge Pump Ground
B7 CPFCP I/O Charge Pump Flying Capacitor P Terminal
B8 SLVDD P Left Channel Class-D Output Stage Power Supply
B9 SLVSS P Left Channel Class-D Output Stage Ground
C1 IN4L I Analog Input 4 Left
C2 AVDD1_18 P 1.8V Analog Power Supply
C3 MICBIAS_EXT O Output Bias Voltage for Headset Microphone.
C4 MICBIAS O Output Bias Voltage for Microphone to be used for on-board Microphones
C5 AVDD2_18 P 1.8V Analog Power Supply
C6 LOL O Left Line Output
C7 AVDD4_18 P 1.8V Analog Power Supply for Class-D
C8 SPKLM O Left Channel M side Class-D Output
C9 SPKRM O Right Channel M side Class-D Output
D1 VREF_AUDIO O Analog Reference Filter Output
SAR ADC Voltage Reference Input or Internal SAR ADC Voltage Reference Bypass
D2 VREF_SAR I/O Capacitor Pin
Analog Input 1 Left, Auxiliary 1 Input to SAR ADC
D3 IN1L/AUX1 I (Special Function: Left Channel High Impedance Input for Capacitive Sensor
Measurement)
Analog Input 1 Right, Auxiliary 2 Input to SAR ADC
D4 IN1R/AUX2 I (Special Function: Right Channel High Impedance Input for Capacitive Sensor
Measurement)
D5 IN4R I Analog Input 4 Right
D6 HPVSS_SENSE I Headphone Ground Sense Terminal
D7 LOR O Right Line Output
D8 SRVSS P Right Channel Class-D Output Stage Ground
D9 SRVDD P Right Channel Class-D Output Stage Power Supply
E1 IN3R I Analog Input 3 Right
E2 IN3L I Analog Input 3 Left
E3 AVSS P Analog Ground
E4 AVSS1 P Analog Ground
E5 AVSS3 P Analog Ground
E6 AVSS2 P Analog Ground
E7 DVSS P Digital Ground
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLV320AIC3262
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
E8 SPK_V P Class-D Output Stage Power Supply (Connect to SRVDD through a Resistor)
E9 SPKRP O Right Channel P side Class-D Output
F1 IN2L I Analog Input 2 Left
F2 IN2R I Analog Input 2 Right
F3 AVDD_18 P 1.8V Analog Power Supply
F4 DVSS P Digital Ground
Multi Function Digital Input 3
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
F5 GPI3 I ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 1 (I2C_ADDR0, LSB)
Multi Function Digital Input 2
Primary:General Purpose Input
Secondary:
Audio Serial Data Bus 1 Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
F6 GPI2 I Digital Microphone Data Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Multi Function Digital Input 4
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
F7 GPI4 I ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 2 (I2C_ADDR1, MSB)
F8 IOVSS P Digital I/O Buffer Ground
F9 VBAT I Battery Monitor Voltage Input
G1 MCLK1 I Master Clock Input 1
Primary:Audio Serial Data Bus 2 Bit Clock
Secondary:
Audio Serial Data Bus 1 Data Input (L3/R3)
Audio Serial Data Bus 1 Data Output (L3/R3)
General Purpose Input
G2 BCLK2 I/O General Purpose Output
General CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
General Clock Input
Low-Frequency Clock Input
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SLAS679 –DECEMBER 2011
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
Primary:Audio Serial Data Bus 2 Data Input
Secondary:
G3 DIN2 I Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L2/R2)
General Purpose Input
Low-Frequency Clock Input
Primary:Audio Serial Data Bus 2 Word Clock
Secondary:
Audio Serial Data Bus 1 Data Input (L4/R4)
Audio Serial Data Bus 1 Data Output (L4/R4)
General Purpose Input
G4 WCLK2 I/O General Purpose Output
CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Low-Frequency Clock Input
Primary:Audio Serial Data Bus 3 Word Clock
Secondary:
G5 WCLK3 I/O General Purpose Output
General Purpose Input
Audio Serial Data Bus 1 Data Out (L4/R4)
Low-Frequency Clock Input
Primary:Audio Serial Data Bus 3 Data Input
G6 DIN3 I Secondary:
Audio Serial Data Bus 1 Data Input (L3/R3)
Control Interface Select
G7 SPI_SELECT I SPI_SELECT = ‘1’: SPI Interface selected
SPI_SELECT = ‘0’: I2C Interface selected
G8 RESET I Active Low Reset
Master Clock 2
Primary:Clock Input
G9 MCLK2 I Secondary:
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L3/R3 or L4/R4)
Low-Frequency Clock Input
Primary:Audio Serial Data Bus 1 Bit Clock
H1 BCLK1 I/O Secondary:
General Clock Input
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLV320AIC3262
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SLAS679 –DECEMBER 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
Primary:Audio Serial Data Bus 1 Data Output
Secondary:
Audio Serial Data Bus 1 Data Output (L1/R1)
H2 DOUT1 O General Purpose Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
H3 IOVDD P Digital I/O Buffer Supply
I2C Interface Serial Clock (SPI_SELECT = 0)
H4 SCL I/O SPI interface mode chip-select signal (SPI_SELECT = 1)
I2C interface mode serial data input (SPI_SELECT = 0)
H5 SDA I/O SPI interface mode serial data input (SPI_SELECT = 1)
Multifunction Digital Output 1
Primary: (SPI_SELECT = 1)
Serial Data Output
Secondary: (SPI_SELECT = 0)
General Purpose Output
H6 GPO1 O CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3 or L4/R4)
Primary:Audio Serial Data Bus 3 Bit Clock
Secondary:
H7 BCLK3 I/O General Purpose Input
General Purpose Output
Low-Frequency Clock Input
Audio Serial Data Bus 1 Data Output (L3/R3)
Multi Function Digital IO 2
Outputs:General Purpose Output
ADC MOD Clock Output For Digital Microphone
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3 or L4/R4)
Audio Serial Data Bus 1 Bit Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
H8 GPIO2 I/O ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Inputs: General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
Audio Serial Data Bus 1 Bit Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
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SLAS679 –DECEMBER 2011
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
H9 IOVDD P Digital I/O Buffer Supply
Primary:Audio Serial Data Bus 1 Data Input
Secondary:
J1 DIN1 I Audio Serial Data Bus 1 Data Input (L1/R1)
General Clock Input
Digital Microphone Data Input
Primary:Audio Serial Data Bus 1 Word Clock
J2 WCLK1 I/O Secondary:
Low-Frequency Clock Input
General CLKOUT Output
J3 DVDD P 1.8V Digital Power Supply
J4 IOVSS P Digital I/O Buffer Ground
Multifunction Digital Input 1
Primary: (SPI_SELECT = 1)
SPI Serial Clock
Secondary: (SPI_SELECT = 0)
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
J5 GPI1 I General Clock Input
Low-Frequency Clock Input
General Purpose Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Primary:Audio Serial Data Bus 2 Data Output
Secondary:
General Purpose Output
J6 DOUT2 O ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2)
Primary:Audio Serial Data Bus 3 Data Output
Secondary:
J7 DOUT3 O General Purpose Output
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3)
Audio Serial Data Bus 1 Word Clock Output
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9
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SLAS679 –DECEMBER 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL NAME I/O/P DESCRIPTION
LOCATION
Multi Function Digital IO 1
Outputs:General Purpose Output
ADC MOD Clock Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L3/R3 or L4/R4)
Audio Serial Data Bus 1 Word Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
J8 GPIO1 I/O ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Inputs: General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L3/R3 or L4/R4)
Audio Serial Data Bus 1 Word Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
J9 DVDD P 1.8V Digital Power Supply
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SLAS679 –DECEMBER 2011
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 to AVSS1, AVSS2, AVSS4, AVSS respectively(2) –0.3 to 2.2 V
AVDD3_33 to AVSS3 and RECVDD_33 to RECVSS –0.3 to 3.9 V
DVDD to DVSS –0.3 to 2.2 V
IOVDD to IOVSS –0.3 to 3.9 V
HVDD_18 to AVSS –0.3 to 2.2 V
CPVDD_18 to CPVSS –0.3 to 2.2 V
SLVDD to SLVSS, SRVDD to SRVSS, SPK_V to SRVSS(3) –0.3 to 6.0 V
Digital Input voltage to ground IOVSS – 0.3 to IOVDD + V
0.3
Analog input voltage to ground AVSS – 0.3 to AVDDx_18 V
+ 0.3
VBAT –0.3 to 6 V
Operating temperature range –40 to 85 °C
Storage temperature range –55 to 125 °C
Junction temperature (TJMax) 105 °C
Power dissipation (TJMax – TA)/ θJA W
θJA Junction-to-ambient thermal resistance 39.1 °C/W
θJCtop Junction-to-case (top) thermal resistance 0.1
WCSP-81 package
(YZF) θJB Junction-to-board thermal resistance 12.0
PsiJT Junction-to-top characterization parameter 0.7
PsiJB Junction-to-board characterization parameter 11.5
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) It's recommended to keep all AVDDx_18 supplies within ± 50 mV of each other.
(3) It's recommended to keep SLVDD, SRVDD, and SPK_V supplies within ± 50 mV of each other.
Recommended Operating Conditions MIN NOM MAX UNIT
AVDD1_18, Power Supply Voltage Range Referenced to AVSS1, AVSS2, AVSS4, AVSS 1.5 1.8 1.95 V
AVDD2_18, respectively(1) It is recommended to connect each
AVDD4_18, of these supplies to a single supply rail.
AVDD_18
AVDD3_33 , Referenced to AVSS3 and RECVSS respectively 1.65(2) 3.3 3.6
RECVDD_33
IOVDD Referenced to IOVSS(1) 1.1 3.6
DVDD(3) Referenced to DVSS(1) 1.26 1.8 1.95
CPVDD_18 Power Supply Voltage Range Referenced to CPVSS (1) 1.26 1.8 1.95 V
HVDD_18 Referenced to AVSS(1) Ground-centered 1.5(2) 1.8 1.95
Configuration
Unipolar 1.65(2) 3.6
Configuration
SLVDD(1) Power Supply Voltage Range Referenced to SLVSS(1) 2.7 5.5 V
(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.1V max, for any combination of ground
signals. AVDDx_18 are within +/- 0.05 V of each other. SLVDD, SRVDD, and SPK_V are within +/- 0.05 V of each other.
(2) Minimum voltage for HVDD_18 and RECVDD_33 should be greater than or equal to AVDD2_18. Minimum voltage for AVDD3_33
should be greater than or equal to AVDD1_18 and AVDD2_18.
(3) At DVDD values lower than 1.65V, the PLL does not function. Please see table in SLAU309, Maximum TLV320AIC3262 Clock
Frequencies for details on maximum clock frequencies.
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Recommended Operating Conditions (continued) MIN NOM MAX UNIT
SRVDD(1) Power Supply Voltage Range Referenced to SRVSS(1) 2.7 5.5 V
SPK_V(1) Power Supply Voltage Range Referenced to SRVSS(1) 2.7 5.5 V
VREF_SAR External voltage reference for Referenced to AVSS 1.8 AVDDx_18 V
SAR
PLL Input Frequency(4) Clock divider uses fractional divide 10 20 MHz
(D > 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥1.65V
(Refer to table in SLAU309, Maximum
TLV320AIC3262 Clock Frequencies)
Clock divider uses integer divide 0.512 20 MHz
(D = 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥1.65V
(Refer to table in SLAU309, Maximum
TLV320AIC3262 Clock Frequencies)
MCLK Master Clock Frequency MCLK; Master Clock Frequency; IOVDD ≥1.65V 50 MHz
MCLK; Master Clock Frequency; IOVDD ≥1.1V 33
SCL SCL Clock Frequency 400 kHz
LOL, LOR Stereo line output load 0.6 10 kΩ
resistance
HPL, HPR Stereo headphone output load Single-ended configuration 14.4 16 Ω
resistance
SPKLP- Speaker output load Differential 7.2 8 Ω
SPKLM, resistance
SPKRP-
SPKRM
RECP-RECM Receiver output resistance Differential 24.4 32 Ω
CIN Charge pump input capacitor 10 µF
(CPVDD to CPVSS terminals)
COCharge pump output capacitor Type X7R 2.2 µF
(VNEG terminal)
CFCharge pump flying capacitor Type X7R 2.2 µF
(CPFCP to CPFCM terminals)
TOPR Operating Temperature Range –40 85 °C
(4) The PLL Input Frequency refers to clock frequency after PLL_CLKIN_DIV divider. Frequencies higher than 20MHz can be sent as an
input to this PLL_CLKIN_DIV and reduced in frequency prior to input to the PLL.
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SLAS679 –DECEMBER 2011
Electrical Characteristics, SAR ADC
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAR ADC Inputs
Analog Input voltage range 0 VREF_SAR V
Input Input impedance IN1L/AUX1 or IN1R/AUX2 Selected 1 ÷ (f×CSAR_IN)(1) kΩ
Input capacitance, CSAR_IN 25 pF
Input leakage current 1 µA
Battery VBAT Input voltage range 2.2 5.5 V
Input VBAT Input impedance 5 kΩ
VBAT (Battery measurement) selected
VBAT Input capacitance 25 pF
VBAT Input leakage current 1 µA
SAR ADC Conversion
Resolution Programmable: 8-bit, 10-bit, 12-bit 8 12 Bits
No missing codes 12-bit resolution 11 Bits
IN1L/ Integral linearity ±1 LSB
12-bit resolution, SAR ADC clock =
AUX1 Internal Oscillator Clock, Conversion
Offset error clock = Internal Oscillator / 4, External ±1 LSB
Reference = 1.8V(2)
Gain error 0.07 %
Noise DC voltage applied to IN1L/AUX1 = 1 V, ±1 LSB
SAR ADC clock = Internal Oscillator
Clock, Conversion clock = Internal
Oscillator / 4, External Reference =
1.8V(3)(2)
VBAT Accuracy 12-bit resolution, SAR ADC clock = 2 %
Internal Oscillator Clock, Conversion
Offset error ±2 LSB
clock = Internal Oscillator / 4, Internal
Gain error 1.5 %
Reference = 1.25V
Noise DC voltage applied to VBAT = 3.6 V, 12- ±0.5 LSB
bit resolution, SAR ADC clock = Internal
Oscillator Clock, Conversion clock =
Internal Oscillator / 4, Internal Reference
= 1.25V
Conversion Rate
Normal conversion operation 12-bit resolution, SAR ADC clock = 12 119 kHz
MHz External Clock, Conversion clock =
External Clock / 4, External Reference =
1.8V(2). With Fast SPI reading of data.
High-speed conversion 8-bit resolution,SAR ADC clock = 12 250 kHz
operation MHz External Clock, Internal Conversion
clock = External Clock (Conversion
accuracy is reduced.), External
Reference = 1.8V(2). With Fast SPI
reading of data.
Voltage Reference - VREF_SAR
Voltage range Internal VREF_SAR 1.25±0.05 V
External VREF_SAR 1.25 AVDDx_18 V
Reference Noise CM=0.9V, Cref = 1μF 32 μVRMS
Decoupling Capacitor 1 μF
(1) SAR input impedance is dependent on the sampling frequency (f designated in Hz), and the sampling capacitor is CSAR_IN = 25pF.
(2) When utilizing External SAR reference, this external reference should be restricted VEXT_SAR_REF≤AVDD_18 and AVDD2_18.
(3) Noise from external reference voltage is excluded from this measurement.
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Electrical Characteristics, ADC
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC (CM = 0.9V) (1) (2)
Input signal level (0dB) Single-ended, CM = 0.9V 0.5 VRMS
1kHz sine wave input, Single-ended Configuration
IN2R to Right ADC and IN2L to Left ADC, Rin = 20kΩ, fs= 48kHz,
Device Setup AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4
Inputs ac-shorted to ground 85 93
IN1R, IN3R, IN4R each exclusively routed in separate tests to Right 93
Signal-to-noise ratio, A-
SNR dB
ADC and ac-shorted to ground
weighted(1) (2) IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC and ac-shorted to ground
Dynamic range A- –60dB full-scale, 1-kHz input signal 93 dB
DR weighted(1) (2)
–3 dB full-scale, 1-kHz input signal –87 –70 dB
IN1R,IN3R, IN4R each exclusively routed in separate tests to Right –87
Total Harmonic ADC
THD+N Distortion plus Noise IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC
–3dB full-scale, 1-kHz input signal
1kHz sine wave input at -3dBFS, Single-ended configuration 0.1 dB
Rin = 20K fs= 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled
Gain Error AGC = OFF, Channel Gain=0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4, CM=0.9V
1kHz sine wave input at -3dBFS, Single-ended configuration 110 dB
Input Channel IN1L routed to Left ADC, IN1R routed to Right ADC, Rin = 20K
Separation AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V
1kHz sine wave input at –3dBFS on IN2L, IN2L internally not routed. 116 dB
Input Pin Crosstalk IN1L routed to Left ADC, ac-coupled to ground
1kHz sine wave input at –3dBFS on IN2R, IN2R internally not
routed.
IN1R routed to Right ADC, ac-coupled to ground
Single-ended configuration Rin = 20kΩ, AOSR=128 Channel
Gain=0dB, CM=0.9V
217Hz, 100mVpp signal on AVDD_18, AVDDx_18 59 dB
PSRR Single-ended configuration, Rin=20kΩ, Channel Gain=0dB;
CM=0.9V
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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SLAS679 –DECEMBER 2011
Electrical Characteristics, ADC (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC (CM = 0.75V)
Input signal level (0dB) Single-ended, CM=0.75V, AVDD_18, AVDDx_18 = 1.5V 0.375 VRMS
1kHz sine wave input, Single-ended Configuration
IN2R to Right ADC and IN2L to Left ADC, Rin = 20K, fs= 48kHz,
Device Setup AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4
SNR Signal-to-noise ratio, A- Inputs ac-shorted to ground 91 dB
weighted (3) (4) IN1R, IN3R, IN4R each exclusively routed in separate tests to Right 91 dB
ADC and ac-shorted to ground
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC and ac-shorted to ground
DR Dynamic range A- –60dB full-scale, 1-kHz input signal 91 dB
weighted(3) (4)
THD+N Total Harmonic –3dB full-scale, 1-kHz input signal –85 dB
Distortion plus Noise
(3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, ADC (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC (Differential Input, CM = 0.9V)
Input signal level (0dB) Differential, CM=0.9V, AVDD_18, AVDDx_18 = 1.8V 1 VRMS
1kHz sine wave input, Differential Configuration
IN1L, IN1R Routed to Right ADC, IN2L, IN2R Routed to Left ADC
Device Setup Rin = 20kΩ, fs= 48kHz, AOSR=128, MCLK = 256* fs,
PLL Disabled, AGC = OFF, Channel Gain = 0dB,
Processing Block = PRB_R1, Power Tune = PTM_R4
SNR Signal-to-noise ratio, A- Inputs ac-shorted to ground 94 dB
weighted (5) (6)
DR Dynamic range A- –60dB full-scale, 1-kHz input signal 94 dB
weighted(5) (6)
THD+N Total Harmonic –3dB full-scale, 1-kHz input signal –88 dB
Distortion plus Noise 1kHz sine wave input at -3dBFS, Differential configuration 0.1 dB
Rin = 20kΩ, fs= 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled
Gain Error AGC = OFF, Channel Gain=0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4, CM=0.9V
1kHz sine wave input at -3dBFS, Differential configuration 107 dB
IN1L/IN1R differential signal routed to Right ADC,
Input Channel
Separation IN2L/IN2R differential signal routed to Left ADC, Rin = 20kΩ
AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V
1kHz sine wave input at –3dBFS on IN2L/IN2R, IN2L/IN2R internally 109 dB
not routed.
Input Pin Crosstalk IN1L/IN1R differentially routed to Right ADC, ac-coupled to ground
1kHz sine wave input at –3dBFS on IN2L/IN2R, IN2L/IN2R internally
not routed.
IN3L/IN3R differentially routed to Left ADC, ac-coupled to ground
Differential configuration Rin = 20kΩ, AOSR=128 Channel Gain=0dB,
CM=0.9V
217Hz, 100mVpp signal on AVDD_18, AVDDx_18 59 dB
PSRR Differential configuration, Rin=20K, Channel Gain=0dB; CM=0.9V
AUDIO ADC
IN1 - IN3, Single-Ended, Rin = 10K, PGA gain set to 0dB 0 dB
IN1 - IN3, Single-Ended, Rin = 10K, PGA gain set to 47.5dB 47.5 dB
IN1 - IN3, Single-Ended, Rin = 20K, PGA gain set to 0dB –6 dB
IN1 - IN3, Single-Ended, Rin = 20K, PGA gain set to 47.5dB 41.5 dB
ADC programmable gain
amplifier gain IN1 - IN3, Single-Ended, Rin = 40K, PGA gain set to 0dB –12 dB
IN1 - IN3, Single-Ended, Rin = 40K, PGA gain set to 47.5dB 35.5 dB
IN4, Single-Ended, Rin = 20K, PGA gain set to 0dB –6 dB
IN4, Single-Ended, Rin = 20K, PGA gain set to 47.5dB 41.5 dB
ADC programmable gain 1-kHz tone 0.5 dB
amplifier step size
(5) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(6) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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SLAS679 –DECEMBER 2011
Electrical Characteristics, Bypass Outputs
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG BYPASS TO RECEIVER AMPLIFIER, DIRECT MODE
Load = 32Ω(differential), 56pF;
Input CM=0.9V; Output CM=1.65V;
Device Setup IN1L routed to RECP and IN1R routed to
RECM;
Channel Gain=0dB
Full scale differential input voltage (0dB) 1 VRMS
Gain Error 707mVrms (-3dBFS), 1-kHz input signal 0.5 dB
Noise, A-weighted(1) Idle Channel, IN1L and IN1R ac-shorted to 13 μVRMS
ground
THD+N Total Harmonic Distortion plus Noise 707mVrms (-3dBFS), 1-kHz input signal –88 dB
ANALOG BYPASS TO HEADPHONE AMPLIFIER, PGA MODE
Load = 16Ω(single-ended), 56pF; HVDD_18
= 3.3V
Input CM=0.9V; Output CM=1.65V
Device Setup IN1L routed to ADCPGA_L, ADCPGA_L
routed through MAL to HPL; and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
MAR to HPR; Rin = 20K; Channel Gain = 0dB
Full scale input voltage (0dB) 0.5 VRMS
Gain Error 446mVrms (-1dBFS), 1-kHz input signal –1.2 dB
Noise, A-weighted(1) Idle Channel, IN1L and IN1R ac-shorted to 6 μVRMS
ground
THD+N Total Harmonic Distortion plus Noise 446mVrms (-1dBFS), 1-kHz input signal –81 dB
ANALOG BYPASS TO HEADPHONE AMPLIFIER (GROUND-CENTERED CIRCUIT CONFIGURATION), PGA MODE
Load = 16Ω(single-ended), 56pF;
Input CM=0.9V;
IN1L routed to ADCPGA_L, ADCPGA_L
Device Setup routed through MAL to HPL; and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
MAR to HPR; Rin = 20K; Channel Gain = 0dB
Full scale input voltage (0dB) 0.5 VRMS
Gain Error 446mVrms (-1dBFS), 1-kHz input signal –1.0 dB
Noise, A-weighted(1) Idle Channel, IN1L and IN1R ac-shorted to 11 μVRMS
ground
THD+N Total Harmonic Distortion plus Noise 446mVrms (-1dBFS), 1-kHz input signal –67 dB
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Bypass Outputs (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Load = 10KOhm (single-ended), 56pF;
Input and Output CM=0.9V;
IN1L routed to ADCPGA_L and IN1R routed
Device Setup to ADCPGA_R; Rin = 20k
ADCPGA_L routed through MAL to LOL and
ADCPGA_R routed through MAR to LOR;
Channel Gain = 0dB
Full scale input voltage (0dB) 0.5 VRMS
Gain Error 446mVrms (-1dBFS), 1-kHz input signal –0.7 dB
Idle Channel, 6 μVRMS
IN1L and IN1R ac-shorted to ground
Noise, A-weighted (2) Channel Gain=40dB, 3 μVRMS
Inputs ac-shorted to ground, Input Referred
ANALOG BYPASS TO LINE-OUT AMPLIFIER, DIRECT MODE
Load = 10KOhm (single-ended), 56pF;
Input and Output CM=0.9V;
Device Setup IN1L routed to LOL and IN1R routed to LOR;
Channel Gain = 0dB
Full scale input voltage (0dB) 0.5 VRMS
Gain Error 446mVrms (-1dBFS), 1-kHz input signal –0.3 dB
Idle Channel, 3 μVRMS
Noise, A-weighted(2) IN1L and IN1R ac-shorted to ground
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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SLAS679 –DECEMBER 2011
Electrical Characteristics, Microphone Interface
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MICROPHONE BIAS (MICBIAS or MICBIAS_EXT)
Bias voltage CM=0.9V, AVDD3_33 = 1.8V
Micbias Mode 0 1.63 V
Micbias Mode 3 AVDD3_33 V
CM=0.75V, AVDD3_33 = 1.8V
Micbias Mode 0 1.36 V
Micbias Mode 3 AVDD3_33 V
MICROPHONE BIAS (MICBIAS or MICBIAS_EXT)
Bias voltage CM=0.9V, AVDD3_33 = 3.3V
Micbias Mode 0 1.63 V
Micbias Mode 1 2.36 V
Micbias Mode 2 2.91 V
Micbias Mode 3 AVDD3_33 V
CM=0.75V, AVDD3_33 = 3.3V
Micbias Mode 0 1.36 V
Micbias Mode 1 1.97 V
Micbias Mode 2 2.42 V
Micbias Mode 3 AVDD3_33 V
Output Noise CM=0.9V, Micbias Mode 2, A-weighted, 20Hz 26 μVRMS
to 20kHz bandwidth, 184 nV/√Hz
Current load = 0mA.
Current Sourcing Micbias Mode 0 (CM=0.9V)(1) 3 mA
Micbias Mode 1 or Micbias Mode 2 7 mA
(CM=0.9V)(2)
Inline Resistance Micbias Mode 3 63.6 Ω
(1) To provide 3mA, Micbias Mode 0 voltage yields typical voltage of 1.60V for Common Mode of 0.9V.
(2) To provide 7mA, Micbias Mode 1 voltage yields typical voltage of 2.31V, and Micbias Mode 2 voltage yields typical voltage of 2.86V for
Common Mode of 0.9V.
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SLAS679 –DECEMBER 2011
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Electrical Characteristics, Audio DAC Outputs
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Load = 10 kΩ(single-ended), 56pF
Input & Output CM=0.9V
DOSR = 128, MCLK=256* fs,
Device Setup Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB) 0.5 VRMS
SNR Signal-to-noise ratio A-weighted(1) (2) All zeros fed to DAC input 85 101 dB
DR Dynamic range, A-weighted (1) (2) –60dB 1kHz input full-scale signal, Word length=20 101 dB
bits
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –88 dB
DAC Gain Error –3dB full-scale, 1-kHz input signal 0.1 dB
DAC Mute Attenuation Mute 119 dB
DAC channel separation –1 dB, 1kHz signal, between left and right Line out 108 dB
100mVpp, 1kHz signal applied to AVDD_18, 71 dB
AVDDx_18
DAC PSRR 100mVpp, 217Hz signal applied to AVDD_18, 71 dB
AVDDx_18
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Load = 10 kΩ(single-ended), 56pF
Input & Output CM=0.75V; AVDD_18, AVDDx_18,
HVDD_18=1.5V
DOSR = 128
Device Setup MCLK=256* fs
Channel Gain = 0dB
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB) 0.375 VRMS
SNR Signal-to-noise ratio, A-weighted (1) All zeros fed to DAC input 99 dB
(2)
DR –60dB 1 kHz input full-scale signal, Word length=20 99 dB
Dynamic range, A-weighted (1) (2) bits
THD+N Total Harmonic Distortion plus Noise –3 dB full-scale, 1-kHz input signal –88 dB
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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SLAS679 –DECEMBER 2011
Electrical Characteristics, Audio DAC Outputs (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – MONO DIFFERENTIAL LINE OUTPUT
Load = 10 kΩ(differential), 56pF
Input & Output CM=0.9V, LOL signal routed to LOR
amplifier
DOSR = 128, MCLK=256* fs,
Device Setup Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB) 1 VRMS
SNR Signal-to-noise ratio A-weighted(3) (4) All zeros fed to DAC input 101 dB
DR Dynamic range, A-weighted (3) (4) –60dB 1kHz input full-scale signal, 101 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –86 dB
DAC Gain Error –3dB full-scale, 1-kHz input signal 0.1 dB
DAC Mute Attenuation Mute 97 dB
100mVpp, 1kHz signal applied to AVDD_18, 62 dB
AVDDx_18
DAC PSRR 100mVpp, 217Hz signal applied to AVDD_18, 63 dB
AVDDx_18
(3) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(4) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION)
Load = 16Ω(single-ended), 56pF,
Input CM=0.9V;
DOSR = 128, MCLK=256* fs,
Device Setup Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P3,
Headphone Output Strength=100%
Output 1 Output voltage 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted (5) All zeros fed to DAC input 80 94 dB
(6)
DR Dynamic range, A-weighted (5) (6) –60dB 1 kHz input full-scale signal 93 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –71 –55 dB
DAC Gain Error –3dB, 1kHz input full scale signal –0.2 dB
DAC Mute Attenuation Mute 92 dB
DAC channel separation –3dB, 1kHz signal, between left and right HP out 83 dB
100mVpp, 1kHz signal applied to AVDD_18, 55 dB
AVDD1x_18
DAC PSRR 100mVpp, 217Hz signal applied to AVDD_18, 55 dB
AVDD1x_18
Power Delivered THDN ≤-40dB, Load = 16Ω15 mW
Output 2 Output voltage Load = 16Ω(single-ended), Channel Gain = 5dB 0.8 VRMS
SNR Signal-to-noise ratio, A-weighted(5) (6) All zeros fed to DAC input, Load = 16Ω96 dB
Power Delivered THDN ≤-40dB, Load = 16Ω24 mW
Output 3 Output voltage Load = 32Ω(single-ended), Channel Gain = 5dB 0.9 VRMS
SNR Signal-to-noise ratio, A-weighted(5) (6) All zeros fed to DAC input, Load = 32Ω97 dB
Power Delivered THDN ≤-40dB, Load = 32Ω22 mW
(5) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(6) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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SLAS679 –DECEMBER 2011
Electrical Characteristics, Audio DAC Outputs (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω(single-ended), 56pF
Input & Output CM=0.9V, DOSR = 128,
MCLK=256* fs, Channel Gain=0dB
Device Setup Processing Block = PRB_P1
Power Tune = PTM_P4
Headphone Output Control = 100%
Full scale output voltage (0dB) 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted(7) (8) All zeros fed to DAC input 100 dB
DR Dynamic range, A-weighted (7) (8) –60dB 1kHz input full-scale signal, Power Tune = 100 dB
PTM_P4
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –79 dB
DAC Gain Error –3dB, 1kHz input full scale signal –0.2 dB
DAC Mute Attenuation Mute 119 dB
DAC channel separation –1dB, 1kHz signal, between left and right HP out 88 dB
100mVpp, 1kHz signal applied to AVDD_18, 64 dB
AVDD1x_18
DAC PSRR 100mVpp, 217Hz signal applied to AVDD_18, 70 dB
AVDD1x_18
RL=16Ω15
Power Delivered THDN ≤-40dB, Input CM=0.9V, mW
Output CM=0.9V
(7) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(8) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω(single-ended), 56pF,
Input & Output CM=0.75V; AVDD_18, AVDDx_18,
HVDD_18=1.5V,
DOSR = 128, MCLK=256* fs,
Device Setup Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P4
Headphone Output Control = 100%
Full scale output voltage (0dB) 0.375 VRMS
SNR Signal-to-noise ratio, A-weighted(9) All zeros fed to DAC input 99 dB
(10)
DR Dynamic range, A-weighted (9) (10) -60dB 1 kHz input full-scale signal 99 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –77 dB
AUDIO DAC – MONO DIFFERENTIAL RECEIVER OUTPUT
Load = 32 Ω(differential), 56pF,
Output CM=1.65V,
AVDDx_18=1.8V, DOSR = 128
MCLK=256* fs, Left DAC routed to LOL to RECP,
Device Setup LOL signal routed to LOR to RECM, Channel
(Receiver Driver) Gain = 6dB for full scale output
signal,
Processing Block = PRB_P4,
Power Tune = PTM_P4
Full scale output voltage (0dB) 2 VRMS
SNR Signal-to-noise ratio, A-weighted(9) All zeros fed to DAC input 90 99 dB
(10)
DR Dynamic range, A-weighted (9) (10) –60dB 1kHz input full-scale signal 97 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –81 dB
100mVpp, 1kHz signal applied to AVDD_18, 56 dB
AVDD1x_18
DAC PSRR 100mVpp, 217Hz signal applied to AVDD_18, 58 dB
AVDD1x_18
RL=32Ω117 mW
Power Delivered THDN ≤-40dB, Input CM=0.9V,
Output CM=1.65V
(9) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(10) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Class-D Outputs
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8Ω(Differential), 56pF+33µH
SLVDD=SRVDD=3.6, BTL measurement, DAC input
Output voltage = 0dBFS, class-D gain = 12dB, THD+N ≤–20dB, 2.67 VRMS
CM=0.9V
SLVDD=SRVDD=3.6V, BTL measurement, class-D
gain = 6dB, measured as idle-channel noise, A-
SNR Signal-to-noise ratio 91 dB
weighted (with respect to full-scale output value of 2
Vrms)(1) (2), CM=0.9V
SLVDD=SRVDD=3.6V, BTL measurement, DAC input
THD Total harmonic distortion –66 dB
= 0dBFS, class-D gain = 6dB, CM=0.9V
Total harmonic distortion SLVDD=SRVDD=3.6V, BTL measurement, DAC input
THD+N –66 dB
+ noise = 0dBFS, class-D gain = 6dB, CM=0.9V
SLVDD=SRVDD=3.6V, BTL measurement, ripple on 67 dB
SPKVDD = 200 mVp-p at 1 kHz, CM=0.9V
Power-supply rejection
PSRR ratio SLVDD=SRVDD=3.6V, BTL measurement, ripple on 67 dB
SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V
Mute attenuation Analog Mute Only 102 dB
SLVDD = SRVDD = 0.72
3.6 V
THD+N = 10%, f = 1 kHz, SLVDD = SRVDD =
Class-D Gain = 12 dB, CM = 1.00
4.2 V
0.9 V, RL= 8 ΩSLVDD = SRVDD = 1.70
5.5 V
POMaximum output power W
SLVDD = SRVDD = 0.58
3.6 V
THD+N = 1%, f = 1 kHz, SLVDD = SRVDD =
Class-D Gain = 12 dB, CM = 0.80
4.2 V
0.9 V, RL= 8 ΩSLVDD = SRVDD = 1.37
5.5 V
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω(Differential), 56pF+33µH
SLVDD=SRVDD=5.0V, BTL measurement, DAC input
Output voltage = 0dBFS, class-D gain = 12dB, THD+N ≤–20dB, 3.46 VRMS
CM=0.9V
SLVDD=SRVDD=5.0V, BTL measurement, class-D
gain = 6dB, measured as idle-channel noise, A-
SNR Signal-to-noise ratio 91
weighted (with respect to full-scale output value of 2
Vrms)(1) (2) , CM=0.9V
SLVDD=SRVDD=5.0V, BTL measurement, DAC input
THD Total harmonic distortion –70
= 0dBFS, class-D gain = 6dB, CM=0.9V
Total harmonic distortion SLVDD=SRVDD=5.0V, BTL measurement, DAC input
THD+N –70
+ noise = 0dBFS, class-D gain = 6dB, CM=0.9V
SLVDD=SRVDD=5.0V, BTL measurement, ripple on 67
SPKVDD = 200mVp-p at 1kHz, CM=0.9V
Power-supply rejection
PSRR ratio SLVDD=SRVDD=5.0V, BTL measurement, ripple on 67
SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V
Mute attenuation Analog Mute Only 102 dB
THD+N = 10%, f = 1 kHz, SLVDD = SRVDD =
POMaximum output power Class-D Gain = 12 dB, CM = 1.41 W
5.0 V
0.9 V, RL= 8 Ω
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Misc.
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE - VREF_AUDIO
CMMode = 0 (0.9V) 0.9
Reference Voltage Settings V
CMMode = 1 (0.75V) 0.75
Reference Noise CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, 1.2 μVRMS
Cref = 1μF
Decoupling Capacitor 1 μF
Bias Current 99 μA
miniDSP(1)
miniDSP clock frequency - ADC DVDD = 1.26V 37.5 MHz
miniDSP clock frequency - DAC DVDD = 1.26V 33.0 MHz
miniDSP clock frequency - ADC DVDD = 1.65V 59.5 MHz
miniDSP clock frequency - DAC DVDD = 1.65V 55.0 MHz
miniDSP clock frequency - ADC DVDD = 1.71V 62.5 MHz
miniDSP clock frequency - DAC DVDD = 1.71V 58.0 MHz
Shutdown Power
Coarse AVdd supply turned off, All External analog
Device Setup supplies powered and set available, No external
digital input is toggled, register values are retained.
P(total)(2) Sum of all supply currents, all supplies at 1.8 V 9.8 μW
except for SLVDD = SRVDD = SPK_V = 3.6 V and
RECVDD_33 = AVDD3_33 = 3.3 V
I(DVDD) 2.6 μA
I(IOVDD) 0.15 μA
I(AVDD1_18, AVDD2_18, AVDD4_18, 1.15 μA
AVDD_18, HVDD_18, CPVDD_18)
I(RECVDD_33, AVDD3_33) 0.15 μA
I(SLVDD, SRVDD, SPK_V) 0.5 μA
(1) miniDSP clock speed is specified by design and not tested in production.
(2) For further details on playback and recording power consumption, refer to Powertune section in SLAU309.
Electrical Characteristics, Logic Levels
TA= 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS(Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC FAMILY CMOS
VIH Logic Level IIH = 5 μA, IOVDD > 1.65V 0.7 × IOVDD V
IIH = 5μA, 1.2V ≤IOVDD <1.65V 0.9 × IOVDD V
IIH = 5μA, IOVDD < 1.2V IOVDD V
VIL IIL = 5 μA, IOVDD > 1.65V –0.3 0.3 × IOVDD V
IIL = 5μA, 1.2V ≤IOVDD <1.65V 0.1 × IOVDD V
IIL = 5μA, IOVDD < 1.2V 0 V
VOH IOH = 3mA load, IOVDD > 1.65V 0.8 × IOVDD V
IOH = 1mA load, IOVDD < 1.65V 0.8 × IOVDD V
VOL IOL = 3mA load, IOVDD > 1.65V 0.1 × IOVDD V
IOL = 1mA load, IOVDD < 1.65V 0.1 × IOVDD V
Capacitive Load 10 pF
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WCLK
BCLK
DOUT
DIN
t (WS)
d
t (DO-WS)
dt (DO-BCLK)
d
t (DI)
St (DI)
h
I2S/LJF TiminginMasterMode
TLV320AIC3262
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SLAS679 –DECEMBER 2011
Interface Timing
Note: All timing specifications are measured at characterization but not tested at final test. The audio serial interface timing
specifications are applied to Audio Serial Interface #1, Audio Serial Interface #2 and Audio Serial Interface #3.
Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
WCLK represents WCLK1 pin for Audio Serial Interface #1, WCLK2 pin for Audio Serial Interface #2, and WCLK3 pin for
Audio Serial Interface #3. BCLK represents BCLK1 pin for Audio Serial Interface #1, BCLK2 pin for Audio Serial Interface #2,
and BCLK3 pin for Audio Serial Interface #3. DOUT represents DOUT1 pin for Audio Serial Interface #1, DOUT2 pin for
Audio Serial Interface #2, and DOUT3 pin for Audio Serial Interface #3. DIN represents DIN1 pin for Audio Serial Interface #1,
DIN2 pin for Audio Serial Interface #2, and DIN3 pin for Audio Serial Interface #3. Specifications are at 25° C with DVDD =
1.8V and IOVDD = 1.8 V.
Figure 3. I2S/LJF/RJF Timing in Master Mode
Table 2. I2S/LJF/RJF Timing in Master Mode (see Figure 3)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
td(WS) WCLK delay 22 20 ns
td(DO-WS) WCLK to DOUT delay (For LJF Mode only) 22 20 ns
td(DO-BCLK) BCLK to DOUT delay 22 20 ns
ts(DI) DIN setup 4 4 ns
th(DI) DIN hold 4 4 ns
trBCLK Rise time 10 8 ns
tfBCLK Fall time 10 8 ns
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th(WS)
WCLK
BCLK
DOUT
DIN
tL(BCLK) tH(BCLK)
ts(WS)
td(DO-WS) td(DO-BCLK)
th(DI)
ts(DI)
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SLAS679 –DECEMBER 2011
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Figure 4. I2S/LJF/RJF Timing in Slave Mode
Table 3. I2S/LJF/RJF Timing in Slave Mode (see Figure 4)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
tH(BCLK) BCLK high period 30 30 ns
tL(BCLK) BCLK low period 30 30
ts(WS) WCLK setup 4 4
th(WS) WCLK hold 4 4
td(DO-WS) WCLK to DOUT delay (For LJF mode only) 22 20
td(DO-BCLK) BCLK to DOUT delay 22 20
ts(DI) DIN setup 4 4
th(DI) DIN hold 4 4
trBCLK Rise time 5 4
tfBCLK Fall time 5 4
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WCLK
BCLK
DOUT
DIN
t (WS)
dt (WS)
d
t (DO-BCLK)
d
t (DI)
st (DI)
h
WCLK
BCLK
DOUT
DIN
t (BCLK)
H
t (ws)
h
t (BCLK)
L
t (ws)
s
t (ws)
h
t (DO-BCLK)
d
t (ws)
h
t (DI)
st (DI)
h
TLV320AIC3262
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SLAS679 –DECEMBER 2011
Typical DSP Timing Characteristics
Specifications are at 25° C with DVDD = 1.8 V.
Figure 5. DSP/Mono PCM Timing in Master Mode
Table 4. DSP/Mono PCM Timing in Master Mode (see Figure 5)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
td(WS) WCLK delay 22 20 ns
td(DO-BCLK) BCLK to DOUT delay 22 20 ns
ts(DI) DIN setup 4 4 ns
th(DI) DIN hold 4 4 ns
trBCLK Rise time 10 8 ns
tfBCLK Fall time 10 8 ns
Figure 6. DSP/Mono PCM Timing in Slave Mode
Table 5. DSP/Mono PCM Timing in Slave Mode (see Figure 6)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
tH(BCLK) BCLK high period 30 30 ns
tL(BCLK) BCLK low period 30 30 ns
ts(WS) WCLK setup 4 4 ns
th(WS) WCLK hold 4 4 ns
td(DO-BCLK) BCLK to DOUT delay 22 20 ns
ts(DI) DIN setup 5 5 ns
th(DI) DIN hold 5 5 ns
trBCLK Rise time 5 4 ns
tfBCLK Fall time 5 4 ns
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I2C Interface Timing
Figure 7. I2C Interface Timing Diagram
Table 6. I2C Interface Timing (see Figure 7)
PARAMETER TEST CONDITION Standard-Mode Fast-Mode UNITS
MIN TYP MAX MIN TYP MAX
fSCL SCL clock frequency 0 100 0 400 kHz
tHD;STA Hold time (repeated) START 4.0 0.8 μs
condition. After this period, the first
clock pulse is generated.
tLOW LOW period of the SCL clock 4.7 1.3 μs
tHIGH HIGH period of the SCL clock 4.0 0.6 μs
tSU;STA Setup time for a repeated START 4.7 0.8 μs
condition
tHD;DAT Data hold time: For I2C bus 0 3.45 0 0.9 μs
devices
tSU;DAT Data set-up time 250 100 ns
trSDA and SCL Rise Time 1000 20+0.1Cb300 ns
tfSDA and SCL Fall Time 300 20+0.1Cb300 ns
tSU;STO Set-up time for STOP condition 4.0 0.8 μs
tBUF Bus free time between a STOP 4.7 1.3 μs
and START condition
CbCapacitive load for each bus line 400 400 pF
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ttd
S
ta
MSB OUT BIT 6 . . . 1 LSB OUT
tsck
tLead
tLag
tsckh
tsckl
tr
tf
tvtdis
MSB IN BIT 6 . . . 1 LSB IN
thi
tsu
SS
SCLK
MISO
MOSI
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SLAS679 –DECEMBER 2011
SPI Interface Timing
SS = SCL pin, SCLK = GPI1 pin, MISO = GPO1 pin, and MOSI = SDA pin. Specifications are at 25° C with DVDD = 1.8 V.
Figure 8. SPI Interface Timing Diagram
Timing Requirements (See Figure 8)
Specifications are at 25° C with DVDD = 1.8 V.
Table 7. SPI Interface Timing
PARAMETER TEST CONDITION IOVDD=1.8V IOVDD=3.3V UNITS
MIN TYP MAX MIN TYP MAX
tsck SCLK Period(1) 50 40 ns
tsckh SCLK Pulse width High 25 20 ns
tsckl SCLK Pulse width Low 25 20 ns
tlead Enable Lead Time 25 20 ns
ttrail Enable Trail Time 25 20 ns
td;seqxfr Sequential Transfer Delay 25 20 ns
taSlave DOUT (MISO) access time 25 20 ns
tdis Slave DOUT (MISO) disable time 25 20 ns
tsu DIN (MOSI) data setup time 8 8 ns
th;DIN DIN (MOSI) data hold time 8 8 ns
tv;DOUT DOUT (MISO) data valid time 20 14 ns
trSCLK Rise Time 4 4 ns
tfSCLK Fall Time 4 4 ns
(1) These parameters are based on characterization and are not tested in production.
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Typical Characteristics
Device Power Consumption
Device power consumption largely depends on PowerTune configuration. For information on device power
consumption, see the TLV320AIC3262 Application Reference Guide, literature number SLAU309.
Typical Performance
Audio ADC Performance
ADC SNR
vs ADC SINGLE ENDED INPUT TO ADC FFT @ -3dBr
CHANNEL GAIN vs
Input-Referred FREQUENCY
Figure 9. Figure 10.
ADC DIFFERENTIAL INPUT TO ADC FFT @ -3dBr
vs
FREQUENCY
Figure 11.
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Audio DAC Performance
DAC TO HEADPHONE OUTPUT (GCHP) FFT AMPLITUDE
DAC TO LINE OUTPUT FFT AMPLITUDE @ -3dBFS @ -3dBFS
vs vs
FREQUENCY FREQUENCY
10kΩLoad 16ΩLoad
Figure 12. Figure 13.
DAC TO HEADPHONE OUTPUT (GCHP) FFT AMPLITUDE DAC TO DIFFERENTIAL RECEIVER OUTPUT FFT
@ -3dBFS AMPLITUDE @ -3dBFS
vs vs
FREQUENCY FREQUENCY
32ΩLoad 32ΩLoad
Figure 14. Figure 15.
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0.8 1.0 1.2 1.4 1.6
60
70
80
90
100
110
120
SNR
0
25
50
75
100
125
150
Output Common Mode Setting (V)
SNR − Signal To Noise Ratioi (dB)
Power delivered (mW)
Output Power
G009
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
TOTAL HARMONIC DISTORTION+NOISE TOTAL HARMONIC DISTORTION+NOISE
vs vs
HEADPHONE (GCHP) OUTPUT POWER DIFFERENTIAL RECEIVER OUTPUT POWER
9dB Gain 32ΩLoad
Figure 16. Figure 17.
DIFFERENTIAL RECEIVER SNR AND OUTPUT POWER
vs
OUTPUT COMMON MODE SETTING
32ΩLoad
Figure 18.
Class-D Driver Performance
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Different Gain Settings, 8ΩLoad, Different SLVDD/SRVDD/SPK_V Supplies, 8ΩLoad, 12dB
SLVDD=SRVDD=SPK_V=3.6V Gain
Figure 19. Figure 20.
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SLAS679 –DECEMBER 2011
MICBIAS Performance MICBIAS MODE 2, CM = 0.9V, AVDD3_33 OP STAGE
vs
MICBIAS LOAD CURRENT
Figure 21.
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Product Folder Link(s): TLV320AIC3262
SPI_SELECT
IN1R/AUX2
IN2R
IN3R
IN4R
IN4L
IN3L
IN2L
VREF_AUDIO
LOL
LOR
CPVDD_18
CPVSS
CPFCP
CPFCM
VNEG
SPKLM
SPKLP
SPKRP
MICBIAS
SDA
GPI4
GPO1
GPI3
GPI1
GPI2
VREF_SAR
RECM
BCLK2
WCLK2
DIN2
DOUT2
BCLK3
WCLK3
DIN3
DOUT3
MCLK1
WCLK1
DIN1
DOUT1
MCLK2
BCLK1
SCL
HOST PROCESSOR
GPIO1
GPIO2
SRVDD
SLVDD
RESET
0.1 F
1 F
10 F
2.2 F
X7R Type
+1.8VA
Headset
MICDET
1 F
1 F
Analog_In1
Analog_In2
1 F
1 F
Analog_In3
Analog_In4
1 F
1 F
1 F
Analog_In5
Analog_In6
Analog_In7
Receiver
Lineout
1 F
1 F
1 F
VBAT
0.1 F
0.1 F
1 F
RECVSS
RECVDD_33
+3.3VA
+1.8VD
SVDD
2.2 F
X7R Type
Note: VBAT is used for
voltage measurement.
S0441-02
System
Battery
To Internal
Mic
AVDD3_33
AVSS3
+3.3VA
0.1 F
1 F
0.1 F
2
SVDD
10 F
0.1 F
10 F
SPK_V
+1.8VA
0.1 F
+1.8VD
10 F0.1 F 10 F 0.1 F 0.1 F 0.1 F 0.1 F
0.1 F 10 F
DVDD
IOVDD
DVSS
IOVSS
HVDD_18
AVSS1
SLVSS
SRVSS
AVDD1_18
AVDD2_18
AVDD4_18
AVDD_18
AVSS2
AVSS4
AVSS
8
8
SPKRM
32
RECP
HPVSS_SENSE
AGND at Connector
MICBIAS_EXT
IN1L/AUX1
HPL
HPR
2.2k
0.1 F
1 F
1 F
Audio
Interface #3
Audio
Interface #2
Audio
Interface #1
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
Application Overview
Typical Circuit Configuration
Figure 22 shows a typical circuit configuration for a system utilizing TLV320AIC3262. Note that while this circuit
configuration shows all three Audio Serial Interfaces connected to a single Host Processor, it is also quite
common for these Audio Serial Interfaces to connect to separate devices (e.g. Host Processor on Audio Serial
Interface #1, and modems and/or Bluetooth devices on the other audio serial interfaces).
Figure 22. Typical Circuit Configuration
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
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The fixed-function pins are hardware-control pins RESET and SPI_SELECT pin. Depending on the state of
SPI_SELECT, four pins SCL, SDA, GPO1, and GPI1 are configured for either I2C or SPI protocol. Only in I2C
mode, GPI3 and GPI4 provide four possible I2C addresses for the TLV320AIC3262.
Other digital IO pins can be configured for various functions via register control.
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
The possible analog routings of analog input pins to ADCs and output amplifiers as well as the routing from
DACs to output amplifiers can be seen in the Analog Routing Diagram.
Multifunction Pins
Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 9 pins (MCLK1, MCLK2, BCLK1, DIN1, BCLK2, GPIO1, GPIO2, GPI1, GPI2).
Table 8. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2,
BCLK2, DIN2, and DOUT2
1 2 3 4 5 6 7 8 9 10
Pin Function MCLK1 MCLK2 WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2
AINT1 Output E E E E
BINT2 Output E E E E
CSAR ADC Interrupt E E E E
DCLOCKOUT Output E E E E
EADC_MOD_CLOCK Output E E E
FSingle DOUT for ASI1 (All E, D
Channels)
FSingle DOUT for ASI2 E, D
FSingle DOUT for ASI3
GMultiple DOUTs for ASI1 (L1, E
R1)
GMultiple DOUTs for ASI1 (L2, E
R2)
GMultiple DOUTs for ASI1 (L3, E
R3)
GMultiple DOUTs for ASI1 (L4, E
R4)
IGeneral Purpose Output (via E(1) E E E
Reg)
FSingle DIN for ASI1 (All E, D(2)
Channels)
FSingle DIN for ASI2 E, D
FSingle DIN for ASI3
HMultiple DINs for ASI1 (L1, E
R1)
HMultiple DINs for ASI1 (L2, E
R2)
HMultiple DINs for ASI1 (L3, E E
R3)
HMultiple DINs for ASI1 (L4, E E
R4)
JDigital Mic Data E E E
(1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if DOUT1 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
(2) D: Default Function
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Table 8. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2,
BCLK2, DIN2, and DOUT2 (continued)
1 2 3 4 5 6 7 8 9 10
Pin Function MCLK1 MCLK2 WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2
KInput to PLL_CLKIN S(3), D S S(4) S S(4)
LInput to ADC_CLKIN S(3), D S S(4) S(4)
MInput to DAC_CLKIN S(3), D S S(4) S(4)
NInput to CDIV_CLKIN S(3), D S S S S
OInput to LFR_CLKIN S(3), D S S S S S
PInput to HF_CLK S(3)
QInput to REF_1MHz_CLK S(3)
RGeneral Purpose Input (via E E E E
Reg)
SISR Interrupt for miniDSP E
(via Reg)
TWCLK Output for ASI1 E
UWCLK Input for ASI1 S, D
VBCLK Output for ASI1 E
WBCLK Input for ASI1 S(4), D
XWCLK Output for ASI2 E
YWCLK Input for ASI2 S, D
ZBCLK Output for ASI2 E
AA BCLK Input for ASI2 S(4), D
BB WCLK Output for ASI3
CC WCLK Input for ASI3
DD BCLK Output for ASI3
EE BCLK Input for ASI3
(3) S(3): The MCLK1 pin could be chosen to drive the PLL, ADC Clock, DAC Clock, CDIV Clock, LFR Clock, HF Clock, and
REF_1MHz_CLK inputs simultaneously
(4) S(4): The BCLK1 or BCLK2 pins could be chosen to drive the PLL, ADC Clock, DAC Clock, and audio interface bit clock inputs
simultaneously
Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4
11 12 13 14 15 16 17 18 19 20 21
Pin Function WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ GPI1/ GPI2 GPI3(2) GPI4(2)
MISO(1) SCLK(1)
AINT1 Output E E E
BINT2 Output E E E
CSAR ADC Interrupt E E E
DCLOCKOUT Output E E E
EADC_MOD_CLOCK E E E
Output
FSingle DOUT for ASI1 E
(All Channels)
FSingle DOUT for ASI2
FSingle DOUT for ASI3 E, D
GMultiple DOUTs for
ASI1 (L1, R1)
(1) GPO1 and GPI1 can only be utilized for functions defined in this table when part utilizes I2C for control. In SPI mode, these pins serve
as the MISO and SCLK, respectively.
(2) GPI3 and GPI4 can only be utilized for functions defined in this table when part utilizes SPI for control. In I2C mode, these pins serve as
I2C address pins.
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Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4 (continued)
11 12 13 14 15 16 17 18 19 20 21
Pin Function WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ GPI1/ GPI2 GPI3(2) GPI4(2)
MISO(1) SCLK(1)
GMultiple DOUTs for E E E
ASI1 (L2, R2)
GMultiple DOUTs for E E E E E
ASI1 (L3, R3)
GMultiple DOUTs for E E E E
ASI1 (L4, R4)
IGeneral Purpose E(3) E E E E E
Output (via Reg)
FSingle DIN for ASI1 E
(All Channels)
FSingle DIN for ASI2
FSingle DIN for ASI3 E, D
HMultiple DINs for ASI1
(L1, R1)
HMultiple DINs for ASI1 E E E
(L2, R2)
HMultiple DINs for ASI1 E E E E E
(L3, R3)
HMultiple DINs for ASI1 E E E E
(L4, R4)
JDigital Mic Data E E E E
KInput to PLL_CLKIN S(4) S(4) S(4) S(4)
LInput to ADC_CLKIN S(4) S(4) S(4) S(4)
MInput to DAC_CLKIN S(4) S(4) S(4) S(4)
NInput to CDIV_CLKIN S S
OInput to LFR_CLKIN S S S S S S
PInput to HF_CLK
QInput to
REF_1MHz_CLK
RGeneral Purpose Input E E E E E E E
(via Reg)
SISR Interrupt for E E E
miniDSP (via Reg)
TWCLK Output for ASI1 E E
UWCLK Input for ASI1 E
VBCLK Output for ASI1 E
WBCLK Input for ASI1 E
XWCLK Output for ASI2
YWCLK Input for ASI2
ZBCLK Output for ASI2
AA BCLK Input for ASI2
BB WCLK Output for ASI3 E
CC WCLK Input for ASI3 S, D(5)
DD BCLK Output for ASI3 E
EE BCLK Input for ASI3 S, D
(3) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if WCLK3 has been
allocated for General Purpose Output, it cannot be used as the ASI3 WCLK output at the same time)
(4) S(4): The GPIO1, GPIO2, GPI1, or GPI2 pins could be chosen to drive the PLL, ADC Clock, and DAC Clock inputs simultaneously
(5) D: Default Function
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 39
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Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4 (continued)
11 12 13 14 15 16 17 18 19 20 21
Pin Function WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ GPI1/ GPI2 GPI3(2) GPI4(2)
MISO(1) SCLK(1)
FF ADC BCLK Input for E E E E E E
ASI1
GG ADC WCLK Input for E E E E E E
ASI1
HH ADC BCLK Output for E E
ASI1
II ADC WCLK Output for E E
ASI1
JJ ADC BCLK Input for E E E E E E
ASI2
KK ADC WCLK Input for E E E E E E
ASI2
LL ADC BCLK Output for E E
ASI2
MM ADC WCLK Output for E E
ASI2
NN ADC BCLK Input for E E E E E E
ASI3
OO ADC WCLK Input for E E E E E E
ASI3
PP ADC BCLK Output for E E
ASI3
QQ ADC WCLK Output for E E
ASI3
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Product Folder Link(s): TLV320AIC3262
IN3R
IN2R
-12, -6, 0dB
IN1L
IN2L
IN3L
IN1R
IN2R
IN3R
IN1L
IN3L
IN2L
Left Channel Input Options:
Single Ended: IN1L or IN2L or IN3L or IN1R or IN4L
Differential: IN2L (P) and IN2R (M) or IN3L (P) and IN3R (M)
or IN4L (P) and IN4R (M)
Right Channel Input Options:
Single Ended: IN1R or IN2R or IN3R or IN2L or IN4R
Differential: IN1R (P) and IN1L (M) or IN3R (P) and IN3L (M)
or IN4R (P) and IN4L (M)
CM
CM2L
CM1L
CM1R
CM2R
P
M
Left ADC
Mic PGA
Left
P
M
-12, -6, 0dB
0 to +47.5 dB
0 to +47.5 dB
Right ADC
Left DAC
Right DAC
P
M
MAR
RDACP
P1_R27_D6
P
M
LDACM
P1_R29_D[6:0]
LOR-B1
-78dB to 0dB
IN1R-B
IN1R-B
RDACM
MAR
LOR
Lineout
Amplifier
Right
Headphone
Amplifier Right
-6dB to +14dB
HPR
Receiver
Amplifier
-6db to +29dB
RECM
RECP
1
2
LOR-B2
IN1L
IN1R
LOL-B2
RDACP
MAL
LDACM
IN1L-B
Headphone
Amplifier Left
-6dB to14dB
HPL
MAL
LDACP
LOL-B1
LOL
Lineout
Amplifier
Left
Class-D
Speaker Amp L
6, 12, 18, 24, 30
dB
SPKLM
SPKLP
SPR_IN
SPKRM
SPKRP
MAL
LOL
MAR
LOR
SPR_IN
IN1L-B
LOL
MAR
P1_R23_D7
P1_R23_D6
P1_R27_D7
P1_R45_D7
Mixer Amp
Left
MAL
P1_R17_D5
-36dB to 0dB
Mixer Amp
Right
-36d to 0dB
P1_R19_D[5:0]
P1_R45_D6
P1_R17_D4
P1_R22_D5
P1_R22_D2
P1_R23_D[4:3]
P1_R23_D[1:0]
-78dB to 0dB
-78dB to 0dB
P1_R46_D[6:0]
P1_R45_D2
P1_R47_D[6:0]
P1_R27_D5
P1_R28_D[6:0]
P1_R23_D[4:3]
P1_R18_D[5:0]
P1_R55_D[7:6]
P1_R22_D7
Class-D
Speaker Amp R
6, 12, 18, 24,
30 dB
-78dB to 0dB
-78dB to 0dB
P1_R45_D1=Power
P1_R48_D[6:4]=Gain
P1_R27_D0=Power
P1_R32_D[5:0]=Gain
P1_R22_D1=Power
P1_R22_D0=Power
-78dB to 0dB
P1_R36_D[6:0]
P1_R37_D[6:0]
-78dB to 0dB
P1_R40_D[5:0]=Gain RECP
P1_R40_D7=Power RECP
P1_R38_D[6:0]
-78dB to 0dB
P1_R39_D[6:0]
P1_R27_D4
P1_R27_D2
P1_R19_D[5:0]
P1_R59
P1_R60
IN1L
IN1R
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
10/20/40K
Note (For All Inputs to Mic PGA):
PGA Input = 0 dB for Singled Ended Input with R
IN
= 10K
PGA Input = +6 dB for Differential Input with R
IN
= 10K
PGA Input = -6 dB for Singled Ended Input with R
IN
= 20K
PGA Input = 0 dB for Differential Input with R
IN
= 20K
PGA Input = -12 dB for Singled Ended Input with R
IN
= 40K
PGA Input = -6 dB for Differential Input with R
IN
= 40K
P1_R22_D6
IN4L
P1_R53_D5
20K
IN4R
20K
IN4R
20K P1_R53_D4
20K P1_R56_D4
IN4L
20K
20K
P1_R55_D[5:4]
P1_R55_D[3:2]
P1_R55_D[1:0]
P1_R56_D5
P1_R57_D[5:4]
P1_R57_D[3:2]
P1_R57_D[7:6]
P1_R57_D[1:0]
P1_R54_D[1:0]
P1_R54_D[7:6]
P1_R54_D[3:2]
P1_R54_D[5:4]
P1_R52_D[7:6]
P1_R52_D[5:4]
P1_R52_D[3:2]
P1_R52_D[1:0]
P1_R46_D[6:0]
P1_R28_D[6:0]
P1_R45_D0=Power
P1_R48_D[2:0]=Gain
P1_R27_D1=Power
P1_R31_D[5:0]=Gain
P1_R47_D[6:0]
Mic PGA
Right
P1_R18_D[5:0]
IN1R
P1_R23_D[1:0]
P1_R36_D[6:0]
P1_R38_D[6:0]
P1_R39_D[6:0]
P1_R37_D[6:0]
IN1R
IN1L
P1_R17_D2=Power
P1_R17_D3=Power
P1_R41_D[5:0]=Gain RECM
P1_R40_D6=Power RECM
P1_R29_D[6:0]
TLV320AIC3262
www.ti.com
SLAS679 –DECEMBER 2011
Analog Audio I/O
Figure 23. Analog Routing Diagram
For more detailed information see the TLV320AIC3262 Application Reference Guide, SLAU309.
Analog Low Power Bypass
The TLV320AIC3262 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation; this supports low-power operation during analog-bypass mode. In
analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left
lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog
inputs to the differential receiver amplifier, which outputs on RECP and RECM.
ADC Bypass Using Mixer Amplifiers
In addition to the low-power bypass mode, there is a bypass mode that uses the programmable gain amplifiers of
the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line, speaker, or headphone outputs, fully bypassing the ADC and DAC. To enable this mode,
the mixer amplifiers are powered on via software command.
Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 41
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HPR
HPVSS_SENSE
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Headphone Outputs
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ωin single-
ended DC-coupled headphone configurations. An integral charge pump generates the negative supply required
to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is made
equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in dc-
coupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
Figure 24. TLV320AIC3262 Ground-Centered Headphone Output
Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking
capacitors.
Stereo Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ωto 10kΩ. The output common mode of line level drivers can be configured to equal the analog
input common-mode setting, either 0.75V or 0.9V. The line-level drivers can drive out a mixed combination of
DAC signal and attenuated ADC PGA signal, and signal mixing is register-programmable.
Differential Receiver Output
The differential receiver amplifier output spans the RECP and RECM pins and can drive a 32Ωreceiver driver.
With output common-mode setting of 1.65V and RECVDD_33 supply at 3.3V, the receiver driver can drive up to
a 1Vrms output signal. With the RECVDD_33 supply at 3.3V, the receiver driver can deliver greater than 128mW
into a 32ΩBTL load. If desired, the RECVDD_33 supply can be set to 1.8V, at which the driver can deliver about
40mW into the 32ΩBTL load.
Stereo Class-D Speaker Outputs
The integrated Class-D stereo speaker drivers (SPKLP/SPKLN and SPKRP/SPKRN) are capable of driving two
8Ωdifferential loads. The speaker drivers can be powered directly from the power supply (2.7V to 5.5V) on the
SLVDD and SRVDD pins, however the voltage (including spike voltage) must be limited below the Absolute
Maximum Voltage of 6.0V.
The speaker drivers are capable of supplying 750 mW per channel at 10% THD+N with a 3.6-V power supply
and 1.46W per channel at 10% THD+N with a 5.0V power supply. Separate left and right channels can be sent
to each Class-D driver through the Lineout signal path, or from the mixer amplifiers in the ADC bypass. If only
one speaker is being utilized for playback, the analog mixer before the Left Speaker amplifier can sum the left
and right audio signals for monophonic playback.
ADC / Digital Microphone Interface
The TLV320AIC3262 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter and a programmable miniDSP. The ADC supports
sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo
recording path can be powered up one channel at a time, to support the case where only mono record capability
is required.
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The ADC path of the TLV320AIC3262 features a large set of options for signal conditioning as well as signal
routing:
• 2 ADCs
• 8 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration
• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• 2 mixer amplifiers for analog bypass
• 2 low power analog bypass channels
• Fine gain adjust of digital channels with 0.1 dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
• Automatic gain control (AGC)
In addition to the standard set of ADC features the TLV320AIC3262 also offers the following special functions:
• Built in microphone biases
• Stereo digital microphone interface
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
• Adaptive filter mode
ADC Processing Blocks — Overview
The TLV320AIC3262 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The
decimation filter can be chosen from three different types, depending on the required frequency response, group
delay and sampling rate.
ADC Processing Blocks
The TLV320AIC3262 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Decreasing the use of signal-processing capabilities reduces the power
consumed by the device. Table 10 gives an overview of the available processing blocks of the ADC channel and
their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user programmable coefficients.
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Table 10. ADC Processing Blocks
Processing Channel Decimation 1st Order Number FIR Required AOSR Resource
Blocks Value
Filter IIR Available BiQuads Class
PRB_R1(1) Stereo A Yes 0 No 128,64,32,16,8,4 7
PRB_R2 Stereo A Yes 5 No 128,64,32,16,8,4 8
PRB_R3 Stereo A Yes 0 25-Tap 128,64,32,16,8,4 8
PRB_R4 Left A Yes 0 No 128,64,32,16,8,4 4
PRB_R5 Left A Yes 5 No 128,64,32,16,8,4 4
PRB_R6 Left A Yes 0 25-Tap 128,64,32,16,8,4 4
PRB_R7 Stereo B Yes 0 No 64,32,16,8,4,2 3
PRB_R8 Stereo B Yes 3 No 64,32,16,8,4,2 4
PRB_R9 Stereo B Yes 0 17-Tap 64,32,16,8,4,2 4
PRB_R10 Left B Yes 0 No 64,32,16,8,4,2 2
PRB_R11 Left B Yes 3 No 64,32,16,8,4,2 2
PRB_R12 Left B Yes 0 17-Tap 64,32,16,8,4,2 2
PRB_R13 Stereo C Yes 0 No 32,16,8,4,2,1 3
PRB_R14 Stereo C Yes 5 No 32,16,8,4,2,1 4
PRB_R15 Stereo C Yes 0 25-Tap 32,16,8,4,2,1 4
PRB_R16 Left C Yes 0 No 32,16,8,4,2,1 2
PRB_R17 Left C Yes 5 No 32,16,8,4,2,1 2
PRB_R18 Left C Yes 0 25-Tap 32,16,8,4,2,1 2
(1) Default
For more detailed information see the Application Reference Guide, SLAU309.
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DAC
The TLV320AIC3262 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal
images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize
power dissipation and performance, the TLV320AIC3262 allows the system designer to program the
oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling
ratios for lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3262 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3262 features many options for signal conditioning and signal routing:
• 2 headphone amplifiers
– Usable in single-ended stereo or differential mono mode
– Analog volume setting with a range of -6 to +14 dB
• 2 line-out amplifiers
– Usable in single-ended stereo or differential mono mode
• 2 Class-D speaker amplifiers
– Usable in stereo differential mode
– Analog volume control with a settings of +6, +12, +18, +24, and +30 dB
• 1 Receiver amplifier
– Usable in mono differential mode
– Analog volume setting with a range of -6 to +29 dB
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320AIC3262 also offers the following special features:
• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode
• Asynchronous Sample Rate Conversion
DAC Processing Blocks — Overview
The TLV320AIC3262 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy balancing power conservation
and signal processing flexibility. Less signal processing capability will result in less power consumed by the
device. The Table 11 gives an overview over all available processing blocks of the DAC channel and their
properties. The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• 3D – Effect
• Beep Generator
The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients.
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Table 11. Overview – DAC Predefined Processing Blocks
Processing Interpolation Channel 1st Order Num. of DRC 3D Beep RC Class
Block No. Filter IIR Available Biquads Generator
PRB_P1(1) A Stereo No 3 No No No 8
PRB_P2 A Stereo Yes 6 Yes No No 12
PRB_P3 A Stereo Yes 6 No No No 10
PRB_P4 A Left No 3 No No No 4
PRB_P5 A Left Yes 6 Yes No No 6
PRB_P6 A Left Yes 6 No No No 5
PRB_P7 B Stereo Yes 0 No No No 5
PRB_P8 B Stereo No 4 Yes No No 9
PRB_P9 B Stereo No 4 No No No 7
PRB_P10 B Stereo Yes 6 Yes No No 9
PRB_P11 B Stereo Yes 6 No No No 7
PRB_P12 B Left Yes 0 No No No 3
PRB_P13 B Left No 4 Yes No No 4
PRB_P14 B Left No 4 No No No 4
PRB_P15 B Left Yes 6 Yes No No 5
PRB_P16 B Left Yes 6 No No No 4
PRB_P17 C Stereo Yes 0 No No No 3
PRB_P18 C Stereo Yes 4 Yes No No 6
PRB_P19 C Stereo Yes 4 No No No 4
PRB_P20 C Left Yes 0 No No No 2
PRB_P21 C Left Yes 4 Yes No No 3
PRB_P22 C Left Yes 4 No No No 2
PRB_P23 A Stereo No 2 No Yes No 8
PRB_P24 A Stereo Yes 5 Yes Yes No 12
PRB_P25 A Stereo Yes 5 Yes Yes Yes 13
PRB_P26 D Stereo No 0 No No No 1
(1) Default
For more detailed information see the Application Reference Guide, SLAU309.
Powertune
The TLV320AIC3262 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3262 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the Application Reference Guide, SLAU309.
Clock Generation and PLL
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3262.
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The TLV320AIC3262 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require source reference clocks, and
these clocks can be from a single source or from two separate sources. They can be provided on a variety of
device pins such as MCLKx, BCLK1, BCLK2, GPI1, GPI2, or GPIOx pins. The clocks, ADC_CLKIN and
DAC_CLKIN, can then be routed through highly-flexible clock dividers to generate the various clocks required for
ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be
generated from the reference clocks on MCLKx, BCLK1, BCLK2, or GPIOx, the codec also provides the option of
using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required
clocks. The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate
the various clocks required for ADC, DAC and the miniDSP sections.
For more detailed information see the Application Reference Guide, SLAU309.
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Interfaces
Control Interfaces
The TLV320AIC3262 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
It is not recommended to change the state of SPI_SELECT during device operation.
I2C Control
The TLV320AIC3262 supports the I2C control protocol, and will respond by default (GPI3 and GPI4 grounded) to
the 7-bit I2C address of 0011000. With the two I2C address pins, GPI3 and GPI4, the device can be configured to
respond to one of four 7-bit I2C addresses, 0011000, 0011001, 0011010, or 0011011. The full 8-bit I2C address
can be calculated as:
8-Bit I2C Address = "00110" + GPI4 + GPI3 + R/W
E.g. to write to the TLV320AIC3262 with GPI4 = 1 and GPI3 = 0 the 8-Bit I2C Address is "00110" + GPI4 + GPI3
+ R/W = "00110100" = 0x34
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
SPI Control
In the SPI control mode, the TLV320AIC3262 uses the pins SCL as SS, GPI1 as SCLK, GPO1 as MISO, SDA as
MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and
clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex,
synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The
SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates
transmissions. The SPI slave devices (such as the TLV320AIC3262) depend on a master to start and
synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master
begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the
byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
For more detailed information see the Application Reference Guide, SLAU309.
Digital Audio Interfaces
The TLV320AIC3262 features three digital audio data serial interfaces, or audio buses. These three interfaces
can be run simultaneously, thereby enabling reception and transmission of digital audio from/to three separate
devices. A common example of this scenario would be individual connections to an application processor, a
communication baseband processor, and a Bluetooth chipset. By utilizing the TLV320AIC3262 as the center of
the audio processing in a portable audio system, mixing of voice and music audio is greatly simplified. In
addition, the miniDSP can be utilized to greatly enhance the portable device experience by providing advanced
audio processing to both communication and media audio streams simultaneously. In addition to the three
simultaneous digital audio interfaces, a fourth set of digital audio pins can be muxed into Audio Serial Interface
#1. In other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3262, with up to
three of these 4-wire buses receiving and sending digital audio data.
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Audio Serial Interfaces
AUDIO SERIAL INTERFACE #1 AUDIO SERIAL INTERFACE #2
DOUT1
DIN1
BCLK1
WCLK1
DIN2
BCLK2
WCLK2
DOUT2
AUDIO SERIAL INTERFACE #3
DIN3
BCLK3
WCLK3
DOUT3
WCLK BCLK DIN DOUT WCLK BCLK DIN DOUT WCLK BCLK DIN DOUT
GPO1
GPI2
GPIO2
GPIO1
TLV320AIC3262
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Figure 25. Typical Multiple Connections to Three Audio Serial Interfaces
Each audio bus on the TLV320AIC3262 is very flexible, including left or right-justified data options, support for
I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a
system directly.
Each of the three audio buses of the TLV320AIC3262 can be configured for left or right-justified, I2S, DSP, or
TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the
TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition,
the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible
connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may
be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the
maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-wire
mode, the ADC and DAC paths can operate based on separate word clocks.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number
of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support
the case when multiple TLV320AIC3262s may share the same audio bus. When configuring an audio interface
for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks.
The TLV320AIC3262 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks.
The TLV320AIC3262 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen.
The TLV320AIC3262 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on
a single audio serial data bus. When the audio serial data bus is powered down while configured in master
mode, the pins associated with the interface are put into a 3-state output condition.
By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3262, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word-clock or bit-clocks are used in the system as general-purpose clocks.
For more detailed information see the Application Reference Guide, SLAU309.
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miniDSP
The TLV320AIC3262 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled
to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1145 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. The TLV320AIC3262 features the ability to process a multitude of
algorithms simultaneously. For example, the miniDSPs enable simultaneous noise cancellation, acoustic echo
cancellation, sidetone, equalization filtering, dynamic range compression, conversation recording, user-interface
sound mixing, and other voice enhancement processing at voice-band sampling rates (e.g. 8kHz) and high-
defintion voice sampling rates (e.g. 16kHz). The TLV320AIC3262 miniDSPs also enable advanced DSP sound
enhancement algorithms for an enhanced media experience on a portable audio device.
Software
Software development for the TLV320AIC3262 is supported through TI's comprehensive PurePath Studio
Development Environment. A powerful, easy-to-use tool designed specifically to simplify software development
on the TLV320AIC3xxx miniDSP audio platform. The Graphical Development Environment consists of a library of
common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected
together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.
For more detailed information see the Application Reference Guide, SLAU309.
Asynchronous Sample Rate Conversion (ASRC)
For playing back audio/speech signals at various sampling rates, AIC3262 provides an efficient asynchronous
sampling rate conversion with the combination of a dedicated ASRC coefficient calculator and the DAC miniDSP
engine. The coefficient calculator estimates the audio/speech data input rate versus the DAC playback rate and
feeds the calculated coefficients to the miniDSP, with which it converts the audio/speech data to the DAC
playback rate. The whole process can be configured automatically without the need of any input sampling rate
related information. The input sampling rates as well as the DAC playback rate are not limited to the typical
audio/speech sampling rates. A reliable and efficient handshaking is involved between the miniDSP software and
the coefficient calculator. For detailed information, please refer to the AIC3262 software programming manual.
For more detailed information see the Application Reference Guide, SLAU309.
Power Supply
The TLV320AIC3262 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance and
power consumption. The device has separate power domains for digital IO, digital core, analog core, analog
input, receiver driver, charge-pump input, headphone driver, and speaker drivers. If desired, all of the supplies
(except for the supplies for speaker drivers, which can directly connect to the battery) can be connected together
and be supplied from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied
in the range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core voltages (AVDD1_18, AVDD2_18, AVDD4_18, and AVDD_18) can range from 1.5V to
1.95V. The microphone bias (AVDD3_33) and receiver driver supply (RECVDD_33) voltages can range from
1.65V to 3.6V. The charge-pump input voltage (CPVDD_18) can range from 1.26V to 1.95V, and the headphone
driver supply (HVDD_18) voltage can range from 1.5V to 1.95V. The speaker driver voltages (SLVDD, SRVDD,
and SPK_V) can range from 2.7V to 5.5V.
For more detailed information see the Application Reference Guide, SLAU309.
Device Special Functions
The following special functions are available to support advanced system requirements:
• SAR ADC
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the Application Reference Guide, SLAU309.
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Register Map Summary
Table 12. Summary of Register Map
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 0 0 0x00 0x00 0x00 Page Select Register
0 0 1 0x00 0x00 0x01 Software Reset Register
0 0 2-3 0x00 0x00 0x02- Reserved Registers
0x03
0 0 4 0x00 0x00 0x04 Clock Control Register 1, Clock Input Multiplexers
0 0 5 0x00 0x00 0x05 Clock Control Register 2, PLL Input Multiplexer
0 0 6 0x00 0x00 0x06 Clock Control Register 3, PLL P and R Values
0 0 7 0x00 0x00 0x07 Clock Control Register 4, PLL J Value
0 0 8 0x00 0x00 0x08 Clock Control Register 5, PLL D Values (MSB)
0 0 9 0x00 0x00 0x09 Clock Control Register 6, PLL D Values (LSB)
0 0 10 0x00 0x00 0x0A Clock Control Register 7, PLL_CLKIN Divider
0 0 11 0x00 0x00 0x0B Clock Control Register 8, NDAC Divider Values
0 0 12 0x00 0x00 0x0C Clock Control Register 9, MDAC Divider Values
0 0 13 0x00 0x00 0x0D DAC OSR Control Register 1, MSB Value
0 0 14 0x00 0x00 0x0E DAC OSR Control Register 2, LSB Value
0 0 15-17 0x00 0x00 0x0F- Reserved Registers
0x11
0 0 18 0x00 0x00 0x12 Clock Control Register 10, NADC Values
0 0 19 0x00 0x00 0x13 Clock Control Register 11, MADC Values
0 0 20 0x00 0x00 0x14 ADC Oversampling (AOSR) Register
0 0 21 0x00 0x00 0x15 CLKOUT MUX
0 0 22 0x00 0x00 0x16 Clock Control Register 12, CLKOUT M Divider Value
0 0 23 0x00 0x00 0x17 Timer clock
0 0 24 0x00 0x00 0x18 Low Frequency Clock Generation Control
0 0 25 0x00 0x00 0x19 High Frequency Clock Generation Control 1
0 0 26 0x00 0x00 0x1A High Frequency Clock Generation Control 2
0 0 27 0x00 0x00 0x1B High Frequency Clock Generation Control 3
0 0 28 0x00 0x00 0x1C High Frequency Clock Generation Control 4
0 0 29 0x00 0x00 0x1D High Frequency Clock Trim Control 1
0 0 30 0x00 0x00 0x1E High Frequency Clock Trim Control 2
0 0 31 0x00 0x00 0x1F High Frequency Clock Trim Control 3
0 0 32 0x00 0x00 0x20 High Frequency Clock Trim Control 4
0 0 33-35 0x00 0x00 0x21- Reserved Registers
0x23
0 0 36 0x00 0x00 0x24 ADC Flag Register
0 0 37 0x00 0x00 0x25 DAC Flag Register
0 0 38 0x00 0x00 0x26 DAC Flag Register
0 0 39-41 0x00 0x00 0x27- Reserved Registers
0x29
0 0 42 0x00 0x00 0x2A Sticky Flag Register 1
0 0 43 0x00 0x00 0x2B Interrupt Flag Register 1
0 0 44 0x00 0x00 0x2C Sticky Flag Register 2
0 0 45 0x00 0x00 0x2D Sticky Flag Register 3
0 0 46 0x00 0x00 0x2E Interrupt Flag Register 2
0 0 47 0x00 0x00 0x2F Interrupt Flag Register 3
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 0 48 0x00 0x00 0x30 INT1 Interrupt Control
0 0 49 0x00 0x00 0x31 INT2 Interrupt Control
0 0 50 0x00 0x00 0x32 SAR Control 1
0 0 51 0x00 0x00 0x33 Interrupt Format Control Register
0 0 52-59 0x00 0x00 0x34- Reserved Registers
0x3B
0 0 60 0x00 0x00 0x3C DAC Processing Block and miniDSP Power Control
0 0 61 0x00 0x00 0x3D ADC Processing Block Control
0 0 62 0x00 0x00 0x3E Reserved Register
0 0 63 0x00 0x00 0x3F Primary DAC Power and Soft-Stepping Control
0 0 64 0x00 0x00 0x40 Primary DAC Master Volume Configuration
0 0 65 0x00 0x00 0x41 Primary DAC Left Volume Control Setting
0 0 66 0x00 0x00 0x42 Primary DAC Right Volume Control Setting
0 0 67 0x00 0x00 0x43 Headset Detection
0 0 68 0x00 0x00 0x44 DRC Control Register 1
0 0 69 0x00 0x00 0x45 DRC Control Register 2
0 0 70 0x00 0x00 0x46 DRC Control Register 3
0 0 71 0x00 0x00 0x47 Beep Generator Register 1
0 0 72 0x00 0x00 0x48 Beep Generator Register 2
0 0 73 0x00 0x00 0x49 Beep Generator Register 3
0 0 74 0x00 0x00 0x4A Beep Generator Register 4
0 0 75 0x00 0x00 0x4B Beep Generator Register 5
0 0 76 0x00 0x00 0x4C Beep Sin(x) MSB
0 0 77 0x00 0x00 0x4D Beep Sin(x) LSB
0 0 78 0x00 0x00 0x4E Beep Cos(x) MSB
0 0 79 0x00 0x00 0x4F Beep Cos(x) LSB
0 0 80 0x00 0x00 0x50 Reserved Register
0 0 81 0x00 0x00 0x51 ADC Channel Power Control
0 0 82 0x00 0x00 0x52 ADC Fine Gain Volume Control
0 0 83 0x00 0x00 0x53 Left ADC Volume Control
0 0 84 0x00 0x00 0x54 Right ADC Volume Control
0 0 85 0x00 0x00 0x55 ADC Phase Control
0 0 86 0x00 0x00 0x56 Left AGC Control 1
0 0 87 0x00 0x00 0x57 Left AGC Control 2
0 0 88 0x00 0x00 0x58 Left AGC Control 3
0 0 89 0x00 0x00 0x59 Left AGC Attack Time
0 0 90 0x00 0x00 0x5A Left AGC Decay Time
0 0 91 0x00 0x00 0x5B Left AGC Noise Debounce
0 0 92 0x00 0x00 0x5C Left AGC Signal Debounce
0 0 93 0x00 0x00 0x5D Left AGC Gain
0 0 94 0x00 0x00 0x5E Right AGC Control 1
0 0 95 0x00 0x00 0x5F Right AGC Control 2
0 0 96 0x00 0x00 0x60 Right AGC Control 3
0 0 97 0x00 0x00 0x61 Right AGC Attack Time
0 0 98 0x00 0x00 0x62 Right AGC Decay Time
0 0 99 0x00 0x00 0x63 Right AGC Noise Debounce
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 0 100 0x00 0x00 0x64 Right AGC Signal Debounce
0 0 101 0x00 0x00 0x65 Right AGC Gain
0 0 102 0x00 0x00 0x66 ADC DC Measurement Control Register 1
0 0 103 0x00 0x00 0x67 ADC DC Measurement Control Register 2
0 0 104 0x00 0x00 0x68 Left Channel DC Measurement Output Register 1 (MSB Byte)
0 0 105 0x00 0x00 0x69 Left Channel DC Measurement Output Register 2 (Middle Byte)
0 0 106 0x00 0x00 0x6A Left Channel DC Measurement Output Register 3 (LSB Byte)
0 0 107 0x00 0x00 0x6B Right Channel DC Measurement Output Register 1 (MSB Byte)
0 0 108 0x00 0x00 0x6C Right Channel DC Measurement Output Register 2 (Middle Byte)
0 0 109 0x00 0x00 0x6D Right Channel DC Measurement Output Register 3 (LSB Byte)
0 0 110-114 0x00 0x00 0x6E- Reserved Registers
0x72
0 0 115 0x00 0x00 0x73 I2C Interface Miscellaneous Control
0 0 116-118 0x00 0x00 0x74- Reserved Registers
0x76
0 0 119 0x00 0x00 0x77 miniDSP Control Register 1, Register Access Control
0 0 120 0x00 0x00 0x78 miniDSP Control Register 2, Register Access Control
0 0 121 0x00 0x00 0x79 miniDSP Control Register 3, Register Access Control
0 0 122-126 0x00 0x00 0x7A- Reserved Registers
0x7E
0 0 127 0x00 0x00 0x7F Book Selection Register
0 1 0 0x00 0x01 0x00 Page Select Register
0 1 1 0x00 0x01 0x01 Power Configuration Register
0 1 2 0x00 0x01 0x02 Reserved Register
0 1 3 0x00 0x01 0x03 Left DAC PowerTune Configuration Register
0 1 4 0x00 0x01 0x04 Right DAC PowerTune Configuration Register
0 1 5-7 0x00 0x01 0x05- Reserved Registers
0x07
0 1 8 0x00 0x01 0x08 Common Mode Register
0 1 9 0x00 0x01 0x09 Headphone Output Driver Control
0 1 10 0x00 0x01 0x0A Receiver Output Driver Control
0 1 11 0x00 0x01 0x0B Headphone Output Driver De-pop Control
0 1 12 0x00 0x01 0x0C Receiver Output Driver De-Pop Control
0 1 13-16 0x00 0x01 0x0D- Reserved Registers
0x10
0 1 17 0x00 0x01 0x11 Mixer Amplifier Control
0 1 18 0x00 0x01 0x12 Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control
0 1 19 0x00 0x01 0x13 Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control
0 1 20-21 0x00 0x01 0x14- Reserved Registers
0x15
0 1 22 0x00 0x01 0x16 Lineout Amplifier Control 1
0 1 23 0x00 0x01 0x17 Lineout Amplifier Control 2
0 1 24-26 0x00 0x01 0x18- Reserved
0x1A
0 1 27 0x00 0x01 0x1B Headphone Amplifier Control 1
0 1 28 0x00 0x01 0x1C Headphone Amplifier Control 2
0 1 29 0x00 0x01 0x1D Headphone Amplifier Control 3
0 1 30 0x00 0x01 0x1E Reserved Register
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 1 31 0x00 0x01 0x1F HPL Driver Volume Control
0 1 32 0x00 0x01 0x20 HPR Driver Volume Control
0 1 33 0x00 0x01 0x21 Charge Pump Control 1
0 1 34 0x00 0x01 0x22 Charge Pump Control 2
0 1 35 0x00 0x01 0x23 Charge Pump Control 3
0 1 36 0x00 0x01 0x24 Receiver Amplifier Control 1
0 1 37 0x00 0x01 0x25 Receiver Amplifier Control 2
0 1 38 0x00 0x01 0x26 Receiver Amplifier Control 3
0 1 39 0x00 0x01 0x27 Receiver Amplifier Control 4
0 1 40 0x00 0x01 0x28 Receiver Amplifier Control 5
0 1 41 0x00 0x01 0x29 Receiver Amplifier Control 6
0 1 42 0x00 0x01 0x2A Receiver Amplifier Control 7
0 1 43-44 0x00 0x01 0x2B- Reserved Registers
0x2C
0 1 45 0x00 0x01 0x2D Speaker Amplifier Control 1
0 1 46 0x00 0x01 0x2E Speaker Amplifier Control 2
0 1 47 0x00 0x01 0x2F Speaker Amplifier Control 3
0 1 48 0x00 0x01 0x30 Speaker Amplifier Volume Controls
0 1 49-50 0x00 0x01 0x31- Reserved Registers
0x32
0 1 51 0x00 0x01 0x33 Microphone Bias Control
0 1 52 0x00 0x01 0x34 Input Select 1 for Left Microphone PGA P-Terminal
0 1 53 0x00 0x01 0x35 Input Select 2 for Left Microphone PGA P-Terminal
0 1 54 0x00 0x01 0x36 Input Select for Left Microphone PGA M-Terminal
0 1 55 0x00 0x01 0x37 Input Select 1 for Right Microphone PGA P-Terminal
0 1 56 0x00 0x01 0x38 Input Select 2 for Right Microphone PGA P-Terminal
0 1 57 0x00 0x01 0x39 Input Select for Right Microphone PGA M-Terminal
0 1 58 0x00 0x01 0x3A Input Common Mode Control
0 1 59 0x00 0x01 0x3B Left Microphone PGA Control
0 1 60 0x00 0x01 0x3C Right Microphone PGA Control
0 1 61 0x00 0x01 0x3D ADC PowerTune Configuration Register
0 1 62 0x00 0x01 0x3E ADC Analog PGA Gain Flag Register
0 1 63 0x00 0x01 0x3F DAC Analog Gain Flags Register 1
0 1 64 0x00 0x01 0x40 DAC Analog Gain Flags Register 2
0 1 65 0x00 0x01 0x41 Analog Bypass Gain Flags Register
0 1 66 0x00 0x01 0x42 Driver Power-Up Flags Register
0 1 67-118 0x00 0x01 0x43- Reserved Registers
0x76
0 1 119 0x00 0x01 0x77 Headset Detection Tuning Register 1
0 1 120 0x00 0x01 0x78 Headset Detection Tuning Register 2
0 1 121 0x00 0x01 0x79 Microphone PGA Power-Up Control Register
0 1 122 0x00 0x01 0x7A Reference Powerup Delay Register
0 1 123-127 0x00 0x01 0x7B- Reserved Registers
0x7F
0 3 0 0x00 0x03 0x00 Page Select Register
0 3 1 0x00 0x03 0x01 Reserved Register
0 3 2 0x00 0x03 0x02 Primary SAR ADC Control
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 3 3 0x00 0x03 0x03 Primary SAR ADC Conversion Mode
0 3 4-5 0x00 0x03 0x04- Reserved Registers
0x05
0 3 6 0x00 0x03 0x06 SAR Reference Control
0 3 7-8 0x00 0x03 0x07- Reserved Registers
0x08
0 3 9 0x00 0x03 0x09 SAR ADC Flags Register 1
0 3 10 0x00 0x03 0x0A SAR ADC Flags Register 2
0 3 11-12 0x00 0x03 0x0B- Reserved Registers
0x0C
0 3 13 0x00 0x03 0x0D SAR ADC Buffer Mode Control
0 3 14 0x00 0x03 0x0E Reserved Register
0 3 15 0x00 0x03 0x0F Scan Mode Timer Control
0 3 16 0x00 0x03 0x10 Reserved Register
0 3 17 0x00 0x03 0x11 SAR ADC Clock Control
0 3 18 0x00 0x03 0x12 SAR ADC Buffer Mode Data Read Control
0 3 19 0x00 0x03 0x13 SAR ADC Measurement Control
0 3 20 0x00 0x03 0x14 Reserved Register
0 3 21 0x00 0x03 0x15 SAR ADC Measurement Threshold Flags
0 3 22 0x00 0x03 0x16 IN1L Max Threshold Check Control 1
0 3 23 0x00 0x03 0x17 IN1L Max Threshold Check Control 2
0 3 24 0x00 0x03 0x18 IN1L Min Threshold Check Control 1
0 3 25 0x00 0x03 0x19 IN1L Min Threshold Check Control 2
0 3 26 0x00 0x03 0x1A IN1R Max Threshold Check Control 1
0 3 27 0x00 0x03 0x1B IN1R Max Threshold Check Control 2
0 3 28 0x00 0x03 0x1C IN1R Min Threshold Check Control 1
0 3 29 0x00 0x03 0x1D IN1R Min Threshold Check Control 2
0 3 30 0x00 0x03 0x1E TEMP Max Threshold Check Control 1
0 3 31 0x00 0x03 0x1F TEMP Max Threshold Check Control 2
0 3 32 0x00 0x03 0x20 TEMP Min Threshold Check Control 1
0 3 33 0x00 0x03 0x21 TEMP Min Threshold Check Control 2
0 3 34-53 0x00 0x03 0x22- Reserved Registers
0x35
0 3 54 0x00 0x03 0x36 IN1L Measurement Data (MSB)
0 3 55 0x00 0x03 0x37 IN1L Measurement Data (LSB)
0 3 56 0x00 0x03 0x38 IN1R Measurement Data (MSB)
0 3 57 0x00 0x03 0x39 IN1R Measurement Data (LSB)
0 3 58 0x00 0x03 0x3A VBAT Measurement Data (MSB)
0 3 59 0x00 0x03 0x3B VBAT Measurement Data (LSB)
0 3 60-65 0x00 0x03 0x3C- Reserved Registers
0x41
0 3 66 0x00 0x03 0x42 TEMP1 Measurement Data (MSB)
0 3 67 0x00 0x03 0x43 TEMP1 Measurement Data (LSB)
0 3 68 0x00 0x03 0x44 TEMP2 Measurement Data (MSB)
0 3 69 0x00 0x03 0x45 TEMP2 Measurement Data (LSB)
0 3 70-127 0x00 0x03 0x46- Reserved Registers
0x7F
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 4 0 0x00 0x04 0x00 Page Select Register
0 4 1 0x00 0x04 0x01 Audio Serial Interface 1, Audio Bus Format Control Register
0 4 2 0x00 0x04 0x02 Audio Serial Interface 1, Left Ch_Offset_1 Control Register
0 4 3 0x00 0x04 0x03 Audio Serial Interface 1, Right Ch_Offset_2 Control Register
0 4 4 0x00 0x04 0x04 Audio Serial Interface 1, Channel Setup Register
0 4 5 0x00 0x04 0x05 Audio Serial Interface 1, Multi-Channel Setup Register 1
0 4 6 0x00 0x04 0x06 Audio Serial Interface 1, Multi-Channel Setup Register 2
0 4 7 0x00 0x04 0x07 Audio Serial Interface 1, ADC Input Control
0 4 8 0x00 0x04 0x08 Audio Serial Interface 1, DAC Output Control
0 4 9 0x00 0x04 0x09 Audio Serial Interface 1, Control Register 9, ADC Slot Tristate Control
0 4 10 0x00 0x04 0x0A Audio Serial Interface 1, WCLK and BCLK Control Register
0 4 11 0x00 0x04 0x0B Audio Serial Interface 1, Bit Clock N Divider Input Control
0 4 12 0x00 0x04 0x0C Audio Serial Interface 1, Bit Clock N Divider
0 4 13 0x00 0x04 0x0D Audio Serial Interface 1, Word Clock N Divider
0 4 14 0x00 0x04 0x0E Audio Serial Interface 1, BCLK and WCLK Output
0 4 15 0x00 0x04 0x0F Audio Serial Interface 1, Data Output
0 4 16 0x00 0x04 0x10 Audio Serial Interface 1, ADC WCLK and BCLK Control
0 4 17 0x00 0x04 0x11 Audio Serial Interface 2, Audio Bus Format Control Register
0 4 18 0x00 0x04 0x12 Audio Serial Interface 2, Data Offset Control Register
0 4 19-22 0x00 0x04 0x13- Reserved Registers
0x16
0 4 23 0x00 0x04 0x17 Audio Serial Interface 2, ADC Input Control
0 4 24 0x00 0x04 0x18 Audio Serial Interface 2, DAC Output Control
0 4 25 0x00 0x04 0x19 Reserved Register
0 4 26 0x00 0x04 0x1A Audio Serial Interface 2, WCLK and BCLK Control Register
0 4 27 0x00 0x04 0x1B Audio Serial Interface 2, Bit Clock N Divider Input Control
0 4 28 0x00 0x04 0x1C Audio Serial Interface 2, Bit Clock N Divider
0 4 29 0x00 0x04 0x1D Audio Serial Interface 2, Word Clock N Divider
0 4 30 0x00 0x04 0x1E Audio Serial Interface 2, BCLK and WCLK Output
0 4 31 0x00 0x04 0x1F Audio Serial Interface 2, Data Output
0 4 32 0x00 0x04 0x20 Audio Serial Interface 2, ADC WCLK and BCLK Control
0 4 33 0x00 0x04 0x21 Audio Serial Interface 3, Audio Bus Format Control Register
0 4 34 0x00 0x04 0x22 Audio Serial Interface 3, Data Offset Control Register
0 4 35-38 0x00 0x04 0x23- Reserved Registers
0x26
0 4 39 0x00 0x04 0x27 Audio Serial Interface 3, ADC Input Control
0 4 40 0x00 0x04 0x28 Audio Serial Interface 3, DAC Output Control
0 4 41 0x00 0x04 0x29 Reserved Register
0 4 42 0x00 0x04 0x2A Audio Serial Interface 3, WCLK and BCLK Control Register
0 4 43 0x00 0x04 0x2B Audio Serial Interface 3, Bit Clock N Divider Input Control
0 4 44 0x00 0x04 0x2C Audio Serial Interface 3, Bit Clock N Divider
0 4 45 0x00 0x04 0x2D Audio Serial Interface 3, Word Clock N Divider
0 4 46 0x00 0x04 0x2E Audio Serial Interface 3, BCLK and WCLK Output
0 4 47 0x00 0x04 0x2F Audio Serial Interface 3, Data Output
0 4 48 0x00 0x04 0x30 Audio Serial Interface 3, ADC WCLK and BCLK Control
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SLAS679 –DECEMBER 2011
Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
0 4 49-64 0x00 0x04 0x31- Reserved Registers
0x40
0 4 65 0x00 0x04 0x41 WCLK1 (Input/Output) Pin Control
0 4 66 0x00 0x04 0x42 Reserved Register
0 4 67 0x00 0x04 0x43 DOUT1 (Output) Pin Control
0 4 68 0x00 0x04 0x44 DIN1 (Input) Pin Control
0 4 69 0x00 0x04 0x45 WCLK2 (Input/Output) Pin Control
0 4 70 0x00 0x04 0x46 BCLK2 (Input/Output) Pin Control
0 4 71 0x00 0x04 0x47 DOUT2 (Output) Pin Control
0 4 72 0x00 0x04 0x48 DIN2 (Input) Pin Control
0 4 73 0x00 0x04 0x49 WCLK3 (Input/Output) Pin Control
0 4 74 0x00 0x04 0x4A BCLK3 (Input/Output) Pin Control
0 4 75 0x00 0x04 0x4B DOUT3 (Output) Pin Control
0 4 76 0x00 0x04 0x4C DIN3 (Input) Pin Control
0 4 77-81 0x00 0x04 0x4D- Reserved Registers
0x51
0 4 82 0x00 0x04 0x52 MCLK2 (Input) Pin Control
0 4 83-85 0x00 0x04 0x53- Reserved Registers
0x55
0 4 86 0x00 0x04 0x56 GPIO1 (Input/Output) Pin Control
0 4 87 0x00 0x04 0x57 GPIO2 (Input/Output) Pin Control
0 4 88-90 0x00 0x04 0x58- Reserved Registers
0x5A
0 4 91 0x00 0x04 0x5B GPI1 (Input) Pin Control
0 4 92 0x00 0x04 0x5C GPI2 (Input) Pin Control
0 4 93-95 0x00 0x04 0x5D- Reserved Registers
0x5F
0 4 96 0x00 0x04 0x60 GPO1 (Output) Pin Control
0 4 97-100 0x00 0x04 0x61- Reserved Registers
0x64
0 4 101 0x00 0x04 0x65 Digital Microphone Input Pin Control
0 4 102-117 0x00 0x04 0x66- Reserved Registers
0x75
0 4 118 0x00 0x04 0x76 miniDSP Data Port Control
0 4 119 0x00 0x04 0x77 Digital Audio Engine Synchronization Control
0 4 120-127 0x00 0x04 0x78- Reserved Registers
0x7F
0 252 0 0x00 0xFC 0x00 Page Select Register
0 252 1 0x00 0xFC 0x01 SAR Buffer Mode Data (MSB) and Buffer Flags
0 252 2 0x00 0xFC 0x02 SAR Buffer Mode Data (LSB)
0 252 3-127 0x00 0xFC 0x03- Reserved Registers
0x7F
20 0 0 0x14 0x00 0x00 Page Select Register
20 0 1-126 0x14 0x00 0x01- Reserved Registers
0x7E
20 0 127 0x14 0x00 0x7F Book Selection Register
20 1-26 0 0x14 0x01- 0x00 Page Select Register
0x1A
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
20 1-26 1-7 0x14 0x01- 0x01- Reserved Registers
0x1A 0x07
20 1-26 8-127 0x14 0x01- 0x08- ADC Fixed Coefficients C(0:767)
0x1A 0x7F
40 0 0 0x28 0x00 0x00 Page Select Register
40 0 1 0x28 0x00 0x01 ADC Adaptive CRAM Configuration Register
40 0 2-126 0x28 0x00 0x02- Reserved Registers
0x7E
40 0 127 0x28 0x00 0x7F Book Selection Register
40 1-17 0 0x28 0x01- 0x00 Page Select Register
0x11
40 1-17 1-7 0x28 0x01- 0x01- Reserved Registers
0x11 0x07
40 1-17 8-127 0x28 0x01- 0x08- ADC Adaptive Coefficients C(0:509)
0x11 0x7F
40 18 0 0x28 0x12 0x00 Page Select Register
40 18 1-7 0x28 0x12 0x01- Reserved Registers
0x07
40 18 8-15 0x28 0x12 0x08- ADC Adaptive Coefficients C(510:511)
0x0F
40 18 16-127 0x28 0x12 0x10- Reserved Registers
0x7F
60 0 0 0x3C 0x00 0x00 Page Select Register
60 0 1-126 0x3C 0x00 0x01- Reserved Registers
0x7E
60 0 127 0x3C 0x00 0x7F Book Selection Register
60 1-35 0 0x3C 0x01- 0x00 Page Select Register
0x23
60 1-35 1-7 0x3C 0x01- 0x01- Reserved Registers
0x23 0x07
60 1-35 8-127 0x3C 0x01- 0x08- DAC Fixed Coefficients C(0:1023)
0x23 0x7F
80 0 0 0x50 0x00 0x00 Page Select Register
80 0 1 0x50 0x00 0x01 DAC Adaptive Coefficient Bank #1 Configuration Register
80 0 2-126 0x50 0x00 0x02- Reserved Registers
0x7E
80 0 127 0x50 0x00 0x7F Book Selection Register
80 1-17 0 0x50 0x01- 0x00 Page Select Register
0x11
80 1-17 1-7 0x50 0x01- 0x01- Reserved Registers
0x11 0x07
80 1-17 8-127 0x50 0x01- 0x08- DAC Adaptive Coefficient Bank #1 C(0:509)
0x11 0x7F
80 18 0 0x50 0x12 0x00 Page Select Register
80 18 1-7 0x50 0x12 0x01- Reserved Registers
0x07
80 18 8-15 0x50 0x12 0x08- DAC Adaptive Coefficient Bank #1 C(510:511)
0x0F
80 18 16-127 0x50 0x12 0x10- Reserved Registers
0x7F
82 0 0 0x52 0x00 0x00 Page Select Register
82 0 1 0x52 0x00 0x01 DAC Adaptive Coefficient Bank #2 Configuration Register
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SLAS679 –DECEMBER 2011
Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
82 0 2-126 0x52 0x00 0x02- Reserved Registers
0x7E
82 0 127 0x52 0x00 0x7F Book Selection Register
82 1-17 0 0x52 0x01- 0x00 Page Select Register
0x11
82 1-17 1-7 0x52 0x01- 0x01- Reserved Registers
0x11 0x07
82 1-17 8-127 0x52 0x01- 0x08- DAC Adaptive Coefficient Bank #2 C(0:509)
0x11 0x7F
82 18 0 0x52 0x12 0x00 Page Select Register
82 18 1-7 0x52 0x12 0x01- Reserved Registers
0x07
82 18 8-15 0x52 0x12 0x08- DAC Adaptive Coefficient Bank #2 C(510:511)
0x0F
82 18 16-127 0x52 0x12 0x10- Reserved Registers
0x7F
100 0 0 0x64 0x00 0x00 Page Select Register
100 0 1-47 0x64 0x00 0x01- Reserved Registers
0x2F
100 0 48 0x64 0x00 0x30 ADC miniDSP_A Instruction Control Register 1
100 0 49 0x64 0x00 0x31 ADC miniDSP_A Instruction Control Register 2
100 0 50 0x64 0x00 0x32 ADC miniDSP_A Decimation Ratio Control Register
100 0 51-56 0x64 0x00 0x33- Reserved Registers
0x38
100 0 57 0x64 0x00 0x39 ADC miniDSP_A Instruction Control Register 3
100 0 58 0x64 0x00 0x3A ADC miniDSP_A ISR Interrupt Control
100 0 59-126 0x64 0x00 0x3B- Reserved Registers
0x7E
100 0 127 0x64 0x00 0x7F Book Selection Register
100 1-52 0 0x64 0x01- 0x00 Page Select Register
0x34
100 1-52 1-7 0x64 0x01- 0x01- Reserved Registers
0x34 0x07
100 1-52 8-127 0x64 0x01- 0x08- miniDSP_A Instructions
0x34 0x7F
120 0 0 0x78 0x00 0x00 Page Select Register
120 0 1-47 0x78 0x00 0x01- Reserved Registers
0x2F
120 0 48 0x78 0x00 0x30 DAC miniDSP_D Instruction Control Register 1
120 0 49 0x78 0x00 0x31 DAC miniDSP_D Instruction Control Register 2
120 0 50 0x78 0x00 0x32 DAC miniDSP_D Interpolation Factor Control Register
120 0 51-56 0x78 0x00 0x33- Reserved Registers
0x38
120 0 57 0x78 0x00 0x39 DAC miniDSP_D Instruction Control Register 3
120 0 58 0x78 0x00 0x3A DAC miniDSP_D ISR Interrupt Control
120 0 59-126 0x78 0x00 0x3B- Reserved Registers
0x7E
120 0 127 0x78 0x00 0x7F Book Selection Register
120 1-103 0 0x78 0x01- 0x00 Page Select Register
0x67
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SLAS679 –DECEMBER 2011
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Table 12. Summary of Register Map (continued)
Decimal Hex DESCRIPTION
BOOK PAGE REG. BOOK PAGE REG.
NO. NO. NO. NO. NO. NO.
120 1-103 1-7 0x78 0x01- 0x01- Reserved Registers
0x67 0x07
120 1-103 8-127 0x78 0x01- 0x08- miniDSP_D Instructions
0x67 0x7F
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV320AIC3262IYZFR ACTIVE DSBGA YZF 81 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TLV320AIC3262IYZFT ACTIVE DSBGA YZF 81 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV320AIC3262IYZFR DSBGA YZF 81 2500 330.0 12.4 5.04 5.07 0.75 8.0 12.0 Q1
TLV320AIC3262IYZFT DSBGA YZF 81 250 330.0 12.4 5.04 5.07 0.75 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC3262IYZFR DSBGA YZF 81 2500 367.0 367.0 35.0
TLV320AIC3262IYZFT DSBGA YZF 81 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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