BR34E02FVT-3E2 - ROHM Co., Ltd. - searchdatasheet.com

Datashee

t

○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays

1/30 TSZ02201-0R2R0G100520-1-2

31.May.2013 Rev .003

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Serial EEPROM Series Standard EEPROM

Plug & Play EEPROM

BR34E02-3

General Description

BR34E02-3 is 256×8 bit Electrically Erasable PROM (Based on Serial Presence Detect)

Features

 256×8 bit Architecture Serial EEPROM

 Wide Operating Voltage Range: 1.7V to 5.5V

 Two-Wire Serial Interface

 Self-Timed Erase and Write Cycle

 Page Write Function (16byte)

 Write Protect Mode

¾ Settable Reversible Write Protect Function : 00h-7Fh

¾ Write Protect 1 (Onetime Rom) : 00h-7Fh

¾ Write Protect 2 (Hardwire WP PIN) : 00h-FFh

 Low Power consumption

¾ Write (at 1.7V) : 0.4mA (typ)

¾ Read (at 1.7V) : 0.1mA (typ)

¾ Standby (at 1.7V) : 0.1µA (typ)

 Prevention of Write Mistake

¾ Write Protect Feature (WP pin)

¾ Prevention of Write Mistake at Low Voltage

 High Reliability Fine Pattern CMOS Technology

 More than 1 million write cycles

 More than 40 years data retention

 Noise Reduction Filtered Inputs in SCL / SDA

 Initial delivery state FFh

Packages W(Typ) x D(Typ) x H(Max)

BR34E02-3

Capacity Bit Format Type Power Source

Voltage Package

2Kbit 256x8

BR34E02FVT-3 1.7V to 5.5V TSSOP-B8

BR34E02NUX-3 VSON008X2030

Absolute Maximum Ratings (Ta=25℃)

Parameter Symbol Rating Unit Remark

Supply Voltage VCC -0.3 to +6.5 V

Power Dissipation Pd 330 (TSSOP-B8) mW Derate by 3.3mW/°C when operating above Ta=25°C

300 (VSON008X2030) Derate by 3.0mW/°C when operating above Ta=25°C

Storage Temperature Tstg -65 to +125 ℃

Operating Temperature Topr -40 to +85 ℃

Input Voltage / Output

Voltage (A0) - -0.3 to 10.0 V

Input Voltage / Output

Voltage (others) - -0.3 to VCC+1.0 V

Electrostatic discharge

voltage

(human body model) VESD -4000 to +4000 V

Memory Cell Characteristics (Ta=25℃, VCC=1.7V to 5.5V)

Parameter Limit Unit

Min Typ Max

Write / Erase Cycle (1) 1,000,000 - - Times

Data Retention(1) 40 - - Years

(1) Not 100% TESTED

TSSOP-B8

3.00mm x 6.40mm x 1.20mm

V

SON008X2030

2.00mm x 3.00mm x 0.60mm

Datasheet

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BR34E02-3

Recommended Operating Ratings

Parameter Symbol Rating Unit

Supply Voltage VCC 1.7 to 5.5 V

Input Voltage VIN 0 to VCC V

DC Characteristics (Unless othe rwise specified Ta=-40℃ to +85℃, VCC =1.7V to 5.5V)

Parameter Symbol Limit Unit Test Conditions

Min Typ Max

Input High Voltage VIH 0.7 VCC - Vcc+1.0 V

Input Low Voltage VIL -0.3 - 0.3 VCC V

Output Low Voltage 1 VOL1 - - 0.4 V IOL=2.1mA, 2.5V≦VCC≦5.5V(SDA)

Output Low Voltage 2 VOL2 - - 0.2 V IOL=0.7mA, 1.7V≦VCC＜2.5V(SDA)

Input Leakage Current 1 ILI1 -1 - 1 µA VIN=0V to VCC (A0, A1, A2, SCL)

Input Leakage Current 2 ILI2 -1 - 15 µA VIN=0V to VCC (WP)

Input Leakage Current 3 ILI3 -1 - 20 µA VIN=VHV(A0)

Output Leakage Current ILO -1 - 1 µA VOUT=0V to VCC

Supply Current (Write) ICC1 - - 2.0 mA

VCC =5.5V, fSCL=400kHz, tWR=5ms

Byte Write

Page Write

Write Protect

Supply Current (Read) ICC2 - - 0.5 mA

VCC =5.5V, fSCL=400kHz

Random Read

Current Read

Sequential Read

Standby Current ISB - - 2.0 µA

VCC =5.5V, SDA, SCL= VCC

A0, A1, A2=GND, WP=GND

A0 HV Voltage VHV 7 - 10 V VHV-VCC≧4.8V

AC Characteristics (Unless othe rwise specified Ta=-40℃ to +85℃, VCC =1.7V to 5.5V)

Parameter Symbol Limit Unit

Min Typ Max

Clock Frequency fSCL - - 400 kHz

Data Clock High Period tHIGH 0.6 - - µs

Data Clock Low Period tLOW 1.2 - - µs

SDA and SCL Rise Time( 1) tR - - 0.3 µs

SDA and SCL Fall Time(1) t

F - - 0.3 µs

Start Condition Hold Time tHD:STA 0.6 - - µs

Start Condition Setup Time tSU:STA 0.6 - - µs

Input Data Hold Time tHD:DAT 0 - - ns

Input Data Setup Time tSU:DAT 100 - - ns

Output Data Delay Time tPD 0.1 - 0.9 µs

Output Data Hold Time tDH 0.1 - - µs

Stop Condition Setup Time tSU:STO 0.6 - - µs

Bus Free Time tBUF 1.2 - - µs

Write Cycle Time tWR - - 5 ms

Noise Spike Width

(SDA and SCL) tI - - 0.1 µs

WP Hold Time tHD:WP 0 - - µs

WP Setup Time tSU:WP 0.1 - - µs

WP High Period tHIGH:WP 1.0 - - µs

(1) Not 100% TESTED

Datasheet

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BR34E02-3

SDA

SCL

D0 ACK

STOP

CONDITION

START

CONDITION

tWR

WRITE DATA(n)

Figure 1-(a). Serial Input / Output Timing

Figure 1-(b). Start/Stop Bit Timing

○SDA data is latched into the chip at the rising edge of SCL clock.

○Output data toggles at the falling edge of SCL clock.

Fi

g

ure 1-

(

d

)

.WP Timin

g

of the Write O

p

eration

Figure 1-(e). WP Timing of the Write Cancel Operation

○For WRITE operation, WP must be "Low" from the rising edge of the

clock (which takes in D0 of first byte) until the end of tWR. (See Figure

1-(d) ) During this period, WRITE operation can be canceled by setting

WP "High".（See Figure 1-(e)）

○When WP is set to "High" during tWR, WRITE operation is immediately

ceased, making the data unreliable. It must then be re-written.

SDA

(IN)

SCL

SDA

(OUT)

tHD:STA tHD:DATtSU:DAT

tBUF t

PD t

DH

tLOW

tHIGH tR tF

SDA

SCL

tSU:STA tSU:STO tHD:STA

START BIT STOP BI

T

Figure 1-(c). Write Cycle Timing

Serial Input / Output Timing

tWR

t

HIGH : WP

DATA(n)

DATA(1)

D1 ACK ACK

D0

SDA

SCL

WP

tWR

DATA(n)

D1 ACK

D0

STOP CONDITION

SDA

tHD：WP

ACK

DATA(1)

tSU：WP

SCL

WP

Datasheet

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BR34E02-3

Block Diagram

Pin Configuration

Pin Descriptions

Pin Name Input/Output Descriptions

VCC - Power supply

GND - Ground 0V

A0, A1, A2 IN Slave address set(1)

SCL IN Serial clock input

SDA IN / OUT Slave and word address(2)

Serial data input, serial data output

WP IN Write protect input(3)

(1) A0, A1 and A2 are not allowed to use as open.

(2) Open drain output requires a pull-up resistor.

(3) WP Pin has a Pull-Down resistor. Please leave unconnected or connect to GND when not in use.

(TOP VIEW)

8

7

6

5

1

2

3

4

VCC

WP

SCL

SDA

A

0

A

1

A

2

GND

BR34E02-3

8

7

6

5 4

3

2

1

SDA

SCL

WP

VCC

GND

A2

A1

A0

ADDRESS

DECODER SLAVE , W OR D

ADDRESS DATA

REGISTE

CONTOROL LOGIC

HIGH VOLTAGE VCC LEVEL DETECT

8bit

ACK

START STOP

PROTECT_MEM ORY_ARRAY

2Kbit_M EM OR Y_A RR AY VCC

Datasheet

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BR34E02-3

Figure 4. Output Low Voltage1 vs Output Low Current

(Vcc=2.5V)

Figure 5. Output Low Voltage2 vs Output Lo

w

Current

(Vcc=1.7V)

Figure 2. Input High Voltage vs Supply Voltage

(A0, A1, A2, SCL, SDA, WP)

Figure 3. Input Low Voltage vs Supply Voltage

(A0, A1, A2, SCL, SDA, WP)

Typical Performance Curves

Output Low Voltage1: VOL1(V)

Out

p

ut Low Current: IOL

(

mA

)

Output Low Voltage2: VOL2(V)

Out

p

ut Low Current: IOL

(

mA

)

VIH

(

V

)

Input High Voltage: VIH(V)

Supply Voltage : VCC(V)

VIL

(

V

)

Input Low Voltage: VIL(V)

Supply Voltage : VCC(V)

Datasheet

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BR34E02-3

Figure 9. Supply Current (WRITE) vs Supply Voltage

(fSCL=400kHz)

Figure 8. Output Leakage Current vs Supply Voltage

(SDA)

Figure 6. Input Leakage Current1 vs Supply Voltage

(A0, A1, A2, SCL)

Figure 7. Input Leakage Current2 vs Supply Voltage

(WP)

Typical Performance Curves‐Continued

ILI1

(

uA

)

INPUT LEA

K

AGE CURRENT1 : I

LI

1

(

uA

)

Supply Voltage : VCC(V)

Input Leakage Current1: ILI1(µA)

INPUT LEA

K

AGE CURRENT2 : I

LI2

(

uA

)

SUPPLY VOLTAGE : Vcc

(

V

)

Supply Voltage : VCC(V)

Input Leakage Current2: ILI2(µA)

OUTPUT LEA

K

AGE CURRENT: I

L

O

(

uA

)

Supply Voltage : VCC(V)

Output Leakage Current: ILO(µA)

SUPPLY CURRENT

(

WRITE

)

: Icc1

(

mA

)

Supply Voltage : VCC(V)

Supply Current (WRITE): ICC1(mA)

Datasheet

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BR34E02-3

Figure 12. Clock Fr equency vs Supply Voltage

Figure 13. Data Clock High Period vs Supply Voltage

Figure 10. Suppl

y

Current (READ) vs Supply Voltage

(fSCL=400kHz)

Figure 11. Standby Current vs Supply Voltage

Typical Performance Curves‐Continued

SUPPLY CURRENT

(

READ

)

: Icc2

(

mA

)

Supply Current (READ): ICC2(mA)

Supply Voltage : VCC(V) Supply Voltage : VCC(V)

Standby Current: ISB(µA)

Supply Voltage : VCC(V)

Clock Frequency: fSCL(KHz)

DATA CLK H TIME : tHIGH (us)

Supply Voltage : VCC(V)

Data Clock High Period: tHIGH(µs)

Datasheet

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BR34E02-3

Figure 16. Start Condition Setup Time vs Supply Voltage Figure 17. Input Data Hold Time vs Supply Voltage

(HIGH)

Typical Performance Curves‐Continued

START CONDITION

SET UP TIME : tSU:STA (us)

INPUT DATA HOLD TIME : tHD:DAT

(

ns

)

Figure 14. Data Clock Low Period vs Supply Voltage

Figure 15. Start Condition Hold Time vs Supply Voltage

Supply Voltage : VCC(V)

Data Clock Low Period: tLOW(µs)

Supply Voltage : VCC(V)

Start Condition Hold Time: tHD:STA(µs)

Supply Voltage : VCC(V)

Start Condition Setup Time

:

t

SU

:STA

(

µ

s

)

Supply Voltage : VCC(V)

Input Data Hold Time: tHD:DAT(ns)

Datasheet

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BR34E02-3

Figure 18. Input Data Hold Time vs Supply Voltage

(LOW)

Figure 19. Input Data Setup Time vs Supply Voltage

(HIGH)

Figure 20. Input Data Setup Time vs Supply Voltage

(LOW) Figure 21. Low Output Data Delay Time vs Supply Voltage

Typical Performance Curv es‐Continued

Supply Voltage : VCC(V)

Input Data Setup Time: tSU:DAT(ns)

Supply Voltage : VCC(V)

Input Data Hold Time: tHD:DAT(ns)

Supply Voltage : VCC(V)

Input Data Setup Time: tSU:DAT(ns)

Supply Voltage : VCC(V)

Low Output Data Delay Time: tPD(µs)

Datasheet

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BR34E02-3

Figure 24. Bus Free Time vs Supply Voltage

Figure 25. Write Cycle Time vs Supply Voltage

Figure 22. High Output Da

t

a Delay Time vs Suppl y Vo ltage

Figure 23. Stop Condition Setup Time vs Supply Voltage

Typical Performance Curv es‐Continued

STOP CONDITION SETUP TIME : tSU:STO

(

us

)

Supply Voltage : VCC(V)

High Output Data Delay Time: tPD(µs)

Supply Voltage : VCC(V)

Stop Condition Setup Time: tSU:STO(µs)

Supply Voltage : VCC(V)

Bus Free Time: tBUF(µs)

Supply Voltage : VCC(V)

Write Cycle Time: tWR(ms)

Datasheet

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BR34E02-3

Figure 28. Noise Spike Width vs Supply Voltage

(SDA H)

Figure 29. Noise Spike Width vs Supply Voltage

(SDA L)

Figure 26. Noise Spike Width vs Supply Voltage

(SCL H)

Figure 27. Noise Spike Width vs Supply Voltage

(SCL L)

Typical Performance Curv es‐Continued

Supply Voltage : VCC(V)

Noise Spike Width(SCL H): tl(µs)

Supply Voltage : VCC(V)

Noise Spike Wi dth(SCL L): tl(µs)

Supply Voltage : VCC(V)

Noise Spike Width(SDA H): tl(µs)

NOISE REDUCTION

EFFECTIVE TIME : Tl(SD

A

L)(us)

Supply Voltage : VCC(V)

Noise Spike Wi dth(SDA L): tl(µs)

Datasheet

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BR34E02-3

Figure 30. WP Hold Time vs Supply Voltage

Figure 31. WP Setup Time vs Supply Voltage

Figure 32. WP High Period vs Supply Voltage

Typical Performance Curv es‐Continued

Supply Voltage : VCC(V)

WP Hold Time: tHD:WP(µs)

WP SETUP TIME : tSU:WP (us)

Supply Voltage : VCC(V)

WP Setup Time: tSU:WP(µs)

Supply Voltage : VCC(V)

WP High Period: tHIGH:WP(µs)

Datasheet

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BR34E02-3

Timing Chart

1. I2C BUS Data Communication

I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,

and acknowledge is al ways required after ea ch byte. I2C BUS data comm unication with several devic es is possib le by

connecting with 2 communication lines: serial data (SDA) and serial clock (SCL).

Among the devices, there should be a “master” that generates clock and control communication start and end. The

rest become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that

outputs data to the bus during data communication is called “transmitter”, and the device that receives data is called

“receiver”.

2. START Condition (START bit Recognition)

(1) Before executing eac h command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL i s

‘HIGH' is necessary.

(2) This IC always d etects wh ether SDA a nd SCL are in start condition (start bit) or not, therefore, unless this condition

is satisfied, any command cannot be executed.

3. STOP Condition (STOP bit Recognitio n)

(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is

'HIGH'. (See Figure 1-(b) START/STOP Bit Timing)

4. Write Protect By Soft Ware

(1) Set Write Protect command and permanent set Write Protect command set data of 00h to 7Fh in 256 words write

protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect

command. Cancel of write protection block which is set by permanent set Write Protect command at once is

impossibility. When these commands are carried out, WP pin must be OPEN or GND.

5. Acknowledge

(1) Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS

after transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the

µ-COM. When outputting the data during read operation, th e Transmitter is the EEPROM.

(2) During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been

received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When

outputting the data during read operation the receiver is the µ-COM.)

(3) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).

(4) In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word

(word address and write data).

(5) In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an

Acknowledge.

(6) If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit

the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP

condition before returning to standby mode.

6. Device Addressing

Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits

of the slave address are the “device type indentifier.” For this EEPROM it is “1010.” (For WP register access this

code is "0110". ) The next three bits identif y the specif ied device on the BUS (device a ddress). The devic e address is

defined by the state of the A0,A1 and A2 input pins. T his IC works only when the device address input from the SDA

pin corresponds to the status of the A0,A1 and A2 input pins. Using this address sc heme allows up to eight devices

to be connected to the BUS. The last bit of the stream (R/W…READ/WRITE) determines the operation to be

performed.

R/W=0 ････ WRITE (including word address input of Random Read)

R/W=1 ････ READ

Datasheet

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BR34E02-3

Slave Address Set Pin Device Type Device Address Read Write Mode Access Area

A2 A1 A0 1010 A2 A1 A0 W/R 2kbit Access to Memor y

A2 A1 A0

0110

A2 A1 A0 W/R Access to Permanent Set Write

Protect Memory

GND GND VHV 0 0 1 W/R Access to Set Write Protect Memroy

GND VCC VHV 0 1 1 W/R Access to Clear Write Protect Memory

7. Write Protect Pin (WP)

When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level),

it is enable to write 256 words (all address).

If permanent protection is done by Write Protect command, lower half area (00 to 7Fh address) is inhibited writing

regardless of WP pin state.

WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use.

8. Confirm Write Protect Resistor by ACK

According to state of Write Protect Resistor, ACK is as follows.

State of Write

Protect Register WP

Input Input Command ACK Address ACK Data ACK Write

Cycle(tWR)

In case,

protect by PSWP - PSWP,SWP,CWP No ACK - No ACK - No ACK No

Page or Byte Write

(00 to 7Fh) ACK WA7 to WA0 ACK D7 to D0 No ACK No

In case,protect by

SWP

0

SWP No ACK - No ACK - No ACK No

CWP ACK - ACK - ACK Yes

PSWP ACK - ACK - ACK Yes

Page or Byte Write

(00 to 7Fh) ACK WA7 to WA0 ACK D7 to D0 No ACK No

1

SWP No ACK - No ACK - No ACK No

CSP ACK - ACK - No ACK No

PSWP ACK - ACK - No ACK No

Page or Byte Write ACK WA7 to WA0 ACK D7 to D0 No ACK No

In case,

Not protect

0 PSWP, SWP, CWP ACK - ACK - ACK Yes

Page or Byte Write ACK WA7 to WA0 ACK D7 to D0 ACK Yes

1 PSWP, SWP, CWP ACK - ACK - No ACK No

Page or Byte Write ACK WA7 to WA0 ACK D7 to D0 No ACK No

Acknowledge when writing data or defining the write-protection (instructions with R/W bit=0) - is Don’t Care

State of Write Protect Register Command ACK Address ACK Data ACK

In case, protect by PSWP PSWP, SWP, CWP No ACK - No ACK - No ACK

In case, protect by SWP

SWP No ACK - No ACK - No ACK

CWP ACK - No ACK - No ACK

PSWP ACK - No ACK - No ACK

Case, Not protect PSWP, SWP, CWP ACK - No ACK - No ACK

Acknowledge when reading data the write-prot ection (instructions with R/W bit=1)

Datasheet

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BR34E02-3

Command

1. Write Cycle

During WRITE CYCLE operation data is written in the EEPROM . The Byte Write Cycle is used to write only one byte.

In the case of writing conti nuous data consisting of more than one b yte, Page Write is used. The maximum bytes th at

can be written at one time is 16 bytes.

(1) With this command the data is programmed into the indicated word address.

(2) When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory

array.

(3) Once programming is started no commands are accepted for tWR (5ms max).

(4) This device is capable of 16-byte Page Write operations.

(5) If the Master transmits more than 16 words prior to generating the STOP condition, the address counter will “roll

over” and the previously transm itted data will be overwritten. When t wo or more byte of data are input, the four low

order address bits are interna lly increment ed by one after the receipt of ea ch word, while the four higher order bits

of the address (WA7 to WA4) remain co nstant.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS(n) DATA(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+15)

A

C

K

SLAVE

ADDRESS

100

1A0A1A2 WA

7D0D7 D0

WA

0

A1A2 WA

7D7

1100

W

R

I

T

E

S

T

A

R

T

R

/

W

S

T

O

P

WORD

ADDRESS DAT

A

SLAVE

ADDRESS

A0 WA

0D0

A

C

K

SDA

LINE

A

C

K

A

C

K

Figure 33. Byte Write Cycle Timing

Figure 34. Page Write Cycle Timing

Datasheet

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BR34E02-3

2. Read Cycle

During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle

and Current Read Cycle. T he Random Read Cycle reads the data in the indicated address.

The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the

Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With

the Sequential Read Cycle it is possible to continuously read the next data.

(1) Random Read operation allows the Master to access any memory location indicated by word address.

(2) In cases where the previous operati on is Random or Current Read ( which includes Sequential Read), the internal

address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of

the next word address (n+1).

(3) If an Acknowledge is detected and no STOP condition is generated by the Master (µ-COM), the device will

continue to transmit data. (It can transmit all data (2kbit 256word))

(4) If an Acknowledge is not detected, the device will terminat e further data transmissions and await a STOP condition

before returning to standby mode.

(5) If an Ackno wledge is detected with the "Low" level (not "High " level), the command will become Sequential Read,

and the next data will be transmitted. T herefore, the Read command is not terminate d. In order to terminate Read

input Acknowledge with "High" always, then input a STOP condition.

It is necessary to input

“High” at last ACK timing.

A1A2 D71100

R

E

A

D

S

T

A

R

T

R

/

W

S

T

O

P

DAT

A

SDA

LINE

SLAVE

ADDRESS

A0 D0

A

C

K

A

C

K

Figure 36. Current Read Cycle Timing

It is necessary to input

“High” at last ACK timing.

Figure 35. Random Read Cycle Timing

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS(n)

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10 01A0A1A2 WA

7A0 D0

SLAVE

ADDRESS

10 0

1A1A2

S

T

A

R

T

D7

R

/

W

R

E

A

D

WA

0

Figure 37. Sequential Read C ycle Timing（With Current Read）

R

E

A

D

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

DATA(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+x)

A

C

K

SLAVE

ADDRESS

10 0

1A0A1A2 D0D7 D0D7

It is necessary to

input “High” at

last ACK timing.

Datasheet

17/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

3. Write Protect Cycle

(1) Permanent Set Write Protect Cycle

(a) Permanent set Write Protect command set data of 00h to 7Fh in 256 words write protection block. Cancel of

write protection block which is set b y permanent set Write Protect command at once is impossibility. When

these commands are carried out, WP pin must be OPEN or GND.

(b) Permanent Set Write Protect command needs tWR from stop condition same as Byte Write and Page Write,

during tWR, input command is canceled.

(c) Refer to Page14 about reply of ACK in each protect state.

(2) Set Write Protect Cycle

(a) Set Write Protect command set data of 00h to 7Fh in 256 words write protection block. Clear Write Protect

command can cancel write protection block which is set by set write Protect command. When these

commands are carried out, WP pin must be OPEN or GND.

(b) Set write Protect command needs tWR from stop condition same as Byte Write and Page Write, during tWR,

input command is canceled.

(c) Refer to Page14 about reply of ACK in each protect state.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS

SDA

LINE

A

C

K

DATA

A

C

K

SLAVE

ADDRESS

10 0

1A0 A1 A2 * ** *

WP

*:DO N’T CARE

Figure 38. Permanent Set Write Protect Cycle

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS

SDA

LINE

A

C

K

DATA

A

C

K

SLAVE

ADDRESS

100 11 0 0 * ** *

WP

*:DO N’T CARE

Figure 39. Set Write Protect Cycle

Datasheet

18/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

(3) Clear Write Protect Cycle

(a) Clear Write Protect command can cancel write protection block which is set by set write Protect command.

When these commands are carried out, WP pin must be O PEN or GND.

(b) Clear W rite Protect command needs tWR from stop condition same as Byte Write and Page Wr ite, during tWR,

input command is canceled.

(c) Refer to Page14 about reply of ACK in each protect state.

Sof tware Reset

Software reset is executed to avoid malfunction after power on and during command input. Software reset has several

kinds and 3 kinds of them are sho wn in the figure belo w. (Refer to Figure 41.-(a), F igure 41.-(b), and Figure 41.-(c).) Within

the dummy clock input area, the SDA bus is released (' H' by pull up) and ACK output and read data '0' (both 'L' level) ma y

be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to

instantaneous power failure of system power source or influence upon devices.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS

SDA

LINE

A

C

K

DATA

A

C

K

SLAVE

ADDRESS

100 11 1 0 * ** *

WP

*:DO N’T CARE

Figure 40. Clear Write Protect Cycle

* COMMAND start s with start condition.

Figure 41-(a). DUMMY CLOCK x 14 + START + START

Figure 41-(c). START x 9

Figure 41-(b). START + DUMMY CLOCK x 9 + START

COMMAND

1 2 13

14

SCL

SD

DUMMY CLOCK x 14 START x 2

COMMAND

SDA

COMMAND

SCL

SD

2

1 8 9

DUMMY CLOCK x 9 START

START

COMMAND

SDA

SCL

SD

タト

1 2 3 8 9

7 COMMAND

COMMAND

START x 9

SDA

Datasheet

19/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Acknowledge Polling

During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic

write execution after write cycle input, next command (slave addr ess) is sent. If the first ACK signal sends back 'L', then it

means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge

polling, next command can be exec uted without waiting for tWR = 5ms.

To write continuously, W/R = 0, then to carry out current read cycle after write, slave address with W/R = 1 is sent. If

ACK signal sends back 'L', and then execute word address input and data output and s o forth.

WP Effe ctive Timing

WP is usually fixed to 'H' or 'L' , but when WP is used to canc el write cycle a nd so on, obse rve the following WP valid timing.

During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write

cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of data(in

page write cycle, the first byte data) is the cancel invalid area.

WP input in this area becomes ‘Don't care’. The area from the rise of SCL to take in D0 to the stop condition input is the

cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status..

Figure 43. WP Effective Timing

Figure 42. Case of Continuous Write by Acknowledge Polling

WP cancellation invalid period

No data will be written

・The rising edge of the clock

which take in D0

SCL

D0

A

CK

A

N ENLARGEMENT

SCL

SDA

AN ENLARGEMENT

A

CK

D0

・The rising edge

・of SDA

SDA

WP

WP cancellation

effective period

Data is not

guaranteed

Stop of the write

operation

SLAVE

ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0 DATA tWR

SDA D1

S

T

A

R

T

A

C

K

L

A

C

K

L

A

C

K

L

A

C

K

L

S

T

O

P

WORD

ADDRESS

SLAVE

ADDRESS

SLAVE

ADDRESS

SLAVE

ADDRESS

WRITE COMMAND

SLAVE DATA

ADDRESS

WORD

ADDRESS

S

T

A

R

T

S

Ｔ

O

P

A

C

K

H

S

T

A

R

T

S

T

A

R

T

A

C

K

H

S

T

A

R

T

A

C

K

H

S

T

A

R

T

A

C

K

L

A

C

K

L

A

C

K

L

S

Ｔ

O

P

After completion of internal write,

ACK=LOW is returned, so input next

word address and data in succession.

During internal write,

ACK = HIGH is returned.

THE FIRST WRITE COMMAND

t

WR

THE SECOND WRITE COMMAND

・・・

t

WR

Datasheet

20/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Figure 45. I/O Circuit

Command Cancellation from the START and STOP Conditions

During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure

44.) However, within ACK out put area and during data read, SDA bus may output 'L'. In this case, start conditi on and stop

condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by

start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not

determined. Therefore, it is not possible to ca rr y out current read c ycle in s uccession. To carry out read cycle in succes sion,

carry out random read cycle.

I/O Peripheral Circuit

1. Pull-Up Resist ance of SDA Terminal

SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (RPU), select an appropriate

value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited.

The smaller the RPU, the larger is the supply current (Rea d).

2. Maximum RPU

The maximum value of RPU is determined by the following factors.

(1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.

Furthermore, AC timing should be satisfied even when SDA rise time is slow.

(2) The bus. electric potential ○

A to be determined by the input current leak total (IL) of device connected to bus at

output of 'H' to the SDA line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and

EEPROM including recommended noise margin of 0.2Vcc.

VCC-ILRPU-0.2 VCC ≧ VIH

∴RPU ≦0.8VCC-VIH

IL

Examples: When VCC =3V, IL=10µA, VIH=0.7 VCC

According to (2)

Figure 44. Command Cancel lation by the START and STOP Conditions during Input of the Slave Address

SCL

SDA 1 1

0 0

START

CONDITION STOP

CONDITION

≦300 [k]

RPU ≦0.8×3-0.7×3

10×10-6

RPU

A

BR34E02

SDA PIN

IL IL

Microcontroller

THE CAPACITANCE

OF BUS LINE (CBUS)

Datasheet

21/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

“L” OUTPUT OF EEPROM

“H” OUTPUT OF

MICROCONTROLLER

Figure 47. Input/Output Collision Timing

MICRO CONTROLLER

3. Minimum RPU

The minimum value of RPU is determined by following factors.

(1) Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.

(2) VOLMAX=0.4V must be lower than the input Low level of the micro controller and the EEPROM including the

recommended noise margin of 0.1VCC.

VOLMAX ≦ VIL-0.1 VCC

Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the micro controller and the EEPROM is VIL=0.3VCC,

And VOL=0.4 [V]

And VIL=0.3×3

=0.9 [V]

so that condition (2) is met

4. Pull-up Resistance of SCL Terminal

When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time

where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several k to several ten k

is recommended in considerat ion of drive performance of output port of microcontroller.

A0, A1, A2, WP Pin Connections

1. Device Address Pin (A0, A1, A2) Connections

The status of the device address pins is co mpared with the device address sent by the Master. One of the devices that

are connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that

are not used as device address (N.C.Pins) may be High, Low, or Hi-Z.

2. WP Pin Connection

The WP input allows or prohibits write operations. When WP is High, onl y Read is available and Write to all address is

prohibited. Both Read and Write are available when WP is Low.

In the event that the device is used as a RO M, it is recommended th at the WP input be pulled up or connected to VCC.

When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled.

Microcontroller Connection

1. RS

In I2C BUS, it is recommended that SDA port is of open drain input/output. Ho we ver, wh en using CMOS input / output

of tri state to SDA port, insert a series resistance RS between the pull up resistor Rpu and the SDA terminal of

EEPROM. This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM

are turned ON simultaneously. RS also plays the role of protecting the SDA terminal against surge. Therefore, even

when SDA port is open drain input/outp ut, RS can be used.

≧867 []

RPU ≧3-0.4

3×10-3

According to (1)

∴

VCC-VOL

RPU ≦IOL

RPU ≧VCC-VOL

IOL

RPU

RS

EEPROM

Figure 46. I/O Circuit

A

CK

The “H” output of micro controller and the “L” output of

EEPROM may cause current overload to SDA line.

SCL

SDA

Datasheet

22/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

2. Maximum Value of RS

The maximum value of RS is determined by the following relations.

(1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.

Furthermore, AC timing should be satisfied even when SDA rise time is slow.

(2) The bus’ electric potential ○

A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus

should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1Vcc.

3. Minimum Value of RS

The minimum value of RS is determined by over current at bus collision. When over cur rent flo ws, noises in power source

line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the

following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source

line in set and so forth. Set the over current to EEPROM at 10mA or lower.

RPU

MICRO CONTROLLER

RS

EEPROM

IOL

A

BUS

CAPACITANCE

VOL

VCC

VIL

Figure 48. I/O Circuit

Figure 49. I/O Circuit

≦

(VCC-VOL)×RS+V

OL+0.1VCC≦VIL

RS≦×

Examples: When VCC=3V, VIL=0.3VCC, VOL=0.4 V, RPU=20

k

RS×20×103

1.67[k]

RPU+RS

≦

A

ccordin

g

RPU

∴VIL-VOL-0.1VCC

1.1VCC-VIL

1.1×3-0.3×3

0.3×3-0.4-0.1×3

Vcc

RS

Vcc

I

≧300 []

∴

RS≧3

10×10-3

Examples: When V

CC=3V, I=10mA

≦I

RS≧

MICRO CONTROLLER EEPROM

"L" OUTPUT

R

S

RPU

"H" OUTPUT MAXIMUM

CURRENT

Datasheet

23/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

I/O Equivalence Circuit

1. Input (A0,A1,A2,SCL)

2. Input (SDA)

3. Input (WP)

Figure 50. Input Pin Circuit Diagram

Figure 52. Input Pin Circuit Diagram

Figure 51. Input Pin Circuit Diagram

Datasheet

24/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Power-Up/Do wn Conditions

At power ON, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal

logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and

LVCC circuit. To assure the operation, observe the following conditions at power ON.

1. "SDA='H'" and "SCL='L' or 'H'".

2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up.

tOFF

tR

Vbot

0 Figure 53. VCC rising wavefrom

VCC

tRtOFF Vbot

Below 10ms Above 10m s Below 0.3V

Below 100ms Above 10ms Bel ow 0.2V

Recommended conditions of tR, tOFF, Vbot

3. Set SDA and SCL so as not to become "Hi-Z".

When the above conditions 1 and 2 cannot be observed, take following countermeasures.

(1) In the case when the above conditi on 1 cannot be observed such that SDA becomes ‘L’ at power ON.

→Control SCL and SDA as shown below, to make SCL and SDA, ‘H’ and ‘H’.

tLOW

tSU:DAT tDH

A

fter Vcc becomes stabl

e

SCL

VCC

SDA

Figure 54. S CL ="H" and SDA= " L"

tSU:DAT

A

fter Vcc becomes stabl

e

Figure 55. SCL="L" and SDA= " L"

(2) In the case when the above conditi on 2 cannot be observed.

→After the power source become stable, execute software reset.(Figure 41)

(3) In the case when the above conditi on 1 and 2 cannot be observed.

→Carry out (1), and then carry out (2).

Low Voltage Malfunction Prev ention Function

LVCC circuit pr events data rewrite operation at low power, and pr events write error. At LV CC voltage (Typ =1.2V) or below,

data rewrite is prevented.

Noise Countermeasures

1. Bypass Capacitor

When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a

bypass capac itor (0.1µF) between IC Vcc and GND pins. Connect the capacitor as close to IC as possible. In addition, it

is also recommended to connect a bypass capacitor between board’s Vcc and GND.

Figure 53. Vcc Rising Waveform

Datasheet

25/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Operational Notes

1. Described numeric values and data are design representative values only, and the values are not guaranteed.

2. We bel ieve that the applicatio n circuit examples in this d ocument are recommendabl e. However, in actu al use, confirm

characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with

sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts

and our LSI.

3. Absolute maximum ratings

If the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, LSI

may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings.

In the case of fear of e xceeding the absolute maximum rat ings, take physical safety countermeasures such as adding

fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplie d to the LSI.

4. GND electric potential

Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower

than that of GND terminal.

5. Thermal design

Use a thermal design that allo ws for a sufficient margin by taking into acco unt the permis sible power dissipation (Pd) in

actual operating conditions.

6. Short between Pins and Mounting Errors

Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong

orientation or if pins are shorted together. Short circuit ma y be caus ed by conductive particles caught between the pins.

7. Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design

sufficiently.

Datasheet

26/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Part Numbering

B R 3 4 E 0 2 x x x - 3 x x

BUS Type

34 : I2C

Operating Temperature

-40℃ to+85℃

Capacity

02=2K

Package

FVT :TSSOP-B8

NUX :VSON008X2030

Process

Packaging and Forming Specification

E2 : Embossed tape and reel

(TSSOP-B8)

TR : Embossed tape and reel

(VSON008X2030)

Datasheet

27/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Physical Dimension Tape and Reel Information

Direction of feed

Reel ∗ Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

3000pcs

E2

()

1pin

(Unit : mm)

TSSOP-B8

0.08 S

0.08

M

4 ± 4

234

8765

1

1.0±0.05

1PIN MARK

0.525

0.245+0.05

−0.04

0.65

0.145+0.05

−0.03

0.1±0.05

1.2MAX

3.0±0.1

4.4±0.1

6.4±0.2

0.5±0.15

1.0±0.2

(MAX 3.35 include BURR)

S

TSSOP-B8

Datasheet

28/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Physical Dimension Tape and Reel Information‐Continued

∗ Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper right when you hold

reel on the left hand and you pull out the tape on the right hand

4000pcs

TR

()

Direction of feed

Reel 1pin

(Unit : mm)

VSON008X2030

5

1

8

4

1.4±0.1

0.25

1.5±0.1

0.5

0.3±0.1

0.25 +0.05

−0.04

C0.25

0.6MAX

(0.12)

0.02+0.03

−0.02 3.0±0.1

2.0±0.1

1PIN MARK

0.08 S

S

VSON008X2030

Datasheet

29/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Marking Diagrams

VSON008X2030 (TOP VIEW)

23

Part Number Marking

LOT Number

1PIN MARK

3E0

TSSOP-B8 (TOP VIEW)

3E023

Part Number Marking

LOT Numbe

r

1PIN MARK

Datasheet

30/30 TSZ02201-0R2R0G100520-1-2

www.rohm.com

TSZ22111・15・001

BR34E02-3

Revision History

Date Revision Changes

07.Sep.2012 001 New Release

25.Feb.2013 002

Update some English words, sentences’ descriptions, grammar and

formatting.

31.May.2013 003

P1 Change format of package line-up table.

Add VESD in Absolute Maximum Ratings

P.4 Add directions in Pin Descriptions

Datasheet

Notice - Rev.004

Notice

●General Precaution

1) Before you use our Products, you are requested to carefully read this document and fully understand its contents.

ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any

ROHM’s Products against warning, caution or note contained in this document.

2) All information contained in this document is current as of the issuing date and subject to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales

representative.

●Precaution on using ROHM Products

1) Our Products are designed and manufactured for applicat ion in ordinar y el ectronic eq uipm ents (such as AV equipment ,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred b y you or third parti es arising from the use of an y ROHM’s Prod ucts for Specific

Applications.

2) ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe d esign against the physical injur y, damage to any property, which

a failure or malfunction of our Products may cause. T he following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3) Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-produci ng comp onents, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flu x (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4) The Products are not subject to radiation-proof design.

5) Please verify and confirm cha racteristics of the final or mounted products in using the Products.

6) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding nor mal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7) De-rate Power Dissipation (Pd) depe nding on Ambient temperature (T a). When us ed in sealed area, confirm the actual

ambient temperature.

8) Confirm that operation temperature is within the specified range d escribed in the product specification.

9) ROHM shall not be in any way responsible or liable for fail ure induced under deviant condition from what is defined in

this document.

Datasheet

Notice - Rev.004

●Precaution for Mounting / Circuit board design

1) W hen a highly active hal ogen ous (chlori ne, bromine, etc.) flu x is used, the residue of flux may negatively affect prod uct

performance and reliability.

2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the

ROHM representative in advance.

For details, please refer to ROHM Mounting specificati on

●Precautions Regarding Application Examples and External Circuits

1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2) You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise you r own indepen dent verificatio n and judgmen t in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

●Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please t ake special care under dry con dition (e.g. Grounding of human body / equipment / sol der iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

●Precaution for Storage / Transportation

1) Product performance and soldered conn ections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, i nclud ing Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2) Even under ROHM recommended storage c ondition, solderabilit y of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommen de d storage time period.

3) Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4) Use Products within the specified time after opening a hum idity barrier bag. Baking is required before u s ing Products of

which storage time is exceeding the recommended storage time period.

●Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

●Precaution for Disposition

When disposing Products pl ease dispose them properly using an authorized industr y waste company.

●Precaution for Foreign Exchange and Foreign Trade act

Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,

please consult with ROHM representative in case of export.

●Precaution Regarding Intellectual Pro perty Rights

1) All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoi ng information or data will not infringe any int ellectual property rights or any

other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable

for infringement of any intellectual property rights or other damages arising from use of such information or data.:

2) No license, expressly or implied, is grante d hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the information contained in this document.

Datasheet

Notice - Rev.004

●Other Precaution

1) The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.

2) This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

3) The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

4) In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including b ut not limited to, the development of m ass-destruction

weapons.

5) The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated compani es or third parties.