Triple-Channel Digital Isolators
Data Sheet ADuM1300/ADuM1301
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Qualified for automotive applications
Low power operation
5 V operation
1.2 mA per channel maximum @ 0 Mbps to 2 Mbps
3.5 mA per channel maximum @ 10 Mbps
32 mA per channel maximum @ 90 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps
2.2 mA per channel maximum @ 10 Mbps
20 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
TÜV approval: IEC/EN/UL/CSA 61010-1
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Automotive systems
GENERAL DESCRIPTION
The ADuM130x1 are triple-channel digital isolators based on the
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic transformer technology, these
isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers.
By avoiding the use of LEDs and photodiodes, iCoupler
devices remove the design difficulties commonly associated
with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other
discrete components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
of the power of optocouplers at comparable signal data rates.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM130x provide low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and when power is not applied to one of the supplies.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
G
ND
1
V
IA
V
IB
V
IC
NC
NC
G
ND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NC
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-001
Figure 1. ADuM1300 Functional Block Diagram
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
OC
NC
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
NC
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-002
Figure 2. ADuM1301 Functional Block Diagram
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V,
105°C Operation........................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation... 15
Electrical Characteristics—Mixed 3 V/5 V 125°C Operation... 17
Package Characteristics ............................................................. 19
Regulatory Information............................................................. 19
Insulation and Safety-Related Specifications.......................... 19
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information.............................................................. 25
PC Board Layout ........................................................................ 25
Propagation Delay-Related Parameters................................... 25
DC Correctness and Magnetic Field Immunity........................... 25
Power Consumption .................................................................. 26
Insulation Lifetime..................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Automotive Products................................................................. 29
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 3 of 32
REVISION HISTORY
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section .................................................................1
Change to PC Board Layout Section ............................................25
Updated Outline Dimensions........................................................28
Moved Automotive Products Section...........................................28
5/08—Rev. G to Rev. H
Added ADuM1300W and ADuM1301W Parts............. Universal
Changes to Features List...................................................................1
Added Table 4 ..................................................................................11
Added Table 5 ..................................................................................13
Added Table 6 ..................................................................................15
Added Table 7 ..................................................................................17
Changes to Table 12 ........................................................................20
Changes to Table 13 ........................................................................21
Added Automotive Products Section ...........................................27
Changes to Ordering Guide...........................................................28
11/07—Rev. F to Rev. G
Changes to Note 1 and Figure 2 ......................................................1
Added ADuM130xARW Change vs. Temperature Parameter ...3
Added ADuM130xARW Change vs. Temperature Parameter ...5
Added ADuM130xARW Change vs. Temperature Parameter ...8
Changes to Figure 14 ......................................................................16
6/07—Rev. E to Rev. F
Updated VDE Certification Throughout.......................................1
Changes to Features, Note 1, Figure 1, and Figure 2 ....................1
Changes to Regulatory Information Section...............................10
Added Table 10 ................................................................................12
Added Insulation Lifetime Section ...............................................17
Updated Outline Dimensions........................................................19
Changes to Ordering Guide...........................................................19
2/06—Rev. D to Rev. E
Updated Format ................................................................. Universal
Added TÜV Approval ....................................................... Universal
Changes to Figure 2 ..........................................................................1
5/05—Rev. C to Rev. D
Changes to Format............................................................. Universal
Changes to Figure 2 ..........................................................................1
Changes to Table 6 ..........................................................................10
Changes to Ordering Guide...........................................................18
6/04—Rev. B to Rev. C
Changes to Format............................................................. Universal
Changes to Features..........................................................................1
Changes to Electrical Characteristics—5 V Operation................3
Changes to Electrical Characteristics—3 V Operation................5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................7
Changes to Ordering Guide...........................................................18
5/04—Rev. A to Rev. B
Changes to the Format ...................................................... Universal
Changes to the Features....................................................................1
Changes to Table 7 and Table 8 .....................................................14
Changes to Table 9 ..........................................................................15
Changes to the DC Correctness and Magnetic Field Immunity
Section ..............................................................................................19
Changes to the Power Consumption Section..............................20
Changes to the Ordering Guide....................................................21
9/03—Rev. 0 to Rev. A
Edits to Regulatory Information ...................................................13
Edits to Absolute Maximum Ratings............................................15
Deleted the Package Branding Information................................16
9/03—Revision 0: Initial Version
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 4 of 32
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These
specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.24 mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.6 2.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.0 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 6.5 8.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.9 2.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 57 77 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 16 18 mA 45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.3 2.1 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.0 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 5.0 6.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 3.4 4.2 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 43 57 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 29 37 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
Logic High Output Voltages VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 5.0 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 5 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM130xBRW
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 10 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output7
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section.
See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
Power Consumption
Power Consumption
Figure 6
Figure 6
Figure 9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 6 of 32
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.15 mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.9 1.7 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.4 0.7 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 3.4 4.9 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.1 1.6 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 31 48 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 8 13 mA 45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.7 1.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.6 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 2.6 3.7 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.8 2.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 24 36 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 16 23 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 7 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM130xBRW
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 26 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 16 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to
High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output7
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section.
See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
Power Consumption
Power Consumption
Figure 6
Figure 6
Figure 9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 8 of 32
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifica-
tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.11 0.15 mA
3 V/5 V Operation 0.19 0.24 mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.6 2.5 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.7 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.4 0.7 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.7 1.0 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 6.5 8.1 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.1 1.6 mA 5 MHz logic signal freq.
3 V/5 V Operation 1.9 2.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 57 77 mA 45 MHz logic signal freq.
3 V/5 V Operation 31 48 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 8 13 mA 45 MHz logic signal freq.
3 V/5 V Operation 16 18 mA 45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.3 2.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.7 1.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.6 0.9 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.0 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 5.0 6.2 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.7 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.8 2.5 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.4 4.2 mA 5 MHz logic signal freq.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 9 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 43 57 mA 45 MHz logic signal freq.
3 V/5 V Operation 24 36 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 16 23 mA 45 MHz logic signal freq.
3 V/5 V Operation 29 37 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM130xBRW
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 22 ns CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 14 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 10 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF C
L = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at
Logic High Output7
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D)
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D)
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate may be calculated as described in the P section. See through
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Fi for total VDD1 and VDD2
supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
ower Consumption
ower Consumption
Figure 6
igure 6
Figure 8
Figure 8
Figure 9 gure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured
from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing
sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be
sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the
range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on
per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a given
data rate.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 11 of 32
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These
specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.24 mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.6 2.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.0 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 6.5 8.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.9 2.5 mA 5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.3 2.1 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.0 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 5.0 6.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 3.4 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
VDD1, VDD2 − 0.1 5.0 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH
VDD1, VDD2 − 0.4 4.8 V IOx = −4 mA, VIx = VIxH
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages VOAL, VOBL, VOCL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 12 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output7
|CMH| 25 35 kV/μs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output7
|CML| 25 35 kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D) 0.05 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section.
See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
Power Consumption
Power Consumption
Figure 6
Figure 6
Figure 9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 13 of 32
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.15 mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.9 1.7 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.4 0.7 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.4 4.9 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.1 1.6 mA 5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.7 1.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.6 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 2.6 3.7 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.8 2.5 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH, VOCH V
DD1, VDD2 − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 26 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 14 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to
High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance
to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output7
|CMH| 25 35 kV/μs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section.
See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
Power Consumption
Power Consumption
Figure 6
Figure 6
Figure 9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 15 of 32
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V.
These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.15 mA
ADuM1300W, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.6 2.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.4 0.7 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 6.5 8.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.1 1.6 mA 5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.3 2.1 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.6 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 5.0 6.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.8 2.5 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH
VDD1, VDD2 − 0.4 VDD1,
VDD2 − 0.2
V IOx = −4 mA, VIx = VIxH
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages VOAL, VOBL, VOCL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 22 ns CL = 15 pF, CMOS signal levels
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 16 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 I
DDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D) 0.03 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2
supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
Power Consumption
ower Consumption
Figure 6
igure 6
Figure 8
Figure 8
Figure 9 Figure 12
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured
from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing
sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be
sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the
range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on
per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a
given data rate.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 17 of 32
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V.
These apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.24 mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.9 1.7 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2(Q) 0.7 1.0 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.4 4.9 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.9 2.5 mA 5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.7 1.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.0 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 2.6 3.7 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 3.4 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 7≤ VIA,VIB, VIC ≤ VDD1 or VDD2,
0 7≤ VE1,VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH
VDD1, VDD2 − 0.4 VDD1,
VDD2 − 0.2
V IOx = −4 mA, VIx = VIxH
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages VOAL, VOBL, VOCL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD 22 ns CL = 15 pF, CMOS signal levels
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 18 of 32
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF C
L = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at Logic
High Output7
|CMH| 25 35 kV/μs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2
supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
Power Consumption
ower Consumption
Figure 6
igure 6
Figure 8
Figure 8
Figure 9 Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured
from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing
sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be
sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the
range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on
per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a
given data rate.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 19 of 32
PACKAGE CHARACTERISTICS
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 R
I-O 1012 Ω
Capacitance (Input-to-Output)1 CI-O 1.7 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W
Thermocouple located at center of
package underside
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM130x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 9.
UL CSA VDE TÜV
Recognized under 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according
to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Approved according to
IEC 61010-1:2001 (2nd Edition),
EN 61010-1:2001 (2nd Edition),
UL 61010-1:2004 CSA C22.2.61010.1:2005
Double/reinforced
insulation, 2500 V rms
isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
Reinforced insulation,
560 V peak
Reinforced insulation, 400 V rms
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001 Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM130x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM130x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 20 of 32
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 11.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input-to-Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
(see Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
CASE T E M P E RATURE (° C)
SAFE TY-LIM IT ING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
03787-003
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting
Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter Rating
Operating Temperature (TA)1 −40°C to +105°C
Operating Temperature (TA)2 −40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3 2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2) 2, 3 3.0 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground. See the
section for information on immunity to external
magnetic fields.
DC Correctness
and Magnetic Field Immunity
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 21 of 32
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter Rating
Storage Temperature (TST) −65°C to +150°C
Ambient Operating Temperature (TA)1 −40°C to +105°C
Ambient Operating Temperature (TA)2 −40°C to +125°C
Supply Voltages (VDD1, VDD2)3 −0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VE1, VE2)3, 4 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC)3, 4 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin5
Side 1 (IO1) −23 mA to +23 mA
Side 2 (IO2) −30 mA to +30 mA
Common-Mode Transients6 −100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1300W and ADuM1301W automotive grade
versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
5 See Figure 3 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Ratings may
cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1 V
Ex Input1, 2 V
DDI State1 V
DDO State1 V
Ox Output1 Notes
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to the input state within 1 μs of VDDI power restoration.
X L Unpowered Powered Z
X X Powered Unpowered Indeterminate Outputs return to the input state within 1 μs of VDDO power restoration
if the VEx state is H or NC. Outputs return to a high impedance state
within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO
refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 22 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
NC
6
NC
11
NC
7
V
E2
10
*GND
18
GND
2
*
9
NC = NO CO NNE CT
ADuM1300
TOP VIEW
(No t t o S cale)
03787-004
*
PIN 2 AND P IN 8 ARE I NTERNAL LY CO NNE CTED, AND CONNECTING
BOT H T O G ND
1
IS RE COMME NDE D. PI N 9 AND PIN 15 ARE I NTERNAL LY
CONNECTED, AND CONNECT ING BOTH TO GND
2
IS RE COMMENDED.
03787-005
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
NC
6
NC
11
V
E1 7
V
E2
10
*GND
18
GND
2
*
9
NC = NO CONNECT
ADuM1301
TO P VI EW
(Not to Scale)
*PIN 2 AND PIN 8 ARE INTE RNALLY CONNECT ED, AND CONNE CTI NG
BOTH TO GND
1
IS RECOM M E NDE D. PI N 9 AND P IN 15 ARE INTE RNALLY
CONNECTED, AND CONNECT ING BOTH TO GND
2
IS RE COMME NDE D.
Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration
Table 16. ADuM1300 Pin Function Descriptions
Pin
No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 NC No Connect.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB,
and VOC outputs are enabled when VE2 is high or
disconnected. VOA, VOB, and VOC outputs are disabled
when VE2 is low. In noisy environments, connecting
VE2 to an external logic high or low is recommended.
11 NC No Connect.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2.
Table 17. ADuM1301 Pin Function Descriptions
Pin
No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 NC No Connect.
7 VE1 Output Enable 1. Active high logic input. VOC output
is enabled when VE1 is high or disconnected. VOC
output is disabled when VE1 is low. In noisy environ-
ments, connecting VE1 to an external logic high
or low is recommended.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA and
VOB outputs are enabled when VE2 is high or discon-
nected. VOA and VOB outputs are disabled when VE2 is
low. In noisy environments, connecting VE2 to an
external logic high or low is recommended.
11 NC No Connect.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 23 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RAT E ( M bp s)
CURRENT/ CHANNE L (mA)
0
0
6
4
2
14
12
10
8
16
18
20
4020 60 80 100
5V
3V
03787-008
Figure 6. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( M bp s)
CURRENT/CHANNEL ( mA)
0
0
2
4
3
5
1
6
20 40 60 80 100
5V
3V
03787-009
Figure 7. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
DATA RAT E ( M bp s)
0
0
1
20 40 8060 100
CURRENT/ CHANNE L (mA)
10
9
8
7
6
5
4
3
2
5V
3V
03787-010
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
DATA RAT E ( M bp s)
CURRENT ( mA)
020
0
20
10
50
40
30
60
40 60 80 100
5V
3V
03787-011
Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
4
2
10
8
6
12
16
14
4020 60 80 100
5V
3V
03787-012
Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
15
10
5
45
40
35
30
25
20
50
20 40 60 80 100
5V
3V
03787-013
Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 24 of 32
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
10
5
20
15
25
30
20 40 60 80 100
5V
3V
03787-014
Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
TEM P E RATURE (°C)
PROP AGATION DE LAY (ns)
–50 –25
25
30
35
40
0507525 100
3V
5V
03787-019
Figure 13. Propagation Delay vs. Temperature, C Grade
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 25 of 32
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 14). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
NC
NC/V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
NC
V
E2
GND
2
0
3787-015
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high output.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
0
3787-016
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM130x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM130x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 15)
by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the
ADuM130x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough
to either falsely set or reset the decoder. The following analysis
defines the conditions under which this may occur. The 3 V
operating condition of the ADuM130x is examined because it
represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
MAGNE TI C F IEL D FREQ UE NCY ( Hz)
100
MAXIMUM ALLO WABLE MAGNETI C FL UX
DENSI TY ( kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
0
3787-017
Figure 16. Maximum Allowable External Magnetic Flux Density
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 26 of 32
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM130x transformers. Figure 17 shows these allowable
current magnitudes as a function of frequency for selected
distances. The ADuM130x is extremely immune and can be
affected only by extremely large currents operated at a high
frequency very close to the component. For the 1 MHz example
noted, one would have to place a 0.5 kA current 5 mm away
from the ADuM130x to affect the operation of the component.
MAG NET I C F I E L D FRE Q UENCY (Hz )
MAXI MUM ALLO WABLE CURRENT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
03787-018
Figure 17. Maximum Allowable Current
for Various Current-to-ADuM130x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM130x
isolator is a function of the supply voltage, the data rate of
the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 6 and Figure 7
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 9 through Figure 12 provide total VDD1 and
VDD2 supply current as a function of data rate for ADuM1300/
ADuM1301 channel configurations.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 27 of 32
INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insu-
lation is significantly lower, which allows operation at higher
working voltages while still achieving a 50-year service life. The
working voltages listed in Table 14 can be applied while main-
taining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any cross
insulation voltage waveform that does not conform to Figure 19
or Figure 20 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 14.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM130x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the
actual working voltage. The values shown in Table 14 summarize
the peak voltage for 50 years of service life for a bipolar ac
operating condition and the maximum CSA/VDE approved
working voltages. In many cases, the approved working voltage
is higher than the 50-year service life voltage. Operation at these
high working voltages can lead to shortened insulation life in
some cases.
Note that the voltage presented in Figure 19 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage
cannot cross 0 V.
0V
RATED P E AK V OLTAGE
03787-021
Figure 18. Bipolar AC Waveform
The insulation lifetime of the ADuM130x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 18, Figure 19, and Figure 20 illustrate these
different isolation voltage waveforms, respectively.
0V
RATED P E AK V OLTAGE
03787-022
Figure 19. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
0V
RATED P E AK V OLTAGE
03787-023
Figure 20. DC Waveform
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 28 of 32
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters (and inches)
ORDERING GUIDE
Model1, 2, 3, 4
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns) Temperature Range
Package
Option5
ADuM1300ARW 3 0 1 100 40 −40°C to +105°C RW-16
ADuM1300CRW 3 0 90 32 2 −40°C to +105°C RW-16
ADuM1300ARWZ 3 0 1 100 40 −40°C to +105°C RW-16
ADuM1300BRWZ 3 0 10 50 3 −40°C to +105°C RW-16
ADuM1300CRWZ 3 0 90 32 2 −40°C to +105°C RW-16
ADuM1300WSRWZ 3 0 1 100 40 −40°C to +125°C RW-16
ADuM1300WTRWZ 3 0 10 32 3 −40°C to +125°C RW-16
ADuM1301ARW 2 1 1 100 40 −40°C to +105°C RW-16
ADuM1301BRW 2 1 10 50 3 −40°C to +105°C RW-16
ADuM1301CRW 2 1 90 32 2 −40°C to +105°C RW-16
ADuM1301ARWZ 2 1 1 100 40 −40°C to +105°C RW-16
ADuM1301BRWZ 2 1 10 50 3 −40°C to +105°C RW-16
ADuM1301CRWZ 2 1 90 32 2 −40°C to +105°C RW-16
ADuM1301WSRWZ 2 1 1 100 40 −40°C to +125°C RW-16
ADuM1301WTRWZ 2 1 10 32 3 −40°C to +125°C RW-16
EVAL-ADuMQSEBZ
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
4 No tape-and-reel option is available for the ADuM1301CRW model.
5 RW-16 = 16-lead wide body SOIC.
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 29 of 32
AUTOMOTIVE PRODUCTS
The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
ADuM1300/ADuM1301 Data Sheet
Rev. I | Page 30 of 32
NOTES
Data Sheet ADuM1300/ADuM1301
Rev. I | Page 31 of 32
NOTES
