December 2011 Doc ID 16100 Rev 5 1/103
1
SPC560P34L1, SPC560P34L3
SPC560P40L1, SPC560P40L3
32-bit Power Architecture® based MCU with 320 KB Flash memory
and 20 KB RAM for automotive chassis and safety applications
Features
■Up to 64 MHz, single issue, 32-bit CPU core
complex (e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
■Memory organization
– Up to 256 KB on-chip code flash memory
with ECC and erase/program controller
– Additional 64 (4 × 16) KB on-chip data
flash memory with ECC for EEPROM
emulation
– Up to 20 KB on-chip SRAM with ECC
■Fail-safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
■Nexus Class 1 interface
■Interrupts and events
– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC
■1 general purpose eTimer unit
– 6 timers each with up/down capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
■GPIO (37 on LQFP64; 64 on LQFP100)
individually programmable as I/O or special
function
■Communications interfaces
– 2 LINFlex channels (1× Master/Slave, 1×
Master only)
– Up to 3 DSPI channels with automatic chip
select generation (up to 8/4/4 chip selects)
– Up to 2 FlexCAN interface (2.0B Active)
with 32 message buffers
– 1 safety port based on FlexCAN with 32
message buffers and up to 8 Mbit/s at
64 MHz capability usable as second CAN
when not used as safety port
■One 10-bit analog-to-digital converter (ADC)
– Up to 16 input channels (16 on LQFP100 /
12 on LQFP64)
– Conversion time < 1 µs including sampling
time at full precision
– Programmable Cross Triggering Unit (CTU)
– 4 analog watchdogs with interrupt
capability
■On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
■1 FlexPWM unit: 8 complementary or
independent outputs with ADC synchronization
signals
Table 1. Device summary
Package 192 Kbyte
Code Flash
256 Kbyte
Code Flash
LQFP100 SPC560P34L3 SPC560P40L3
LQFP64 SPC560P34L1 SPC560P40L1
LQFP64 (10 x 10 x 1.4 mm
LQFP100 (14 x 14 x 1.4 mm)
www.st.com
Contents SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
2/103 Doc ID 16100 Rev 5
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1 High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5 Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.7 System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 16
1.5.8 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.9 Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17
1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.13 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.16 System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20 Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.22 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22
1.5.23 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22
1.5.24 Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.25 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.26 Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.27 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.28 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Contents
Doc ID 16100 Rev 5 3/103
1.5.29 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.30 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.31 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.3 Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.2 General notes for specifications at maximum junction temperature . . . 52
3.6 Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 54
3.7 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 54
3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 54
3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54
3.8.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56
3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.10.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.10.4 Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 63
3.10.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.11 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.13 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 67
3.14 Analog-to-digital converter (ADC) electrical characteristics . . . . . . . . . . . 67
Contents SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
4/103 Doc ID 16100 Rev 5
3.14.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.14.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.15.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.15.2 Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 75
3.15.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.1 LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.2 LQFP64 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 List of tables
Doc ID 16100 Rev 5 5/103
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC560P34/SPC560P40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. SPC560P40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. SPC560P34/SPC560P40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 11. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 16. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 18. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 60
Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 61
Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 65
Table 26. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 65
Table 27. Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 29. 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 30. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 31. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 32. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 33. Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 35. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 36. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 37. RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 39. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 40. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 41. DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 42. LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 43. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 44. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
List of figures SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
6/103 Doc ID 16100 Rev 5
List of figures
Figure 1. Block diagram (SPC560P40 full-featured configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. 64-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3. 64-pin LQFP pinout – airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. 100-pin LQFP pinout – full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. 100-pin LQFP pinout – airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. Power supplies constraints (–0.3 V ≤VDD_HV_IOx ≤6.0 V). . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7. Independent ADC supply (–0.3 V ≤VDD_HV_REG ≤6.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 8. Power supplies constraints (3.0 V ≤VDD_HV_IOx ≤5.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9. Independent ADC supply (3.0 V ≤VDD_HV_REG ≤5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10. Voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 11. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 12. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 13. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 14. Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 16. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 17. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 26. Nexus event trigger and test clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. DSPI classic SPI timing – Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 30. DSPI classic SPI timing – Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 31. DSPI classic SPI timing – Slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 32. DSPI classic SPI timing – Slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 33. DSPI modified transfer format timing – Master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 34. DSPI modified transfer format timing – Master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 37. DSPI PCS Strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 38. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 39. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 40. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
Doc ID 16100 Rev 5 7/103
1 Introduction
1.1 Document overview
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC560P34/40 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.
1.2 Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement
in integrated automotive application controllers. It belongs to an expanding range of
automotive-focused products designed to address chassis applications—specifically,
electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as
airbag applications.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates at speeds of up to
64 MHz and offers high performance processing optimized for low power consumption. It
capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems and configuration code to
assist with users implementations.
1.3 Device comparison
Ta bl e 2
provides a summary of different members of the SPC560P34/SPC560P40 family
and their features—relative to full-featured version—to enable a comparison among the
family members and an understanding of the range of functionality offered within this family.
Table 2. SPC560P34/SPC560P40 device comparison
Feature SPC560P34 SPC560P40
Full-featured
Code flash memory (with ECC) 192 KB 256 KB
Data flash memory / EE option (with ECC) 64 KB
SRAM (with ECC) 12 KB 20 KB
Processor core 32-bit e200z0h
Instruction set VLE (variable length encoding)
CPU performance 0–64 MHz
FMPLL (frequency-modulated phase-locked loop)
module 1
INTC (interrupt controller) channels 120
PIT (periodic interrupt timer) 1 (with four 32-bit timers)
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
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SPC560P34/SPC560P40 is available in two configurations having different features: Full-
featured and airbag.
Ta bl e 3
shows the main differences between the two versions of the
SPC560P40 MCU.
eDMA (enhanced direct memory access)
channels 16
FlexCAN (controller area network) 1(1) 2(1),(2)
Safety port No Yes (via second
FlexCAN module)
FCU (fault collection unit) Yes
CTU (cross triggering unit) Yes Yes
eTimer 1 (16-bit, 6 channels)
FlexPWM (pulse-width modulation) channels
8
(capture capabity not
supported)
8
(capture capability not
supported)
Analog-to-digital converter (ADC) 1 (10-bit, 16 channels)
LINFlex
2
(1 × Master/Slave,
1 × Master only)
2
(1 × Master/Slave,
1 × Master only)
DSPI (deserial serial peripheral interface) 2 3
CRC (cyclic redundancy check) unit Yes
Junction temperature sensor No
JTAG controller Yes
Nexus port controller (NPC) Yes (Nexus Class 1)
Supply
Digital power supply(3) 3.3 V or 5 V single supply with external transistor
Analog power supply 3.3 V or 5 V
Internal RC oscillator 16 MHz
External crystal oscillator 4–40 MHz
Packages LQFP64
LQFP100
Temperature Standard ambient temperature –40 to 125 °C
1. Each FlexCAN module has 32 message buffers.
2. One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.
3. The different supply voltages vary according to the part number ordered.
Table 2. SPC560P34/SPC560P40 device comparison (continued)
Feature SPC560P34 SPC560P40
Full-featured
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
Doc ID 16100 Rev 5 9/103
1.4 Block diagram
Figure 1
shows a top-level block diagram of the SPC560P34/SPC560P40 MCU.
Ta bl e 4
summarizes the functions of the blocks.
Table 3. SPC560P40 device configuration differences
Feature
Configuration
Airbag Full-featured
SRAM (with ECC) 16 KB 20 KB
FlexCAN (controller area network) 1 2
Safety port No Ye s
(via second FlexCAN module)
FlexPWM (pulse-width modulation) channels No
8
(capture capability not
supported)
CTU (cross triggering unit) No Yes
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
10/103 Doc ID 16100 Rev 5
Figure 1. Block diagram (SPC560P40 full-featured configuration)
SRAM
(with ECC)
Slave SlaveSlave
Code Flash
(with ECC)
Data Flash
(with ECC)
PIT
STM
SWT
MC_RGM
MC_CGM
MC_ME
BAM
SIUL
WKPU
CRC
ECSM
e200z0 Core
32-bit
general
purpose
registers
Special
purpose
registers
Integer
execution
unit
Exception
handler
Variable
length
encoded
instructions
Instruction
unit
Load/store
unit
Branch
prediction
unit
JTAG
1.2 V regulator
control
XOSC
16 MHz
RC oscillator
FMPLL_0
(System)
Nexus port
controller
Interrupt
controller
eDMA
16 channels
Master Master
Instruction
32-bit
Master
Data
32-bit
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
Peripheral bridge
FCU
Legend:
ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller
LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System Integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch
External ballast
Nexus 1
eDMA
16 channels
FlexPWM
CTU
3×
eTimer
DSPI
2×
FlexCAN
LINFlex
Safety port
ADC
(6 ch)
SSCM
(10 bit, 16 ch)
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Table 4. SPC560P34/SPC560P40 series block summary
Block Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM) Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network
(FlexCAN) Supports the standard CAN communications protocol
Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR) Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC) CRC checksum generator
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host
processor via “
n
” programmable channels
Enhanced timer (eTimer) Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC) Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU) Provides functional safety to the device
Flash memory Provides non-volatile storage for program code, constants and variables
Frequency-modulated phase-
locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
JTAG controller Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE) Is the interface between the system bus and on-chip peripherals
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
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Pulse width modulator
(FlexPWM)
Contains four PWM submodules, each of which capable of controlling a single
half-bridge power stage and two fault input channels
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Static random-access memory
(SRAM) Provides storage for program code, constants, and variables
System integration unit lite (SIUL)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM) Provides a set of output compare events to support AUTOSAR(1) and operating
system tasks
System watchdog timer (SWT) Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup
events
1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)
Table 4. SPC560P34/SPC560P40 series block summary (continued)
Block Function
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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1.5 Feature details
1.5.1 High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
●High performance e200z0 core processor for managing peripherals and interrupts
●Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
●Harvard architecture
●Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions
– Results in smaller code size footprint
– Minimizes impact on performance
●Branch processing acceleration using lookahead instruction buffer
●Load/store unit
– 1-cycle load latency
– Misaligned access support
– No load-to-use pipeline bubbles
●Thirty-two 32-bit general purpose registers (GPRs)
●Separate instruction bus and load/store bus Harvard architecture
●Hardware vectored interrupt support
●Reservation instructions for implementing read-modify-write constructs
●Long cycle time instructions, except for guarded loads, do not increase interrupt latency
●Extensive system development support through Nexus debug port
●Non-maskable interrupt support
1.5.2 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access a slave port in round-robin fashion, based upon the ID of the last master to
be granted access.
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
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The crossbar provides the following features:
●3 master ports:
– e200z0 core complex instruction port
– e200z0 core complex Load/Store Data port
–eDMA
●3 slave ports:
– Flash memory (Code and Data)
–SRAM
– Peripheral bridge
●32-bit internal address, 32-bit internal data paths
●Fixed Priority Arbitration based on Port Master
●Temporary dynamic priority elevation of masters
1.5.3 Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels.
The eDMA module provides the following features:
●16 channels support independent 8-, 16- or 32-bit single value or block transfers
●Supports variable-sized queues and circular queues
●Source and destination address registers are independently configured to either post-
increment or to remain constant
●Each transfer is initiated by a peripheral, CPU, or eDMA channel request
●Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
●DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer
and CTU
●Programmable DMA channel multiplexer allows assignment of any DMA source to any
available DMA channel with as many as 30 request sources
●eDMA abort operation through software
1.5.4 Flash memory
The SPC560P34/SPC560P40 provides 320 KB of programmable, non-volatile, flash
memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.
The flash memory module is interfaced to the system bus by a dedicated flash memory
controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data
interface to flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch
buffer hits allow no-wait responses. Normal flash memory array accesses are registered and
are forwarded to the system bus on the following cycle, incurring two wait-states.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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The flash memory module provides the following features:
●As much as 320 KB flash memory
– 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory
– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory
– Full Read-While-Write (RWW) capability between code flash memory and data
flash memory
●Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
●Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page
buffer miss at 64 MHz
●Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
●Hardware and software configurable read and write access protections on a per-master
basis
●Configurable access timing allowing use in a wide range of system frequencies
●Multiple-mapping support and mapping-based block access timing (up to 31 additional
cycles) allowing use for emulation of other memory types
●Software programmable block program/erase restriction control
●Erase of selected block(s)
●Read page sizes
– Code flash memory: 128 bits (4 words)
– Data flash memory: 32 bits (1 word)
●ECC with single-bit correction, double-bit detection for data integrity
– Code flash memory: 64-bit ECC
– Data flash memory: 32-bit ECC
●Embedded hardware program and erase algorithm
●Erase suspend and program abort
●Censorship protection scheme to prevent flash memory content visibility
●Hardware support for EEPROM emulation
1.5.5 Static random access memory (SRAM)
The SPC560P34/SPC560P40 SRAM module provides up to 20 KB of general-purpose
memory.
The SRAM module provides the following features:
●Supports read/write accesses mapped to the SRAM from any master
●Up to 20 KB general purpose SRAM
●Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
●Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8-
and 16-bit writes if back-to-back with a read to same memory block
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
16/103 Doc ID 16100 Rev 5
1.5.6 Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 128
selectable-priority interrupt sources.
For high-priority interrupt requests, the time from the assertion of the interrupt request by
the peripheral to the execution of the interrupt service routine (ISR) by the processor has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.
The INTC provides the following features:
●Unique 9-bit vector for each separate interrupt source
●8 software triggerable interrupt sources
●16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●Ability to modify the ISR or task priority: modifying the priority can be used to
implement the priority ceiling protocol for accessing shared resources.
●1 external high priority interrupt (NMI) directly accessing the main core and I/O
processor (IOP) critical interrupt mechanism
1.5.7 System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
●System configuration and status
– Memory sizes/status
– Device mode and security status
– Determine boot vector
– Search code flash for bootable sector
– DMA status
●Debug status port enable and selection
●Bus and peripheral abort enable/disable
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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1.5.8 System clocks and clock generation
The following list summarizes the system clock and clock generation on the
SPC560P34/SPC560P40:
●Lock detect circuitry continuously monitors lock status
●Loss of clock (LOC) detection for PLL outputs
●Programmable output clock divider (÷1, ÷2, ÷4, ÷8)
●FlexPWM module and eTimer module running at the same frequency as the e200z0h
core
●Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency
trimming by user application
1.5.9 Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.
The FMPLL has the following major features:
●Input clock frequency: 4–40 MHz
●Maximum output frequency: 64 MHz
●Voltage controlled oscillator (VCO)—frequency 256–512 MHz
●Reduced frequency divider (RFD) for reduced frequency operation without forcing the
FMPLL to relock
●Frequency-modulated PLL
– Modulation enabled/disabled through software
– Triangle wave modulation
●Programmable modulation depth (±0.25% to ±4% deviation from center frequency):
programmable modulation frequency dependent on reference frequency
●Self-clocked mode (SCM) operation
1.5.10 Main oscillator
The main oscillator provides these features:
●Input frequency range: 4–40 MHz
●Crystal input mode or oscillator input mode
●PLL reference
1.5.11 Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
18/103 Doc ID 16100 Rev 5
The RC oscillator provides these features:
●Nominal frequency 16 MHz
●±5 % variation over voltage and temperature after process trim
●Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
●RC oscillator is used as the default system clock during startup
1.5.12 Periodic interrupt timer (PIT)
The PIT module implements these features:
●4 general-purpose interrupt timers
●32-bit counter resolution
●Clocked by system clock frequency
●Each channel usable as trigger for a DMA request
1.5.13 System timer module (STM)
The STM implements these features:
●One 32-bit up counter with 8-bit prescaler
●Four 32-bit compare channels
●Independent interrupt source for each channel
●Counter can be stopped in debug mode
1.5.14 Software watchdog timer (SWT)
The SWT has the following features:
●32-bit time-out register to set the time-out period
●Programmable selection of window mode or regular servicing
●Programmable selection of reset or interrupt on an initial time-out
●Master access protection
●Hard and soft configuration lock bits
●Reset configuration inputs allow timer to be enabled out of reset
1.5.15 Fault collection unit (FCU)
The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.
The FCU module has the following features:
●FCU status register reporting the device status
●Continuous monitoring of critical fault signals
●User selection of critical signals from different fault sources inside the device
●Critical fault events trigger 2 external pins (user selected signal protocol) that can be
used externally to reset the device and/or other circuitry (for example, a safety relay)
●Faults are latched into a register
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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1.5.16 System integration unit – Lite (SIUL)
The SPC560P34/SPC560P40 SIUL controls MCU pad configuration, external interrupt,
general purpose I/O (GPIO), and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIUL provides the following features:
●Centralized general purpose input output (GPIO) control of up to 49 input/output pins
and 16 analog input-only pads (package dependent)
●All GPIO pins can be independently configured to support pull-up, pull-down, or no pull
●Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
●All peripheral pins, except ADC channels, can be alternatively configured as both
general purpose input or output pins
●ADC channels support alternative configuration as general purpose inputs
●Direct readback of the pin value is supported on all pins through the SIUL
●Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination
●Up to 4 internal functions can be multiplexed onto 1 pin
1.5.17 Boot and censorship
Different booting modes are available in the SPC560P34/SPC560P40: booting from internal
flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down resistor is
used to select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the
boot assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
Boot assist module (BAM)
The BAM is a block of read-only memory that is programmed once and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.
The BAM provides the following features:
●Serial bootloading via FlexCAN or LINFlex
●Ability to accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory
1.5.18 Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
20/103 Doc ID 16100 Rev 5
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:
●Registers for capturing information on platform memory errors if error-correcting codes
(ECC) are implemented
●For test purposes, optional registers to specify the generation of double-bit memory
errors are enabled on the SPC560P34/SPC560P40.
The sources of the ECC errors are:
●Flash memory
●SRAM
1.5.19 Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
●Duplicated periphery
●Master access privilege level per peripheral (per master: read access enable; write
access enable)
●Write buffering for peripherals
●Checker applied on PBRIDGE output toward periphery
●Byte endianess swap capability
1.5.20 Controller area network (FlexCAN)
The SPC560P34/SPC560P40 MCU contains one controller area network (FlexCAN)
module. This module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-
time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. The FlexCAN module contains 32 message buffers.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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The FlexCAN module provides the following features:
●Full implementation of the CAN protocol specification, version 2.0B
– Standard data and remote frames
– Extended data and remote frames
– Up to 8-bytes data length
– Programmable bit rate up to 1 Mbit/s
●32 message buffers of up to 8-bytes data length
●Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
●Programmable loop-back mode supporting self-test operation
●3 programmable mask registers
●Programmable transmit-first scheme: lowest ID or lowest buffer number
●Time stamp based on 16-bit free-running timer
●Global network time, synchronized by a specific message
●Maskable interrupts
●Independent of the transmission medium (an external transceiver is assumed)
●High immunity to EMI
●Short latency time due to an arbitration scheme for high-priority messages
●Transmit features
– Supports configuration of multiple mailboxes to form message queues of scalable
depth
– Arbitration scheme according to message ID or message buffer number
– Internal arbitration to guarantee no inner or outer priority inversion
– Transmit abort procedure and notification
●Receive features
– Individual programmable filters for each mailbox
– 8 mailboxes configurable as a 6-entry receive FIFO
– 8 programmable acceptance filters for receive FIFO
●Programmable clock source
– System clock
– Direct oscillator clock to avoid PLL jitter
1.5.21 Safety port (FlexCAN)
The SPC560P34/SPC560P40 MCU has a second CAN controller synthesized to run at high
bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:
●Identical to the FlexCAN module
●Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required)
●32 message buffers of up to 8-bytes data length
●Can be used as a second independent CAN module
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
22/103 Doc ID 16100 Rev 5
1.5.22 Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the SPC560P34/SPC560P40 features
the following:
●Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and
UART mode
●LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications
●Handles LIN frame transmission and reception without CPU intervention
●LIN features
– Autonomous LIN frame handling
– Message buffer to store Identifier and up to 8 data bytes
– Supports message length of up to 64 bytes
– Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,
checksum, and time-out)
– Classic or extended checksum calculation
– Configurable Break duration of up to 36-bit times
– Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
– Interrupt-driven operation with 16 interrupt sources
●LIN slave mode features:
– Autonomous LIN header handling
– Autonomous LIN response handling
– Optional discarding of irrelevant LIN responses using ID filter
●UART mode:
– Full-duplex operation
– Standard non return-to-zero (NRZ) mark/space format
– Data buffers with 4-byte receive, 4-byte transmit
– Configurable word length (8-bit or 9-bit words)
– Error detection and flagging
– Parity, Noise and Framing errors
– Interrupt-driven operation with four interrupt sources
– Separate transmitter and receiver CPU interrupt sources
– 16-bit programmable baud-rate modulus counter and 16-bit fractional
– 2 receiver wake-up methods
1.5.23 Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P34/SPC560P40 MCU and external
devices.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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The DSPI modules provide these features:
●Full duplex, synchronous transfers
●Master or slave operation
●Programmable master bit rates
●Programmable clock polarity and phase
●End-of-transmission interrupt flag
●Programmable transfer baud rate
●Programmable data frames from 4 to 16 bits
●Up to 8 chip select lines available:
–8 on DSPI_0
– 4 each on DSPI_1 and DSPI_2
●8 clock and transfer attributes registers
●Chip select strobe available as alternate function on one of the chip select pins for
deglitching
●FIFOs for buffering up to 4 transfers on the transmit and receive side
●Queueing operation possible through use of the I/O processor or eDMA
●General purpose I/O functionality on pins when not used for SPI
1.5.24 Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules each of which is
set up to control a single half-bridge power stage. There are also three fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
24/103 Doc ID 16100 Rev 5
The FlexPWM block implements the following features:
●16-bit resolution for center, edge-aligned, and asymmetrical PWMs
●Clock frequency same as that used for e200z0h core
●PWM outputs can operate as complementary pairs or independent channels
●Can accept signed numbers for PWM generation
●Independent control of both edges of each PWM output
●Synchronization to external hardware or other PWM supported
●Double buffered PWM registers
– Integral reload rates from 1 to 16
– Half cycle reload capability
●Multiple ADC trigger events can be generated per PWM cycle via hardware
●Write protection for critical registers
●Fault inputs can be assigned to control multiple PWM outputs
●Programmable filters for fault inputs
●Independently programmable PWM output polarity
●Independent top and bottom deadtime insertion
●Each complementary pair can operate with its own PWM frequency and deadtime
values
●Individual software-control for each PWM output
●All outputs can be programmed to change simultaneously via a “Force Out” event
●PWMX pin can optionally output a third PWM signal from each submodule
●Channels not used for PWM generation can be used for buffered output compare
functions
●Channels not used for PWM generation can be used for input capture functions
●Enhanced dual-edge capture functionality
●eDMA support with automatic reload
●2 fault inputs
●Capture capability for PWMA, PWMB, and PWMX channels not supported
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
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1.5.25 eTimer
The SPC560P34/SPC560P40 includes one eTimer module which provides six 16-bit
general purpose up/down timer/counter units with the following features:
●Clock frequency same as that used for the e200z0h core
●Individual channel capability
– Input capture trigger
– Output compare
– Double buffer (to capture rising edge and falling edge)
– Separate prescaler for each counter
– Selectable clock source
– 0–100% pulse measurement
– Rotation direction flag (quad decoder mode)
●Maximum count rate
– External event counting: max. count rate = peripheral clock/2
– Internal clock counting: max. count rate = peripheral clock
●Counters are:
– Cascadable
– Preloadable
●Programmable count modulo
●Quadrature decode capabilities
●Counters can share available input pins
●Count once or repeatedly
●Pins available as GPIO when timer functionality not in use
1.5.26 Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
●1 on-chip analog-to-digital converter
– 10-bit AD resolution
– 1 sample and hold unit
– Conversion time, including sampling time, less than 1 µs (at full precision)
– Typical sampling time is 150 ns minimum (at full precision)
– DNL/INL ±1 LSB
–TUE <1.5LSB
– Single-ended input signal up to 3.3 V/5.0 V
– 3.3 V/5.0 V input reference voltage
– ADC and its reference can be supplied with a voltage independent from VDDIO
– ADC supply can be equal or higher than VDDIO
– ADC supply and ADC reference are not independent from each other (both
internally bonded to same pad)
– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
26/103 Doc ID 16100 Rev 5
Digital part:
●16 input channels
●4 analog watchdogs comparing ADC results against predefined levels (low, high,
range) before results are stored in the appropriate ADC result location
●2 modes of operation: Motor Control mode or Regular mode
●Regular mode features
– Register based interface with the CPU: control register, status register and 1 result
register per channel
– ADC state machine managing 3 request flows: regular command, hardware
injected command and software injected command
– Selectable priority between software and hardware injected commands
– DMA compatible interface
●CTU-controlled mode features
– Triggered mode only
– 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)
– Result alignment circuitry (left justified and right justified)
– 32-bit read mode allows to have channel ID on one of the 16-bit part
– DMA compatible interfaces
1.5.27 Cross triggering unit (CTU)
The cross triggering unit allows automatic generation of ADC conversion requests on user
selected conditions without CPU load during the PWM period and with minimized CPU load
for dynamic configuration.
It implements the following features:
●Double buffered trigger generation unit with up to 8 independent triggers generated
from external triggers
●Trigger generation unit configurable in sequential mode or in triggered mode
●Each trigger can be appropriately delayed to compensate the delay of external low
pass filter
●Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●Double buffered ADC command list pointers to minimize ADC-trigger unit update
●Double buffered ADC conversion command list with up to 24 ADC commands
●Each trigger capable of generating consecutive commands
●ADC conversion command allows to control ADC channel, single or synchronous
sampling, independent result queue selection
1.5.28 Nexus Development Interface (NDI)
The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-
ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal busses
to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Introduction
Doc ID 16100 Rev 5 27/103
The development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers.
The NDI provides the following features:
●Configured via the IEEE 1149.1
●All Nexus port pins operate at VDDIO (no dedicated power supply)
●Nexus Class 1 supports Static debug
1.5.29 Cyclic redundancy check (CRC)
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:
●Support for CRC-16-CCITT (
x
25 protocol):
–
x
16 +
x
12 +
x
5 + 1
●Support for CRC-32 (Ethernet protocol):
–
x
32 +
x
26 +
x
23 +
x
22 +
x
16 +
x
12 +
x
11 +
x
10 +
x
8 +
x
7 +
x
5 +
x
4 +
x
2 +
x
+ 1
●Zero wait states for each write/read operations to the CRC_CFG and CRC_INP
registers at the maximum frequency
1.5.30 IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features:
●IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)
●Selectable modes of operation include JTAGC/debug or normal system operation.
●5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
– BYPASS
– IDCODE
–EXTEST
– SAMPLE
– SAMPLE/PRELOAD
●5-bit instruction register that supports the additional following public instructions:
– ACCESS_AUX_TAP_NPC
– ACCESS_AUX_TAP_ONCE
●3 test data registers:
– Bypass register
– Boundary scan register (size parameterized to support a variety of boundary scan
chain lengths)
– Device identification register
●TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
Introduction SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
28/103 Doc ID 16100 Rev 5
1.5.31 On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
●Uses external NPN (negative-positive-negative) transistor
●Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic
●Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 29/103
2 Package pinouts and signal descriptions
2.1 Package pinouts
The LQFP pinouts are shown in the following figures. For pin signal descriptions, please
refer to
Tabl e 7
.
Figure 2. 64-pin LQFP pinout – Full featured configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NMI
A[6]
A[7]
A[8]
A[5]
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
VSS_LV_COR0
VDD_LV_COR0
A[4]
VPP TEST
D[14]]
D[12]
D[13
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
B[9]
B[10]
B[11]
B[12]
VDD_HV_AD0
VSS_HV_AD0
E[3]/B[13]
BCTRL
VDD_HV_REG
A[15]
A[14]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
VSS_HV_IO3
VDD_HV_IO3
A[12]
A[11]
A[10]
B[2]
B[1]
B[0]
LQFP64
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
30/103 Doc ID 16100 Rev 5
Figure 3. 64-pin LQFP pinout – airbag configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NMI
A[6]
A[7]
A[8]
A[5]
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
VSS_LV_COR0
VDD_LV_COR0
A[4]
VPP TEST
D[14]
D[12]
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
B[9]
B[10]
B[11]
B[12]
VDD_HV_AD0
VSS_HV_AD0
E[3]/B[13]
BCTRL
VDD_HV_REG
A[15]
A[14]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
VSS_HV_IO3
VDD_HV_IO3
A[12]
A[11]
A[10]
B[2]
B[1]]
B[0]
LQFP64
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 31/103
Figure 4. 100-pin LQFP pinout – full featured configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
N.C.
N.C.
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR0
VDD_LV_COR0
A[4]
VPP TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
N.C.
N.C.
B[9]
B[10]
B[11]
B[12]
VDD_HV_AD0
VSS_HV_AD0
E[7]/D[15]
E[3]/B[13]
E[5]/B[15]
E[4]/B[14]
E[6]/C[0]
N.C.
BCTRL
N.C.
N.C.
VDD_HV_REG
A[15]
A[14]
C[6]
D[2]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
LQFP100
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
32/103 Doc ID 16100 Rev 5
Figure 5. 100-pin LQFP pinout – airbag configuration (top view)
2.2 Pin description
The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC560P34/SPC560P40 devices.
2.2.1 Power supply and reference voltage pins
Ta bl e 5
lists the power supply and reference voltage for the SPC560P34/SPC560P40
devices.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
N.C.
N.C.
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR0
VDD_LV_COR0
A[4]
VPP TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
N.C.
N.C.
B[9]
B[10]
B[11]
B[12]
VDD_HV_AD0
VSS_HV_AD0
E[7]/D[15]
E[3]/B[13]
E[5]/B[15]
E[4]/B[14]
E[6]/C[0]
N.C.
BCTRL
N.C.
N.C.
VDD_HV_REG
A[15]
A[14]
C[6]
D[2]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
LQFP100
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 33/103
Table 5. Supply pins
Supply Pin
Symbol Description 64-pin 100-pin
VREG control and power supply pins. Pins available on 64-pin and 100-pin packages
BCTRL Voltage regulator external NPN ballast base control pin 31 47
VDD_HV_REG
(3.3 V or 5.0 V) Voltage regulator supply voltage 32 50
ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages
VDD_HV_ADC0(1) ADC_0 supply and high reference voltage 28 39
VSS_HV_ADC0 ADC_0 ground and low reference voltage 29 40
Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages
VDD_HV_IO1 Input/output supply voltage 6 13
VSS_HV_IO1 Input/output ground 7 14
VDD_HV_IO2 Input/output supply voltage and data Flash memory supply voltage 40 63
VSS_HV_IO2 Input/output ground and Flash memory HV ground 39 62
VDD_HV_IO3 Input/output supply voltage and code Flash memory supply voltage 55 87
VSS_HV_IO3 Input/output ground and code Flash memory HV ground 56 88
VDD_HV_OSC Crystal oscillator amplifier supply voltage 9 16
VSS_HV_OSC Crystal oscillator amplifier ground 10 17
Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages
VDD_LV_COR0
1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV_COR pin. 16 25
VSS_LV_COR0
1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin. 15 24
VDD_LV_COR1
1.2 V supply pins for core logic and data Flash. Decoupling capacitor
must be connected between these pins and the nearest VSS_LV_COR
pin.
42 65
VSS_LV_COR1
1.2 V supply pins for core logic and data Flash. Decoupling capacitor
must be connected between these pins and the nearest VDD_LV_COR
pin.
43 66
VDD_LV_COR2
1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected between these pins and the nearest VSS_LV_COR
pin.
58 92
VSS_LV_COR2
1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected betwee.n these pins and the nearest VDD_LV_COR
pin.
59 93
1. Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding
connection on VDD_HV_ADCx/VSS_HV_ADCx pins.
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
34/103 Doc ID 16100 Rev 5
2.2.2 System pins
Ta bl e 6
and
Ta bl e 7
contain information on pin functions for the SPC560P34/SPC560P40
devices. The pins listed in
Ta bl e 6
are single-function pins. The pins shown in
Tabl e 7
are
multi-function pins, programmable via their respective pad configuration register (PCR)
values.
2.2.3 Pin multiplexing
Ta bl e 7
defines the pin list and muxing for the SPC560P34/SPC560P40 devices.
Each row of
Tabl e 7
shows all the possible ways of configuring each pin, via alternate
functions. The default function assigned to each pin after reset is the ALT0 function.
SPC560P34/SPC560P40 devices provide three main I/O pad types, depending on the
associated functions:
●
Slow pads
are the most common, providing a compromise between transition time and
low electromagnetic emission.
●
Medium pads
provide fast enough transition for serial communication channels with
controlled current to reduce electromagnetic emission.
●
Fast pads
provide maximum speed. They are used for improved NEXUS debugging
capability.
Table 6. System pins
Symbol Description Direction
Pad speed(1) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Dedicated pins
NMI Non-maskable Interrupt Input only Slow — 1 1
XTAL
Analog output of the oscillator amplifier
circuit—needs to be grounded if oscillator is
used in bypass mode
———1118
EXTAL
Analog input of the oscillator amplifier circuit,
when the oscillator is not in bypass mode
Analog input for the clock generator when the
oscillator is in bypass mode
———1219
TDI JTAG test data input Input only Slow — 35 58
TMS JTAG state machine control Input only Slow — 36 59
TCK JTAG clock Input only Slow — 37 60
TDO JTAG test data output Output only Slow Fast 38 61
Reset pin
RESET Bidirectional reset with Schmitt trigger
characteristics and noise filter Bidirectional Medium — 13 20
Te s t p in
VPP_TEST Pin for testing purpose only. To be tied to
ground in normal operating mode. ———4774
1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 35/103
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance. For more information, see
Section 3.16.1: Pad AC
specifications
.
Table 7. Pin muxing
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Port A (16-bit)
A[0] PCR[0]
ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
ETC[0]
SCK
F[0]
EIRQ[0]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
I/O
O
I
Slow Medium — 51
A[1] PCR[1]
ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
ETC[1]
SOUT
F[1]
EIRQ[1]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
O
O
I
Slow Medium — 52
A[2] PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
ETC[2]
—
A[3]
SIN
ABS[0]
EIRQ[2]
SIUL
eTimer_0
—
FlexPWM_0
DSPI_2
MC_RGM
SIUL
I/O
I/O
—
O
I
I
I
Slow Medium — 57
A[3] PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[3]
ETC[3]
CS0
B[3]
ABS[1]
EIRQ[3]
SIUL
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
I/O
I/O
I/O
O
I
I
Slow Medium 41 64
A[4] PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[4]
—
CS1
ETC[4]
FAB
EIRQ[4]
SIUL
—
DSPI_2
eTimer_0
MC_RGM
SIUL
I/O
—
O
I/O
I
I
Slow Medium 48 75
A[5] PCR[5]
ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
CS0
—
CS7
EIRQ[5]
SIUL
DSPI_1
—
DSPI_0
SIUL
I/O
I/O
—
O
I
Slow Medium 5 8
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
36/103 Doc ID 16100 Rev 5
A[6] PCR[6]
ALT0
ALT1
ALT2
ALT3
—
GPIO[6]
SCK
—
—
EIRQ[6]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
Slow Medium 2 2
A[7] PCR[7]
ALT0
ALT1
ALT2
ALT3
—
GPIO[7]
SOUT
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
Slow Medium 3 4
A[8] PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[8]
—
—
—
SIN
EIRQ[8]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
Slow Medium 4 6
A[9] PCR[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
CS1
—
B[3]
FAULT[0]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium 60 94
A[10] PCR[10]
ALT0
ALT1
ALT2
ALT3
—
GPIO[10]
CS0
B[0]
X[2]
EIRQ[9]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
O
I
Slow Medium 52 81
A[11] PCR[11]
ALT0
ALT1
ALT2
ALT3
—
GPIO[11]
SCK
A[0]
A[2]
EIRQ[10]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
O
I
Slow Medium 53 82
A[12] PCR[12]
ALT0
ALT1
ALT2
ALT3
—
GPIO[12]
SOUT
A[2]
B[2]
EIRQ[11]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
O
O
O
I
Slow Medium 54 83
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 37/103
A[13] PCR[13]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[13]
—
B[2]
—
SIN
FAULT[0]
EIRQ[12]
SIUL
—
FlexPWM_0
—
DSPI_2
FlexPWM_0
SIUL
I/O
—
O
—
I
I
I
Slow Medium 61 95
A[14] PCR[14]
ALT0
ALT1
ALT2
ALT3
—
GPIO[14]
TXD
—
—
EIRQ[13]
SIUL
Safety Port_0
—
—
SIUL
I/O
O
—
—
I
Slow Medium 63 99
A[15] PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[15]
—
—
—
RXD
EIRQ[14]
SIUL
—
—
—
Safety Port_0
SIUL
I/O
—
—
—
I
I
Slow Medium 64 100
Port B (16-bit)
B[0] PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TXD
—
DEBUG[0]
EIRQ[15]
SIUL
FlexCAN_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow Medium 49 76
B[1] PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[17]
—
—
DEBUG[1]
RXD
EIRQ[16]
SIUL
—
—
SSCM
FlexCAN_0
SIUL
I/O
—
—
—
I
I
Slow Medium 50 77
B[2] PCR[18]
ALT0
ALT1
ALT2
ALT3
—
GPIO[18]
TXD
—
DEBUG[2]
EIRQ[17]
SIUL
LIN_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow Medium 51 79
B[3] PCR[19]
ALT0
ALT1
ALT2
ALT3
—
GPIO[19]
—
—
DEBUG[3]
RXD
SIUL
—
—
SSCM
LIN_0
I/O
—
—
—
I
Slow Medium — 80
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
38/103 Doc ID 16100 Rev 5
B[6] PCR[22]
ALT0
ALT1
ALT2
ALT3
—
GPIO[22]
CLKOUT
CS2
—
EIRQ[18]
SIUL
Control
DSPI_2
—
SIUL
I/O
O
O
—
I
Slow Medium 62 96
B[7] PCR[23]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[23]
—
—
—
AN[0]
RXD
SIUL
—
—
—
ADC_0
LIN_0
Input only — — 20 29
B[8] PCR[24]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[24]
—
—
—
AN[1]
ETC[5]
SIUL
—
—
—
ADC_0
eTimer_0
Input only — — 22 31
B[9] PCR[25]
ALT0
ALT1
ALT2
ALT3
—
GPIO[25]
—
—
—
AN[11]
SIUL
—
—
—
ADC_0
Input only — — 24 35
B[10] PCR[26]
ALT0
ALT1
ALT2
ALT3
—
GPIO[26]
—
—
—
AN[12]
SIUL
—
—
—
ADC_0
Input only — — 25 36
B[11] PCR[27]
ALT0
ALT1
ALT2
ALT3
—
GPIO[27]
—
—
—
AN[13]
SIUL
—
—
—
ADC_0
Input only — — 26 37
B[12] PCR[28]
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
—
—
AN[14]
SIUL
—
—
—
ADC_0
Input only — — 27 38
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 39/103
B[13] PCR[29]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[29]
—
—
—
AN[6]
emu. AN[0]
RXD
SIUL
—
—
—
ADC_0
emu. ADC_1(6)
LIN_1
Input only — — 30 42
B[14] PCR[30]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[30]
—
—
—
AN[7]
emu. AN[1]
ETC[4]
EIRQ[19]
SIUL
—
—
—
ADC_0
emu. ADC_1(6)
eTimer_0
SIUL
Input only — — — 44
B[15] PCR[31]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[31]
—
—
—
AN[8]
emu. AN[2]
EIRQ[20]
SIUL
—
—
—
ADC_0
emu. ADC_1(6)
SIUL
Input only — — — 43
Port C (16-bit)
C[0] PCR[32]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[32]
—
—
—
AN[9]
emu. AN[3]
SIUL
—
—
—
ADC_0
emu. ADC_1(6)
Input only — — — 45
C[1] PCR[33]
ALT0
ALT1
ALT2
ALT3
—
GPIO[33]
—
—
—
AN[2]
SIUL
—
—
—
ADC_0
Input only — — 19 28
C[2] PCR[34]
ALT0
ALT1
ALT2
ALT3
—
GPIO[34]
—
—
—
AN[3]
SIUL
—
—
—
ADC_0
Input only — — 21 30
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
40/103 Doc ID 16100 Rev 5
C[3] PCR[35]
ALT0
ALT1
ALT2
ALT3
—
GPIO[35]
CS1
—
TXD
EIRQ[21]
SIUL
DSPI_0
—
LIN_1
SIUL
I/O
O
—
O
I
Slow Medium — 10
C[4] PCR[36]
ALT0
ALT1
ALT2
ALT3
—
GPIO[36]
CS0
X[1]
DEBUG[4]
EIRQ[22]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
I/O
O
—
I
Slow Medium — 5
C[5] PCR[37]
ALT0
ALT1
ALT2
ALT3
—
GPIO[37]
SCK
—
DEBUG[5]
EIRQ[23]
SIUL
DSPI_0
—
SSCM
SIUL
I/O
I/O
—
—
I
Slow Medium — 7
C[6] PCR[38]
ALT0
ALT1
ALT2
ALT3
—
GPIO[38]
SOUT
B[1]
DEBUG[6]
EIRQ[24]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
O
O
—
I
Slow Medium — 98
C[7] PCR[39]
ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
—
A[1]
DEBUG[7]
SIN
SIUL
—
FlexPWM_0
SSCM
DSPI_0
I/O
—
O
—
I
Slow Medium — 9
C[8] PCR[40]
ALT0
ALT1
ALT2
ALT3
GPIO[40]
CS1
—
CS6
SIUL
DSPI_1
—
DSPI_0
I/O
O
—
O
Slow Medium 57 91
C[9] PCR[41]
ALT0
ALT1
ALT2
ALT3
GPIO[41]
CS3
—
X[3]
SIUL
DSPI_2
—
FlexPWM_0
I/O
O
—
O
Slow Medium — 84
C[10] PCR[42]
ALT0
ALT1
ALT2
ALT3
—
GPIO[42]
CS2
—
A[3]
FAULT[1]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium — 78
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 41/103
C[11] PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[4]
CS2
—
SIUL
eTimer_0
DSPI_2
—
I/O
I/O
O
—
Slow Medium 33 55
C[12] PCR[44]
ALT0
ALT1
ALT2
ALT3
GPIO[44]
ETC[5]
CS3
—
SIUL
eTimer_0
DSPI_2
—
I/O
I/O
O
—
Slow Medium 34 56
C[13] PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
—
—
—
EXT_IN
EXT_SYNC
SIUL
—
—
—
CTU_0
FlexPWM_0
I/O
—
—
—
I
I
Slow Medium — 71
C[14] PCR[46]
ALT0
ALT1
ALT2
ALT3
GPIO[46]
—
EXT_TGR
—
SIUL
—
CTU_0
—
I/O
—
O
—
Slow Medium — 72
C[15] PCR[47]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[47]
—
—
A[1]
EXT_IN
EXT_SYNC
SIUL
—
—
FlexPWM_0
CTU_0
FlexPWM_0
I/O
—
—
O
I
I
Slow Medium — 85
Port D (16-bit)
D[0] PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
—
—
B[1]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow Medium — 86
D[1] PCR[49]
ALT0
ALT1
ALT2
ALT3
GPIO[49]
—
—
EXT_TRG
SIUL
—
—
CTU_0
I/O
—
—
O
Slow Medium — 3
D[2] PCR[50]
ALT0
ALT1
ALT2
ALT3
GPIO[50]
—
—
X[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow Medium — 97
D[3] PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
—
—
A[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow Medium — 89
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
42/103 Doc ID 16100 Rev 5
D[4] PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
—
—
B[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow Medium — 90
D[5] PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
CS3
F[0]
—
SIUL
DSPI_0
FCU_0
—
I/O
O
O
—
Slow Medium — 22
D[6] PCR[54]
ALT0
ALT1
ALT2
ALT3
—
GPIO[54]
CS2
—
—
FAULT[1]
SIUL
DSPI_0
—
—
FlexPWM_0
I/O
O
—
—
I
Slow Medium — 23
D[7] PCR[55]
ALT0
ALT1
ALT2
ALT3
GPIO[55]
CS3
F[1]
CS4
SIUL
DSPI_1
FCU_0
DSPI_0
I/O
O
O
O
Slow Medium 17 26
D[8] PCR[56]
ALT0
ALT1
ALT2
ALT3
GPIO[56]
CS2
—
CS5
SIUL
DSPI_1
—
DSPI_0
I/O
O
—
O
Slow Medium 14 21
D[9] PCR[57]
ALT0
ALT1
ALT2
ALT3
GPIO[57]
X[0]
TXD
—
SIUL
FlexPWM_0
LIN_1
—
I/O
O
O
—
Slow Medium 8 15
D[10] PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
A[0]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 53
D[11] PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
B[0]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 54
D[12] PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
X[1]
—
—
RXD
SIUL
FlexPWM_0
—
—
LIN_1
I/O
O
—
—
I
Slow Medium 45 70
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
Doc ID 16100 Rev 5 43/103
D[13] PCR[61]
ALT0
ALT1
ALT2
ALT3
GPIO[61]
A[1]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium 44 67
D[14] PCR[62]
ALT0
ALT1
ALT2
ALT3
GPIO[62]
B[1]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium 46 73
D[15] PCR[63]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[63]
—
—
—
AN[10]
emu. AN[4]
SIUL
—
—
—
ADC_0
emu. ADC_1(6)
Input only — — — 41
Port E (16-bit)
E[1] PCR[65]
ALT0
ALT1
ALT2
ALT3
—
GPIO[65]
—
—
—
AN[4]
SIUL
—
—
—
ADC_0
Input only — — 18 27
E[2] PCR[66]
ALT0
ALT1
ALT2
ALT3
—
GPIO[66]
—
—
—
AN[5]
SIUL
—
—
—
ADC_0
Input only — — 23 32
E[3] PCR[67]
ALT0
ALT1
ALT2
ALT3
—
GPIO[67]
—
—
—
AN[6]
SIUL
—
—
—
ADC_0
Input only — — 30 42
E[4] PCR[68]
ALT0
ALT1
ALT2
ALT3
—
GPIO[68]
—
—
—
AN[7]
SIUL
—
—
—
ADC_0
Input only — — — 44
E[5] PCR[69]
ALT0
ALT1
ALT2
ALT3
—
GPIO[69]
—
—
—
AN[8]
SIUL
—
—
—
ADC_0
Input only — — — 43
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
Package pinouts and signal descriptions SPC560P34L1, SPC560P34L3, SPC560P40L1,
44/103 Doc ID 16100 Rev 5
E[6] PCR[70]
ALT0
ALT1
ALT2
ALT3
—
GPIO[70]
—
—
—
AN[9]
SIUL
—
—
—
ADC_0
Input only — — — 45
E[7] PCR[71]
ALT0
ALT1
ALT2
ALT3
—
GPIO[71]
—
—
—
AN[10]
SIUL
—
—
—
ADC_0
Input only — — — 41
1. ALT0 is the primary (default) function for each port after reset.
2. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 →ALT0;
PCR.PA = 01 →ALT1; PCR.PA = 10 →ALT2; PCR.PA = 11 →ALT3. This is intended to select the output functions; to
use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA
bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
3. Module included on the MCU.
4. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
5. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
6. ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between SPC560P34/SPC560P40
and SPC560P50. Refer to ADC chapter of reference manual for more details.
Table 7. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function(1),
(2)
Functions Peripheral(3)
I/O
direction
(4)
Pad speed(5) Pin
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 45/103
3 Electrical characteristics
3.1 Introduction
This section contains device electrical characteristics as well as temperature and power
considerations.
This microcontroller contains input protection against damage due to high static voltages.
However, it is advisable to take precautions to avoid application of any voltage higher than
the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down resistors, which are provided
by the device for most general purpose pins.
The following tables provide the device characteristics and its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution: All of the following parameter values can vary depending on the application and must be
confirmed during silicon characterization or silicon reliability trial.
3.2 Parameter classification
The electrical parameters are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in
Tabl e 8
are used and the parameters are tagged
accordingly in the tables where appropriate.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Table 8. Parameter classifications
Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
46/103 Doc ID 16100 Rev 5
3.3 Absolute maximum ratings
Table 9. Absolute maximum ratings(1)
Symbol Parameter Conditions
Value
Unit
Min Max(2)
VSS SR Device ground — 0 0 V
VDD_HV_IOx(3) SR
3.3 V/5.0 V input/output supply
voltage (supply).
Code flash memory supply with
VDD_HV_IO3 and data flash
memory with VDD_HV_IO2
—–0.36.0V
VSS_HV_IOx SR
3.3 V/5.0 V input/output supply
voltage (ground).
Code flash memory ground with
VSS_HV_IO3 and data flash
memory with VSS_HV_IO2
—–0.10.1V
VDD_HV_OSC SR 3.3 V/5.0 V crystal oscillator
amplifier supply voltage (supply)
—–0.36.0
V
Relative to VDD_HV_IOx –0.3 VDD_HV_IOx +0.3
VSS_HV_OSC SR 3.3 V/5.0 V crystal oscillator
amplifier supply voltage (ground) —–0.10.1V
VDD_HV_ADC0 SR 3.3 V/5.0 V ADC_0 supply and
high- reference voltage
VDD_HV_REG < 2.7 V –0.3 VDD_HV_REG +0.3 V
VDD_HV_REG > 2.7 V –0.3 6.0
VSS_HV_ADC0 SR 3.3 V/5.0 V ADC_0 ground and
low- reference voltage —–0.10.1V
VDD_HV_REG SR 3.3 V/5.0 V voltage-regulator
supply voltage
—–0.36.0
V
Relative to VDD_HV_IOx –0.3 VDD_HV_IOx +0.3
TVDD SR Slope characteristics on all VDD
during power up(4) — 0.5 250 V/ms
VDD_LV_CORx
C
C
1.2 V supply pins for core logic
(supply) —–0.11.5V
VSS_LV_CORx SR 1.2 V supply pins for core logic
(ground) —–0.10.1V
VIN SR Voltage on any pin with respect
to ground (VSS_HV_IOx)
—–0.36.0
V
Relative to VDD_HV_IOx –0.3 VDD_HV_IOx +0.3
(5)
IINJPAD SR Input current on any pin during
overload condition — –10 10 mA
IINJSUM SR Absolute sum of all input currents
during overload condition — –50 50 mA
TSTG SR Storage temperature — –55 150 °C
TJSR Junction temperature under bias — −40 150 °C
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 47/103
Figure 6
shows the constraints of the different power supplies.
Figure 6. Power supplies constraints (–0.3 V ≤VDD_HV_IOx ≤6.0 V)
The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard VDD_HV supply.
Figure 7
shows the constraints of the ADC
power supply.
2. Absolute maximum voltages are currently maximum burn-in voltages.
3. The difference between each couple of voltage supplies must be less than 300 mV, ⏐VDD_HV_IOy –V
DD_HV_IOx⏐< 300 mV.
4. Guaranteed by device validation.
5. Only when VDD_HV_IOx < 5.2 V.
VDD_HV_xxx
VDD_HV_IOx
–0.3 V
6.0 V
–0.3 V 6.0 V
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
48/103 Doc ID 16100 Rev 5
Figure 7. Independent ADC supply (–0.3 V ≤VDD_HV_REG ≤6.0 V)
3.4 Recommended operating conditions
VDD_HV_ADCx
6.0 V
VDD_HV_REG
–0.3 V
2.7 V
–0.3 V 6.0 V
Table 10. Recommended operating conditions (5.0 V)
Symbol Parameter Conditions
Value
Unit
Min Max(1)
VSS SR Device ground — 0 0 V
VDD_HV_IOx(2) SR 5.0 V input/output supply
voltage —4.5 5.5V
VSS_HV_IOx SR Input/output ground
voltage —0 0V
VDD_HV_OSC SR 5.0 V crystal oscillator
amplifier supply voltage
—4.5 5.5
V
Relative to
VDD_HV_IOx
VDD_HV_IOx –0.1 V
DD_HV_IOx +0.1
VSS_HV_OSC SR
5.0 V crystal oscillator
amplifier reference
voltage
—0 0V
VDD_HV_REG SR 5.0 V voltage regulator
supply voltage
—4.5 5.5
V
Relative to
VDD_HV_IOx
VDD_HV_IOx –0.1 V
DD_HV_IOx +0.1
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 49/103
VDD_HV_ADC0 SR 5.0 V ADC_0 supply and
high reference voltage
—4.5 5.5
V
Relative to
VDD_HV_REG
VDD_HV_REG –0.1 —
VSS_HV_ADC0 SR ADC_0 ground and low
reference voltage —0 0V
VDD_LV_REGCOR(3)
,(4) CC Internal supply voltage — — — V
VSS_LV_REGCOR(3) SR Internal reference voltage — 0 0 V
VDD_LV_CORx3,4 CC Internal supply voltage — — — V
VSS_LV_CORx3SR Internal reference voltage — 0 0 V
TASR Ambient temperature
under bias
fCPU =60MHz −40 125 °C
fCPU =64MHz −40 105 °C
1. Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, ⏐VDD_HV_IOy –
VDD_HV_IOx⏐< 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on-
chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
– VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
– VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 10. Recommended operating conditions (5.0 V) (continued)
Symbol Parameter Conditions
Value
Unit
Min Max(1)
Table 11. Recommended operating conditions (3.3 V)
Symbol Parameter Conditions
Value
Unit
Min Max(1)
VSS SR Device ground — 0 0 V
VDD_HV_IOx(2) SR 3.3 V input/output supply
voltage —3.0 3.6V
VSS_HV_IOx SR Input/output ground
voltage —0 0V
VDD_HV_OSC SR 3.3 V crystal oscillator
amplifier supply voltage
—3.0 3.6
V
Relative to
VDD_HV_IOx
VDD_HV_IOx –0.1 V
DD_HV_IOx +0.1
VSS_HV_OSC SR
3.3 V crystal oscillator
amplifier reference
voltage
—0 0V
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
50/103 Doc ID 16100 Rev 5
Figure 8
shows the constraints of the different power supplies.
VDD_HV_REG SR 3.3 V voltage regulator
supply voltage
—3.0 3.6
V
Relative to
VDD_HV_IOx
VDD_HV_IOx –0.1 V
DD_HV_IOx +0.1
VDD_HV_ADC0 SR 3.3 V ADC_0 supply and
high reference voltage
—3.0 5.5
V
Relative to
VDD_HV_REG
VDD_HV_REG −0.1 5.5
VSS_HV_ADC0 SR ADC_0 ground and low
reference voltage —0 0V
VDD_LV_REGCOR(3)
,(4) CC Internal supply voltage — — — V
VSS_LV_REGCOR(3) SR Internal reference voltage — 0 0 V
VDD_LV_CORx(3),(4) CC Internal supply voltage — — — V
VSS_LV_CORx(3) SR Internal reference voltage — 0 0 V
TASR Ambient temperature
under bias
fCPU =60MHz −40 125 °C
fCPU =64MHz −40 105 °C
1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, ⏐VDD_HV_IOy –
VDD_HV_IOx⏐< 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on-
chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
– VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
– VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11. Recommended operating conditions (3.3 V) (continued)
Symbol Parameter Conditions
Value
Unit
Min Max(1)
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 51/103
Figure 8. Power supplies constraints(a) (3.0 V ≤VDD_HV_IOx ≤5.5 V)
The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard VDD_HV supply.
Figure 9
shows the constraints of the ADC
power supply.
Figure 9. Independent ADC supply (3.0 V ≤VDD_HV_REG ≤5.5 V)
a. IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when PAD3V5V is low, and in the range of
4.5–5.5 V when PAD3V5V is high.
VDD_HV_xxx
VDD_HV_IOx
3.0 V
5.5 V
3.0 V 5.5 V
3.3 V
3.3 V
5.5 V
3.0 V
VDD_HV_REG
3.0 V 5.5 V
VDD_HV_ADCx
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
52/103 Doc ID 16100 Rev 5
3.5 Thermal characteristics
3.5.1 Package thermal characteristics
3.5.2 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from
Equation 1
:
Equation 1 TJ = TA + (RθJA * PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in
Equation 2
as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance:
Table 12. LQFP thermal characteristics
Symbol Parameter Conditions
Typical value
Unit
100-pin 64-pin
RθJA
Thermal resistance junction-to-ambient, natural
convection(1)
Single layer board—1s 63 57 °C/W
Four layer board—2s2p 51 41 °C/W
RθJB Thermal resistance junction-to-board(2) Four layer board—2s2p 33 22 °C/W
RθJCtop Thermal resistance junction-to-case (top)(3) Single layer board—1s 15 13 °C/W
ΨJB Junction-to-board, natural convection(4) Operating conditions 33 22 °C/W
ΨJC Junction-to-case, natural convection(5) Operating conditions 1 1 °C/W
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package. When Greek letters are not available, the symbols are typed as RthJB or Theta-JB.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JC.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 53/103
Equation 2 RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case-to-ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case-to-ambient thermal resistance, RθCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using
Equation 3
:
Equation 3 TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at (800) 854-7179 or (303) 397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner,
An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module
, Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison,
Thermal Modeling of a PBGA for Air-Cooled
Applications
, Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams,
Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling
, Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
54/103 Doc ID 16100 Rev 5
3.6 Electromagnetic interference (EMI) characteristics
3.7 Electrostatic discharge (ESD) characteristics
3.8 Power management electrical characteristics
3.8.1 Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast, approved ballast list
availbale in
Ta bl e 1 5
, to be connected as shown in
Figure 10
. Capacitances should be
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than
LReg (refer to
Figure 16
).
Table 13. EMI testing specifications
Symbol Parameter Conditions Clocks Frequency Level
(Typ) Unit
VEME
Radiated
emissions
VDD = 5.0 V; TA=25°C
Other device configuration,
test conditions and EM
testing per standard
IEC61967-2
fOSC =8MHz
fCPU =64MHz
No PLL frequency
modulation
150 kHz–150 MHz 11 dBµV
150–1000 MHz 13
IEC level M —
fOSC =8MHz
fCPU =64MHz
±4% PLL frequency
modulation
150 kHz–150 MHz 8 dBµV
150–1000 MHz 12
IEC level N —
VDD = 3.3 V; TA=25°C
Other device configuration,
test conditions and EM
testing per standard
IEC61967-2
fOSC =8MHz
fCPU =64MHz
No PLL frequency
modulation
150 kHz–150 MHz 9 dBµV
150–1000 MHz 12
IEC level M —
fOSC =8MHz
fCPU =64MHz
±4% PLL frequency
modulation
150 kHz–150 MHz 7 dBµV
150–1000 MHz 12
IEC level N —
Table 14. ESD ratings(1),(2)
Symbol Parameter Conditions Value Unit
VESD(HBM) SR Electrostatic discharge (Human Body Model) — 2000 V
VESD(CDM) SR Electrostatic discharge (Charged Device Model) — 750 (corners) V
500 (other)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 55/103
Note: The voltage regulator output cannot be used to drive external circuits. Output pins are to be
used only for decoupling capacitance.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is not
possible to provide VDD_LV_COR through external regulator.
For the SPC560P34/SPC560P40 microcontroller, capacitor(s), with total values not below
CDEC1, should be placed between VDD_LV_CORx/VSS_LV_CORx close to external ballast
transistor emitter. 4 capacitors, with total values not below CDEC2, should be placed close to
microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair. Additionally, capacitor(s) with total values not below
CDEC3, should be placed between the VDD_HV_REG/VSS_HV_REG pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.
All reported information are valid for voltage and temperature ranges described in
recommended operating condition,
Tabl e 1 0
and
Ta bl e 1 1
.
Figure 10. Voltage regulator configuration
Table 15. Approved NPN ballast components
Part Manufacturer Approved derivatives(1)
BCP68
ON Semi BCP68
NXP BCP68-25
Infineon BCP68-25
BCX68 Infineon BCX68-10; BCX68-16; BCX-25
BC868 NXP BC868
BC817 Infineon BC817-16; BC817-25; BC817SU
NXP BC817-16; BC817-25
BCTRL
VDD_LV_COR
CDEC3
CDEC2 CDEC1
VDD_HV_REG
BJT(1)
SPC560P34/SPC560P40
1. Refer to
Table 15
.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
56/103 Doc ID 16100 Rev 5
3.8.2 Voltage monitor electrical characteristics
The device implements a power on reset module to ensure correct power-up initialization, as
well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while device
is supplied:
●POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state
●LVDHV3 monitors VDD to ensure device reset below minimum functional supply
●LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range
●LVDLVCOR monitors low voltage digital power domain
BCP56
ST BCP56-16
Infineon BCP56-10; BCP56-16
ON Semi BCP56-10
NXP BCP56-10; BCP56-16
1. For automotive applications please check with the appropriate transistor vendor for automotive grade
certification
Table 15. Approved NPN ballast components (continued)
Part Manufacturer Approved derivatives(1)
Table 16. Voltage regulator electrical characteristics
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
VDD_LV_REGCOR CC P
Output voltage under
maximum load run
supply current
configuration
Post-trimming 1.15 — 1.32 V
CDEC1 SR —
External
decoupling/stability
ceramic capacitor
BJT from
Ta b l e 1 5
. Three
capacitors (i.e. X7R or X8R
capacitors) with nominal value
of 10 µF
19.5 30 — µF
BJT BC817, one capacitance of
22 µF 14.3 22 — µF
RREG SR — Resulting ESR of either
one or all three CDEC1
Absolute maximum value
between 100 kHz and 10 MHz ——45mΩ
CDEC2 SR —
External
decoupling/stability
ceramic capacitor
Four capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 440 nF
1200 1760 — nF
CDEC3 SR —
External
decoupling/stability
ceramic capacitor on
VDD_HV_REG
Three capacitors (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to be
equal or greater than CDEC1
19.5 30 — µF
LReg SR —
Resulting ESL of
VDD_HV_REG, BCTRL
and VDD_LV_CORx pins
———5nH
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 57/103
3.9 Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the
SPC560P34/SPC560P40 implements the following sequence to ensure each module is
started only when all conditions for switching it ON are available:
●A POWER_ON module working on voltage regulator supply controls the correct start-
up of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5 V. Associated POWER_ON (or POR)
signal is active low.
●Several low voltage detectors, working on voltage regulator supply monitor the voltage
of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain).
LVDs are gated low when POWER_ON is active.
●A POWER_OK signal is generated when all critical supplies monitored by the LVD are
available. This signal is active high and released to all modules including I/Os, flash
memory and 16 MHz RC oscillator needed during power-up phase and reset phase.
When POWER_OK is low the associated modules are set into a safe state.
Table 17. Low voltage monitor electrical characteristics
Symbol C Parameter Conditions(1) Value
Unit
Min Max
VPORH T Power-on reset threshold — 1.5 2.7 V
VPORUP P Supply for functional POR module TA = 25 °C 1.0 — V
VREGLVDMOK_H P Regulator low voltage detector high threshold — — 2.95 V
VREGLVDMOK_L P Regulator low voltage detector low threshold — 2.6 — V
VFLLVDMOK_H P Flash low voltage detector high threshold — — 2.95 V
VFLLVDMOK_L P Flash low voltage detector low threshold — 2.6 — V
VIOLVDMOK_H P I/O low voltage detector high threshold — — 2.95 V
VIOLVDMOK_L P I/O low voltage detector low threshold — 2.6 — V
VIOLVDM5OK_H P I/O 5 V low voltage detector high threshold — — 4.4 V
VIOLVDM5OK_L P I/O 5 V low voltage detector low threshold — 3.8 — V
VMLVDDOK_H P Digital supply low voltage detector high — — 1.145 V
VMLVDDOK_L P Digital supply low voltage detector low — 1.08 — V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to TA MAX, unless otherwise specified.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
58/103 Doc ID 16100 Rev 5
Figure 11. Power-up typical sequence
Figure 12. Power-down typical sequence
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR
0V
1.2V
0V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK 3.3V
RC16MHz Oscillator
0V
1.2V
P0 P1 0V
1.2V
Internal Reset Generation Module
FSM
~1us
VPOR_UP
VPORH
VLVDHV3H
VMLVDOK_H
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR 0V
1.2V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0IDLE 0V
1.2V
Internal Reset Generation Module
FSM
VLVDHV3L VPORH
0V
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 59/103
Figure 13. Brown-out typical sequence
3.10 DC electrical characteristics
3.10.1 NVUSRO register
Portions of the device configuration, such as high voltage supply and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
(NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value.
Ta bl e 1 8
shows
how NVUSRO[PAD3V5V] controls the device configuration.
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR 0V
1.2V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0IDLE 0V
1.2V
Internal Reset Generation Module
FSM
VLVDHV3L
0V
VLVDHV3H
P1
~1us
Table 18. PAD3V5V field description
Value(1)
1. Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Description
0 High voltage supply is 5.0 V
1 High voltage supply is 3.3 V
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
60/103 Doc ID 16100 Rev 5
3.10.2 DC electrical characteristics (5 V)
Ta bl e 1 9
gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V,
NVUSRO[PAD3V5V] = 0).
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol C Parameter Conditions
Value
Unit
Min Max
VIL
DLow level input voltage —−0.4(1) —V
P——0.35V
DD_HV_IOx V
VIH
PHigh level input voltage —0.65V
DD_HV_IOx —V
D——V
DD_HV_IOx +0.4
(1) V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx —V
VOL_S PSlow, low level output
voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_S PSlow, high level output
voltage IOH =−3mA 0.8V
DD_HV_IOx —V
VOL_M PMedium, low level output
voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_M PMedium, high level output
voltage IOH =−3mA 0.8V
DD_HV_IOx —V
VOL_F PFast, low level output
voltage IOL =14mA — 0.1V
DD_HV_IOx V
VOH_F PFast, high level output
voltage IOH =−14 mA 0.8 VDD_HV_IOx —V
IPU P Equivalent pull-up current VIN =V
IL −130 — µA
VIN =V
IH —−10
IPD P Equivalent pull-down current VIN =V
IL 10 — µA
VIN =V
IH —130
IIL PInput leakage current
(all bidirectional ports) TA = −40 to 125 °C −11µA
IIL PInput leakage current
(all ADC input-only ports) TA = −40 to 125 °C −0.5 0.5 µA
CIN D Input capacitance — — 10 pF
1. “SR” parameter values must not exceed the absolute maximum ratings shown in
Table 9
.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 61/103
3.10.3 DC electrical characteristics (3.3 V)
Ta bl e 2 1
gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V,
NVUSRO[PAD3V5V] = 1); see
Figure 14
.
Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol C Parameter Conditions
Value(1)
Unit
Typ Max
IDD_LV_CORx
T
Supply current
RUN—Maximum mode(2)
VDD_LV_CORx externally
forced at 1.3 V
40 MHz 44 55
mA
P 64 MHz 52 65
T RUN—Typical mode(3) 40 MHz 38 46
64 MHz 45 54
PHALT mode(4) —1.510
STOP mode(5) —110
IDD_FLASH T
Flash during read VDD_HV_FL at 5.0 V — 8 10
Flash during erase
operation on 1 flash module VDD_HV_FL at 5.0 V — 15 19
IDD_ADC TADC VDD_HV_ADC0 at 5.0 V
fADC =16MHz ADC_0 3 4
IDD_OSC T Oscillator VDD_HV_OSC at 5.0 V 8 MHz 2.6 3.2
1. All values to be confirmed after characterization/data collection.
2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.
3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.
4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)(1)
Symbol C Parameter Conditions
Value
Unit
Min Max
VIL
DLow level input voltage —−0.4(2) —V
P——0.35V
DD_HV_IOx V
VIH
PHigh level input voltage —0.65V
DD_HV_IOx —V
D——V
DD_HV_IOx +0.4
(2) V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx —V
VOL_S P Slow, low level output voltage IOL = 1.5 mA — 0.5 V
VOH_S P Slow, high level output voltage IOH =−1.5 mA VDD_HV_IOx − 0.8 — V
VOL_M P Medium, low level output voltage IOL =2mA — 0.5 V
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
62/103 Doc ID 16100 Rev 5
VOH_M PMedium, high level output
voltage IOH =−2mA V
DD_HV_IOx − 0.8 — V
VOL_F P Fast, low level output voltage IOL =11mA — 0.5 V
VOH_F P Fast, high level output voltage IOH =−11 mA VDD_HV_IOx − 0.8 — V
IPU P Equivalent pull-up current VIN =V
IL −130 — µA
VIN =V
IH —−10
IPD P Equivalent pull-down current VIN =V
IL 10 — µA
VIN =V
IH —130
IIL PInput leakage current (all
bidirectional ports)
TA=−40 to
125 °C —1µA
IIL PInput leakage current (all ADC
input-only ports)
TA=−40 to
125 °C —0.5µA
CIN D Input capacitance — — 10 pF
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in
Table 9
.
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)(1) (continued)
Symbol C Parameter Conditions
Value
Unit
Min Max
Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)
Symbol C Parameter Conditions
Value(1)
Unit
Typ Max
IDD_LV_CORx
T
Supply current
RUN—Maximum mode(2)
VDD_LV_CORx externally
forced at 1.3 V
40 MHz 44 55
mA
64 MHz 52 65
RUN—Typical mode(3) 40 MHz 38 46
64 MHz 45 54
PHALT mode(4) —1.510
STOP mode(5) —110
IDD_ADC TADC VDD_HV_ADC0 at 3.3 V
fADC =16MHz ADC_0 3 4
IDD_OSC T Oscillator VDD_HV_OSC at 3.3 V 8 MHz 2.6 3.2
1. All values to be confirmed after characterization/data collection.
2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.
3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.
4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 63/103
3.10.4 Input DC electrical characteristics definition
Figure 14
shows the DC electrical characteristics behavior as function of time.
Figure 14. Input DC electrical characteristics definition
3.10.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in
Ta bl e 2 3
.
VIL
VIN
VIH
PDIx = ‘1’
VDD
VHYS
(GPDI register of SIUL)
PDIx = ‘0’
Table 23. I/O supply segment
Package
Supply segment
12345
LQFP100 pin15–pin26 pin27–pin46 pin51–pin61 pin64–pin86 pin89–pin10
LQFP64 pin8–pin17 pin18–pin30 pin33–pin38 pin41–pin54 pin57–pin5
Table 24. I/O consumption
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
ISWTSLW(2) C
CD
Dynamic I/O current
for SLOW
configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——20
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——16
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
64/103 Doc ID 16100 Rev 5
3.11 Main oscillator electrical characteristics
The SPC560P34/SPC560P40 provides an oscillator/resonator driver.
ISWTMED(2) C
CD
Dynamic I/O current
for MEDIUM
configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——29
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——17
ISWTFST(2) C
CD
Dynamic I/O current
for FAST
configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——110
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——50
IRMSSLW
C
CD
Root medium
square I/O current
for SLOW
configuration
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
——2.3
mA
CL = 25 pF, 4 MHz — — 3.2
CL = 100 pF, 2 MHz — — 6.6
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——1.6
CL = 25 pF, 4 MHz — — 2.3
CL = 100 pF, 2 MHz — — 4.7
IRMSMED
C
CD
Root medium
square I/O current
for MEDIUM
configuration
CL = 25 pF, 13 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
——6.6
mA
CL = 25 pF, 40 MHz — — 13.4
CL = 100 pF, 13 MHz — — 18.3
CL = 25 pF, 13 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——5
CL = 25 pF, 40 MHz — — 8.5
CL = 100 pF, 13 MHz — — 11
IRMSFST
C
CD
Root medium
square I/O current
for FAST
configuration
CL = 25 pF, 40 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
——22
mA
CL = 25 pF, 64 MHz — — 33
CL = 100 pF, 40 MHz — — 56
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——14
CL = 25 pF, 64 MHz — — 20
CL = 100 pF, 40 MHz — — 35
IAVGSEG
S
RD
Sum of all the static
I/O current within a
supply segment
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70
mA
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 24. I/O consumption (continued)
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 65/103
Table 25. Main oscillator output electrical characteristics (5.0 V,
NVUSRO[PAD3V5V] = 0)
Symbol C Parameter Conditions
Value
Unit
Min Max
fOSC SR — Oscillator frequency 4 40 MHz
gm— P Transconductance 6.5 25 mA/V
VOSC — T Oscillation amplitude on XTAL pin 1 — V
tOSCSU — T Start-up time(1),(2)
1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL.
8—ms
CLCC
T
XTAL load capacitance(3)
3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.
4MHz 5 30
pf
T8MHz526
T12MHz523
T16MHz519
T20MHz516
T40MHz58
Table 26. Main oscillator output electrical characteristics (3.3 V,
NVUSRO[PAD3V5V] = 1)
Symbol C Parameter Conditions
Value
Unit
Min Max
fOSC SR — Oscillator frequency 4 40 MHz
gm— P Transconductance 4 20 mA/V
VOSC — T Oscillation amplitude on XTAL pin 1 — V
tOSCSU — T Start-up time(1),(2)
1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL.
8—ms
CLCC
T
XTAL load capacitance(3)
3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.
4MHz 5 30
pf
T8MHz526
T12MHz523
T16MHz519
T20MHz516
T40MHz58
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
66/103 Doc ID 16100 Rev 5
3.12 FMPLL electrical characteristics
Table 27. Input clock characteristics
Symbol Parameter
Value
Unit
Min Typ Max
fOSC SR Oscillator frequency 4 — 40 MHz
fCLK SR Frequency in bypass — — 64 MHz
trCLK SR Rise/fall time in bypass — — 1 ns
tDC SR Duty cycle 47.5 50 52.5 %
Table 28. FMPLL electrical characteristics
Symbol C Parameter Conditions(1) Value
Unit
Min Max
fref_crystal
fref_ext
D PLL reference frequency range(2) Crystal reference 4 40 MHz
fPLLIN DPhase detector input frequency range
(after pre-divider) —416MHz
fFMPLLOUT D Clock frequency range in normal mode — 16 64 MHz
fFREE P Free-running frequency Measured using clock
division—typically /16 20 150 MHz
tCYC D System clock period — — 1 / fSYS ns
fLORL DLoss of reference frequency window(3) Lower limit 1.6 3.7 MHz
fLORH D Upper limit 24 56
fSCM D Self-clocked mode frequency(4),(5) —20150MHz
CJITTER TCLKOUT period
jitter(6),(7),(8),(9)
Short-term jitter(10) fSYS maximum −44%f
CLKOUT
Long-term jitter
(average over 2 ms
interval)
fPLLIN =16MHz
(resonator), fPLLCLK at
64 MHz, 4000 cycles
—10 ns
tlpll DPLL lock time
(11), (12) ——200µs
tdc D Duty cycle of reference — 40 60 %
fLCK D Frequency LOCK range — −66%f
SYS
fUL D Frequency un-LOCK range — −18 18 % fSYS
fCS DModulation depth Center spread ±0.25 ±4.0
(13) %f
SYS
fDS DDown spread−0.5 −8.0
fMOD D Modulation frequency(14) ——70kHz
1. VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified.
2. Considering operation with PLL not bypassed.
3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 67/103
3.13 16 MHz RC oscillator electrical characteristics
3.14 Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital
converter.
4. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
5. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
6. This value is determined by the crystal manufacturer and board design.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDD_LV_COR0 and VSS_LV_COR0 and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
8. Proper PC board layout procedures must be followed to achieve specifications.
9. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER
and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
13. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 29. 16 MHz RC oscillator electrical characteristics
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
fRC P RC oscillator frequency TA = 25 °C — 16 — MHz
ΔRCMVAR P
Fast internal RC oscillator variation over
temperature and supply with respect to fRC at
TA= 25 °C in high-frequency configuration
—−5— 5%
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
68/103 Doc ID 16100 Rev 5
Figure 15. ADC characteristics and error definitions
3.14.1 Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high-frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; it
sources charge during the sampling phase, when the analog signal source is a high-
impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.
(2)
(1)
(3)
(4)
(5)
Offset Error (EO)
Offset Error (EO)
Gain Error (EG)
1 LSB (ideal)
1023
1022
1021
1020
1019
1018
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
1 LSB ideal = VDD_ADC / 1024
Vin(A) (LSBideal)
code out
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 69/103
The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS being substantially a switched capacitance, with a frequency
equal to the ADC conversion rate, it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is
obtained (REQ = 1 / (fc × CS), where fc represents the conversion rate at the considered
channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the
Equation 4
:
Equation 4
Equation 4
generates a constraint for external network design, in particular on resistive path.
Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
Figure 16. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF
, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in
Figure 16
): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch closed).
VA
RSRFRLRSW RAD
+++ +
REQ
---------------------------------------------------------------------------
•1
2
---LSB
<
RF
CF
RSRLRSW1
CP2 CS
VDD
Sampling
Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
CP1
RAD
Channel
Selection
VA
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
70/103 Doc ID 16100 Rev 5
Figure 17. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
●A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
Equation 5
can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time ts is always
much longer than the internal time constant:
Equation 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of
the voltage VA1 on the capacitance according to
Equation 7
:
Equation 7
●A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
VA
VA1
VA2
t
ts
VCS Voltage Transient on CS
ΔV < 0.5 LSB
12
τ1 < (RSW + RAD) CS << ts
τ
2
= R
L
(C
S
+ C
P1
+ C
P2
)
τ1RSW RAD
+()=
CPCS
•
CPCS
+
----------------------
•
τ1RSW RAD
+()<CSts
«•
VA1 CSCP1 CP2
++()•VACP1 CP2
+()•=
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 71/103
Equation 8
In this case, the time constant depends on the external circuit: in particular
imposing that the transient is completed well before the end of sampling time ts, a
constraints on RL sizing is obtained:
Equation 9
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of
the charge transfer transient) will be much higher than VA1.
Equation 10
must be
respected (charge balance assuming now CS already charged at VA1):
Equation 10
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (ts). The filter is typically designed to act as anti-aliasing.
Figure 18. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period tc is longer than the sampling time
ts, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time ts, so the
τ2RL
<CSCP1 CP2
++()•
10 τ2
•10 RLCSCP1 CP2
++()••=ts
<
VA2 CSCP1 CP2 CF
+++()•VACF
•VA1
+C
P1 CP2
+C
S
+()•=
f0
f
Analog Source Bandwidth (VA)
f0
f
Sampled Signal Spectrum (fC = conversion Rate)
fC
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
2 f0 ≤ fC
(Nyquist)
fF = f0
(Anti-aliasing Filtering Condition)
tc
≤ 2 RFCF
(Conversion Rate vs. Filter Pole)
Noise
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
72/103 Doc ID 16100 Rev 5
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive
Equation 11
between the ideal and real sampled voltage on CS:
Equation 11
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
Equation 12
3.14.2 ADC conversion characteristics
VA
VA2
------------
CP1 CP2
+C
F
+
CP1 CP2
+C
FCS
++
--------------------------------------------------------=
CF2048 CS
•>
Table 30. ADC conversion characteristics
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
fCK
S
R—
ADC clock frequency (depends on
ADC configuration)
(The duty cycle depends on ADC
clock(2) frequency)
—3
(3) —60MHz
fs
S
R— Sampling frequency — — — 1.53 MHz
ts— D Sampling time(4) fADC = 20 MHz, INPSAMP = 3 125 — — ns
fADC = 9 MHz, INPSAMP = 255 — — 28.2 µs
tc— P Conversion time(5) fADC = 20 MHz(6), INPCMP = 1 0.65
0——µs
tADC_PU
S
R—
ADC power-up delay (time needed
for ADC to settle exiting from
software power down; PWDN bit = 0)
———1.5µs
CS(7) — D ADC input sampling capacitance — — — 2.5 pF
CP1(7) — D ADC input pin capacitance 1 — — — 3 pF
CP2(7) — D ADC input pin capacitance 2 — — — 1 pF
RSW1(7) — D Internal resistance of analog source VDD_HV_ADC0 = 5 V ± 10% — — 0.6 kΩ
VDD_HV_ADC0 = 3.3 V ± 10% — — 3 kΩ
RAD(7) — D Internal resistance of analog source — — — 2 kΩ
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 73/103
3.15 Flash memory electrical characteristics
3.15.1 Program/Erase characteristics
IINJ — T Input current injection
Current injection on one ADC
input, different from the
converted one. Remains
within TUE specification
-5 — 5 mA
INL C
CP Integral non-linearity No overload −1.5 — 1.5 LSB
DNL C
CP Differential non-linearity No overload −1.0 — 1.0 LSB
EO
C
CT Offset error — — ±1 — LSB
EG
C
CT Gain error — — ±1 — LSB
TUE C
CPTotal unadjusted error without
current injection —-2.5—2.5LSB
TUE C
CTTotal unadjusted error with current
injection —−3— 3LSB
1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = −40 °C to TA MAX, unless otherwise specified and analog input voltage from
VSS_HV_ADC0 to VDD_HV_ADC0.
2. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which the precision is lost.
4. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of the
sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock
ts depend on programming.
5. This parameter includes the sampling time ts.
6. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
7. See
Figure 16
.
Table 30. ADC conversion characteristics (continued)
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
Table 31. Program and erase specifications
Symbol C Parameter
Value
Unit
Min Typ(1) Initial
Max(2) Max(3)
Twprogram P Word Program Time for data flash memory(4) —3070500µs
Tdwprogram P Double Word Program Time for code flash memory(4) —2250500µs
TBKPRG
P Bank Program (256 KB)4(5) — 0.73 0.83 17.5 s
P Bank Program (64 KB)(4)(5) —0.491.24.1s
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
74/103 Doc ID 16100 Rev 5
T16kpperase P
16 KB Block Pre-program and Erase Time for code
flash memory — 300 500 5000
ms
16 KB Block Pre-program and Erase Time for data
flash memory — 700 800 5000
T32kpperase P 32 KB Block Pre-program and Erase Time — 400 600 5000 ms
T128kpperase P 128 KB Block Pre-program and Erase Time — 800 1300 7500 ms
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see “Initial Max” column).
Table 31. Program and erase specifications (continued)
Symbol C Parameter
Value
Unit
Min Typ(1) Initial
Max(2) Max(3)
Table 32. Flash memory module life
Symbol C Parameter Conditions
Value
Unit
Min Typ
P/E C
Number of program/erase cycles per
block for 16 KB blocks over the
operating temperature range (TJ)
— 100000 — cycles
P/E C
Number of program/erase cycles per
block for 32 KB blocks over the
operating temperature range (TJ)
— 10000 100000 cycles
P/E C
Number of program/erase cycles per
block for 128 KB blocks over the
operating temperature range (TJ)
— 1000 100000 cycles
Retention C Minimum data retention at 85 °C
average ambient temperature(1)
Blocks with 0–1000 P/E cycles 20 — years
Blocks with 10000 P/E cycles 10 — years
Blocks with 100000 P/E cycles 5 — years
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
Table 33. Flash memory read access timing
Symbol C Parameter Conditions(1) Max value Unit
fmax CMaximum working frequency for code flash memory at given
number of wait states in worst conditions
2 wait states 66 MHz
0 wait states 18
fmax CMaximum working frequency for data flash memory at given
number of wait states in worst conditions 8 wait states 66 MHz
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 75/103
3.15.2 Flash memory power supply DC characteristics
Table 34.
shows the power supply DC characteristics on external supply.
3.15.3 Start-up/Switch-off timings
Table 34. Flash memory power supply DC electrical characteristics
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
IFLPW
C
CDSum of the current consumption on VDD_HV_IOx
and VDD_LV_CORx during low-power mode Code flash memory — — 900 µA
IFPWD
C
CDSum of the current consumption on VDD_HV_IOx
and VDD_LV_CORx during power-down mode
Code flash memory — — 150 µA
Data flash memory — — 150
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Table 35. Start-up time/Switch-off time
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
TFLARSTEXIT
C
C
TDelay for Flash module to exit reset mode Code flash memory — — 125
µs
T Data flash memory — — 125
TFLALPEXIT
C
CDDelay for Flash module to exit low-power
mode Code flash memory — — 0.5
TFLAPDEXIT
C
C
TDelay for Flash module to exit power-down
mode
Code flash memory — — 30
T Data flash memory — — 30
TFLALPENTRY
C
CDDelay for Flash module to enter low-power
mode Code flash memory — — 0.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
76/103 Doc ID 16100 Rev 5
3.16 AC specifications
3.16.1 Pad AC specifications
Table 36. Output pin transition times
Symbol C Parameter Conditions(1) Value
Unit
Min Typ Max
ttr CC
D
Output transition time output pin(2)
SLOW configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
——50
ns
TC
L = 50 pF — — 100
DC
L = 100 pF — — 125
DC
L = 25 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——40
TC
L = 50 pF — — 50
DC
L = 100 pF — — 75
ttr CC
D
Output transition time output pin(2)
MEDIUM configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
——10
ns
TC
L = 50 pF — — 20
DC
L = 100 pF — — 40
DC
L = 25 pF VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
——12
TC
L = 50 pF — — 25
DC
L = 100 pF — — 40
ttr CC D Output transition time output pin(2)
FAST configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
—— 4
ns
CL = 50 pF — — 6
CL = 100 pF — — 12
CL = 25 pF VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
—— 4
CL = 50 pF — — 7
CL = 100 pF — — 12
tSYM
(3) CC T Symmetric transition time, same drive
strength between N and P transistor
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 4 ns
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to TA MAX, unless otherwise specified.
2. CL includes device and package capacitances (CPKG < 5 pF).
3. Transition timing of both positive and negative slopes will differ maximum 50%.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 77/103
Figure 19. Pad output delay
3.17 AC timing characteristics
3.17.1 RESET pin characteristics
The SPC560P34/SPC560P40 implements a dedicated bidirectional RESET pin.
Figure 20. Start-up reset requirements
VDD_HV_IOx/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
VIL
VDD
device reset forced by VRESET
VDDMIN
VRESET
VIH
device start-up phase
tPOR
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
78/103 Doc ID 16100 Rev 5
Figure 21. Noise filtering on reset signal
VRESET
VIL
VIH
VDD
filtered by
hysteresis
filtered by
lowpass filter
WFRST
WNFRST
hw_rst
‘1’
‘0’
filtered by
lowpass filter
WFRST
unknown reset
state device under hardware reset
Table 37. RESET electrical characteristics
Symbol C Parameter Conditions(1) Value(2)
Unit
Min Typ Max
VIH
S
RP
Input high level
CMOS
(Schmitt Trigger)
—0.65V
DD —V
DD +0.4 V
VIL
S
RPInput low level CMOS
(Schmitt Trigger) —−0.4 — 0.35VDD V
VHYS
C
CC
Input hysteresis
CMOS
(Schmitt Trigger)
—0.1V
DD ——V
VOL
C
CP Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
——0.1V
DD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V =
1(3)
——0.1V
DD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——0.5
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 79/103
ttr
C
CD
Output transition time
output pin(4)
MEDIUM
configuration
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 ——10
ns
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 ——20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 ——40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——40
WFRST
S
RPRESET input filtered
pulse ———40ns
WNFRS
T
S
RP
RESET input not
filtered
pulse
— 500 — — ns
tPOR
C
CD
Maximum delay
before internal reset
is released after all
VDD_HV reach
nominal supply
Monotonic VDD_HV supply ramp — — 1 ms
|IWPU|C
CPWeak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150
VDD = 5.0 V ± 10%, PAD3V5V =
1(5) 10 — 250
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).
4. CL includes device and package capacitance (CPKG <5pF).
5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 37. RESET electrical characteristics (continued)
Symbol C Parameter Conditions(1) Value(2)
Unit
Min Typ Max
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
80/103 Doc ID 16100 Rev 5
3.17.2 IEEE 1149.1 interface timing
Figure 22. JTAG test clock input timing
Table 38. JTAG pin AC electrical characteristics
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
JCYC CC D TCK cycle time — 100 — ns
2t
JDC CC D TCK clock pulse width (measured at VDD_HV_IOx/2) — 40 60 ns
3t
TCKRISE CC D TCK rise and fall times (40 %–70 %) — — 3 ns
4tTMSS,
tTDIS
CC D TMS, TDI data setup time — 5 — ns
5tTMSH,
tTDIH
CC D TMS, TDI data hold time — 25 — ns
6t
TDOV CC D TCK low to TDO data valid — — 40 ns
7t
TDOI CC D TCK low to TDO data invalid — 0 — ns
8t
TDOHZ CC D TCK low to TDO high impedance — 40 — ns
9t
BSDV CC D TCK falling edge to output valid — — 50 ns
10 tBSDVZ CC D TCK falling edge to output valid out of high
impedance — — 50 ns
11 tBSDHZ CC D TCK falling edge to output high impedance — — 50 ns
12 tBSDST CC D Boundary scan input valid to TCK rising edge — 50 — ns
13 tBSDHT CC D TCK rising edge to boundary scan input invalid — 50 — ns
TCK
1
2
2
3
3
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 81/103
Figure 23. JTAG test access port timing
TCK
4
5
6
78
TMS, TDI
TDO
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
82/103 Doc ID 16100 Rev 5
Figure 24. JTAG boundary scan timing
3.17.3 Nexus timing
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
Table 39. Nexus debug port timing(1)
No. Symbol C Parameter
Value
Unit
Min Typ Max
1t
TCYC CC D TCK cycle time 4(2) ——t
CYC
2tNTDIS CC D TDI data setup time 5 — — ns
tNTMSS CC D TMS data setup time 5 — — ns
3tNTDIH CC D TDI data hold time 25 — — ns
tNTMSH CC D TMS data hold time 25 — — ns
4t
TDOV CC D TCK low to TDO data valid 10 — 20 ns
5t
TDOI CC D TCK low to TDO data invalid — — — ns
1. All Nexus timing relative to MCKO is measured from 50 % of MCKO and 50 % of the respective signal.
2. Lower frequency is required to be fully compliant to standard.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 83/103
Figure 25. Nexus output timing
Figure 26. Nexus event trigger and test clock timing
1
3
4
MCKO
MDO
MSEO
EVTO
Output Data Valid
2
TCK
5
EVTI
EVTO
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
84/103 Doc ID 16100 Rev 5
Figure 27. Nexus TDI, TMS, TDO timing
3.17.4 External interrupt timing (IRQ pin)
TDO
6
7
TMS, TDI
8
TCK
9
Table 40. External interrupt timing(1)
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
IPWL CC D IRQ pulse width low — 4 — tCYC
2t
IPWH CC D IRQ pulse width high — 4 — tCYC
3t
ICYC CC D IRQ edge to edge time(2) —4+N
(3) —t
CYC
1. IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA=T
L to TH, and CL= 200 pF with SRC = 0b00.
2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3. N = ISR time to clear the flag.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 85/103
Figure 28. External interrupt timing
3.17.5 DSPI timing
IRQ
2
3
1
Table 41. DSPI timing(1)
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
SCK CC D DSPI cycle time Master (MTFE = 0) 60 — ns
Slave (MTFE = 0) 60 —
2t
CSC CC D CS to SCK delay — 16 — ns
3t
ASC CC D After SCK delay — 26 — ns
4t
SDC CC D SCK duty cycle — 0.4 * tSCK 0.6 * tSCK ns
5t
ACC D Slave access time SS active to SOUT valid —30 ns
6t
DIS CC D Slave SOUT disable
time
SS inactive to SOUT high
impedance or invalid —16 ns
7t
PCSC CC D PCSx to PCSS time — 13 — ns
8t
PASC CC D PCSS to PCSx time — 13 — ns
9t
SUI CC D Data setup time for
inputs
Master (MTFE = 0) 35 —
ns
Slave 4—
Master (MTFE = 1, CPHA = 0) 35 —
Master (MTFE = 1, CPHA = 1) 35 —
10 tHI CC D Data hold time for inputs
Master (MTFE = 0) −5 —
ns
Slave 4 —
Master (MTFE = 1, CPHA = 0) 11 —
Master (MTFE = 1, CPHA = 1) −5—
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
86/103 Doc ID 16100 Rev 5
Figure 29. DSPI classic SPI timing – Master, CPHA = 0
11 tSUO CC D Data valid (after SCK
edge)
Master (MTFE = 0) — 12
ns
Slave — 36
Master (MTFE = 1, CPHA = 0) — 12
Master (MTFE = 1, CPHA = 1) — 12
12 tHO CC D Data hold time for
outputs
Master (MTFE = 0) −2—
ns
Slave 6 —
Master (MTFE = 1, CPHA = 0) 6 —
Master (MTFE = 1, CPHA = 1) −2—
1. All timing are provided with 50 pF capacitance on output, 1 ns transition time on input signal.
Table 41. DSPI timing(1) (continued)
No. Symbol C Parameter Conditions
Value
Unit
Min Max
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output
4
9
12
1
11
10
4
SCK Output
(CPOL=0)
(CPOL=1)
3
2
Note: Numbers shown reference Ta b l e 4 1 .
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 87/103
Figure 30. DSPI classic SPI timing – Master, CPHA = 1
Figure 31. DSPI classic SPI timing – Slave, CPHA = 0
Note
: Numbers shown reference
Ta b le 4 1
.
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
Note
: Numbers shown reference
Ta b l e 4 1
.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
88/103 Doc ID 16100 Rev 5
Figure 32. DSPI classic SPI timing – Slave, CPHA = 1
Figure 33. DSPI modified transfer format timing – Master, CPHA = 0
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta b l e 4 1 .
PCSx
3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta bl e 4 1 .
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics
Doc ID 16100 Rev 5 89/103
Figure 34. DSPI modified transfer format timing – Master, CPHA = 1
Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta b l e 4 1 .
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
12
Note: Numbers shown reference Table 41.
Electrical characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
90/103 Doc ID 16100 Rev 5
Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1
Figure 37. DSPI PCS Strobe (PCSS) timing
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta bl e 4 1 .
PCSx
78
PCSS
Note: Numbers shown reference Ta bl e 4 1 .
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics
Doc ID 16100 Rev 5 91/103
4 Package characteristics
4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK® is an ST trademark.
Package characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
92/103 Doc ID 16100 Rev 5
4.2 Package mechanical data
4.2.1 LQFP100 mechanical outline drawing
Figure 38. LQFP100 package mechanical drawing
D
D1
D3
75 51
50
76
100 26
125
E3 E1 E
e
b
Pin 1
identification
SEATING PLANE
GAGE PLANE
C
A
A2
A1
Cccc
0.25 mm
0.10 inch
L
L1
k
C
1L_ME
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics
Doc ID 16100 Rev 5 93/103
Table 42. LQFP100 package mechanical data
Symbol
Dimensions
mm inches(1)
Min Typ Max Min Typ Max
A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 — 12.000 — — 0.4724 —
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 — 12.000 — — 0.4724 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc(2) 0.08 0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance.
Package characteristics SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
94/103 Doc ID 16100 Rev 5
4.2.2 LQFP64 mechanical outline drawing
Figure 39. LQFP64 package mechanical drawing
5W_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
32
33
48
49
b
64
1
Pin 1
identification 16
17
Table 43. LQFP64 package mechanical data
Symbol
Dimensions
mm inches(1)
Min Typ Max Min Typ Max
A——1.6——0.063
A1 0.05 — 0.15 0.002 — 0.0059
A2 1.35 1.4 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 — 0.2 0.0035 — 0.0079
D 11.8 12 12.2 0.4646 0.4724 0.4803
D1 9.8 10 10.2 0.3858 0.3937 0.4016
D3 — 7.5 — — 0.2953 —
E 11.8 12 12.2 0.4646 0.4724 0.4803
E1 9.8 10 10.2 0.3858 0.3937 0.4016
E3 — 7.5 — — 0.2953 —
e — 0.5 — — 0.0197 —
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 — 1 — — 0.0394 —
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package characteristics
Doc ID 16100 Rev 5 95/103
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc(2) 0.08 0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance.
Table 43. LQFP64 package mechanical data (continued)
Symbol
Dimensions
mm inches(1)
Min Typ Max Min Typ Max
Ordering information SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
96/103 Doc ID 16100 Rev 5
5 Ordering information
Figure 40. Commercial product code structure
Memory PackingCore Family
Y = Tray
R = Tape and Reel
X = Tape and Reel 90°
A = 64 MHz, 5 V
B = 64 MHz, 3.3 V
C = 40 MHz, 5 V
D = 40 MHz, 3.3 V
F = Full-featured
A = Airbag
E = Data Flash
0 = No Data Flash
B = –40 to 105 °C
C = –40 to 125 °C
L1 = LQFP64
L3 = LQFP100
34 = 192 KB
40 = 256 KB
P = SPC560Px family
0 = e200z0
SPC56 = Power Architecture in 90 nm
TemperaturePackage Custom vers.
SPC56 40 Y0P CL3 E F A
Example code:
Product identifier
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Abbreviations
Doc ID 16100 Rev 5 97/103
Appendix A Abbreviations
Ta bl e 4 4
lists abbreviations used in this document.
Table 44. Abbreviations
Abbreviation Meaning
CMOS Complementary metal–oxide–semiconductor
CPHA Clock phase
CPOL Clock polarity
CS Peripheral chip select
DUT Device under test
ECC Error code correction
EVTO Event out
GPIO General purpose input / output
MC Modulus counter
MCKO Message clock out
MCU Microcontroller unit
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format enable
NPN Negative-positive-negative
NVUSRO Non-volatile user options register
PTF Post trimming frequency
PWM Pulse width modulation
RISC Reduced instruction set computer
SCK Serial communications clock
SOUT Serial data out
TBC To be confirmed
TBD To be defined
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select
Revision history SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
98/103 Doc ID 16100 Rev 5
Revision history
Table 45. Document revision history
Date Revision Changes
01-Sep-2009 1 Initial release.
21-May-2010 2
Editorial updates
Updated the following items in the “SPC560P34/SPC560P40 device comparison”
table:
– The heading
– The “SRAM” row
– The “FlexCAN” row
– The “CTU” row
– The “FlexPWM” row
– The “LINFlex” row
– The “DSPI” row
– The “Nexus” row
Updated the “SPC560P34/SPC560P40 device configuration difference” table:
– Editorial updates
– Added the “CTU” row
– Deleted the “temperature” row
– Swapped the content of Airbag and Full Featured cells
Added the “Wakeup unit” block in the SPC560P34/SPC560P40 block diagram
Updated the “Absolute Maximum Ratings“ table
Updated the “Recommended operating conditions (5.0 V)“ table
Updated the “Recommended operating conditions (3.3 V)“ table
Updated the “Thermal characteristics for 100-pin LQFP“ table:
–ΨJT: changed the typical value
Updated the “EMI testing specifications“ table: replaced all values in “Level (Max)“
column with TBD
Updated the “Electrical characteristics“ section:
– Added the “Introduction” section
– Added the “Parameter classification“ section
– Added the “NVUSRO register“ section
– Added the “Power supplies constraints (–0.3 V ≤VDD_HV_IOx ≤6.0 V)” figure
– Added the “Independent ADC supply (–0.3 V ≤VDD_HV_REG ≤6.0 V)“ figure
– Added the “Power supplies constraints (3.0 V ≤VDD_HV_IOx ≤5.5 V)“ figure
– Added the “Independent ADC supply (3.0 V ≤VDD_HV_REG ≤5.5 V)“ figure
Updated the “Power management electrical characteristics” section
Updated the “Power Up/Down sequencing” section
Updated the “DC electrical characteristics“ section
– Deleted the “NVUSRO register” section
– Updated the “DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)“ section:
– Deleted all rows concerning RESET
– Deleted “IVPP“ row
– Added the max value for CIN
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Revision history
Doc ID 16100 Rev 5 99/103
21-May-2010 2
(continued)
– Updated the “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 0)“ section:
– Deleted all rows concerning RESET
– Deleted “IVPP“ row
– Added the max value for CIN
Added the “I/O pad current specification“ section
Updated the Order codes table.
Added “Appendix A”
23-Dec-2010 3
“Introduction” section:
– Changed title (was “Overview“)
– Updated contents
“SPC560P34/SPC560P40 device comparison” table:
– Added sentence above table
– Removed “FlexRay” row
– “FlexCAN” row: removed link to footnote 2 for SPC560P34
– Updated “Safety port” row for SPC560P34
– Updated “DSPI” row for SPC560P34
“SPC560P34/SPC560P40 block diagram”: added the following blocks: MC_CGM,
MC_ME, MC_PCU, MC_RGM, CRC, and SSCM
Added “SPC560P34/SPC560P40 series block summary” table
“Pin muxing” section: removed information on “Symmetric pads”
“Electrical characteristics” section:
– Updated “Caution” note
– Demoted “NVUSRO register” section to subsection of “DC electrical characteristics”
section
– “NVUSRO register” section: deleted “NVUSRO[WATCHDOG_EN] field description“
section
Updated “EMI testing specifications” table
“Low voltage monitor electrical characteristics” table: updated VMLVDDOK_H max value
“DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)” table: removed VOL_SYM,
and VOH_SYM rows
“Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)” table:
–I
DD_LV_CORE, RUN—Maximum mode, 40/64 MHz: updated typ/max values
–I
DD_LV_CORE, RUN—Airbag mode, 40/64 MHz: updated typ/max values
–I
DD_LV_CORE, RUN—Maximum mode, “P” parameter classification: removed
–I
DD_FLASH: removed rows
–I
DD_ADC, Maximum mode: updated typ/max values
–I
DD_OSC: updated max value
Updated “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)” table
“Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)” table:
–I
DD_LV_CORE, RUN—Maximum mode, 40/64 MHz: updated typ/max values
–I
DD_LV_CORE, RUN—Airbag mode, 40/64 MHz: updated typ/max values
–I
DD_FLASH: removed rows
–I
DD_ADC, Maximum mode: updated typ/max values
–I
DD_OSC: updated max value
Added “I/O consumption” table
Removed “I/O weight” table
Table 45. Document revision history (continued)
Date Revision Changes
Revision history SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
100/103 Doc ID 16100 Rev 5
23-Dec-2010 3
(continued)
Updated “Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)”
table
Updated “Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)”
table
“Input clock characteristics” table: updated fCLK max value
“PLLMRFM electrical specifications (VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V,
TA=T
Lto TH)” table:
– Updated supply voltage range for VDDPLL in the table title
– Updated fSCM max value
– Updated CJITTER row
– Updated fMOD max value
Updated “16 MHz RC oscillator electrical characteristics” table
Updated “ADC conversion characteristics” table
“Program and erase specifications” table:
–T
wprogram: updated initial max and max values
–T
BKPRG, 64 KB: updated initial max and max values
– added information about “erase time” for Data Flash
“Flash module life” table:
– P/E, 32 KB: added typ value
– P/E, 128 KB: added typ value
Replaced “Pad AC specifications (5.0 V, NVUSRO[PAD3V5V] = 0)” and “Pad AC
specifications (3.3 V, INVUSRO[PAD3V5V] = 1)” tables with “Output pin transition
times” table
“JTAG pin AC electrical characteristics” table:
–t
TDOV: updated max value
–t
TDOHZ: added min value and removed max value
“Nexus debug port timing” table: removed the rows “tMCYC”, “tMDOV”, “tMSEOV”, and
“tEVTOV”
Updated “External interrupt timing (IRQ pin)” table
Updated “FlexCAN timing” table
Updated “DSPI timing” table
Updated “Ordering information” section
Table 45. Document revision history (continued)
Date Revision Changes
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Revision history
Doc ID 16100 Rev 5 101/103
13-May-2011 4
Editorial and formatting changes throughout
Cover page features list:
• changed core feature “64 MHz” to “Up to 64 MHz”
• changed Data flash memory “64 (4 × 16) KB” to “Additional 64 (4 × 16) KB”
• changed “1 FlexCAN interface” to “Up to 2 FlexCAN interface”
Updated Device summary
Section “Introduction“: Reorganized contents
SPC560P40 device configuration differences: Editorial changes to indicate that the table
concerns only the SPC560P40 devices); removed “DSPI” row
Block diagram (SPC560P40 full-featured configuration): reorganized blocks above and
below peripheral bridge; made arrow going from peripheral bridge to crossbar switch
bidirectional; removed SPC560P34 part number from title
Added section “Features details”
64-pin and 100-pin LQFP pinout diagrams: replaced instances of HV_AD0 with
HV_ADC0
System pins: updated “XTAL” and “EXTAL” rows
Updated LQFP thermal characteristics
Updated EMI testing specifications
section “Voltage regulator electrical characteristics“: removed BCP56 from named
BJTs; replaced two configuration diagrams and two electrical characteristics tables
with single diagram and single table
Voltage regulator electrical characteristics: updated VDD_LV_REGCOR row
Low voltage monitor electrical characteristics: updated VMLVDDOK_H max value—was
1.15 V; is 1.145 V
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): changed symbol IDD_LV_CORE to
IDD_LV_CORx; changed parameter classification from T to P for IDD_LV_CORx RUN—
Maximum mode at 64 MHz; added IDD_FLASH characteristics; replaced instances of
“Airbag” mode with “Typical mode”
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): changed symbol IDD_LV_CORE to
IDD_LV_CORx; replaced instances of “Airbag” mode with “Typical mode”
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1): corrected parameter
description for VOL_F—was “Fast, high level output voltage”; is “Fast, low level output
voltage”
Added Section 3.10.4, Input DC electrical characteristics definition
Main oscillator output electrical characteristics tables: replaced instances of EXTAL with
XTAL; added load capacitance parameter
FMPLL electrical characteristics: updated conditions and table title; removed fsys row;
updated fFMPLLOUT values; replaced instances of VDDPLL with VDD_LV_COR0; replaced
instances of VSSPLL with VSS_LV_COR0
16 MHz RC oscillator electrical characteristics: removed rows ΔRCMTRIM and
ΔRCMSTEP
ADC characteristics and error definitions: updated symbols
ADC conversion characteristics: updated symbols; added row tADC_PU
Added Section 3.15.2, Flash memory power supply DC characteristics
Added Section 3.15.3, Start-up/Switch-off timings
Removed section “Generic timing diagrams”
Updated Start-up reset requirements diagram
Removed FlexCAN timing characteristics
RESET electrical characteristics: added row for tPOR
In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS
Strobe (PCSS) Timing”: added note
Updated Order codes
Table 45. Document revision history (continued)
Date Revision Changes
Revision history SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
102/103 Doc ID 16100 Rev 5
13-May-2011 4
(continued)
Commercial product code structure: Replaced “Conditioning” with “Packing”
Ta b l e 4 4
: added “DUT”, “NPN”, and “RISC”
22-Dec-2011 5
Updated
Table 1: Device summary
Updated
Section 1.5.28: Nexus Development Interface (NDI)
Section Table 2.: SPC560P34/SPC560P40 device comparison
: changed Nexus L1+
with Nexus Class 1
Ta bl e 7 : P i n m u x i n g
: removed E[0] row
Table 9: Absolute maximum ratings
: updated minumum and maximum values for TVDD
parameter
Section 3.10: DC electrical characteristics
: Removed oscillator margin.
Removed Section NVUSRO[OSCILLATOR_MARGIN] field description and Table
NVUSRO[OSCILLATOR_MARGIN] field description
Updated
Section 3.8.1: Voltage regulator electrical characteristics
Updated
Section Figure 10.: Voltage regulator configuration
Table 16: Voltage regulator electrical characteristics
: added LReg row, updated condition
for CDEC1, CDEC2 and CDEC3
Removed “Order codes” tables
Table 45. Document revision history (continued)
Date Revision Changes
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Doc ID 16100 Rev 5 103/103
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