DDR4 SDRAM SODIMM
MTA18ASF2G72HZ – 16GB
Features
DDR4 functionality and operations supported as
defined in the component data sheet
260-pin, small-outline dual in-line memory module
(SODIMM)
Fast data transfer rates: PC4-3200, PC4-2666 or
PC4-2400
16GB (2 Gig x 72)
VDD = 1.20V (NOM)
VPP = 2.5V (NOM)
VDDSPD = 2.5V (NOM)
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
Low-power auto self refresh (LPASR)
Data bus inversion (DBI) for data bus
On-die VREFDQ generation and calibration
Dual-rank
On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
16 internal banks; 4 groups of 4 banks each
Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
Gold edge contacts
Halogen-free
Fly-by topology
Terminated control, command, and address bus
Figure 1: 260-Pin SODIMM (MO-310 R/C H)
Module Height: 30mm (1.181in)
Figure 2: 260-Pin SODIMM (MO-310 R/C G1)
Module Height: 30mm (1.181 in)
Options Marking
Operating temperature
Commercial
(0°C TOPER 95°C)
None
Package
260-pin DIMM (halogen-free) Z
Frequency/CAS latency
0.62ns @ CL = 22 (DDR4-3200) -3G2
0.75ns @ CL = 19 (DDR4-2666) -2G6
0.83ns @ CL = 17 (DDR4-2400) -2G3
Table 1: Key Timing Parameters
Speed
Grade
PC4-
Data Rate (MT/s)
CL =
tRCD
(ns)
tRP
(ns)
tRC
(ns)24
22/
21 20 19 18 17 16 15 14 13 12 11 10 9
-3G2 3200 3200 3200/
2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 13.75 13.75 45.75
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Features
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 1: Key Timing Parameters (Continued)
Speed
Grade
PC4-
Data Rate (MT/s)
CL =
tRCD
(ns)
tRP
(ns)
tRC
(ns)24
22/
21 20 19 18 17 16 15 14 13 12 11 10 9
-2G9 2933 2933/
2933
2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.32 14.32 46.32
-2G6 2666 2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.16 14.16 46.16
-2G3 2400 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.16 14.16 46.16
-2G1 2133 2133 2133 1866 1866 1600 1600 1333 1333 13.5 13.5 46.5
Table 2: Addressing
Parameter 16GB
Row address 64K A[15:0]
Column address 1K A[9:0]
Device bank group address 4 BG[1:0]
Device bank address per group 4 BA[1:0]
Device configuration 8Gb (1Gig x 8), 16 banks
Module rank address CS_n[1:0]
Table 3: Part Numbers and Timing Parameters – 16GB Modules
Base device: MT40A1G8,1 8Gb DDR4 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MTA18ASF2G72HZ-3G2__ 16GB 2 Gig x 72 25.6 GB/s 0.625ns/3200
MT/s
22-22-22
MTA18ASF2G72HZ-2G6__ 16GB 2 Gig x 72 21.3 GB/s 0.75ns/2666 MT/s 19-19-19
MTA18ASF2G72HZ-2G3__ 16GB 2 Gig x 72 19.2 GB/s 0.83ns/2400 MT/s 17-17-17
Notes: 1. The data sheet for the base device can be found on micron.com.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MTA18ASF2G72HZ-3G2E1.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Features
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
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including without limitation specifications and product descriptions. This document supersedes and replaces all
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16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Features
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Pin Assignments
The pin assignment table below is a comprehensive list of all possible pin assignments
for DDR4 SODIMM modules. See Functional Block Diagram for pins specific to this
module.
Table 4: Pin Assignments
260-Pin DDR4 SODIMM Front 260-Pin DDR4 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VSS 67 DQ29 133 A1 199 DM5_n/
DBI5_n
2 VSS 68 VSS 134 EVENT_n,
NF
200 DQS5_t
3 DQ5 69 VSS 135 VDD 201 VSS 4 DQ4 70 DQ24 136 VDD 202 VSS
5 VSS 71 DQ25 137 CK0_t 203 DQ46 6 VSS 72 VSS 138 CK1_t/NF 204 DQ47
7 DQ1 73 VSS 139 CK0_c 205 VSS 8 DQ0 74 DQS3_c 140 CK1_c/NF 206 VSS
9 VSS 75 DM3_n/
DBI3_n
141 VDD 207 DQ42 10 VSS 76 DQS3_t 142 VDD 208 DQ43
11 DQS0_c 77 VSS 143 PARITY 209 VSS 12 DM0_n/
DBI0_n
78 VSS 144 A0 210 VSS
13 DQS0_t 79 DQ30 145 BA1 211 DQ52 14 VSS 80 DQ31 146 A10/AP 212 DQ53
15 VSS 81 VSS 147 VDD 213 VSS 16 DQ6 82 VSS 148 VDD 214 VSS
17 DQ7 83 DQ26 149 CS0_n 215 DQ49 18 VSS 84 DQ27 150 BA0 216 DQ48
19 VSS 85 VSS 151 WE_n/
A14
217 VSS 20 DQ2 86 VSS 152 RAS_n/
A16
218 VSS
21 DQ3 87 CB5/NC 153 VDD 219 DQS6_c 22 VSS 88 CB4/NC 154 VDD 220 DM6_n/
DBI6_n
23 VSS 89 VSS 155 ODT0 221 DQS6_t 24 DQ12 90 VSS 156 CAS_n/
A15
222 VSS
25 DQ13 91 CB1/NC 157 CS1_n/
NC
223 VSS 26 VSS 92 CB0/NC 158 A13 224 DQ54
27 VSS 93 VSS 159 VDD 225 DQ55 28 DQ8 94 VSS 160 VDD 226 VSS
29 DQ9 95 DQS8_c/
NC
161 ODT1/
NC
227 VSS
30 VSS 96 DM8_n/
DBI_n/NC
162 C0/
CS2_n/NC
228 DQ50
31 VSS 97 DQS8_t/
NC
163 VDD 229 DQ51 32 DQS1_c 98 VSS 164 VREFCA 230 VSS
33 DM1_n/
DBI_n
99 VSS 165 C1, CS3_n,
NC
231 VSS 34 DQS1_t 100 CB6/NC 166 SA2 232 DQ60
35 VSS 101 CB2/NC 167 VSS 233 DQ61 36 VSS 102 VSS 168 VSS 234 VSS
37 DQ15 103 VSS 169 DQ37 235 VSS 38 DQ14 104 CB7/NC 170 DQ36 236 DQ57
39 VSS 105 CB3/NC 171 VSS 237 DQ56 40 VSS 106 VSS 172 VSS 238 VSS
41 DQ10 107 VSS 173 DQ33 239 VSS 42 DQ11 108 RESET_n 174 DQ32 240 DQS7_c
43 VSS 109 CKE0 175 VSS 241 DM7_n/
DBI7_n
44 VSS 110 CKE1/
NC
176 VSS 242 DQS7_t
45 DQ21 111 VDD 177 DQS4_c 243 VSS 46 DQ20 112 VDD 178 DM4_n/
DBI4_n
244 VSS
47 VSS 113 BG1 179 DQS4_t 245 DQ62 48 VSS 114 ACT_n 180 VSS 246 DQ63
49 DQ17 115 BG0 181 VSS 247 VSS 50 DQ16 116 ALERT_n 182 DQ39 248 VSS
51 VSS 117 VDD 183 DQ38 249 DQ58 52 VSS 118 VDD 184 VSS 250 DQ59
53 DQS2_c 119 A12 185 VSS 251 VSS 54 DM2_n/
DBI2_n
120 A11 186 DQ35 252 VSS
55 DQS2_t 121 A9 187 DQ34 253 SCL 56 VSS 122 A7 188 VSS 254 SDA
57 VSS 123 VDD 189 VSS 255 VDDSPD 58 DQ22 124 VDD 190 DQ45 256 SA0
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Pin Assignments
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 4: Pin Assignments (Continued)
260-Pin DDR4 SODIMM Front 260-Pin DDR4 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
59 DQ23 125 A8 191 DQ44 257 VPP 60 VSS 126 A5 192 VSS 258 VTT
61 VSS 127 A6 193 VSS 259 VPP 62 DQ18 128 A4 194 DQ41 260 SA1
63 DQ19 129 VDD 195 DQ40 64 VSS 130 VDD 196 VSS
65 VSS 131 A3 197 VSS 66 DQ28 132 A2 198 DQS5_c
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Pin Assignments
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Di-
agram for pins specific to this module.
Table 5: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respec-
tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-
mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst chopped). See Com-
mand Truth Table in the DDR4 component data sheet.
ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-
tions. x16-based SDRAM only has BG0.
C0, C1, C2
(RDIMM/LRDIMM on-
ly)
Input Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
CKx_t
CKx_c
Input Clock: Differential clock inputs. All address, command, and control input signals are sampled
on the crossing of the positive edge of CK_t and the negative edge of CK_c.
CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After VREFCA has become stable during the power-on and ini-
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET_n) are disabled during self refresh.
CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Pin Descriptions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 5: Pin Descriptions (Continued)
Symbol Type Description
ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-
bled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode
registers are programmed to disable RTT.
PARITY Input Parity for command and address: This function can be enabled or disabled via the mode
register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the
clock and at the same time as command and address with CS_n LOW.
RAS_n/A16
CAS_n/A15
WE_n/A14
Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-
mand and/or address being entered and have multiple functions. For example, for activation
with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-
mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-
fined in Command Truth Table.
RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-
SET_n is HIGH. RESET_n must be HIGH during normal operation.
SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range
on the I2C bus.
SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
and from the temperature sensor/SPD EEPROM on the I2C bus.
DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents
DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-
dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of
the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-
nal VREF level during test via mode register setting MR[4] A[4] = HIGH; training times change
when enabled.
DM_n/DBI_n/
TDQS_t (DMU_n,
DBIU_n), (DML_n/
DBIl_n)
I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
data is masked when DM_n is sampled LOW coincident with that input data during a write ac-
cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the
mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS
is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only
supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
combo device.
DQS_t
DQS_c
DQSU_t
DQSU_c
DQSL_t
DQSL_c
I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on
DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-
tial data strobe only and does not support a single-ended data strobe.
ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error
flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and
returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-
til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,
this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,
ALERT_n pin must be connected to VDD on DIMMs.
EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-
perature thresholds have been exceeded. This pin has no function (NF) on modules without
temperature sensors.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Pin Descriptions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 5: Pin Descriptions (Continued)
Symbol Type Description
TDQS_t
TDQS_c
(x8 DRAM-based
RDIMM only)
Output Termination data strobe: When enabled via the mode register, the DRAM device enables the
same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the da-
ta mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in
the mode register for both the x4 and x16 configurations. The DM function is supported only in
x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by
mode register settings. For more information about TDQS, see the DDR4 DRAM component da-
ta sheet (TDQS_t and TDQS_c are not valid for UDIMMs).
VDD Supply Module power supply: 1.2V (TYP).
VPP Supply DRAM activating power supply: 2.5V –0.125V / +0.250V.
VREFCA Supply Reference voltage for control, command, and address pins.
VSS Supply Ground.
VTT Supply Power supply for termination of address, command, and control VDD/2.
VDDSPD Supply Power supply used to power the I2C bus for SPD.
RFU Reserved for future use.
NC No connect: No internal electrical connection is present.
NF No function: May have internal connection present, but has no function.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Pin Descriptions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
DQ Maps
Table 6: Component-to-Module DQ Map R/C-H (PCB 1813), Front
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U1 0 14 38 U2 0 31 80
1 12 24 1 28 66
2 15 37 2 30 79
3 13 25 3 29 67
4 11 42 4 27 84
5 8 28 5 24 70
6 10 41 6 26 83
7 9 29 7 25 71
U3 0 CB3 105 U5 0 39 182
1 CB0 92 1 36 170
2 CB2 101 2 38 183
3 CB1 91 3 37 169
4 CB7 104 4 35 186
5 CB4 88 5 32 174
6 CB6 100 6 34 187
7 CB5 87 7 33 173
U6 0 54 224 U7 0 7 17
1 53 212 1 5 3
2 55 225 2 6 16
3 52 211 3 4 4
4 50 228 4 2 20
5 48 216 5 0 8
6 51 229 6 3 21
7 49 215 7 1 7
U8 0 23 59 U9 0 42 207
1 21 45 1 41 194
2 22 58 2 43 208
3 20 46 3 40 195
4 19 63 4 47 204
5 16 50 5 45 190
6 18 62 6 46 203
7 17 49 7 44 191
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 6: Component-to-Module DQ Map R/C-H (PCB 1813), Front (Continued)
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U10 0 58 249
1 56 237
2 59 250
3 57 236
4 63 246
5 61 233
6 62 245
7 60 232
Table 7: Component-to-Module DQ Map R/C-H (PCB 1813), Back
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U11 0 53 212 U12 0 36 170
1 54 224 1 39 182
2 52 211 2 37 169
3 55 225 3 38 183
4 48 216 4 32 174
5 50 228 5 35 186
6 49 215 6 33 173
7 51 229 7 34 187
U13 0 CB0 92 U14 0 28 66
1 CB3 105 1 31 80
2 CB1 91 2 29 67
3 CB2 101 3 30 79
4 CB4 88 4 24 70
5 CB7 104 5 27 84
6 CB5 87 6 25 71
7 CB6 100 7 26 83
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 7: Component-to-Module DQ Map R/C-H (PCB 1813), Back (Continued)
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U15 0 12 24 U16 0 56 237
1 14 38 1 58 249
2 13 25 2 57 236
3 15 37 3 59 250
4 8 28 4 61 233
5 11 42 5 63 246
6 9 29 6 60 232
7 10 41 7 62 245
U17 0 41 194 U18 0 21 45
1 42 207 1 23 59
2 40 195 2 20 46
3 43 208 3 22 58
4 45 190 4 16 50
5 47 204 5 19 63
6 44 191 6 17 49
7 46 203 7 18 62
U19 0 5 3
1 7 17
244
3 6 16
4 0 8
5 2 20
617
7 3 21
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 8: Component-to-Module DQ Map R/C-G1 (PCB 2451), Front
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U1 0 11 42 U2 0 27 84
1 8 28 1 25 71
2 10 41 2 26 83
3 9 29 3 24 70
4 14 38 4 31 80
5 12 24 5 29 67
6 15 37 6 30 79
7 13 25 7 28 66
U3 0 CB3 105 U4 0 34 187
1 CB0 92 1 33 173
2 CB2 101 2 35 186
3 CB1 91 3 32 174
4 CB6 101 4 39 182
5 CB4 88 5 36 170
6 CB7 104 6 38 183
7 CB5 87 7 37 169
U5 0 51 229 U6 0 2 20
1 49 215 1 0 8
2 50 228 2 3 21
3 48 216 3 1 7
4 55 225 4 6 16
5 53 212 5 4 4
6 54 224 6 7 17
7 52 211 7 5 3
U7 0 22 58 U9 0 42 207
1 20 46 1 40 195
2 23 59 2 43 208
3 21 45 3 41 194
4 18 62 4 46 203
5 16 50 5 45 190
6 19 63 6 47 204
7 17 49 7 44 191
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 8: Component-to-Module DQ Map R/C-G1 (PCB 2451), Front (Continued)
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U10 0 59 250
1 57 236
2 58 249
3 56 237
4 63 246
5 61 233
6 62 245
7 60 232
Table 9: Component-to-Module DQ Map R/C-G1 (PCB 2451), Back
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U11 0 49 215 U12 0 33 173
1 51 229 1 34 187
2 48 216 2 32 174
3 50 228 3 35 186
4 53 212 4 36 170
5 55 225 5 39 182
6 52 211 6 37 169
7 54 224 7 38 183
U13 0 CB0 92 U14 0 25 71
1 CB3 105 1 27 84
2 CB1 91 2 24 70
3 CB2 101 3 26 83
4 CB4 88 4 29 67
5 CB6 100 5 31 80
6 CB5 87 6 28 66
7 CB7 104 7 30 79
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 9: Component-to-Module DQ Map R/C-G1 (PCB 2451), Back (Continued)
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ Module DQ
Module Pin
Number
U15 0 8 28 U16 0 57 236
1 11 42 1 59 250
2 9 29 2 56 237
3 10 41 3 58 249
4 12 24 4 61 233
5 14 38 5 63 246
6 13 25 6 60 232
7 15 37 7 62 245
U17 0 40 195 U18 0 20 46
1 42 207 1 22 58
2 41 194 2 21 45
3 43 208 3 23 59
4 45 190 4 16 50
5 46 203 5 18 62
6 44 191 6 17 49
7 47 204 7 19 63
U19 0 0 8
1 2 20
217
3 3 21
4 4 4
5 6 16
653
7 7 17
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DQ Maps
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams
Figure 3: Functional Block Diagram, R/C-H (PCB 1813)
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U19
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U12
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U17
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U8
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U18
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS1_n
CS0_n
Rank 0: U1–U3, U5–U10
Rank 1: U11–U19
Rank 0
CK0_t
CK0_c
CK1_t
CK1_c
Vref CA
Vss
DDR4 SDRAM
DDR4 SDRAM
Vdd
Vddspd Temperature sensor/
SPD EEPROM
Vtt
DDR4 SDRAM
DDR4 SDRAM
Vpp
Clock, control, command, and address line terminations:
Rank 1
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
A0
Temperature
sensor/
SPD EEPROM
A1 A2
SA0 SA1
SDA
SCL
EVT
U4
EVENT_n
SA2
Control, command, and
address termination
DDR4
SDRAM
VTT
CK
CK#
DDR4
SDRAM
VDD
DM_n/ CS_n DQS_t DQS_c
DBI_n
DQS0_t
DQS0_c
DBI0_n/DM0_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DQS1_t
DQS1_c
DBI1_n/DM1_n
DQS2_t
DQS2_c
DBI2_n/DM2_n
DQS3_t
DQS3_c
DBI3_n/DM3_n
DQS8_t
DQS8_c
DBI8_n/DM8_n
DQS4_t
DQS4_c
DBI4_n/DM4_n
DQS5_t
DQS5_c
DBI5_n/DM5_n
DQS6_t
DQS6_c
DBI6_n/DM6_n
DQS7_t
DQS7_c
DBI7_n/DM7_n
BA[1:0]
BG[1:0]
ACT_n
A[13:0]
RAS_n/A16
CAS_n/A15
WE_n/A14
CKE0
CKE1
ODT0
ODT1
RESET
PAR_IN
ALERT_CONN
BA[1:0]: DDR4 SDRAM
BG[1:0]: DDR4 SDRAM
ACT_n: DDR4 SDRAM
A[13:0]: DDR4 SDRAM
RAS_n/A16: DDR4 SDRAM
CAS_n/A15: DDR4 SDRAM
WE_n/A14: DDR4 SDRAM
CKE0: Rank 0
CKE1: Rank 1
ODT0: Rank 0
ODT1: Rank 1
RESET_n: DDR4 SDRAM
PAR: DDR4 SDRAM
ALERT_DRAM: DDR4 SDRAM
CS_n[1:0], BA[1:0], BG[1:0],
ACT_n, A[13:0], RAS_n/A16,
CAS_n/A15, WE_n/A14,
PAR, CKE[1:0], ODT[1:0]
Note: 1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Functional Block Diagrams
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Figure 4: Functional Block Diagram, R/C-G1 (PCB 2451)
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U19
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U12
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U17
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U18
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS1_n
CS0_n
Rank 0: U1–U7, U9, U10
Rank 1: U11–U19
Rank 0
CK0_t
CK0_c
CK1_t
CK1_c
Vref CA
Vss
DDR4 SDRAM
DDR4 SDRAM
Vdd
Vddspd Temperature sensor/
SPD EEPROM
Vtt
DDR4 SDRAM
DDR4 SDRAM
Vpp
Clock, control, command, and address line terminations:
Rank 1
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
ZQ
Vss
A0
Temperature
sensor/
SPD EEPROM
A1 A2
SA0 SA1
SDA
SCL
EVT
U8
EVENT_n
SA2
Control, command, and
address termination
DDR4
SDRAM
VTT
CK
CK#
DDR4
SDRAM
VDD
DM_n/ CS_n DQS_t DQS_c
DBI_n
DQS0_t
DQS0_c
DBI0_n/DM0_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DM_n/ CS_n DQS_t DQS_c
DBI_n
DQS1_t
DQS1_c
DBI1_n/DM1_n
DQS2_t
DQS2_c
DBI2_n/DM2_n
DQS3_t
DQS3_c
DBI3_n/DM3_n
DQS8_t
DQS8_c
DBI8_n/DM8_n
DQS4_t
DQS4_c
DBI4_n/DM4_n
DQS5_t
DQS5_c
DBI5_n/DM5_n
DQS6_t
DQS6_c
DBI6_n/DM6_n
DQS7_t
DQS7_c
DBI7_n/DM7_n
BA[1:0]
BG[1:0]
ACT_n
A[13:0]
RAS_n/A16
CAS_n/A15
WE_n/A14
CKE0
CKE1
ODT0
ODT1
RESET
PAR_IN
ALERT_CONN
BA[1:0]: DDR4 SDRAMs
BG[1:0]: DDR4 SDRAMs
ACT_n: DDR4 SDRAMS
A[13:0]: DDR4 SDRAMs
RAS_n/A16: DDR4 SDRAMs
CAS_n/A15: DDR4 SDRAMs
WE_n/A14: DDR4 SDRAMs
CKE0: Rank 0
CKE1: Rank 1
ODT0: Rank 0
ODT1: Rank 1
RESET_n: DDR4 SDAMS
PAR: DDR4 SDRAMs
ALERT_DRAM: DDR4 SDRAMs
CS_n[1:0], BA[1:0], BG[1:0],
ACT_n, A[13:0], RAS_n/A16,
CAS_n/A15, WE_n/A14,
PAR, CKE[1:0], ODT[1:0]
Note: 1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Functional Block Diagrams
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, provid-
ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-
wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and pro-
vide precise crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR4.
Module Manufacturing Location
Micron Technology manufactures modules at sites world-wide. Customers may receive
modules from any of the following manufacturing locations:
Table 10: DRAM Module Manufacturing Locations
Manufacturing Site Location Country of Origin Specified on Label
Boise, USA USA
Aguadilla, Puerto Rico Puerto Rico
Xian, China China
Singapore Singapore
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
General Description
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Address Mapping to DRAM
Address Mirroring
To achieve optimum routing of the address bus on DDR4 multi rank modules, the ad-
dress bus will be wired as shown in the table below, or mirrored. For quad rank mod-
ules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted ad-
dress pins have no secondary functions allowing for normal operation when cross-
wired. Data is still read from the same address it was written. However, Load Mode op-
erations require a specific address. This requires the controller to accommodate for a
rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module
has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more de-
tails.
Table 11: Address Mirroring
Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A9 A9 A9
A10 A10 A10
A11 A11 A13
A13 A13 A11
A12 A12 A12
A14 A14 A14
A15 A15 A15
A16 A16 A16
A17 A17 A17
BA0 BA0 BA1
BA1 BA1 BA0
BG0 BG0 BG1
BG1 BG1 BG0
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Address Mapping to DRAM
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Temperature Sensor with SPD EEPROM Operation
Thermal Sensor Operations
The integrated thermal sensor continuously monitors the temperature of the module
PCB directly below the device and updates the temperature data register. Temperature
data may be read from the bus host at any time, which provides the host real-time feed-
back of the module's temperature. Multiple programmable and read-only temperature
registers can be used to create a custom temperature-sensing solution based on system
requirements and JEDEC JC-42.2.
EVENT_n Pin
The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pull-
up to VDDSPD. EVENT_n is a temperature sensor output used to flag critical events that
can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial
presence-detect (SPD) EEPROM.
EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In
interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to
the clear event bit in the status register. In comparator mode, the EVENT_n pin clears
itself when the error condition is removed. Comparator mode is always used when the
temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n
pin is only asserted if the measured temperature exceeds the TCRIT limit; it then re-
mains asserted until the temperature drops below the TCRIT limit minus the TCRIT
hysteresis.
SPD EEPROM Operation
DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC
JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable
blocks. The SPD content is aligned with these blocks as shown in the table below.
Block Range Description
0 0–127 000h–07Fh Configuration and DRAM parameters
1 128–255 080h–0FFh Module parameters
2 256–319 100h–13Fh Reserved (all bytes coded as 00h)
320–383 140h–17Fh Manufacturing information
3 384–511 180h–1FFh End-user programmable
The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I2C serial interface and is not integrated with the
memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-
ble at 2.5V (NOM).
Micron implements reversible software write protection on DDR4 SDRAM-based mod-
ules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently pro-
grammed or corrupted. The upper 128 bytes remain available for customer use and are
unprotected.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Temperature Sensor with SPD EEPROM Operation
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 12: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
VDD VDD supply voltage relative to VSS –0.4 1.5 V 1
VDDQ VDDQ supply voltage relative to VSS –0.4 1.5 V 1
VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 2
VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V
Table 13: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
VDD VDD supply voltage 1.14 1.2 1.26 V 1
VPP DRAM activating power supply 2.375 2.5 2.75 V 2
VREFCA(DC) Input reference voltage command/
address bus
0.49 × VDD 0.5 × VDD 0.51 × VDD V 3
IVTT Termination reference current from VTT –500 500 mA
VTT Termination reference voltage (DC) –
command/address bus
0.49 × VDD -
20mV
0.5 × VDD 0.51 × VDD +
20mV
V 4
IIN Input leakage current; any input excluding ZQ;
0V < VIN < 1.1V
–2.0 2.0 µA 5
IZQ Input leakage current; ZQ –50.0 10.0 µA 5, 6
IOZpd Output leakage current; VOUT = VDD; DQ is disabled 10.0 µA
IOZpu Output leakage current; VOUT = VSS; DQ is disabled;
ODT is disabled with ODT input HIGH
–50.0 µA
IVREFCA VREFCA leakage; VREFCA = VDD/2 (after DRAM is ini-
tialized)
–2.0 2.0 µA 5
Notes: 1. VDDQ tracks with VDD; VDDQ and VDD are tied together.
2. VPP must be greater than or equal to VDD at all times.
3. VREFCA must not be greater than 0.6 x VDD. When VDD is less than 500mV, VREF may be
less than or equal to 300mV.
4. VTT termination voltages in excess of the specification limit adversely affect the voltage
margins of command and address signals and reduce timing margins.
5. Multiply by the number of DRAM die on the module.
6. Tied to ground. Not connected to edge connector.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Electrical Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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Table 14: Thermal Characteristics
Symbol Parameter/Condition Value Units Notes
TCCommercial operating case temperature 0 to 85 °C 1, 2, 3
TC>85 to 95 °C 1, 2, 3, 4
TOPER Normal operating temperature range 0 to 85 °C 5, 7
TOPER Extended temperature operating range (optional) >85 to 95 °C 5, 7
TSTG Non-operating storage temperature –55 to 100 °C 6
RHSTG Non-operating Storage Relative Humidity (non-condensing) 5 to 95 %
NA Change Rate of Storage Temperature 20 °C/hour
Notes: 1. Maximum operating case temperature; TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate.
5. The refresh rate must double when 85°C < TOPER 95°C.
6. Storage temperature is defined as the temperature of the top/center of the DRAM and
does not reflect the storage temperatures of shipping trays.
7. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available at micron.com.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Electrical Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR4 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 15: Module and Component Speed Grades
DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-3G2 -062E
-2G9 -068
-2G6 -075
-2G3 -083
-2G1 -093E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the edge connector of the module, not at the DRAM.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
DRAM Operating Conditions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
IDD Specifications
Table 16: DDR4IDD Specifications and Conditions – 16GB (Die Revision A)
Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) compo-
nent data sheet
Parameter Symbol 2400 Units
One bank ACTIVATE-PRECHARGE current IDD01810 mA
One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current IPP0154 mA
One bank ACTIVATE-READ-PRECHARGE current IDD11945 mA
Precharge standby current IDD2N2900 mA
Precharge standby ODT current IDD2NT1810 mA
Precharge power-down current IDD2P2540 mA
Precharge quite standby current IDD2Q2810 mA
Active standby current IDD3N2990 mA
Active standby IPP current IPP3N254 mA
Active power-down current IDD3P2720 mA
Burst read current IDD4R11620 mA
Burst write current IDD4W11710 mA
Burst refresh current (1x REF) IDD5R1846 mA
Burst refresh IPP current (1x REF) IPP5R172 mA
Self refresh current: Normal temp range (0–85°C) IDD6N2540 mA
Self refresh current: Extended temp range (0–95°C) IDD6E2630 mA
Self refresh current: Reduced temp range (0–45°C) IDD6R2450 mA
Auto self refresh current (25°C) IDD6A2360 mA
Auto self refresh current (45°C) IDD6A2450 mA
Auto self refresh current (75°C) IDD6A2630 mA
Auto self refresh IPP current IPP6X290 mA
Bank interleave read current IDD712115 mA
Bank interleave read IPP current IPP71162 mA
Maximum Power Down Current IDD82360 mA
Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
IDD Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 17: DDR4IDD Specifications and Conditions – 16GB (Die Revision B)
Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) compo-
nent data sheet
Parameter Symbol 2400 Units
One bank ACTIVATE-PRECHARGE current IDD01657 mA
One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current IPP0154 mA
One bank ACTIVATE-READ-PRECHARGE current IDD11756 mA
Precharge standby current IDD2N2612 mA
Precharge standby ODT current IDD2NT1675 mA
Precharge power-down current IDD2P2450 mA
Precharge quite standby current IDD2Q2540 mA
Active standby current IDD3N2774 mA
Active standby IPP current IPP3N254 mA
Active power-down current IDD3P2666 mA
Burst read current IDD4R11440 mA
Burst write current IDD4W11332 mA
Burst refresh current (1x REF) IDD5R1702 mA
Burst refresh IPP current (1x REF) IPP5R172 mA
Self refresh current: Normal temp range (0–85°C) IDD6N2540 mA
Self refresh current: Extended temp range (0–95°C) IDD6E2630 mA
Self refresh current: Reduced temp range (0–45°C) IDD6R2360 mA
Auto self refresh current (25°C) IDD6A2154.8 mA
Auto self refresh current (45°C) IDD6A2360 mA
Auto self refresh current (75°C) IDD6A2540 mA
Auto self refresh IPP current IPP6X290 mA
Bank interleave read current IDD711800 mA
Bank interleave read IPP current IPP71162 mA
Maximum Power Down Current IDD82450 mA
Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
IDD Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 18: DDR4IDD Specifications and Conditions – 16GB (Die Revision D)
Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) compo-
nent data sheet
Parameter Symbol 2666 Units
One bank ACTIVATE-PRECHARGE current IDD01684 mA
One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current IPP0154 mA
One bank ACTIVATE-READ-PRECHARGE current IDD11792 mA
Precharge standby current IDD2N2630 mA
Precharge standby ODT current IDD2NT1675 mA
Precharge power-down current IDD2P2450 mA
Precharge quite standby current IDD2Q2540 mA
Active standby current IDD3N2918 mA
Active standby IPP current IPP3N254 mA
Active power-down current IDD3P2702 mA
Burst read current IDD4R11539 mA
Burst write current IDD4W11503 mA
Burst refresh current (1x REF) IDD5R1774 mA
Burst refresh IPP current (1x REF) IPP5R172 mA
Self refresh current: Normal temp range (0–85°C) IDD6N2558 mA
Self refresh current: Extended temp range (0–95°C) IDD6E2648 mA
Self refresh current: Reduced temp range (0–45°C) IDD6R2378 mA
Auto self refresh current (25°C) IDD6A2154.8 mA
Auto self refresh current (45°C) IDD6A2378 mA
Auto self refresh current (75°C) IDD6A2558 mA
Auto self refresh IPP current IPP6X290 mA
Bank interleave read current IDD711845 mA
Bank interleave read IPP current IPP71162 mA
Maximum Power Down Current IDD82450 mA
Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
IDD Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 19: DDR4IDD Specifications and Conditions – 16GB (Die Revision E)
Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) compo-
nent data sheet
Parameter Symbol 3200 2666 Units
One bank ACTIVATE-PRECHARGE current IDD01738 684 mA
One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current IPP0154 54 mA
One bank ACTIVATE-READ-PRECHARGE current IDD11846 792 mA
Precharge standby current IDD2N2666 630 mA
Precharge standby ODT current IDD2NT1765 675 mA
Precharge power-down current IDD2P2450 450 mA
Precharge quite standby current IDD2Q2540 540 mA
Active standby current IDD3N21008 918 mA
Active standby IPP current IPP3N254 54 mA
Active power-down current IDD3P2774 702 mA
Burst read current IDD4R11827 1629 mA
Burst write current IDD4W11620 1458 mA
Burst refresh current (1x REF) IDD5R1819 774 mA
Burst refresh IPP current (1x REF) IPP5R172 72 mA
Self refresh current: Normal temp range (0–85°C) IDD6N2612 612 mA
Self refresh current: Extended temp range (0–95°C) IDD6E2828 828 mA
Self refresh current: Reduced temp range (0–45°C) IDD6R2378 378 mA
Auto self refresh current (25°C) IDD6A2154.8 154.8 mA
Auto self refresh current (45°C) IDD6A2378 378 mA
Auto self refresh current (75°C) IDD6A2558 558 mA
Auto self refresh IPP current IPP6X290 90 mA
Bank interleave read current IDD711971 1881 mA
Bank interleave read IPP current IPP71162 162 mA
Maximum Power Down Current IDD82450 450 mA
Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
IDD Specifications
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Temperature Sensor with SPD EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the serial presence-detect (SPD) EE-
PROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete
details.
SPD Data
For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.
Table 20: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Nom Max Units
Supply voltage VDDSPD 2.5 V
Input low voltage: logic 0; all inputs VIL –0.5 VDDSPD × 0.3 V
Input high voltage: logic 1; all inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Output low voltage: 3mA sink current VDDSPD > 2V VOL 0.4 V
Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD ILI ±5 µA
Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z ILO ±5 µA
Table 21: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition Symbol Min Max Units
Clock frequency fSCL 10 1000 kHz
Clock pulse width HIGH time tHIGH 260 ns
Clock pulse width LOW time tLOW 500 ns
Detect clock LOW timeout tTIMEOUT 25 35 ms
SDA rise time tR 120 ns
SDA fall time tF 120 ns
Data-in setup time tSU:DAT 50 ns
Data-in hold time tHD:DI 0 ns
Data out hold time tHD:DAT 0 350 ns
Start condition setup time tSU:STA 260 ns
Start condition hold time tHD:STA 260 ns
Stop condition setup time tSU:STO 260 ns
Time the bus must be free before a new transi-
tion can start
tBUF 500 ns
Write time tW 5 ms
Warm power cycle time off tPOFF 1 ms
Time from power-on to first command tINIT 10 ms
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Temperature Sensor with SPD EEPROM
CCMTD-1725822587-9881
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Module Dimensions
Figure 5: 260-Pin DDR4 SODIMM, R/C-H (PCB 1813)
3.7 (0.145)
MAX
PIN 1
20.0 (0.787)
TYP
1.8 (0.071)
(2X)
0.5 (0.019)
TYP
0.35 (0.014)
TYP
.65 (0.025) R0
(4X)
PIN 259
PIN 260 PIN 2
Front view
2.0 (0.079)
TYP
6.0 (0.236)
TYP
65.6 (2.58)
TYP
2.55 (0.10)
TYP
30.13 (1.186)
29.87 (1.176)
Back view
1.3 (0.051)
1.1 (0.043)
28.5 (1.12)
TYP
35.5 (1.4)
TYP
2.5 (0.98)
TYP
4.0 (0.157)
TYP
38.3 (1.51)
TYP
0.6 (0.24) x 45° (4X)
1.0 (0.039)
TYP
1.75 (0.07)
TYP (2X)
0.25 (0.1) x 45° (2X)
18.0 (0.71)
TYP
4.0 (0.157) TYP (2X)
69.73 (2.745)
69.47 (2.735)
U1 U2 U3 U4 U5 U6
U7 U8 U9 U10
U11 U12 U13 U14 U15
U16 U17 U18 U19
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Module Dimensions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Figure 6: 260-Pin DDR4 SODIMM, R/C-G1 (PCB 2451)
3.7 (0.145)
MAX
PIN 1
20.0 (0.787)
TYP
1.5 (0.059)
(2X)
0.5 (0.019)
TYP
0.35 (0.014)
TYP
.65 (0.025) R0
(4X)
PIN 259
PIN 260 PIN 2
Front view
2.0 (0.079)
TYP
6.0 (0.236)
TYP
65.6 (2.58)
TYP
2.55 (0.10)
TYP
30.13 (1.186)
29.87 (1.176)
Back view
1.3 (0.051)
1.1 (0.043)
28.5 (1.12)
TYP
35.5 (1.4)
TYP
2.5 (0.98)
TYP
4.0 (0.157)
TYP
38.3 (1.51)
TYP
0.6 (0.24) x 45° (4X)
1.0 (0.039)
TYP
1.75 (0.07)
TYP (2X)
0.25 (0.1) x 45° (2X)
18.0 (0.71)
TYP
4.0 (0.157) TYP (2X)
69.73 (2.745)
69.47 (2.735)
U1 U2
U8
U3 U4 U5
U6 U7 U9 U10
U11 U12 U13 U14 U15
U16 U17 U18 U19
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
16GB (x72, ECC DR) 260-Pin DDR4 SODIMM
Module Dimensions
CCMTD-1725822587-9881
asf18c2gx72hz.pdf – Rev. H 4/18 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.