SEMICONDUCTOR
1
December 1997
HI5703
10-Bit, 40 MSPS A/D Converter
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS
• 8.55 Bits Guaranteed at fIN = 10MHz
• Low Power
• Wide Full Power Input Bandwidth . . . . . . . . . . 250MHz
• On Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V
• TTL Compatible Interface
• 3.3V Digital Outputs Available
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
• Additional Reference Documents
- AN9534 Using the HI5703 Evaluation Board
- AN9413 Driving the Analog Input of the HI5702
- AN9214 Using Harris High Speed A/D Converters
Description
The HI5703 is a monolithic, 10-bit, analog-to-digital
converter fabricated in Harris’s BiCMOS process. It is
designed for high speed applications where wide bandwidth
and low power consumption are essential. Its 40 MSPS
speed is made possible by a fully differential pipeline
architecture with an internal sample and hold.
The HI5703 has excellent dynamic performance while
consuming only 400mW power at 40 MSPS. Data output
latches are provided which present valid data to the output bus
with a latency of 7 clock cycles. It is pin-to-pin compatible with
the HI5702.
F or lower po wer consumption or internal reference, please ref er
to the HI5746 or HI5767.
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI5703KCB 0 to 70 28 Ld SOIC (W) M28.3
HI5703EVAL 25 Evaluation Board
Pinout
HI5703
(SOIC)
TOP VIEW
Typical Application Schematic
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVCC1
DGND
DVCC1
DGND
AVCC
AGND
VREF+
VREF-
VIN+
VIN-
VDC
AGND
AVCC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D0
D2
D3
D4
DVCC2
DGND
D6
D7
D8
D9
DFS
D1
CLK
D5
HI5703
ARE PLACED AS CLOSE
10µF AND 0.1µF CAPS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BNC
CLOCK
VIN+
10µF
0.1µF10µF
+
+
3.25V
2.0V
VIN-
DGND AGND
VREF- (8)
VREF+ (7)
VIN- (10)
CLK (22)
DFS (15)
DGND (21)
DGND (4)
DGND (2)
AGND (6)
AGND (12)
VIN+ (9) (1) DVCC1
VDC (11)
(LSB) (28) D0
(27) D1
(26) D2
(25) D3
(24) D4
(20) D5
(19) D6
(18) D7
(17) D8
(MSB) (16) D9
(5) AVCC
(13) AVCC
(23) DVCC2
(3) DVCC1 TO PART AS POSSIBLE
OE (14) 0.1µF
+5V
+5V
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 3950.6
2
Functional Block Diagram
OE
+-
STAGE 1
STAGE 9
CLOCK
BIAS
VDC
VIN-
VIN+
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
CLK
DFS
AVCC AGND DVCC1 DGND VREF+VREF-
STAGE 10
X2
S/H
2-BIT
FLASH 2-BIT
DAC
X2
2-BIT
FLASH 2-BIT
DAC
1-BIT
FLASH
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
DVCC2
∑
+-
∑
HI5703
3
Absolute Maximum Ratings TA=25
o
CThermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND. . . . . . . . . . +6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range, HI5703KCB. . . . . . . . . . . . . . . . . .0oC to 70oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF- = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL= 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified
PARAMETER TEST CONDITION MIN TYP MAX UNITS
ACCURACY
Resolution 10 - - Bits
Integral Linearity Error, INL fIN = DC - ±1±2.0 LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes) fIN = DC - ±0.5 ±1 LSB
Offset Error, VOS fIN = DC - 4 - LSB
Full Scale Error, FSE fIN = DC - 1 - LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate No Missing Codes - 0.5 1 MSPS
Maximum Conversion Rate No Missing Codes 40 - - MSPS
Effective Number of Bits, ENOB fIN = 1MHz - 9.2 - Bits
fIN = 5MHz - 9.2 - Bits
fIN = 10MHz 8.55 8.9 - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 1MHz - 57 - dB
fIN = 5MHz - 57 - dB
fIN = 10MHz 53.2 55 - dB
Signal to Noise Ratio, SNR fIN = 1MHz - 58 - dB
fIN = 5MHz - 58 - dB
fIN = 10MHz 53.2 57 - dB
Total Harmonic Distortion, THD fIN = 1MHz - -64 - dBc
fIN = 5MHz - -63 - dBc
fIN = 10MHz - -60 - dBc
2nd Harmonic Distortion fIN = 1MHz - -75 - dBc
fIN = 5MHz - -75 - dBc
fIN = 10MHz - -73 - dBc
3rd Harmonic Distortion fIN = 1MHz - -66 - dBc
fIN = 5MHz - -64 - dBc
fIN = 10MHz - -63 - dBc
Spurious Free Dynamic Range, SFDR fIN = 1MHz - 66 - dBc
fIN = 5MHz - 64 - dBc
fIN = 10MHz 54 63 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - -59 - dBc
Differential Gain Error fS = 17.72MHz, 6 Step, Mod Ramp - 0.5 - %
Differential Phase Error fS = 17.72MHz, 6 Step, Mod Ramp - 0.1 - Degree
Transient Response - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive - 1 - Cycle
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------=
RMS Signal
RMS Noise
---------------------------------=
HI5703
4
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog
Input Range (VIN+ - VIN-)-±1.25 - V
Maximum Peak-to-Peak Single-Ended
Analog Input Range - 2.5 - V
Analog Input Resistance, RIN (Note 3) - 1 -MΩ
Analog Input Capacitance, CIN -7-pF
Analog Input Bias Current, IB+ or IB- (Note 3) -10 - +10 µA
Differential Analog Input Bias Current
IB DIFF = (IB+ - IB-) -±0.5 - µA
Analog Input Common Mode Voltage Range
(VIN++ V
IN-) / 2 Differential Mode (Note 1) 0.625 - 4.375 V
Full Power Input Bandwidth (FPBW) - 250 - MHz
REFERENCE INPUT
Total Reference Resistance, RL300 400 500 Ω
Reference Current 2.5 3.125 4.2 mA
Positive Reference Voltage Input, VREF+ (Note 2) - 3.25 3.3 V
Negative Reference Voltage Input, VREF- (Note 2) 1.95 2.0 - V
Reference Common Mode Voltage
(VREF++ V
REF-) / 2 (Note 2) 2.575 2.625 2.675 V
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC - 2.8 - V
Max Output Current - - 1 mA
DIGITAL INPUTS
Input Logic High Voltage, VIH 2.0 - - V
Input Logic Low Voltage, VIL - - 0.8 V
Input Logic High Current, IIH VIH = 5V - - 10.0 µA
Input Logic Low Current, IIL VIL = 0V - - 10.0 µA
Input Capacitance, CIN -7-pF
DIGITAL OUTPUTS
Output Logic Sink Current, IOL VO = 0.4V; DVCC2 = 5V 1.6 - - mA
Output Logic Source Current, IOH VO = 2.4V; DVCC2 = 5V -0.2 - - mA
Output Three-State Leakage Current, IOZ VO = 0/5V; DVCC2 = 5V - ±1±10 µA
Output Logic Sink Current, IOL VO = 0.4V; DVCC2 = 3.3V 1.6 - - mA
Output Logic Source Current, IOH VO = 2.4V; DVCC2 = 3.3V -0.2 - - mA
Output Three-State Leakage Current, IOZ VO = 0/3.3V; DVCC2 = 3.3V - ±1±10 µA
Output Capacitance, COUT -5-pF
TIMING CHARACTERISTICS
Aperture Delay, tAP -5-ns
Aperture Jitter, tAJ -5-ps
Data Output Delay, tOD -7-ns
AVCC = DVCC1 = 5V ±10%,
DVCC2 = 3.3V ±5%,
0oC≤TA≤70oC
5 7 18 ns
Data Output Hold, tH-4-ns
Data Output Enable Time, tEN -7-ns
Data Output Enable Time, tDIS -7-ns
Clock Pulse Width (Low) 40 MSPS Clock 11.875 12.5 13.125 ns
Clock Pulse Width (High) 40 MSPS Clock 11.875 12.5 13.125 ns
Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF- = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL= 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
HI5703
5
Data Latency, tLAT For a Valid Sample (Note 2) - - 7 Cycles
Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC 4.75 5.0 5.25 V
Digital Supply Voltage, DVCC1 4.75 5.0 5.25 V
Digital Output Supply Voltage, DVCC2 At 3.30V 3.135 3.3 3.465 V
At 5.0V 4.75 5.0 5.25 V
Total Supply Current, ICC VIN+ - VIN- = +1.25V and DFS = “0” - 80 - mA
Analog Supply Current, AICC VIN+ - VIN- = +1.25V and DFS = “0” - 48 - mA
Digital Supply Current, DICC1 VIN+ - VIN- = +1.25V and DFS = “0” - 30 - mA
Digital Output Supply Current, DICC2 VIN+ - VIN- = +1.25V and DFS = “0” - 2 - mA
Power Dissipation VIN+ - VIN- = +1.25V and DFS = “0” - 400 - mW
Offset Error Sensitivity, ∆VOS AVCC or DVCC = 5V ±5% - ±1.5 - LSB
Full Scale Error Sensitivity, ∆FSE AVCC or DVCC = 5V ±5% - ±0.2 - LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF- = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL= 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Timing Waveforms
NOTES:
4. SN: N-th sampling period.
5. HN: N-th holding period.
6. BM, N: M-th stage digital output corresponding to N-th sampled input.
7. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5703 INTERNAL CIRCUIT TIMING
DN - 7 DN - 6 DN - 2 DN - 1 DNDN + 1
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
2ND
STAGE
10TH
STAGE
DATA
OUTPUT
SN - 1 HN - 1 SNHNSN + 1 HN + 1 SN + 2 SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
B1, N - 1 B1, N B1, N + 1 B1, N + 4 B1, N + 5 B1, N + 6 B1, N + 7
B2, N - 2 B2, N - 1 B2, N B2, N + 4 B2, N + 5 B2, N + 6
B10, N - 5 B10, N - 4 B10, N B10, N + 1 B10, N + 2 B10, N + 3
tLAT
HI5703
6
FIGURE 2. INPUT-TO-OUTPUT TIMING
Typical Performance Curves
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
NO TE: SFDR depicted here does not include an y harmonic distortion.
FIGURE 4. TO TAL HARMONIC DISTOR TION (THD) AND
SPURIOUS FREE DYNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
FIGURE 5. SINAD, SNR, AND -THD vs INPUT FREQUENCY FIGURE 6. POWER DISSIPATION vs SAMPLE FREQUENCY
Timing Waveforms
(Continued)
tOD
tH
DATA N - 1 DATA N
CLOCK
INPUT
DATA
OUTPUT 0.8V
2.0V
1.5V
tAP
ANALOG
INPUT
tAJ
1.5V
9.0
8.0
7.0
6.0
1246810204060
80 100
EFFECTIVE NUMBER OF BITS (ENOB)
INPUT FREQUENCY (MHz)
fS = 40 MSPS
TEMPERATURE = 25oC
-35
-40
-45
-50
-55
-60
-65
-70
-75 1 2 4 6 8 10 20 40 60 80 100
fS = 40 MSPS
TEMPERATURE = 25oC
INPUT FREQUENCY (MHz)
dBc
THD
SFDR
65
60
55
50
45
40
35 1 2 4 6 8 10 20 40 60 80 100
-THD
SNR
INPUT FREQUENCY (MHz)
fS = 40 MSPS
TEMPERATURE = 25oC
dB
SINAD
450
410
430
390
370
350
330
310
290
270
250 0 5 10 15 20 25 30 35 40 45 50
fS(MSPS)
VIN + - VIN- = +1.25V AND DFS = “0”
TEMPERATURE = 25oC
POWER DISSIPATION (mW)
HI5703
7
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND SAMPLE FREQUENCY FIGURE 8. OUTPUT DELAY TIME (TOD) vs TEMPERATURE
FIGURE 9. POWER DISSIPA TION vs TEMPERATURE FIGURE 10. EFFECTIVE NUMBER OF BITS (ENOB) vs DUTY
CYCLE (TH/TTOTAL)
FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE
FREQUENCY FIGURE 12. INTERMODULATION DISTORTION (IMD) vs
TEMPERATURE
Typical Performance Curves
(Continued)
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0-40 -20 0 20 40 60 80 100
40 MSPS
45 MSPS
50 MSPS
TEMPERATURE (oC)
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10MHz
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
10.0
9.0
8.0
7.0
6.0
5.0
tOD
OUTPUT DELAY TIME (ns)
TEMPERATURE (oC)
450
440
430
420
410
400
390
380-40 -20 0 20 40 60 80
TEMPERATURE (oC)
POWER DISSIPATION (mW)
85
fS = 40 MSPS
VIN+ - VIN- = 1.25V, DFS = 0
9.0
8.0
7.5 45 46 47 48 49 50 51 52 53 54 55
8.5 fS = 40 MSPS
DUTY CYCLE (%)
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10MHz
TEMPERATURE = 25oC
9.5
9.0
8.5
8.0
7.5
7.0 010 20 30 40 50
f
IN = fS/4
TEMPERATURE = 25oC
12.5ns
50%
fS(MSPS)
EFFECTIVE NUMBER OF BITS (ENOB)
58.0
56.0
54.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
TEMPERATURE
IMD 1MHz
IMD 10MHz
INTERMODULATION DISTORTION (dBc)
HI5703
8
FIGURE 13. 4096 POINT FFT SPECTRAL PLOT
FIGURE 14. 4096 POINT FFT SPECTRAL PLOT
Typical Performance Curves
(Continued)
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB 0 200 400 600 800 1000 1200 1400 1600 1800 2047
OUTPUT LEVEL (dB)
FREQUENCY BIN
fIN = 10MHz
fS = 40 MSPS
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB 0 200 400 600 800 1000 1200 1400 1600 1800 2047
FREQUENCY BIN
OUTPUT LEVEL (dB)
fIN = 1MHz
fS = 40 MSPS
HI5703
9
Detailed Description
Theory of Operation
The HI5703 is a 10-bit fully differential sampling pipeline A/D
conver ter with digital error correction. Figure 15 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal,φ1 and
φ2, derived from the master clock. During the sampling
phase, φ1, the input signal is applied to the sampling capaci-
tors, CS. At the same time the holding capacitors, CH, are
discharged to analog ground. At the falling edge of φ1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, φ2, the two bottom
plates of the sampling capacitors are connected together
and the holding capacitors are switched to the op-amp
output nodes. The charge then redistributes between CS
and CH completing one sample-and-hold cycle. The output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the VIN pins see only the on-resistance of a
switch and CS. The relatively small values of these compo-
nents result in a typical full power input bandwidth of
250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, nine identical pipeline subconverter
stages, each containing a two-bit flash conver ter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the tenth stage being a one bit flash converter.
Each conver ter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each individ-
ual subconverter clock signal is offset by 180 degrees from
the previous stage clock signal resulting in alternate stages
in the pipeline performing the same operation.
The two-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to f orm the final ten bit output for the converter.
Because of the pipeline nature of this conver ter, the data on
the bus is output at the 7th cycle of the cloc k after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each suc-
ceeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a double
buffered latching technique.
The digital output bits are available in offset binary or two’s
complement format, the format being set by the Data Format
Select (DFS) input.
Reference Voltage Inputs, VREF- and VREF+
The HI5703 requires two reference voltages connected to the
VREF pins. The HI5703 is tested with VREF- equal to 2V and
VREF+ equal to 3.25V for a fully differential input voltage
range of ±1.25V. VREF+ and VREF- can differ from the above
voltages as long as the reference common mode voltage,
((VREF+ + VREF-)/2), does not exceed 2.625V ±50mV and
the limits on VREF+ and VREF- are not e xceeded.
In order to minimize overall conver ter noise it is recommended
that adequate high frequency decoupling be provided at the
ref erence v oltage input pins , VREF+ and VREF-.
TABLE 1. PIN DESCRIPTION
PIN # NAME DESCRIPTION
1DV
CC1 Digital Supply (+5.0V)
2 DGND Digital Ground
3DV
CC1 Digital Supply (+5.0V)
4 DGND Digital Ground
5AV
CC Analog Supply (+5.0V)
6 AGND Analog Ground
7V
REF+ Positive Reference Voltage Input
8V
REF- Negative Reference Voltage Input
9V
IN+ Positive Analog Input
10 VIN- Negative Analog Input
11 VDC DC Bias Voltage Output
12 AGND Analog Ground
13 AVCC Analog Supply (+5.0V)
14 OE Digital Output Enable Control Input
15 DFS Data Format Select Input
16 D9 Data Bit 9 Output (MSB)
17 D8 Data Bit 8 Output
18 D7 Data Bit 7 Output
19 D6 Data Bit 6 Output
20 D5 Data Bit 5 Output
21 DGND Digital Ground
22 CLK Sample Clock Input
23 DVCC2 Digital Output Supply (+3.3V to +5V)
24 D4 Data Bit 4 Output
25 D3 Data Bit 3 Output
26 D2 Data Bit 2 Output
27 D1 Data Bit 1 Output
28 D0 Data Bit 0 Output (LSB)
-
+
+
-
CH
CS
CS
CH
VIN+VOUT+
VOUT-
VIN-
φ1
φ1
φ1
φ2
φ1
φ1
φ1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
HI5703
10
Analog Input, Differential Connection
The analog input to the HI5703 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
diff erential connection (Figure 16 and Figure 17) will give the
best performance for the converter.
Since the HI5703 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.625V to
4.375V. The performance of the ADC does not change
significantly with the value of the analog input common
mode voltage.
A DC voltage source, VDC, equal to 2.8V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a ref erence b ut makes an
excellent bias source and stays within the analog input com-
mon mode voltage range over temperature. It has a tempera-
ture coefficient of appro ximately +200ppm/oC.
For the AC coupled differential input (Figure 16) assume
the difference between VREF+, typically 3.25V, and VREF-
, typically 2V, is 1.25V. Fullscale is achieved when the
VIN+ and VIN- inputs are 1.25VP-P, with VIN- being 180
degrees out of phase with VIN+. The converter will be at
positive fullscale when the VIN+ input is at VDC + 0.625V
and VIN- is at VDC - 0.625V (VIN+-V
IN- = 1.25V). Con-
versely, the converter will be at negative full scale when
the VIN+ input is equal to VDC - 0.625V and VIN- is at
VDC + 0.625V (VIN+-V
IN- = -1.25V).
The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.625V ≤VDC ≤4.375V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high fre-
quency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 18 may be used with a
single ended AC coupled input.
Again, assume the difference between VREF+, typically
3.25V, and VREF-, typically 2V, is 1.25V. If VIN is a 2.5VP-P
sinewave, then VIN+ is a 2.5VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at posi-
tive fullscale when VIN+ is at VDC + 1.25V and will be at
negative fullscale when VIN+ is equal to VDC - 1.25V. Suffi-
cient headroom must be provided such that the input voltage
never goes above +5V or below AGND. In this case, VDC
could range between 1.25V and 3.75V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the VDC output of the HI5703.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 19 is not absolutely necessar y but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high fre-
quency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first conver ted to differential before driv-
ing the HI5703. Refer to the application notes AN9534,
“Using the HI5703 Evaluation Board”, and AN9413, “Driving
the Analog Input of the HI5702”. Application note AN9413
VIN+
VDC
VIN-
HI5703
VIN
-VIN
R
R
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
VIN+
VDC
VIN-
HI5703
VIN
-VIN R
RC
VDC
VDC
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
VIN+
VIN-
HI5703
VIN
VDC
R
FIGURE 18. AC COUPLED SINGLE ENDED INPUT
VIN+
VIN-
HI5703
VDC
R
C
VIN
VDC
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
HI5703
11
applies to the HI5703 as well as the HI5702 and describes
several different ways of driving the analog differential
inputs.
Digital Output Control and Clock Requirements
The HI5703 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5703, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5703 will only be guaranteed at con-
version rates above 1 MSPS. This ensures proper perfor-
mance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s comple-
ment format. Refer to Table 2 for further information.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
Supply and Ground Considerations
The HI5703 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The dig-
ital data outputs also have a separate supply pin, DVCC2,
which can be powered from a 3.3V to 5.0V supply. This allows
the outputs to interf ace with 3.3V logic if so desired.
The par t should be mounted on a board that provides sepa-
rate low impedance connections for the analog and digital
supplies and grounds. For best performance, the supplies to
the HI5703 should be driven by clean, linear regulated sup-
plies. The board should also have good high frequency
decoupling capacitors mounted as close as possible to the
conver ter. If the part is powered off a single supply then the
analog supply and ground pins should be isolated by ferrite
beads from the digital supply and ground pins.
Refer to the application notes “Using Harris High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below positiv e Fullscale (+FS) with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
OE INPUT DIGITAL DATA OUTPUTS
0 Active
1 High Impedance
TABLE 2. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
OFFSET BINARY OUTPUT CODE
(DFS LOW) TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
M
S
B
L
S
B
M
S
B
L
S
B
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
+Full Scale (+FS) -
1/4 LSB 1.24939V 11111111110111111111
+FS - 11/4 LSB 1.24695V 11111111100111111110
+
3
/
4
LSB 1.83mV 10000000000000000000
-
1
/
4
LSB -0.610mV 01111111111111111111
-FS + 13/4 LSB -1.24573V 00000000011000000001
-Full Scale (-FS)
+3/4 LSB -1.24817V 00000000001000000000
NOTE:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage.
9. VREF+ = 3.25V and VREF- = 2.0V.
HI5703
12
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic perfor mance of the HI5703. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full scale f or all these tests.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction f actors for normalizing to full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02
where: VCORR = 0.5 dB
VCORR adjusts the ENOB for the amount the input is below
fullscale.
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS sum of
all the other spectral components below the Nyquist frequency,
fS/2, excluding DC .
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS/2
excluding the fundamental, the first five harmonics and DC.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic com-
ponents to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate inter-
modulation products when two tones, f1 and f2, are
present at the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in
the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2),
(2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each
tone 6dB below full scale.
Transient Response
Transient response is measured by providing a full scale transi-
tion to the analog input of the ADC and measuring the number of
cycles it takes f or the output code to settle within 10-bit accur acy.
Over-Voltage Recovery
Over-Voltage Recover y is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external sam-
ple command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus at the 7th cycle of the cloc k. This is due to the pipeline
nature of the conver ter where the data has to ripple through
the stages. This delay is specified as the data latency. After
the data latency time, the data representing each succeeding
sample is output at the following clock pulse. The digital data
lags the analog input sample by 7 cycles .
Power-Up initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5703
13
HFA1100
HFA1105
HFA1106
HFA1135
HFA1145
HFA1245
HI5702
HI5703 HSP9501
HSP48410
HSP48908
HSP48212
HSP43891
HSP43168
HSP43216
HI5780
HI1171
CA3338
HA5020
HA2842
HFA1115
HFA1212
HFA1412
HFA1100: 850MHz Video Op Amp
HFA1105: 300MHz Video Op Amp
HFA1106: 250MHz Video Op Amp with Bandwidth Limit Control
HFA1135: 350MHz Video Op Amp with Output Limiting
HFA1145: 300MHz Video Op Amp with Output Disable
HFA1245: Dual 350MHz Video Op Amp with Output Disable
HI5702: 10-Bit, 40 MSPS, A/D Converter
HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter
HSP9501: Programmable Data Buffer
HSP48410: Histogrammer/Accumulating Buffer, 10-Bit Pixel
Resolution
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HSP48212: Digital Video Mixer
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HI5780: 10-Bit, 80 MSPS, Video D/A Converter
HI1171: 8-Bit, 40 MSPS, Video D/A Converter
CA3338: 8-Bit, 50 MSPS, Video D/A Converter
HA5020: 100MHz Video Op Amp
HA2842: High Output Current, Video Op Amp
HFA1115: 225MHz Programmable Gain Video Buffer with
Output Limiting
HFA1212: 350MHz, Dual Programmable Gain Video Buffer
HFA1412: 350MHz, Quad Programmable Gain Video Buffer
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 20. 10-BIT VIDEO IMAGING COMPONENTS
HFA1100
HFA1110
HFA3101
HFA3102
HFA3600
HI5702
HI5703 HSP43168
HSP43216
HSP43220
HSP43891
HSP50016
HSP50110
HSP50210
HI5721
HI5780
HI20201
HI20203
HFA1112
HFA1113
HFA1100: 850MHz Op Amp
HFA1110: 750MHz Unity Gain Video Buffer
HFA3101: Gilbert Cell Transistor Array
HFA3102: Dual Long-Tailed Pair Transistor Array
HFA3600: Low Noise Amplifier/Mixer
HI5702: 10-Bit, 40 MSPS, A/D Converter
HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HSP43220: Decimating Digital Filter
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP50016: Digital Down Converter
HSP50110: Digital Quadrature Tuner
HSP50210: Digital Costas Loop
HI5721: 10-Bit, 100 MSPS, Communications D/A Converter
HI5780: 10-Bit, 80 MSPS, D/A Converter
HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter
HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter
HFA1112: 850MHz Programmable Gain Video Buffer
HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 21. 10-BIT COMMUNICATIONS COMPONENTS
DSP/µPAMPAMP D/AA/D
DSP/µPAMPAMP D/AA/D
HI5703
