INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1JANUARY 2004INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC-4678/2
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µµ
µµ
µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
IDT74LVCH162374A
DESCRIPTION:
The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The output enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH162374A can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH162374A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated thresholds.
The LVCH162374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT
EDGE TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
1OE
1D
C1
1CLK
1D1
1Q1
TO SEVEN OTHER CHANNELS
2OE
1D
C1
2CLK
2D1
2Q1
1
48
47
2
24
25
36
13
TO SEV EN OT HER CHA NNE LS
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, –5 0 mA
IOK VI < 0 or VO < 0
ICC Continuous Current through each ±1 0 0 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 6.5 8 pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTES:
1 . H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
Inputs Outputs
xOE xCLK xDx xQx
L↑HH
L↑LL
L H or L X Q(2)
HXX Z
FUNCTION T ABLE (EACH FLIP-FLOP)(1)
Pin Names Description
xDx Data Inputs(1)
xCLK Clock Inputs
xQx 3-State Outputs
xOE 3-State Output Enable Inputs (Active LOW)
PIN DESCRIPTION
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
1Q2
GND
VCC
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
481
1Q1
1OE
1Q4
1Q3
1Q6
1Q5
1Q8
1Q7
2Q1
2Q3
2Q2
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D2
GND
VCC
GND
GND
1D1
1CLK
1D4
1D3
1D6
1D5
1D8
1D7
2D1
2D3
2D2
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5µA
IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, V IN or VO ≤ 5.5V — — ±50 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC —— 10µA
ICCH
ICCZ 3.6 ≤ VIN ≤ 5.5V(2) —— 10
∆ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1) Test Conditions Min. Typ.(2) Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µ A
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V — — — µ A
IBHL VI = 0.7V — — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Unit
tPLH Propagation Delay 2 6.5 2 6.2 ns
tPHL xCLK to xQx
tPZH Output Enable Time 1.5 6.3 1.5 6.1 ns
tPZL xOE to xQx
tPHZ Output Disable Time 1.5 6.2 1.5 6 ns
tPLZ xOE to xQx
tSU Set-up Time HIGH or LOW, xDx before xCLK 2.5 — 2.5 — ns
tHHold Time HIGH or LOW, xDx after xCLK 1.5 — 1.5 — ns
tWxCLK Pulse Width HIGH or LOW 3 — 3 — ns
tSK(o) Output Skew(2) ———500 ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 4mA 1.9 —
IOH = – 6mA 1.7 —
VCC = 2.7V IOH = – 4mA 2.2 —
IOH = – 8mA 2 —
VCC = 3V IOH = – 6mA 2.4 —
IOH = – 12mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 4mA — 0.4
IOL = 6m A — 0.55
VCC = 2.7V IOL = 4mA — 0.4
IOL = 8mA — 0.6
VCC = 3V IOL = 6m A — 0.55
IOL = 12mA — 0.8
OPERA TING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol Parameter Test Conditions Typical Unit
CPD Power Dissipation Capacitance per Flip-Flop Outputs enabled CL = 0pF, f = 10Mhz —pF
CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled —
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
LVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUT PU T 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LV C Link
SAME PHASE
I N PU T T RAN SITION
OPPO SITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
LVC Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
LVC Link
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
LVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVCH162374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
IDT XX LVC XXXX XX
Package
Device Type
Temp. Range
PV
PA
162
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
16-Bit Edge Triggered D-Type Flip-Flop
-40°C to +85°C
XXX
FamilyBus-Hold
374A
Bus-hold
Double-Den sity with R esistors, ±12mA
H
