DSPIC30F6014-30I/PF - Microchip Technology

dsPIC30F6011/6012/6013/6014

The dsPIC30F6011/6012/6013/6014 family devices that

you have received conform functionally to the current

Device Data Sheet (DS70117F), except for the

anomalies described i n this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errat a described in this document will be addressed

in future revisions of the dsPIC30F6011/6012/6013/

6014 silicon.

Data Sheet clarifications and corrections start on page 25,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the device

to the MPLAB ICD 2 programmer/debugger or

PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Sel ect Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window .

The Device and Revision ID values for the various

dsPIC30F6011/6012/6013/6014 silicon revisions are

shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revision

(B2). Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID(1) Revision ID for Silicon Revision(2)

A3 B1 B2

dsPIC30F6011 0x0192

0x1003 0x1040 0x1042

dsPIC30F6012 0x0193

dsPIC30F6013 0x0197

dsPIC30F6014 0x0198

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC30F Flash Programming Specification” (DS70102) for detailed information on Device

and Revision IDs for your specific device.

dsPIC30F6011/6012/6013/6014 Family

Silicon Errata and Data Sheet Clarification

dsPIC30F6011/6012/6013/6014

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

A3 B1 B2

Data

EEPROM Speed 1. Data EEPROM is operational at 20 MIPS. X X X

CPU Unsigned

MAC

Instruction

2. The Unsigned Integer mode for the MAC-type DSP instructions

does not function as specified. XXX

CPU MAC class

Instructions

with +4

Address

Modification

3. Sequential MAC instructions, which prefetch data from Y data

space using +4 address modification, will cause an address

error trap.

XXX

CPU DAW.b

Instruction 4. The De cimal Adjust instruction, DAW.b, may improperly clear the

Carry bit, C (SR<0>). XXX

PSV

Operations — 5. In certain instructions, fetching one of the operands from

program memory using Program Space Visibility (PSV) will

corrupt specific bits in the STATUS Register, SR.

XXX

CPU Nested DO

Loops 6. When using two DO loops in a nested fash i o n, termi n a ti ng th e

inner-level DO loop by setting the EDT bit (CORCON<11>) will

produce unexpected results.

XXX

Flash

Memory RTSP 7. When a device Reset occurs while an Run-Time Self-

Programming (RTSP) operation is ongoing, code execution may

lead into an address error trap.

XXX

Data

Memory Y Data

Space 8. When an instruction that writes to a location in the address

range of Y data memory is immediately followed by a MAC-type

DSP instruction that reads a location also resident in Y data

memory, the operations will not be performed as specified.

XXX

Interrupt

Controller Trap s 9. When a catastrophic overflow of any of the accumulators causes

an arithmetic (math) error trap, the Overflow Status bits need to

be cleared to exit the trap handler.

XXX

CPU REPEAT

Instruction 10. When a REPEAT loop is interrupted by two or more interrupts in

a nested fashion, an address error trap may be caused. XXX

CPU DISI

Instruction 11. The DISI instruction will not disable interrupts if a DISI

instruction is executed in the same instruction cycle that the

DISI counter decrements to zero.

XXX

Timers 32-bit Mode 12. The 32-bit general purpose timers do not function as specified

for prescaler ratios other than 1:1. XXX

Output

Compare — 13. The Output Compare module will prod uce a glitch on the output

when an I/O pin is initially set high, and the module is configured

to drive the pin low at a specified time.

XXX

ADC Channel

Scanning 14. The 12-bit ADC scans one channel less than that specified when

configured to perform channel scanning on MUX A inputs and

alternately converting a fixed MUX B input.

XXX

DCI Slave Mode 15. In Slave mode, the DCI module does not function correctly when

data communication is configured to start one serial clock after

the frame synchronization pulse.

XXX

DCI Idle Mode 16. The DCI module should not be stopped when the device enters

Idle mode. XXX

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC30F6011/6012/6013/6014

CAN Read

Operations

on SFRs

17. Read operations performed on CAN module Special Function

Registers (SFRs) may yield incorrect results at operation over

20 MIPS.

XXX

Flash

Memory IDD Current 18. This re lease of silicon exhibits a current draw (IDD) of

approximately 370 mA during a Row Erase operation performed

on program Flash memory.

XXX

CPU Voltage

Regulation 19. For this release of silicon, applications operating off 5 volts VDD at

30 MIPS should ensure that the VDD remains within 5% of 5 volts. XXX

Flash

Memory Code

Protection 20. Addresses in the range 0x60 00 through 0xFFFF may not be

code-protected for this revision of dsPIC30F6011 and

dsPIC30F6013 silicon.

XXX

PLL 4x Mode 21. The 4x PLL mode of operation may not function correc tly for

certain input frequencies. XXX

Interrupt

Controller — 22. An interrupt occurrin g imme diately after modifying the CPU IPL,

interrupt IPL, interrupt enable or interrupt fla g may cause an

address error trap.

XXX

PLL 8x Mode 23. If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz

instead of 4 MHz-10 MHz. XXX

Sleep

Mode — 24. Execution of the Sleep instruction (PWRSAV #0) may cause

incorrect program operation after the device wakes up from

Sleep. The current consumption during Sleep may also increase

beyond the specifications listed in the device data sheet.

XXX

I2C™ Slave Mode 25. The I2C module loses incoming data bytes when operating as an

I2C slave. XXX

I/O Port Pin

Multiplexed

with IC1

26. The port I/O pin multiplexed with the Input Capture 1 (IC1)

function cannot be used as a digital input pin when the UART

auto-baud feature is enabled.

XXX

I2C 10-bit

Addressing 27. When the I2C module is configured for 10-bit addressing using

the same address bits (A10 and A9) as other I2C devices, the

A10 and A9 bits may not work as expected.

XXX

Timer Sleep Mode 28. Clock switching prevents the device from waking up from Sleep. X X X

PLL Lock Status

bit 29. The PLL LOCK S tatus bit (OSCCON<5>) can occasionally get

cleared and generate an oscillator failure trap even when the

PLL is still locked and functioning correctly.

XXX

PSV

Operations — 30. An address error trap occurs in certain addressing modes when

accessing the first four bytes of any PSV page. XXX

I2C 10-bit

Addressing 31. The 10-bit slave does not set t he RBF flag or load the I2CxRCV

the address are the same as the 7-bit reserved addresses.

XXX

I2C 10-bit

Addressing 32. When the I2C module is configured as a 10-bit slave with an

address of 0x102, the I2CxRCV register content for the lower

address byte is 0x01 rather than 0x02.

XXX

I2C Bus Collision 33. When the I2C module is enabled, the dsPIC® DSC device

generates a glitch on the SDA and SCL pins, causing a false

communication start in a single-master configuration or a bus

collision in a multi-master configuration.

XXX

CAN RX Filters 3,

4 and 5 34. CAN Receive filters 3, 4 and 5 may not work for a given

combination of instruction cycle speed and CAN bit time quanta. XXX

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

A3 B1 B2

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC30F6011/6012/6013/6014

Interrupt

Controller IPC2 Write

Sequence 35. A specific write sequence for Interrupt Priority Control 2 (IPC2)

SFR is required. XX

Program

Memory RTSP

Operations 36. R TSP operations may not be performed on the Program Memory.

RTSP operations can however be performed on the on-chip Data

EEPROM.

ADC Sequential

Sampling 37. Sampling multiple channels sequential ly us ing any conversion

trigger other than the auto-convert feature requir es SAMC bits to

be non-zero.

QEI In dex Pulse

Mode 38. The Reset on Index Pulse Mode does not work. X

PWM Time Base

Prescalers 39. The Motor Control PWM Time base prescaler options: 1:4, 1:16

and 1:64 may produce unexpected results when used to

generate center-aligned PWM pulses.

PWM Output

Override 40. The output override func tion of the PWM module, controlled by

the OVDCON register and the OSYNC bit (PWMCON2<1>),

produces unexpected results in certain cases when the module

is used in Complementary mode.

CPU IPD Sleep

Current 41. The device exhibits IPD less than 0.1 μA. However, certain work

arounds are required to achieve IPD in this range. X

ADC Current

Consumption

in Sleep

Mode

42. If the ADC module is in an enabled state when the device enters

Sleep Mode, the power-down current (IPD) of the device may

exceed the device data sheet specifications.

XXX

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

A3 B1 B2

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC30F6011/6012/6013/6014

Silicon Errata Issues

1. Module: Data EEPROM

At device throughput greater than 20 MIPS for

VDD, in the range 4.75V to 5.5V (or 10 MIPS for

VDD in the range 3V to 3.6V), Table Read

instructions (TBLRDL/TBLRDH) and instructions

that use Program Space Visibility do not function

correctly when reading data from data EEPROM.

Work around

When reading data from data EEPROM, the

application should perform a clock switch

operation to lower the frequency of the system

clock so that the throughput is less than 20 MIPS.

This may be easily performed at any time via the

Oscillator Postscaler bits, POST<1:0>

(OSCCON<7:6>), that allow the application to

divide the system clock down by a factor of 4, 16

or 64.

Affected Silicon Revisions

2. Module: CPU

The US bit (CORCON<12>) controls whether MAC-

type DSP instructions operate in Signed or Unsigned

mode. The device defaults to a Signed mode on

power-up (US = 0).

For this revision of silicon, MAC-type DSP

instructions do not function as specified in

Unsigned mode (US = 1). Also, for this revision,

the US bit will always read as ‘0’.

Work around

Ensure that the US bit is not set by the application.

In order to perform unsigned integer

multiplications, use the MCU Multiply instruction,

MUL.UU.

Affected Silicon Revisions

3. Module: CPU

Sequential MAC class instructions, which prefetch

data from Y data space using +4 address

modification, will cause an address error trap. The

trap occurs only when all of the following

conditions are true:

1. Two sequential MAC class instructions (or a

MAC class instruction executed in a REPEAT or

DO loop) that prefetch from Y data space.

2. Both instructions prefetch data from Y data

space using the + = 4 or - = 4 address

modification.

3. Neither of the instruction uses an accumulator

write back.

Work arou nd

The problem de scribed above can be avoided by

using any of the following methods:

1. Inserting any other instruction between the two

MAC class instructions.

2. Adding an accumulator write back (a dummy

write back if needed) to either of the MAC class

instructions.

3. Do not use the + = 4 or - = 4 address

modification.

4. Do not prefetch data from Y data space.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (B2).

A3 B1 B2

XXX

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

4. Module: CPU

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>), when

executed.

Work around

Check the state of the Carry bit prior to executing

the DAW.b instruction. If the Carry bit is set, set the

Carry bit again after executing the DAW.b

instruction. Example 1 shows how the applicatio n

should process the Carry bit during a BCD addition

operation.

EXAMPLE 1: CHECK CARRY BIT BEFORE

DAW.b

Affected Silicon Revisions

.include “p30fxxxx.inc”

.......

mov.b #0x80, w0 ;First BCD number

mov.b #0x80, w1 ;Second BCD number

add.b w0, w1, w2 ;Perform addition

bra NC, L0 ;If C set go to L0

daw.b w2 ;If not, do DAW and

bset.b SR, #C ;set the carry bit

bra L1 ;and exit

L0:daw.b w2

L1: ....

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

5. Module: PSV Operations

When one of the operands of instructions shown in

Table 3 is fetched from program memory using

Program Space Visibility (PSV), the STATUS

These instructions are identified in Table 3.

Example 2 demonstrates a scenario where this

occurs.

Also, always use Work around 2 if the C compiler

is used to generate code for dsPIC30F6011/6012/

6013/6014 devices.

EXAMPLE 2: INCORRECT RESULT S

Work arounds

Work around 1: For Assembly Language

Source Code

To work around the erratum in the MPLAB ASM30

assembler, the application may perform a PSV

access to move the source operand from program

memory to RAM or a W register prior to performing

the operations listed in Table 3. The work around

for Example 2 is demonstrated in Example 3.

EXAMPLE 3: CORRECT RESULTS

Work around 2: For C Language Source Code

For applications using C language, MPLAB C30

versions 1.20.04 or higher provide the following

command-line switch that implements a work

around for the erratum.

-merrata=psv

Refer to the “readme.txt” file in the MPLAB C30

v1.20.04 toolsuite for further details.

Affected Silicon Revisions

TABLE 3: AFFECTED INSTRUCTIONS

Instruction(1) Examples of Incorrect Operation(2) Data Corruption IN

ADDC ADDC W0, [W1++], W2 ; SR<1:0> bits(3), Result in W2

SUBB SUBB.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3

SUBBR SUBBR.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3

CPB CPB W0, [W1++], W4 ; SR<1:0> bits(3)

RLC RLC [W1], W4 ; SR<1:0> bits(3), Result in W4

RRC RRC [W1], W2 ; SR<1:0> bits(3), Result in W2

ADD (Accumulator-based) ADD [W1++], A ; SR<1:0> bits(3)

LAC LAC [W1], A ; SR<15:10> bits(4)

Note 1: Refer to the “dsPIC30F/33F Programmer’s Reference Manual”, (DS70157), for details on the dsPIC30F

Instruction set.

2: The errata only affects these instructions when a PSV access is performed to fetch one of the source

operands in the instruction. A PSV access is performed when the Effective Address of the source operand

is greater than 0x8000 and the PSV bit (CORCON<2>) is set to ‘1’. In the examples shown, the data

access from program memory is made via the W1 register.

3: SR<1:0> bits represent Sticky Zero and Carry Status bits respectively.

4: SR<15:10> bits represent Accumulator Overflow and Saturation Status bits.

.include “p30fxxxx.inc”

.......

MOV.B #0x00, W0 ;Load PSVPAG register

MOV.B WREG, PSVPAG

BSET CORCON, #PSV;Enable PSV

....

MOV #0x8200, W1;Set up W1 for

;indirect PSV access

;from 0x000200

ADD W3, [W1++], W5 ;This instruction

;works ok

ADDC W4, [W1++], W6 ;Carry flag and

;W6 gets

;corrupted here!

.include “p30fxxxx.inc”

.......

MOV.B #0x00, w0 ;Load PSVPAG register

MOV.B WREG, PSVPAG

BSET CORCON, #PSV;Enable PSV

....

MOV #0x8200, W1;Set up W1 for

;indirect PSV access

;from 0x000200

ADD W3, [W1++], W5;This instruction

;works ok

MOV [W1++], W2 ;Load W2 with data

;from program memory

ADDC W4, W2, W6 ;Carry flag and W4

;results are ok!

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

6. Module: CPU

When using two DO loops in a nested fashion,

terminating the inner-level DO loop by setting the

EDT bit (CORCON<11>) will produce unexpected

results. Specifically, the device may continue

executing code within the outer DO loop forever.

This erratum does not affect the operation of the

MPLAB C30 compiler.

Work around

The application should save the DCOUNT Special

Function Register (SFR) prior to entering the inner

DO loop and restore it upon exiting the inner DO

loop. This work around is shown in Example 4.

EXAMPLE 4: SAVE AND RESTORE

DCOUNT

Affected Silicon Revisions

7. Module: Flash Memory

If a device Reset occurs while an Ru n-Time Self-

Programming (RTSP) operation is ongoing, code

execution after the Reset may lead to an address

error trap.

Work aro und

The user should define an address error Trap Ser-

vice Routine (TSR), as shown in Example 5, in

order to allow normal code execution to continue.

EXAMPLE 5: TRAP SERVICE ROUTINE

Affected Silicon Revisions

.include “p30fxxxx.inc”

.......

DO #CNT1, LOOP0 ;Outer loop start

....

PUSH DCOUNT ;Save DCOUNT

DO #CNT2, LOOP1 ;Inner loop

.... ;starts

BTSS Flag, #0

BSET CORCON, #EDT;Terminate inner

.... ;DO-loop early

....

LOOP1: MOV W1, W5 ;Inner loop ends

POP DCOUNT ;Restore DCOUNT

...

LOOP0: MOV W5, W8 ;Outer loop ends

Note: For details on the functionality of

EDT bit, see section 2.9.2.4

in the dsPIC30F Family Reference

Manual.

A3 B1 B2

XXX

__AddressError:

bclr RCON, #TRAPR ;Clear the Trap

;Reset Flag Bit

bclr INTCON1, #ADDRERR ;Clear the

;Address Error

;trap flag bit

reset ;Software reset

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

8. Module: Data Memory

When an instruction that writes to a location in the

address range of Y data memory (addresses

between 0x1800 and 0x27FF) is immediately

followed by a MAC-type DSP instruction that reads

a location also resident in Y data memory, the two

operations will not b e executed as specified. This

is demonstrated in Example 6.

EXAMPLE 6: INCORRECT RESULT S

Work arounds

Work around 1:

Insert a NOP between the two instructions as

shown in E xample 7.

EXAMPLE 7: CORRECT RESULTS

Work around 2:

If work around #1 is not feasible due to application

real-time constraints, the user may take

precautions to ensure that a write operation

performed on a location in Y data memory is not

immediately followed by a DSP MAC-type

instruction that performs a read operation of a

location in Y data memory.

Affected Silicon Revisions

9. Module: Interrupt Controller

Catastrophic accumulator overflow traps are

enabled as follows:

- COVTE (INTCON1<8>) = 1

- SATA/SATB (CORCON <7:6>) = 0

A carry generated out of bit 39 in the accu mulator

causes a catastrophic overflow of the accumulator

since the sign bit has been destroyed. If a math

error trap handler has been defined, the processor

will vector to the math error trap handler upon a

catastrophic overflow.

If the respective Accumulator Overflow status bit,

OA or OB (SR<15/14>), is not cleared within the

trap handler routine prior to exiting the trap handler

routine, the processor will immediately re-enter the

trap handler routine.

Work arou nd

If a math error trap occurs due to a catastrophic

accumulator overflow, the overflow status flags,

OA and/or OB (SR<15:14>), should be cleared

within the trap handler routine. Subsequently, the

MATHERR (INTCON1<4>) flag bit should be

cleared within the trap handler prior to executing

the RETFIE instruction.

Since the OA and OB bits are read-only bits, it will be

necessary to execute a dummy accumulator-based

instruction within the trap service routine in order to

clear these status bits, and eventually clear the

MATHERR trap flag. This is shown in Example 8.

EXAMPLE 8: USING DUMMY DSP

INSTRUCTION

Affected Silicon Revisions

MOV #0 x190A, W0 ;Load address > =

;0x1800 into W0

MOV #0 x19B0, W10 ;Load address >=

;0x1800 into W10

MOV W2 , [W0++ ] ;Perform indirect

;write via W0 to

;address >= 0x1800

MAC W4 *W5, A, [W10]+ =2, W5 ;Perform

;read operation

;using Y-AGU

:Unexpected Results !

MOV #0 x190A, W0 ;Load address > =

;0x1800 into W0

MOV #0 x19B0, W10 ;Load address >=

;0x1800 into W10

MOV W2 , [W0++ ] ;Perform indirect

;write via W0 to

;address >= 0x1800

NOP ;No operation

MAC W4 *W5, A, [W10]+ =2, W5 ;Perform

;read operation

;using Y-AGU

:Correct Result s!

A3 B1 B2

XXX

.global __MathError

__MathError: BTSC SR, #OA

CLR A

BTSC SR, #OB

CLR B

BCLR INTCON1, #MATHERR

RETFIE

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

10. Module: CPU

When interrupt nesting is ena bled (or NSTDIS bit

(INTCON1<15>) is ‘0’), the following sequence of

events will lead to an address error trap:

1. REPEAT loop is acti ve.

2. An interrupt is generated d uring the execution

of the REPEAT loop.

3. The CPU executes the Interrupt Service

Routine (ISR) of the source causing the

interrupt.

4. Within the ISR, when the CPU is executing the

first instruction cycle of the 3-cycle RETFIE

(Return-from-Interrupt) instruction, a second

interrupt is generated by a source with a higher

interrupt priority.

Work around

Processing of Interrupt Service Routines should

be disabled while th e RETFIE instruction is being

executed. This may be accomplished in two

different ways:

1. Place a DISI instruction immediately before

the RETFIE instruction in all Interrupt Service

Routines of interrupt sources that may be

interrupted by other higher priority interrupt

sources (with priority levels 1 through 6). This

is shown in Example 9 in the Timer1 ISR. In

this example, a DISI instruction inhibits level 1

through level 6 interrupts for 2 instruction

cycles, while the RETFIE instruction is

executed.

EXAMPLE 9: DISI BEFORE RETFIE

2. Immediately prior to executing the RETFIE

instruction, increase the CPU priority level by

modifying the IPL<2:0> bits (SR<7:5>) to ‘111’

as shown in Example 10. This will disable all

interrupts between priority levels 1 through 7.

EXAMPLE 10: RAISE IPL BEFORE RETFIE

Affected Silicon Revisions

11. Module: CPU

When a user executes a DISI #7, for example,

this will disable interrupts for 7 + 1 cycles (7 + the

DISI instruction itself). In this case, the DISI

instruction uses a counter which counts down from

7 to 0. The counter is loaded with 7 at the end of

the DISI instruction.

If the user code executes another DISI on the

instruction cycle where the DISI counter has

become zero, the new DISI count is loaded, but the

DISI state machine does not properly re-engage

and continue to disable interrupts. At this point, all

interrupts are en abled. The next time the user code

executes a DISI instruction, the feature will act

normally and block interrupts.

In summary, it is only when a DISI execution is

coincident with the current DISI count = 0, that the

issue occurs. Executing a DISI instruction before

the DISI counter reaches zero will not produce

this error. In this case, the DISI counter is loaded

with the new value, and interrupts remain disabled

until the co un te r becomes zero.

Work aro und

When executing multiple DISI instructions wi thin

the source code, make sure that subsequent DISI

instructions have at least one instruction cycle

between the time that the DISI counter

decrements to zero and the next DISI instruction.

Alternatively, make sure that subsequent DISI

instructions are called before the DISI counter

decrements to zero.

Affected Silicon Revisions

__T1Interrupt: ;Timer1 ISR

PUSH W0 ;This line optional

.......

BCLR IFS0, #T1IF

POP W0 ;This line optional

DISI #1

RETFIE ;Another interrupt occurs

;here and it is processed

;correctly

__T1Interrupt: ;Timer1 ISR

PUSH W0

.......

BCLR IFS0, #T1IF

MOV.B #0xE0, W0

MOV.B WREG, SR

POP W0

RETFIE ;Another interrupt occurs

;here and it is processed

;correctly

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

12. Module: Timers

Pairs of 16-bit timers may be combined to form

32-bit timers. For example, T imer2 and T imer3 are

combined into a single 32-bit timer. For this

release of silicon, when a 32-bit timer is prescaled

by ratios other than 1:1, unexpected results may

occur.

Work around

None. The application may only use the 1:1

prescaler for 32-bit timers.

Affected Silicon Revisions

13. Module: Output Compare

A glitch will be produced on an output compare pin

under the following conditions:

• The user software initially drives the I/O pin

high using the Output Compare module or a

write to the associated PORT register.

• The Output Compare module is configured and

enabled to drive the pin low at some point in later

time (OCxCON = 0x0002 or OCxCON = 0x0003).

When these events occur, the Output Compare

module will drive the pin low for one instruction

cycle (TCY) after the module is enabled.

Work around

None. However , the user may use a timer interrupt

and write to the associated PORT register to

control the pin manually.

Affected Silicon Revisions

14. Module: ADC

Input channel scanning allows the ADC to acquire

and convert signals on a selected set of “MUX A”

input pins in sequence. Thi s function is controlled

by the CSCNA bit (ADCON2<10>) and the

ADCSSL SFR.

The ALTS bit (ADCON2<0>), when set, allows the

ADC to alternately acquire and convert a “MUX A”

input signal and a “MUX B” input signal in an

interleaved fashion.

When both CSCNA and ALTS are set, the ADC

module should scan MUX A input pins while

alternating with a fixed MUX B input pin. However ,

for this release of silicon, when both features are

enabled simultaneously, the last input pin enabl ed

for channel scanning in the ADCSSL SFR is not

scanned. Thus, the ADC converts one channel

less than the number specified in the scan

sequence. Note that this erratum does not affect

devices that have a 10-bit 500 ksps ADC.

Work arou nd

The user may enable an extra (“dummy”) input pin

in the channel-scanning sequence. For example, if

it is desirable to scan pins AN 3, AN4 and AN5 on

the set of MUX A inputs while interleaving

conversion from AN6 on the MUX B input, the user

may configure the ADC as follows:

- ADCON2 = 0x041D

- ADCHS = 0x0600

- ADCSSL = 0x8038

For the configuration above, AN15 is the dummy

input that will not be scanned. On the A/D interrupt,

the A/D buffer will contain conversions from the

following pins in sequence:

- ADCBUF0 = AN3

- ADCBUF1 = AN6

- ADCBUF2 = AN4

- ADCBUF3 = AN6

- ADCBUF4 = AN5

- ADCBUF5 = AN6

- ADCBUF6 = AN3

- ADCBUF7 = AN6

Affected Silicon Revisions

A3 B1 B2

XXX

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

15. Module: DCI

The Data Converter Interface (DCI) module does

not function correctly in Slave mode when the

following conditions are true:

• The DCI module is configured to transmit/receive

one serial clock (bit clock) after the frame

synchronization pulse, DJST (DCICON1<5>) = 0.

• The frame length chosen is longer than 1 word,

COFSG<3:0> (DCICON2<8:5>) > ‘0000’.

Work around

The following work around may be applied to

enable DCI communication in Slave mode when it

is configured to transmit one se rial clock after the

frame synchronization pulse is received in a

multi-word frame:

1. Set the DJST bit to ‘1’.

2. Enable an additional time slot immediately

following each time slot intended for

communication.

3. Enable an additional transmit/receive buffer

word (modify COFSG bits) or an additional bit

per word (modify WS) for each time slot

intended for communication.

4. Shift the data word by 1-bit to the right and load

the transmit buffer word(s), such that the Least

Significant bit of the original data word to be

transmitted is loaded into the additionally

enabled bit of the Transmit Buffer register,

TXBUFn, or the Most Significant bit (MSb) of

the additionally enabled transmit buffer,

TXBUFn + 1.

This work around is now demonstrated by an

example.

Assume, the application needs the DCI module to

act as a Slave transmitting 1 serial clock after the

frame synchronization pulse is received. Further,

assume that the application needs to transmit

16-bit data word on Time Slot 0 and the

communication is over a 256*FS channel. In order

to reduce interrupt frequency, we enable all 4

transmit buffers. The DCI module SFRs should be

initialized as follows before being enabled:

- DCICON1 = 0x0720, DCICON2 = 0x0DEF

DCICON3 = 0x0000,

TSCON = RSCON = 0x0003

An example of loading the DCI transmit buffers for

the configuration above is shown in Example 1 1. A

timing diagram in Figure 1 illustrates the various

signals for this example. A similar rule may be

applied to reading the received data from the

RXBUFn SFRs.

Affected Silicon Revisions

EXAMPLE 11: DCI SLAVE W ORK AROUND

FIGURE 1: DCI SLAVE WORK AROUND

A3 B1 B2

XXX

BCLR SR, #C

MOV My1stTxDataWord, W0

RRC W0, W0

RRC W1, W1

MOV W0, TXBUF0

MOV W1, TXBUF1

MOV My2ndTxDataWord, W0

RRC W0, W0

RRC W1, W1

MOV W0, TXBUF2

MOV W1, TXBUF3

CSCK

Data

COFS

Frame Synch and first data bit sampled here

Time Slot 0

LSb

+ 1 LSb

Time Slot 1

Data from TXBUF0 Data from TXBUF1

Note 1: The Slave mode operation shown in this figure uses the DCI module’s operation with DJST = 1, to create a work around

for the erratum associated with the DCI module when DJST = 0.

2: Note that the actual data intended for transmission on Time Slot 0 is now straddled across two time slots – Time Slot

0 and T ime Slot 1. The MSb of T ime Slot 0 is ‘0’; while the MSb of T ime Slot 1 is actually the LSb of the data intended

for transmission.

3: Data loaded into TXBUF0 contains 15 MSbs of the actual 16-bit data to be transmitted, while the MSb of TXBUF0 is

cleared.

4: Not all serial clock pulses are shown in this timing diagram.

MSb

Actual Data to be transmitte d

dsPIC30F6011/6012/6013/6014

16. Module: DCI

For this release of silicon, the DCI module should

not be stopped when the device enters Idle mode.

Work around

Do not set the DCISIDL bit (DCICON1 <13>). This

will ensure the DCI module conti nues to run when

the device enters Idle mode.

Affected Silicon Revisions

17. Module: CAN

Data read from the CAN module Specia l Function

Registers may not be correct at device operation

greater than 20 MIPS for VDD in the range 4.7 5V

to 5.5V (or 10 MIPS for VDD in the range 3V to

3.6V).

If the dsPIC DSC device needs to operate at a

throughput higher than 20 MIPS, the user should

incorporate the suggested work arounds while

reading CAN SFRs.

Applications that use Microchip’s dsPIC30F

Peripheral Library and Vector Informatik’s

CANbedded software, should operate the device

at 20 MIPS or less.

Work arounds

Work around 1: For Assembly Language

Source Code

When reading any CAN SFR, perform two

consecutive read operations of that SFR. The work

around is demonstrated in Example 12. In this

example, a Memory-Direct Addressing mode is

used to read the SFR. The application may use

any addressing mode to perform the read

operation. Note that interrupts must be disabled so

that the two consecutive reads do not get

interrupted.

EXAMPLE 12: CONSECUTIVE READS

Work around 2: For C Language Source Code

For C programmers, the MPLAB C30 v1.20.02

toolsuite provides a built-in function that may be

incorporated in the application source code. This

function may be used to read any CAN module

SFRs. Some examples of usage are shown i n the

“readme.txt” file provided with the MPLAB C30

v1.20.02 toolsuite. The function has the following

prototype:

unsigned __builtin_readsfr(volatile void *);

The function argument is the address of a 16-bit

SFR. This function should only be used to read the

CAN Special Function Registers.

Affected Silicon Revisions

18. Module: Flash Memory

This release of silicon draws a current (IDD) of

approximately 370 mA during any Row Erase

operation performed on program Flash memory.

Work arou nd s

Work arou nd 1:

Supply the VDD pin using a voltage regulator

capable of sourcing a minimum of 300 mA of

current.

Work arou nd 2:

When using a voltage regulator capable of driving

150 mA current and if Brown-out Reset (BOR) is

enabled for a VDD greater than or equal to 4.2V,

then connect a 1000 μF Electrolytic capacitor

across the VDD pin and ground.

If the Row Erase operation is performed as part of

a RTSP operation, the user should ensure that the

device is operating at less than 10 MIPS prior to

the erase operation. To ensure that the device is

operating at less than 10 MIPS, the application

may post-scale the system clock or switch to the

internal FRC oscillator.

Affected Silicon Revisions

A3 B1 B2

XXX

.include “p30f6014.inc”

....

disi #1

mov C1RXF0SIDL, w0 ; first SFR read

mov C1RXF0SIDL, w0 ; second SFR read

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

19. Module: CPU

Applications operating off 5 volts VDD at 30 MIPS

should ensure the VDD remains between 4.75V

and 5.5V. For 5V applications, Table 4 summa-

rizes the maximum MIPS that can be achieved

across various temperatures.

Work around

For 5 volt applications, use a voltage regulator that

ensures VDD is in the range 4.75V to 5.5V, in order

to achieve 30 MIPS operation.

Affected Silicon Revisions

TABLE 4: OPERATING MIPS VS. VOLTAGE

Note: Applications that use the CAN peripherals and data EEPROM should also refer to module 1. (Data EEPROM)

and module 17. (CAN).

20. Module: Flash Memory

Addresses in the range, 0x6000 through 0xFFFF,

may not be code-protected for this revision of

dsPIC30F6011 and dsPIC30F6013 silicon.

Work around

None.

Affected Silicon Revisions

21. Module: PLL

When the 4x PLL mode of operation is selected, the

specified input frequency range of 4 MHz-10 MHz is

not fully supported.

When device VDD is 2.5V-3.0V, the 4x PLL input

frequency must be in the range of 4 MHz-5 MHz.

When device VDD is 3.0V-3.6V, the 4x PLL input

frequency must be in the range of 4 MHz-6 MHz

for both industrial and extended temperature

ranges.

Work aro und

1. Use 8x PLL or 16x PLL mode of operation and

set final device clock speed using the

POST<1:0> oscillator postscaler control bits

(OSCCON<7:6>).

2. Use the EC without PLL Clock mode with a

suitable clock frequency to obtain the

equivalent 4x PLL clock rate.

Affected Silicon Revisions

A3 B1 B2

XXX

VDD Range

(in volts) Temp Range

(in °C) Max MIPS

dsPIC30FXXX-30I dsPIC30FXXX-20I dsPIC30FXXX-20E

4.75 to 5.5 -40 to +85 30 20 —

4.75 to 5.5 -40 to +125 — — 20

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

22. Module: Interrupt Controller

The following sequence of events will lead to an

address error trap. The generic term

“Interrupt 1” is used to represent any enabled

dsPIC30F interrupt.

1. User software performs one of the following

operations:

- CPU IPL is raised to Interrupt 1 IPL

level or higher, or

- Interrupt 1 IPL is lowered to CPU IPL

level or lower , or

- Interrupt 1 is disabled (Interrupt 1 IE

bit set to ‘0’), or

- Interrup t 1 fl a g is cleared

2. Interrupt 1 o ccurs be tween 2 and 4 instructio n

cycles after any of the operations listed above.

Work arounds

Work around 1: For Assembly Language

Source Code

The user may disable in terrupt nesting, disable

interrupts before modifying the Interrupt 1 set-

ting or execute a DISI instruction before modi-

fying the CPU IPL or Interrupt 1. A minimum

DISI value of 4 is required if the DISI instruction

is executed immediately before the CPU IPL or

Interrupt 1 is modified, as shown in Example 13.

It is necessary to have DISI active for four cycles

after the CPU IPL or Interrupt 1 is modified.

EXAMPLE 13: USING DISI

Work around 2: For C Language Source Code

For applications using th e C language, MPLAB

C30 versions 1.32 and higher provide several

macros for modifying the CPU IPL. The

SET_CPU_IPL macro provides the ability to

safely modify the CPU IPL, as shown in

Example 14.

EXAMPLE 14: USING SET_CPU_IPL

MACRO

There is one level of DISI, so this macro saves

and restores the DISI state. For temporarily

modifying and restoring the CPU IPL, the mac-

ros SET_AND_SAVE_CPU_IPL and

RESTORE_CPU_IPL can be used, as shown in

Example 15. These macros also make use of

the SET_CPU_IPL macro.

EXAMPLE 15: USING SET_AND_SAVE_CPU_IPL AND RESTORE_CPU_IPL MACROS

.include "p30fxxxx.inc"

...

DISI #4 ; protect the disable

; of INT1

BCLR IEC1, #INT1IE ; disable interrupt 1

... ; next instruction

;protected by DISI

// Note: Macro defined in device include

// files

#define SET_CPU_IPL (ipl){ \

int DISI_save; \

DISI_save = DISICNT; \

asm volatile ("disi #0x3FFF");\

SRbits.IPL = ipl; \

DISICNT = DISI_save; } (void) 0;

__builtin_nop(); \

#include "p30fxxxx.h"

. . .

SET_CPU_IPL (3)

. . .

// Note: Macros defined in device include files

#define SET_AND_SAVE_CPU_IPL (save_to, ipl){ \

save_to = SRbits.IPL; \

SET_CPU_IPL (ipl); } (void) 0;

#define RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to)

#include "p30fxxxx.h"

. . .

int save_to;

SET_AND_SAVE_CPU_IPL (save_to, 3)

. . .

RESTORE_CPU_IPL (save_to)

dsPIC30F6011/6012/6013/6014

For modification of the Interrupt 1 setting, the

INTERRUPT_PROTECT macro can be used.

This macro disables interrupts before executing

the desired expression, as shown in

Example 16. This macro is not distributed with

the compiler.

EXAMPLE 16: USING INTERRUPT_PROTECT

MACRO

Affected Silicon Revisions

23. Module: PLL

If 8x PLL mode is used, the input frequency range

is 5 MHz-10 MHz instead of 4 MHz-10 MHz.

Work aro und

None. If 8x PLL is used, ensure that the input

crystal or clock frequency is 5 MHz or greater.

Affected Silicon Revisions

Note: If you are using a MPLAB C30 compiler

version earlier than version 1.32, you may

still use the macros by adding them to your

application.

A3 B1 B2

XXX

#define INTERRUPT_PROTECT (x) { \

int save_sr; \

SET_AND_SAVE_CPU_IPL (save_sr, 7);\

x; \

RESTORE_CPU_IPL (save_sr); } (void) 0;

. . .

INTERRUPT_PROTECT (IEC0bits.U1TXIE=0);

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

24. Module: Sleep Mode

Execution of the Sleep instruction (PWRSAV #0)

may cause incorrect program operation after the

device wakes up from Sleep. The current

consumption during Sleep may also increase

beyond the specification s li sted in the device data

sheet.

Work arounds

To avoid this issue, implement any of the following

three work arounds, de pending on th e application

requirements.

Work around 1:

Ensure that the PWRSAV #0 instruction is located

at the end of the last row of program Flash memory

available on the target device and fill the

remainder of the row with NOP instructions.

This can be accomplished by replacing all

occurrences of the PWRSAV #0 instruction with a

function call to a suitably aligned subroutine . The

address( ) attribute provided by the MPLAB

ASM30 assembler can be utilized to correctly align

the instructions in the subroutine. For an

application written in C, the function call wo uld be

GotoSleep( ), while for an assembly language

application, the function call would be

CALL _GotoSleep.

The address error trap service routine software

can then replace the invalid return address saved

on the stack with the address of the instruction

immediately following the _GotoSleep or

GotoSleep( ) function call. This ensures that

the device continues executing the correct code

sequence after waking up from Sleep mode.

Example 17 demonstrates the work around

described above.

EXAMPLE 17:

; ----------------------------------------------------------------------------------------------

.global __reset

.global _main

.global _GotoSleep

.global __AddressError

.global __INT1Interrupt

; ----------------------------------------------------------------------------------------------

.section *, code

_main:

BSET INTCON2, #INT1EP ; Set up INT pins to detect falling edge

BCLR IFS1, #INT1IF ; Clear interrupt pin interrupt flag bits

BSET IEC1, #INT1IE ; Enable ISR processing for INT pins

CALL _GotoSleep ; Call function to enter SLEEP mode

_continue:

BRA _continue

; ----------------------------------------------------------------------------------------------

; Address Error Trap

__AddressError:

BCLR INTCON1, #ADDRERR

; Set program memory return address to _continue

POP.D W0

MOV.B #tblpage (_continue), W1

MOV #tbloffset (_continue), W0

PUSH.D W0

RETFIE

; ----------------------------------------------------------------------------------------------

__INT1Interrupt:

BCLR IFS1, #INT1IF ; Ensure flag is reset

RETFIE ; Return from Interrupt Service Routine

; ----------------------------------------------------------------------------------------------

.section *, code, address (0x1FC0)

_GotoSleep:

; fill remainder of the last row with NOP instructions

.rept 31

NOP

.endr

; Place SLEEP instruction in the last word of program memory

PWRSAV #0

dsPIC30F6011/6012/6013/6014

Work around 2:

Instead of executing a PWRSAV #0 instruction to

put the device into Sleep mode, perform a clock

switch to the 512 kHz Low-Power RC (LPRC)

Oscillator with a 64:1 postscaler mode. This

enables the device to operate at 0.002 MIPS,

thereby significantly reducing the current

consumption of the device. Similarly, instead of

using an interrupt to wake-up the device from

Sleep mode, perform another clock switch back to

the original oscillator source to resume normal

operation. Depending on the device, refer to

Section 7. “Oscillator” (DS70054) or Section

29. “Oscillator” (DS70268) in the “dsPIC30F

Family Reference Manual” (DS70046) for more

details on performing a clock switch operation.

Work aro und 3:

Instead of executing a PWRSAV #0 instruction to

put the device into Sleep mode, perform a clock

switch to the 32 kHz Low-Power (LP) Oscillator

with a 64:1 postscaler mode. This enables the

device to operate at 0.000125 MIPS, thereby

significantly reducing the current consumption of

the device. Similarly, instead of using an interrupt

to wake-up the device from Sleep mode, perform

another clock switch back to the orig inal oscillator

source to resume normal operation. Depending on

the device, refer to Section 7. “Oscillator”

(DS70054) or Section 29. “Oscillator”

(DS70268) in the “dsPIC30F Family Reference

Manual” (DS70046) for more details on performing

a clock switch operation.

Affected Silicon Revisions

Note: The above work around is recommended

for users for whom application hardware

changes are not possible.

Note: The above work around is recommended

for users for whom application hardware

changes are possible, and also for users

whose application hardware already

includes a 32 kHz LP Oscillator crystal.

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

25. Module: I2C

When the I2C module is configured as a slave,

either in single-master or multi-master mode, the

I2C receiver buffer is filled whether a valid slave

address is detected or not. Therefore, an I2C

receiver overflow condition occurs and this

condition is indicated by the I2COV flag in the

I2CSTAT register.

This overflow condition inhibits the ability to set the

I2C receive interrupt flag (SI2CF) when the last

valid data byte is received. Therefore, the I2C

slave Interrupt Service Routine is not called and

the I2C receiver buffer is not read prior receiving

the next data byte.

Work arounds

To avoid this issue, either of the following two work

arounds can be implemented, depending on the

application requirements.

Work around 1:

For applications in which the I2C receiver interrupt

is not required, the following procedure can be

used to receive valid data bytes:

1. Wait until the RBF flag is set.

2. Poll the I2C receiver interrupt SI2CIF flag.

3. If SI2CF is not set in the corresponding

Interrupt Flag Status register (IFSx), a valid

address or data byte has not been received for

the current slave. Execute a dummy read of

the I2C receiver buffer, I2CRCV; this will clear

the RBF flag. Go back to step 1 until SI2CF is

set and then continue to Step 4.

4. If the SI2CF is set in the corresponding

Interrupt Fla g Status register (IF S x), val id data

has been received. Check the D_A flag to

verify that an address or a data byte has been

received.

5. Read the I2CRCV buffer to recover valid data

bytes. This will also clear the RBF flag.

6. Clear the I2C receiver interrupt flag SI2CF.

7. Go back to step 1 to continue receiving

incoming data bytes.

Work arou nd 2:

Use this work around for applicati ons i n whic h the

I2C receiver interrupt is required. Assuming that

the RBF and the I2COV flags in the I2CSTAT

the I2C bus (i.e., between master and other

slaves); the following procedure can be used to

receive valid data bytes:

1. When a valid slave address byte is detected,

SI2CF bit is set and the I2C slave interrupt

service routine is called; however , the RBF and

I2COV bits are already set due to data

transfers between other I2C nodes.

2. Check the status of the D_A flag and the

I2COV flag in the I2CSTAT register when

executing the I2C slave service routine.

3. If the D_A flag is cleared and the I2COV flag

are set, an invalid data byte was received but a

valid address byte was received. The overflow

condition occurred because the I2C receive

buffer was overflowing with previous I2C data

transfers between other I2C nodes. This

condition only occurs after a valid slave

address was detected.

4. Clear the I2COV flag and perform a dummy

read of the I2C receiver buffer, I2CRCV, to

clear the RBF bit and recover the valid address

byte. This action will also avoid the loss of the

next data byte due to an overflow condition.

5. Verify that the recovered address byte

matches the current slave address byte. If they

match, the next data to be received is a valid

data byte.

6. If the D_A flag and the I2COV flag are both set,

a valid data byte wa s received and a previ ous

valid data byte was lost. It will be necessary to

code for handling this overflow condition.

Affected Silicon Revisions

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

26. Module: I/O

If the user application enables the auto-baud

feature in the UART module, the I/O pin

multiplexed with the IC1 (Input Capture) pin cannot

be used as a digital input. However, the external

interrupt fun cti o n (INT 1) ca n be use d.

Work around

None.

Affected Silicon Revisions

27. Module: I2C

If there are two I2C devices on the bus, one of

them is acting as the Master receiver and the other

as the Slave transmitter . If both devices are config-

ured for 10-bit addressing mode, and have the

same value in the A10 and A9 bits of their

addresses, then when th e Slav e sel ect add re ss is

sent from the Master, both the Master and Slave

acknowledge it. When the Master sends out the

read operation, both the Master and the Slave

enter into Read mode and both of them transmit

the data. The resultant data will be the ANDing of

the two transmissions.

Work around

In all I2C devices, the addresses as well as bits

A10 and A9 should be different.

Affected Silicon Revisions

28. Module: Timer

When the timer is being operated in Asynchronous

mode using the secondary oscillator (3 2.768 kHz)

and the device is put into Sleep mode, a clock

switch to any other oscillator mode before putting

the device to Sleep prevents the timer from waking

the device from Sleep.

Work around

Do not clock switch to any other oscillator mode if

the timer is being used in Asynchronous mode

using the secondary oscillator (32.768 kHz).

Affected Silicon Revisions

29. Module: PLL

The PLL LOCK Status bit (OSCCON<5>) can

occasionally get cleared and generate an

oscillator failure trap even when the PLL is still

locked and functioning correctly.

Work aro und

The user application must include an oscillator

failure trap service routine. In the trap service

routine, first inspect the status of the Clock Failure

Status bit (OSCCON<3>). If this bit is clear, return

from the trap service routine immediately and

continue program execution.

Affected Silicon Revisions

30. Module: PSV Operations

An address error trap occurs in certain addressing

modes when accessing the first four bytes of an

PSV page. This only occurs when using the

following addressing modes:

•MOV.D

• Registe r Indirect Addressing (word or byte

mode) with pre/post-decrement

Work aro und

Do not perform PSV accesses to any of the first

four bytes using the above addressing modes. For

applications using the C language, MPLAB C30

version 3.11 or higher, provides the following

command-line switch that implements a work

around for the erratum.

-merrata=psv_trap

Refer to the readme.txt file in the MPLAB C30

v3.11 tool suite for further details.

Affected Silicon Revisions

A3 B1 B2

XXX

A3 B1 B2

XXX

A3 B1 B2

XXX

A3 B1 B2

XXX

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

31. Module: I2C

In 10-bit Addressing mode, some address

matches don’t set the RBF flag or load the receive

matches the reserved addresses. In particular,

these include all addresses with the form

XX0000XXXX and XX1111XXXX, with the

following exceptions:

• 001111000X

• 011111001X

• 101111010X

• 111111011X

Work around

Ensure that the lower address byte in 10-bit

Addressing mode does not match any 7-bit

reserved addresses.

Affected Silicon Revisions

32. Module: I2C

When the I2C module is configured as a 10-bit

slave with and address of 0x102, the I2CxRCV

rather than 0x02; however, the module

acknowledges both address bytes.

Work around

None.

Affected Silicon Revisions

33. Module: I2C

When the I2C module is enabled by setting the

I2CEN bit in the I2CCON register, the dsPIC DSC

device generates a glitch on the SDA and SCL

pins. This glitch falsely indicates “Communica tion

St art” to all devices on the I2C bus, and can cause

a bus collision in a multi-master config uration.

Additionally, when the I2CEN bit is set, the S and

P bits of the I2C module are set to values ‘1’ and

‘0’, respectively, which indicate a “Communication

Start” condition.

Work arou nd s

To avoid this issue, either of the following two work

arounds can be implemented, depending on the

application requirements.

Work arou nd 1:

In a single-master environment, add a delay

between enabling the I2C module and the first data

transmission. The delay should be equal to or

greater than the time it takes to transmit two data

bits.

In the multi-master configuration, in addition to the

delay, all other I2C masters should be synchro-

nized and wait for the I 2C module to be initialized

before initiating any kind of communication.

Work arou nd 2:

In dsPIC DSC devices in which the I2C module is

multiplexed with other modules that have

precedence in the use of the pin, it is possible to

avoid this glitch by enabling the higher priority

module before enabling the I2C module.

Use the following procedure to implement this

work around:

1. Enable the higher priority peripheral module

that is multiplexed on the same pins as the I2C

module.

2. Set up and enable the I2C module.

Disable the higher priority peripheral module that

was enabled in step 1.

Affected Silicon Revisions

A3 B1 B2

XXX

A3 B1 B2

XXX

Note: Work around 2 works only for devices that

share the SDA and SCL pins with another

peripheral that has a higher precedence

over the port latch, such as the UART. The

priority is shown in the pin diagram located

in the data sheet. For example, if the SDA

and SCL pins are shared with the UART

and SPI pins, and the UART has higher

precedence on the port latch pin.

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

34. Module: CAN

CAN Receive filters 3, 4 and 5 may no t work for a

given combination of instruction cycle speed and

CAN bit time quanta.

Work around

Do not use CAN RX filters 3, 4 and 5. Instead, use

filters 0, 1 and 2.

Affected Silicon Revisions

35. Module: Interrupt Controller

A specific write sequence for Interrupt Priority

Control 2 (IPC2) SFR is required to prevent

possible data corruption in the Interrupt Enable

Control 2 (IEC2) SFR. Interrupts must be disabled

during this IPC2 SFR write sequence.

Work around

An example of this write sequence is shown in

Example 18.

EXAMPLE 18:

When coding in C, the write sequence shown

above can be implemented usi ng inline assembly

instructions. The equivalent write seq uence using

the C30 compiler is shown in Example 19.

EXAMPLE 19:

Affected Silicon Revisions

36. Module: Program Memory

For this revision of silicon, run-time self-

programming operations sh ould not be performed

on the User Program Memory and Configuration

Fuse bits. Configuration Fuse bits may be pro-

grammed within the MPLAB IDE using a device

programmer, for example, MPLAB ICD 2.

Note that the on-chip Data EEPROM can be

self-programmed at run-time.

Work aro und

None.

Affected Silicon Revisions

37. Module: ADC

Sampling multiple channels sequentially using any

conversion trigger source other than the auto- convert

feature requires SAMC bits to be non-zero. Thus, if

the following conditions are all satisfied, the module

may not operate as specif ied:

- Multiple S/H channels are sampled

sequentially

CHPS (ADCON2<9:8>) is not equal to ‘00’ and

SIMSAM (ADCON1<3>) = 0

- Auto-convert option is not chosen as the

conversion trigger

SSRC (ADCON1<7:5>) is not equal to ‘111’

- SAMC (ADCON3<12:8>) is equal to ‘00000’

Work aro und

Set the value of the SAMC bits to anything other

than ‘00000’. The module will now operate as

specified.

Affected Silicon Revisions

A3 B1 B2

XXX

mov #IPC2, w0 ;Point w0 to IPC2

mov #0x4444, w1 ;Write data to go to IPC2

disi #2 ;Disable interrupts for

;next two cycles

mov w1, IPC2 ;Write the data to IPC2

mov #IPC2, w0 ;Target w1 to keep IPC2

;address on bus

asm volatile( “mov.d w0, [w15++]\n\t”

“mov #IPC2,w0\n\t”

“mov #0x4444,w1\n\t”

“disi #2\n\t”

“mov w1, IPC2\n\t”

“mov #IPC2, w0\n\t”

“mov.d [--w15], w0”);

//Note: There are no commas between

// the quoted strings in the code

// segment above.

A3 B1 B2

dsPIC30F6011/6012/6013/6014

38. Module: QEI

For this rele ase of silicon, th e Quadrature Encode r

Interface (QEI) module sho uld not be operated in

the Reset on Index Pulse mode.

Work around

None.

Affected Silicon Revisions

39. Module: PWM

The input clock to the PWM time base has

prescaler options of 1:1, 1:4, 1:16 or 1:64, selected

by the PTCKPS (PTCON<3:2>) control bits. In this

release of silicon, the options 1:4, 1:16 and 1:64

may produce unexpected results when used to

generate center-aligned PWM pulses.

Work around

The prescaler should be set to the 1:1 option (i.e.,

prescaler should be disabled) in this release of

silicon when generating center-aligned PWM

pulses.

Affected Silicon Revisions

40. Module: PWM

The output override function of the PWM module,

controlled by the OVDCON register and the

OSYNC bit (PWMCON2<1>), produces unex-

pected results on the output pins in certain cases

when the module is used in Complementary mode.

These cases are shown in Table 5. Future

releases of silicon will operate as shown in the

“Expected Output” columns in Table 5.

Work arou nd

None.

Affected Silicon Revisions

TABLE 5: OUTPUT OVERRIDE: EXPECTED VS. OBSERVED OPERATION(1,2,3)

A3 B1 B2

OVDCON Dead Time

Enabled

Expected Output Observed Output Comments

PWM1H PWM1L PWM1H PWM1L

0x0100 Yes Low PWM Low Low Output on PWM1L pin is shortened by dead time

0x0200 Yes PWM Low Low Low Output on PWM1H pin is shortened by dead time

Note 1: Other Motor Control PWM SFRs were initialized as follows: PTCON = 0x8 002 and PWMCON1 = 0x0011.

2: For these settings of OVDCON, th e OSYNC bit (PWMCON<1>) should be cleared to ‘0’ for correct

operation.

3: Results are shown here for the PWM1H and PWM1L pins onl y. Similar results will be observed for any

other pair of complementary output pins (PWM2H/L, PWM3H/L and PWM4H/L) and any other chosen duty

cycle.

dsPIC30F6011/6012/6013/6014

41. Module: CPU

The device exhibits IPD of approximately 100 μA.

Work around

If the application does not use the on-chip A/D

converter, it is possible to reduce the IPD to values

below 0.1 μA. The following additional measures

need to be taken in these circumstances:

1. In the application hardware, the VREF+/RA10 pin

(pin 24) on the dsPIC30F601X device should be

connected to the circuit ground (GND).

2. In the application software, the code sequence

shown in Example 20 should be executed to

bring the device into the power-saving Sleep

mode.

EXAMPLE 20:

Affected Silicon Revisions

42. Module: ADC

If the ADC module is in an enabled state when the

device enters Sleep mode as a result of executing

a PWRSAV #0 instruction , the de vice po wer-down

current (IPD) may exceed the specifications listed

in the device da ta sheet. This may ha ppen even if

the ADC module is disabled by clearing the ADON

bit prior to entering Sleep mode.

Work around

In order to remain within the IPD specifications

listed in the device data sheet, the user software

must completely disable the ADC module by

setting the ADC Module Disable bit in the

corresponding Peripheral Modul e Disable register

(PMDx), prior to executing a PWRSAV #0

instruction.

Affected Silicon Revisions

.include “p30f6014.inc”

.......

BCLR ADCON1, #ADON ;Required code

MOV #0x2000, W0 ;sequence for

MOV W0, ADCON2 ;low power-down

BCLR PMD1, #ADCMD ;current.

PWRSAV #SLEEP_MODE ;Device enters

;SLEEP mode here

A3 B1 B2

XXX

dsPIC30F6011/6012/6013/6014

Data Sheet Clarifications

The following typographic corrections and clarifications

are to be noted for the latest version of the device data

sheet (DS70117F):

1. Module: DC Characteristics : I/O Pin Input

Specifications

The maximum value for parameter DI19 (VIL specifica-

tions for SDAx and SCLx pins) and the minimum value

for parameter DI29 (VIH specifications for SDAx and

SCLx pins) were stated incorrectl y in Table 23-8 of the

current device data sheet. The correct values are

shown in bold type in Table 6.

TABLE 6: DC CHA RACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

DC CHARACTERISTICS

Standard Operating Conditions: 3.3V and 5.0V (±10%)

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

VIL Input Low Voltage

DI19 SDA, SCL VSS —0.8 V SMbus enabled

VIH Input High Voltage

DI29 SDA, SCL 2.1 —VDD V S Mbus enabled

dsPIC30F6011/6012/6013/6014

APPENDIX A: REVISION HISTORY

Rev A Document (4/2009)

Initial release of this document; issued for revision A3,

B1 and B2 silicon.

Includes silicon issues 1 (Dat a EEPROM), 2-4 (CPU ), 5

(PSV Operations), 6 (CPU), 7 (Flash Memory), 8 (Data

Memory), 9 (Interrupt Controller), 10-11 (CPU), 12

(Timers), 13 (Output Compare), 14 (ADC), 15-16 (DCI),

17 (CAN), 18 (Flash Memory), 19 (CPU), 20 (Flash

Memory), 21 (PLL), 22 (Interrupt Controller), 23 (PLL),

24 (Sleep Mode), 25 (I2C), 26 (I/O), 27 (I2C), 28 (T imer),

29 (PLL), 30 (PSV Operations), 31-33 (I2C), 34 (CAN),

35 (Interrupt Controller), 36 (Program Memory), 37

(ADC), 38 (QEI), 39-40 (PWM) and 41 (CPU).

This document replaces the following errata documents:

• DS80176, “dsPIC30F6011/6012/6013/6014 Rev.

A3 Silicon Errata”

• DS80183, “dsPIC30F6011/6012/6013/6014 Rev.

B1 Silicon Errata”

• DS80198, “dsPIC30F6011/6012/6013/6014 Rev.

B2 Silicon Errata”

Rev B Document (7/2009)

Updated silicon issue 22 (Interrupt Controll er).

Added Affected Revisions table to issue 41 (CPU).

Rev C Document (2/2010)

Updated silicon issue 22 (Interrupt Controll er).

Rev D Document (6/2010)

Added silicon issue 42 (ADC) and data sheet

clarification 1 (DC Characteristics: I/O Pin Input

Specifications).

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-261-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the perso n doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the desig n

and manufacture of development systems is ISO 9001:2000 cert ified.

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