SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DSerial Control With Diagnostics
DSix Power DMOS Transistor Outputs of
350-mA Continuous Current
DInternal 60-V Inductive Load Clamp
DIndependent ON-State
Shorted-Load/Short-to-Battery Fault
Detection on All Drain Terminals
DIndependent OFF-State Open-Load Fault
Sense on All Drain Terminals
DTransition of Drain Outputs to Low Duty
Cycle Pulsed-Width-Modulation (PWM)
Mode for Over-Current Condition
DOver-Battery-Voltage-Lockout Protection
DOver-Temperature Sense W ith Serial
Interface Fault Status
DFault Diagnostics Returned Through Serial
Output Terminal
DInternal Power-On Reset of Registers
DCMOS Compatible Inputs With Hysteresis
description
The TPIC2603 is a monolithic low-side driver which
provides serial interface and diagnostics to control
six on-board power DMOS switches. Each channel
has independent OFF-state open-load sense,
ON-state shorted-load/short-to-battery protection,
over-battery-voltage-lockout protection, and
over-temperature sense with fault status reported
through the serial interface. The device also
provides inductive voltage transient protection for
each drain output. The TPIC2603 drives inductive
and resistive loads such as relays, valves, and
lamps.
Serial data input (SDI) is transferred through the serial register when CS is low on low-to-high transitions of the
serial clock (SCLK). Each string of data must consist of 8 or 16 bits of data. A logic high input data bit turns the
respective output channel ON and a logic low data bit turns it OFF. CS must be transited high after all of the serial
data has been clocked into the device. A low-to-high transition of CS transfers the last six bits of serial data to
the output buffer , places the serial data out (SDO) terminal in a high-impedance state, and re-enables the fault
register. Fault data for the device is sent out the SDO terminal. The first bit of the shift register is exclusively
ORed with the fault registers. When a fault exists, the SDI data is inverted as it is transferred out of SDO. Fault
data consists of fault flags for over-temperature (bit 6) and shorted/open-load (bits 0-5) for each of the six output
channels. Fault register bits are set or cleared asynchronously, when CS is high to reflect the current state of
the hardware. The fault must be present when CS is transited from high to low to be captured and reported in
the serial fault data. New faults cannot be captured in the serial register when CS is low.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DRAIN5
DRAIN4
SCLK
SDI
GND
GND
SDO
CS
DRAIN3
DRAIN2
Vbat
DRAIN0
NC
NC
GND
GND
NC
NC
DRAIN1
VCC
NE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DRAIN5
DRAIN4
SCLK
SDI
GND
GND
GND
GND
SDO
CS
DRAIN3
DRAIN2
Vbat
DRAIN0
NC
NC
GND
GND
GND
GND
NC
NC
DRAIN1
VCC
DW PACKAGE
(TOP VIEW)
NC − No internal connection
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
description (continued)
When an over-current or shorted-load fault occurs, the channel transits into a low duty cycle
pulse-width-modulated (PWM) signal as long as the fault is present. More detail on fault detection operation is
presented in the device operation section of this data sheet.
The TPIC2603 provides pulldown resistors on all active-high inputs except SCLK. A pullup resistor is
used on CS.
The TPIC2603 is characterized for operation over the operating case temperature of −40°C to 125°C.
functional block diagram
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
Fault Register
SDO
Serial Input Control
6-Bit Shift Register
Output Drivers
Fault Sense and Protection
(STB, Current-Limit, Open-Load,
Over-Temperature, Over-Voltage)
SCLK
CS
SDI
Vbat
VCC
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.†
I/O
DESCRIPTION
CS 8 (10) IChip select. The CS is an active-low input used to select the serial interface of the device. The device accepts
serial input data and transmits fault data when CS is held low. An internal pullup resistor is provided on the CS
input.
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
19 (23)
12 (14)
10 (12)
9 (11)
2 (2)
1 (1)
OFET drain outputs. The DRAIN terminals are low-side switches for inductive and resistive loads. Each output
provides an internal drain-gate clamp to snub inductive transients.
GND 5, 6, 15,
16 (5, 6, 7,
8, 17, 18,
19, 20)
OGround. These terminals provide ground return paths for the device.
SCLK 3 (3) ISerial clock. The SCLK clocks the shift register. Serial data is transferred into the SDI port and serial fault data
is transferred out of the SDO port of the device on the rising edges of SCLK.
SDI 4 (4) ISerial data input. The device receives serial data from the control device using the SDI. Serial input data can
be configured in 8-bit or 16-bit data words. Refer to Figures 2 and 4 for input protocol. An internal pulldown
resistor is provided on the SDI input.
SDO 7 (9) OSerial data output. This 3-state output transfers fault data to the control device after the device has been
selected by the CS terminal.
Vbat 20 (24) IBattery voltage. The Vbat terminal monitors the battery voltage to detect over-voltage conditions.
VCC 11 (13) ISupply voltage. The VCC terminal receives a 5-V supply for internal logic.
†Terminal numbers listed in parenthesis are for the 24-pin DW package.
absolute maximum ratings over the recommended operating case temperature range (unless
otherwise noted)‡
Logic supply voltage range, VCC (see Note 1) −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery supply voltage range, Vbat −1.5 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 68 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, ID, TC = 25°C 350 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, single output, IDM, TC = 25°C (see Note 3) 2.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pusle avalanche energy, EAS (see Figure 11) 100 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, IAS (see Note 4) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤100 µs and duty cycle ≤2%.
4. DRAIN supply voltage = 13 V, starting junction temperature (TJS) = 25°C, L = 150 mH, IAS = 1 A (see Figure 11).
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DISSIPATION RATING TABLE
PACKAGE TC ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TC = 25°CTC = 125°C
POWER RATING
DW 1750 mW 14 mW/°C350 mW
NE 2500 mW 20 mW/°C500 mW
recommended operating conditions
MIN NOM MAX UNIT
Logic supply voltage, VCC 4.5 5 5.5 V
Battery supply voltage, Vbat 5.5 12 25 V
High-level input voltage, VIH 0.7 VCC VCC V
Low-level input voltage, VIL 00.3 VCC V
Operating case temperature, TC−40 125 °C
electrical characteristics, TC = −40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vbat Battery supply voltage Normal operation 5.5 25 V
Ibat
Battery supply current
VCC = 5 V 5 mA
Ibat Battery supply current VCC = 0 50 µA
VCC Logic supply voltage 4.5 5.5 V
ICC Logic supply current All outputs off, Vbat = 5.5 V 5 mA
V(turn-on) VCC turn-on voltage
(logic operational) Vbat = 5.5 V, Check output functionality 4.5 V
V(ov) Over-battery voltage
shutdown Gate disabled 30 38 V
Vhys(ov) Over-battery voltage reset
hysteresis 0.4 2 V
Vbat = 13 V
IO = 0.35 A, TC = 25°C
0.7 1
rDS(on)
Drain-to-source on-state
resistance
Vbat = 5.5 V IO = 0.35 A, TC = 25°C1.7 2.3
Ω
rDS(on)
Drain-to-source on-state
resistance Vbat = 13 V
IO = 0.35 A, TC = 125°C
1.2 1.7 Ω
Vbat = 5.5 V IO = 0.35 A, TC = 125°C2.7 3.8
ILOn-state current limit 0.8 2 5 A
IL(sense) Over-current sense 0.8 1.5 3 A
IIH Input pullup current GND < VI < 0.7 VCC, CS input only −5 −10 −50 µA
IIL Input pulldown current 0.3 VCC < VI < VCC,All other inputs 2.5 10 25 µA
ID(off) Off-state drain current Vload = Vbat = 14.5 V 20 40 80 µA
IO(sleep) Sleep-state output current Vbat < 0.5 V, VCC < 0.5 V, Load = 14 V 50 µA
VOH High-level serial output
voltage IO = 1 mA 0.8 VCC V
VOL Low-level serial output
voltage IO = 1 mA 0.2 0.4 V
IOZ High impedance state
output current VCC = 5.5 V to 0 V, SDO output −10 1 10 µA
V(BR)DSX Drain-to-source breakdown
voltage dc < 1%, tw = 100 µs, IO = 20 mA 52 58 68 V
Tj(sense) Thermal flag 150 170 185 °C
Tj(hys) Thermal flag hysteresis 5 10 15 °C
V(open) Open-load detection voltage 0.3 VCC 0.7 VCC V
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
twClock cycle period pulse duration, SCLK See Figure 1 250 555 ns
twH(SCLK) Pulse duration, SCLK high See Figure 1 100 248 ns
twL(SCLK) Pulse duration, SCLK low See Figure 1 100 248 ns
tpd1 Propagation delay from falling edge of CS to SDO valid CS = 0.8 V to SDO low
impedance (see Figure 1) 150 300 ns
tpd2 Propagation delay from rising edge of CS to SDO 3-state CS = 2 V to SDO 3-state 150 200 ns
tpd3 Propagation delay from SCLK to SDO valid CS < 0.8 V 80 172 ns
tr(SDO) Rise time of SDO Cload = 200 pF 30 50 ns
tf(SDO) Fall time of SDO Cload = 200 pF 30 50 ns
t(stb) Short-to-battery/shorted-load/open-load deglitch time See Figures 5 and 6 25 70 100 µs
td(on) Turn-on delay time, rising edge of CS to drain 0.4 5 10
td(off) Turn-off delay time, rising edge of CS to drain
Vbat = 14 V,
R = 30
0.4 5 15
s
tr(drain) Rise time of drain terminal
Vbat = 14 V,
Rload = 30 Ω0.4 5 10 µs
tf(drain) Fall time of drain terminal
load
0.4 5 10
f(SCLK) Serial clock frequency 1.8 4 MHz
tcyc(ref) Short-to-battery sense cycle time See Figure 5 1.6 4 6.4 ms
tw(sense) Short-to-battery sense pulse duration See Figure 5 25 70 100 µs
tsu1 Setup to/from the fall edge of CS to the rising edge of SCLK See Figure 1 150 200 ns
tsu(SDI) Setup time, SDI to SCLK See Figure 1 25 55 ns
th(SDI) Hold time, SDI after SCLK See Figure 1 10 55 ns
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
RθJA Junction-to-ambient thermal resistance All outputs with equal power 50 °C
RθJC Junction-to-case thermal resistance All outputs with equal power 10 °C
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
SCLK
tsu1
123X
twL(SCLK)
twH(SCLK)
tw
tsu(SDI)
th(SDI)
tpd1 tpd3 tpd2
MSB LSB
3-STATE MSB LSB 3-STATE
CS
SDI
SDO
Figure 1. Switching Characteristics
serial interface
Control information is transferred into the TPIC2603 through the serial interface. The serial interface consists
of a serial clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Serial data is
shifted, most significant bit (MSB) first, into the SDI shift register on the rising edge of the first SCLK after CS
has transited from high to low. The controller must shift either eight bits or sixteen bits of data into the device
with the last six bits of input data containing control information for the output drivers. Data bits preceeding the
output control information should be set to 0. A low-to-high transition on CS latches the contents of the last six
bits of the serial shift register into the output buffer. A low input to SDI turns the corresponding parallel output
OFF and a high input will turn the output ON (see Figure 2).
12345678
DRAIN5 OFF
DRAIN4 ON
DRAIN3 ON
DRAIN2 OFF
DRAIN1 OFF
DRAIN0 ON
0
SCLK
CS
SDI
NEW DATA
Figure 2. Serial Input Control
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
serial interface (continued)
Fault isolation data for each channel and global over-temperature status is transferred to the control device
using the serial interface. Fault status for the TPIC2603 is captured as CS transits low. The fault interface
monitors the SDI terminal and exclusively ORs the respective input control bit with the corresponding fault
information bit stored in the fault register. Each exclusive ORed fault bit is transferred out the SDO terminal on
the rising edge of the SCLK. Serial data can be transferred in 8-bit or 16-bit words as illustrated in Figure 4, with
fault data appearing in the first 8-bits of serial output data. The CS must be transited high after the serial transfer
has completely latched the new control data into the output control buffer and re-enable fault reporting on the
device (see Figures 3 and 4).
NA = Unused
OT = Over-temperature fault bit
FLT5 = Shorted or open-load fault on channel 5
FLT4 = Shorted or open-load fault on channel 4
FLT3 = Shorted or open-load fault on channel 3
FLT2 = Shorted or open-load fault on channel 2
FLT1 = Shorted or open-load fault on channel 1
FLT0 = Shorted or open-load fault on channel 0
12345678
SCLK
CS
SDO 3-STATEFLT0FLT1FLT2FLT3FLT4FLT5OTN/A3-STATE
Bit1Bit2Bit3Bit4Bit5Bit6Bit7 Bit0
NOTE A: MSB is the first bit transferred.
Figure 3. Serial Output Control
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
serial interface (continued)
Serial I/O Protocol (8-Bit Configuration)
Serial I/O Protocol (16-Bit Configuration)
Over
Temp
N/A 5 4 3 2 1 0
76543210
Unused
Global over-temperature flag Output control data for Drain (0:5). Fault
data for Drain (0:5) is exclusive ORed and
transmitted in the respective bit locations.
Over
Temp
N/A 5 4 3 2 1 0
15 14 13 12 11 10 98
N/A 5 4 3 2 1 0
76543210
N/A
Output control data for Drain (0:5)
MSB LSB
MSB LSB
NOTE A: MSB is the first bit transferred.
Output control data for Drain (0:5). Fault
data for Drain (0:5) is exclusive ORed and
transmitted in the respective bit locations.
Unused
Global over-temperature flag
Figure 4. Serial Data Fault Protocol
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
fault sense/protection circuitry
over-current/short-to-battery sensing and protection
The internal fault protection circuitry of the TPIC2603 monitors the drain current for each channel. Each channel
offers two levels of protection from over-current conditions. The first level is a current-limit protection which
through the internal FET prevents the switching current from exceeding the on-state current limit. The second
level of protection transits the output to a low duty cycle PWM mode when the current exceeds the over-current
sense threshold. The PWM mode protection is enabled approximately 70 µs after the output has been turned
on. The output remains in the PWM mode until the shorted-load condition has been corrected and then
automatically returns to normal operation. Figure 5 illustrates device operation under an over-current or
shorted-load condition.
t(stb)
t(stb)
Glitches
Glitches
tw(sense)
tcyc(ref)
DRAIN
Control
Register
DRAIN
Fault
Register
NORMAL
SHORTED-LOAD
Control
Register
DRAIN
Fault
Register
Figure 5. Shorted-Load Condition
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
open-load/short-to-ground sensing
The TPIC2603 checks for open-load and short-to-ground conditions when the output is turned OFF. When the
output turns OFF, a 4 0-µA current source switches onto the drain. Under normal conditions, the load provides
adequate current to overcome the current source and the drain voltage remains above the open-load detection
threshold. When the output is open, then the current source pulls the drain low and an open-load condition is
flagged. The open-load test is enabled approximately 70 µs after the output turns OFF to allow the drain to
stabilize. Figure 6 illustrates device operation under open-load conditions.
t(stb)
Glitches
Control
Register
DRAIN
Fault
Register
NORMAL
t(stb)
OPEN-LOAD
Control
Register
DRAIN
Fault
Register
Figure 6. Open-Load Condition
over-voltage sensing and protection
The TPIC2603 monitors the Vbat input terminal to protect the device and load from over-battery voltage
conditions. The device disables all of the drain outputs when Vbat goes above 35 V. An over-battery voltage
hysteresis is provided to prevent the outputs from transiting ON and OFF erratically near the over-voltage
threshold. The device automatically returns to normal operation after the over-voltage condition has been
corrected. Figure 7 illustrates device operation under an over-battery voltage condition.
34 V
35 V
Vbat (Typ)
All Drains
Fault Bit
Figure 7. Over-Battery Voltage Condition
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
over-temperature sensing
The TPIC2603 monitors the junction temperature of the die to detect over-temperature conditions which may
damage the device. When the junction temperature goes above approximately 170°C, the fault logic sets the
global over-temperature fault bit. An over-temperature fault is reported using the serial interface on bit 6 (for 8-bit
configuration) or bit 14 (for 16-bit configuration). The global over-temperature fault output in the serial data is
exclusively ORed with the second bit (bit 6 for 8-bit configuration or bit 14 for 16-bit configuration) of data input
to the SDI terminal. Bit 6 or bit 14 of the input data should be set low. Over-temperature faults are for
informational purposes only and do not af fect the state of the drains. Figure 8 illustrates device operation under
over-temperature conditions.
160°C
170°C
Junction Temperature
Drains (Not Disabled)
Fault Bit
Figure 8. Over-Temperature Sense
PARAMETER MEASUREMENT INFORMATION
OUTPUT CURRENT
vs
TIME FOR INCREASING LOAD RESISTANCE
O
I − Output Current − A
I − Output Current − A
Region 1 Region 2
t1t2
First output current pulses after turn-on in chopping mode with
resistive load.
0
3
O
0
t1 ≈ 55 µs
t2 ≈ 3.5 ms
t -Time
t - Time
REGION 1 CURRENT WAVEFORM
IL
t2
t1t1
2
1
Region 3
TC = 25°C
NOTES: A. Region 1 − Analog current limit holds the maximum current while the device runs in chop mode.
B. Region 2 − Analog current limit is removed but device continues in chop mode.
C. Region 3 − Current is below chop mode sense; therefore, it is in normal operation. Variable load is resistance over time.
Figure 9. Chopping-Mode Characteristics
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
IL
2
1
0
− 50 0 50
OVER-CURRENT SENSE, IL(sense)
vs
CASE TEMPERATURE
100
TC − Case Temperature − °C
3
150
IL(sense)
IL(sense)− Over Current Sense − A
Figure 10
13 V
1 Ω
150 mH
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
twtav†
IAS = 1 A
V(BR)DSX = 52 V MIN
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
VCC
DRAIN
SDI
SCLK
CS
Word
Generator
(see Note A)
DUT
GND
5 V
VDS
ID
5 V
0 V
Vbat
3
4
8
11 20
5, 6, 15, 16
Pinout for NE Package Shown
†Non-JEDEC symbol for avalanche time.
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test level is defined as EAS = (IAS × V(BR)DSX × tav)/2 = 100 mJ.
Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
− Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
1
0.4
0.2
012345
1.4
1.6
6
1.2
0.8
VCC = 5 V
Vbat = 13 V
TC = 25°C
TC = 100°C
TC = 125°C
N − Number of Outputs Conducting Simultaneously
of Each Output − A
D
I
0.6
− Maximum Peak Drain Current of Each Output − A
DM
N − Number of Outputs Conducting Simultaneously
I
0.7
0.6 12 34 56
0.8
0.9
1.1
1
1.2
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
d = 85%
VCC = 5 V
Vbat = 13 V
TC = 25°C
d = 90%
d = 80%
Figure 12 Figure 13
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
NOTE A: Technique should limit T
J
− T
C
to 10°C maximum.
ID − Drain Current − A
Ω
DS(on)
− Static Drain-Source On-State Resistance −r
0.75
0.25
001
1.25
2
0.5
1
TC = 25°C
TC = 125°C
TC = − 40°C
3
VCC = 5 V
Vbat = 13 V
See Note A
IL
VCC − Logic Supply Voltage − V
0
0.25
0.5
0.75
1
1.25
1.5
05
TC = 125°C
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
DS(on) − Static Drain-Source On-State Resistance −r
TC = 25°C
TC = −40°C
VCC = 5 V
ID = 350 mA
See Note A
10 15 20 25 30
NOTE A: Technique should limit TJ − TC to 10°C maximum.
IL(sense)
Figure 14 Figure 15
SLIS056A − FEBRUAR Y 1995 − REVISED MARCH 1996
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
THERMAL INFORMATION
NE PACKAGE
TRANSIENT THERMAL IMPEDANCE
vs
ON TIME
The single-pulse curve represents measured data. The
curves for various pulse durations are based on the
following equation:
t − On Time − s
C
°
θ
Z − Transient Thermal Impedance − /W
JA
0.1
0.001 0.01 0.1 1 10 100
1
10
100
1000
Single Pulse
d = 2%
d = 5%
d = 10%
d = 20%
d = 50%
tw
tc
ID
0
ZqJA +Ťtw
tcŤRqJA )Ť1–tw
tcŤZqǒtw)tcǓ
)ZqǒtwǓ–ZqǒtcǓ
= the single-pulse thermal impedance
for t = tw seconds
= the single-pulse thermal impedance
for t = tc seconds
= the single-pulse thermal impedance
for t = tw + tc seconds
Where:
d = tw/tc
ZqǒtwǓ
ZqǒtcǓ
Zqǒtw)tcǓ
Figure 16
PACKAGE OPTION ADDENDUM
www.ti.com 30-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPIC2603DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC2603DWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC2603DWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC2603DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC2603NE LIFEBUY PDIP NE 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPIC2603DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC2603DWR SOIC DW 24 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
