PIC18F2331/2431/4331/4431 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 2010 Microchip Technology Inc. DS39616D Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. 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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-490-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39616D-page 2 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 14-Bit Power Control PWM Module: Power-Managed Modes: * * * * * * * * * * * * * * Up to 4 Channels with Complementary Outputs Edge or Center-Aligned Operation Flexible Dead-Band Generator Hardware Fault Protection Inputs Simultaneous Update of Duty Cycle and Period: - Flexible Special Event Trigger output Motion Feedback Module: * Three Independent Input Capture Channels: - Flexible operating modes for period and pulse-width measurement - Special Hall sensor interface module - Special Event Trigger output to other modules * Quadrature Encoder Interface: - 2-phase inputs and one index input from encoder - High and low position tracking with direction status and change of direction interrupt - Velocity measurement Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Ultra Low, 50 nA Input Leakage Idle mode Currents Down to 5.8 A, Typical Sleep Current Down to 0.1 A, Typical Timer1 Oscillator, 1.8 A, Typical, 32 kHz, 2V Watchdog Timer (WDT), 2.1 A, typical Oscillator Two-Speed Start-up - Fast wake from Sleep and Idle, 1 s, typical Peripheral Highlights: * * * * High-Current Sink/Source 25 mA/25 mA Three External Interrupts Two Capture/Compare/PWM (CCP) modules Enhanced USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect Special Microcontroller Features: * * * * * * * * 100,000 Erase/Write Cycle Enhanced Flash Program Memory, Typical * 1,000,000 Erase/Write Cycle Data EEPROM Memory, Typical * Flash/Data EEPROM Retention: 100 Years * Self-Programmable under Software Control * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s * Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) via Two Pins: - Drives PWM outputs safely when debugging Up to 9 Channels Simultaneous, Two-Channel Sampling Sequential Sampling: 1, 2 or 4 Selected Channels Auto-Conversion Capability 4-Word FIFO with Selectable Interrupt Frequency Selectable External Conversion Triggers Programmable Acquisition Time Flexible Oscillator Structure: * Four Crystal modes up to 40 MHz * Two External Clock modes up to 40 MHz * Internal Oscillator Block: - 8 user-selectable frequencies: 31 kHz to 8 MHz - OSCTUNE can compensate for frequency drift * Secondary Oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor: - Allows for safe shutdown of device if clock fails Program Memory Device Data Memory Flash # Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) SSP I/O 10-Bit CCP A/D (ch) SPI Slave EUSART I2CTM Quadrature Encoder High-Speed, 200 ksps 10-Bit A/D Converter: 14-Bit Timers PWM 8/16-Bit (ch) PIC18F2331 8192 4096 768 256 24 5 2 Y Y Y Y 6 1/3 PIC18F2431 16384 8192 768 256 24 5 2 Y Y Y Y 6 1/3 PIC18F4331 8192 4096 768 256 36 9 2 Y Y Y Y 8 1/3 PIC18F4431 16384 8192 768 256 36 9 2 Y Y Y Y 8 1/3 2010 Microchip Technology Inc. DS39616D-page 3 PIC18F2331/2431/4331/4431 Pin Diagrams 28-Pin SPDIP, SOIC 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PWM4/PGM RA2/AN2/VREF-/CAP1/INDX 25 24 RB4/KBI0/PWM5 RA3/AN3/VREF+/CAP2/QEA 4 5 RA4/AN4/CAP3/QEB 6 23 RB2/PWM2 AVDD 7 8 22 21 RB1/PWM1 AVSS PIC18F2331/2431 MCLR/VPP RB3/PWM3 RB0/PWM0 VDD 20 19 VSS OSC2/CLKO/RA6 9 10 RC0/T1OSO/T1CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2/FLTA 12 13 14 17 16 15 RC6/TX/CK/SS OSC1/CLKI/RA7 RC2/CCP1 RC3/T0CKI/T5CKI/INT0 RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA 28 27 26 25 24 23 22 RA1/AN1 RA0/AN0 MCLR/VPP RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 28-Pin QFN(1) PIC18F2331 PIC18F2431 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 VDD VSS RC7/RX/DT/SDO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1 RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB AVDD AVSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS39616D-page 4 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN RE0/AN6 RE1/AN7 RE2/AN8 AVDD AVSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI(1)/T5CKI(1)/INT0 RD0/T0CKI/T5CKI RD1/SDO Note 1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F4331/4431 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 VDD VSS RD7/PWM7 RD6/PWM6 RD5/PWM4(3) RD4/FLTA(2) RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 5 PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA NC 44-Pin TQFP PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 AVSS AVDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB NC NC RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RC7/RX/DT/SDO RD4/FLTA(2) RD5/PWM4(3) RD6/PWM6 RD7/PWM7 VSS VDD RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. DS39616D-page 6 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA RC0/T1OSO/T1CKI 44-Pin QFN(2) PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS AVSS AVDD VDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB RB3/PWM3 NC RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM(2) RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RC7/RX/DT/SDO RD4/FLTA(3) RD5/PWM4(4) RD6/PWM6 RD7/PWM7 VSS VDD AVDD RB0/PWM0 RB1/PWM1 RB2/PWM2 Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: For the QFN package, it is recommended that the bottom pad be connected to VSS. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 7 PIC18F2331/2431/4331/4431 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 25 3.0 Oscillator Configurations ............................................................................................................................................................ 29 4.0 Power-Managed Modes ............................................................................................................................................................. 39 5.0 Reset .......................................................................................................................................................................................... 47 6.0 Memory Organization ................................................................................................................................................................. 61 7.0 Data EEPROM Memory ............................................................................................................................................................. 79 8.0 Flash Program Memory .............................................................................................................................................................. 85 9.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 95 10.0 Interrupts .................................................................................................................................................................................... 97 11.0 I/O Ports ................................................................................................................................................................................... 113 12.0 Timer0 Module ......................................................................................................................................................................... 127 13.0 Timer1 Module ......................................................................................................................................................................... 131 14.0 Timer2 Module ......................................................................................................................................................................... 136 15.0 Timer5 Module ......................................................................................................................................................................... 139 16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 145 17.0 Motion Feedback Module ......................................................................................................................................................... 151 18.0 Power Control PWM Module .................................................................................................................................................... 173 19.0 Synchronous Serial Port (SSP) Module ................................................................................................................................... 205 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 217 21.0 10-Bit High-Speed Analog-to-Digital Converter (A/D) Module ................................................................................................. 239 22.0 Low-Voltage Detect (LVD)........................................................................................................................................................ 257 23.0 Special Features of the CPU .................................................................................................................................................... 263 24.0 Instruction Set Summary .......................................................................................................................................................... 283 25.0 Development Support............................................................................................................................................................... 325 26.0 Electrical Characteristics .......................................................................................................................................................... 329 27.0 Packaging Information.............................................................................................................................................................. 363 Appendix A: Revision History............................................................................................................................................................. 375 Appendix B: Device Differences......................................................................................................................................................... 375 Appendix C: Conversion Considerations ........................................................................................................................................... 376 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 376 Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 377 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 377 INDEX ................................................................................................................................................................................................ 379 The Microchip Web Site ..................................................................................................................................................................... 389 Customer Change Notification Service .............................................................................................................................................. 389 Customer Support .............................................................................................................................................................................. 389 Reader Response .............................................................................................................................................................................. 390 Product Identification System............................................................................................................................................................. 391 DS39616D-page 8 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. DS39616D-page 9 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 10 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: * * * * PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 * * * * PIC18LF2331 PIC18LF2431 PIC18LF4331 PIC18LF4431 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price, with the addition of high-endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter. On top of these features, the PIC18F2331/2431/4331/4431 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power control and motor control applications. These special peripherals include: * 14-Bit Resolution Power Control PWM module (PCPWM) with Programmable Dead-Time Insertion * Motion Feedback Module (MFM), including a 3-Channel Input Capture (IC) module and Quadrature Encoder Interface (QEI) * High-Speed 10-Bit A/D Converter (HSADC) The PCPWM can generate up to eight complementary PWM outputs with dead-band time insertion. Overdrive current is detected by off-chip analog comparators or the digital Fault inputs (FLTA, FLTB). The MFM Quadrature Encoder Interface provides precise rotor position feedback and/or velocity measurement. The MFM 3x input capture or external interrupts can be used to detect the rotor state for electrically commutated motor applications using Hall sensor feedback, such as BLDC motor drives. PIC18F2331/2431/4331/4431 devices also feature Flash program memory and an internal RC oscillator with built-in LP modes. 1.1 1.1.1 New Core Features nanoWatt Technology All of the devices in the PIC18F2331/2431/4331/4431 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. 2010 Microchip Technology Inc. * On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes, using crystals or ceramic resonators. * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O). * Two External RC Oscillator modes, with the same pin options as the External Clock modes. * An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies. * A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz - all without using an external crystal or clock circuit. * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. DS39616D-page 11 PIC18F2331/2431/4331/4431 1.2 Other Special Features * Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Power Control PWM Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown on Fault detection and auto-restart to reactivate outputs once the condition has cleared. * Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN/J2602 bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 26.0 "Electrical Characteristics" for time-out periods. DS39616D-page 12 * High-Speed 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. * Motion Feedback Module (MFM): This module features a Quadrature Encoder Interface (QEI) and an Input Capture (IC) module. The QEI accepts two phase inputs (QEA, QEB) and one index input (INDX) from an incremental encoder. The QEI supports high and low precision position tracking, direction status and change of direction interrupt and velocity measurement. The input capture features 3 channels of independent input capture with Timer5 as the time base, a Special Event Trigger to other modules and an adjustable noise filter on each IC input. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 1.3 All other features for devices in this family are identical. These are summarized in Table 1-1. Details on Individual Family Members Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2331/2431) and 40/44-pin (PIC18F4331/4431) packages. The block diagram for the two groups is shown in Figure 1-1. The devices are differentiated from each other in three ways: 1. 2. 3. Flash program memory (8 Kbytes for PIC18F2331/4331 devices, 16 Kbytes for PIC18F2431/4431). A/D channels (5 for PIC18F2331/2431 devices, 9 for PIC18F4331/4431 devices). I/O ports (3 bidirectional ports on PIC18F2331/ 2431 devices, 5 bidirectional ports on PIC18F4331/4431 devices). TABLE 1-1: The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F2331/2431/4331/4431 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an "F" in the part number (such as PIC18F2331), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF2331), function over an extended VDD range of 2.0V to 5.5V. DEVICE FEATURES Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz Program Memory (Bytes) 8192 16384 8192 16384 Program Memory (Instructions) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 Data EEPROM Memory (Bytes) 256 256 256 256 34 34 Operating Frequency Interrupt Sources 22 22 Ports A, B, C Ports A, B, C Timers 4 4 4 4 Capture/Compare/PWM modules 2 2 2 2 14-Bit Power Control PWM (6 Channels) (6 Channels) (8 Channels) (8 Channels) Motion Feedback Module (Input Capture/Quadrature Encoder Interface) 1 QEI or 3x IC 1 QEI or 3x IC 1 QEI or 3x IC 1 QEI or 3x IC I/O Ports Serial Communications SSP, SSP, SSP, SSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART 10-Bit High-Speed 5 Input Channels Analog-to-Digital Converter module Resets (and Delays) Ports A, B, C, D, E Ports A, B, C, D, E 5 Input Channels 9 Input Channels 9 Input Channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions Packages 28-pin SPDIP 28-pin SOIC 28-pin QFN 28-pin SPDIP 28-pin SOIC 28-pin QFN 40-pin PDIP 44-pin TQFP 44-pin QFN 40-pin PDIP 44-pin TQFP 44-pin QFN 2010 Microchip Technology Inc. DS39616D-page 13 PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 (28-PIN) BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 Data RAM (768 bytes) inc/dec logic 21 Address Latch RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 4 12 BSR 31 Level Stack 16 Decode Table Latch PORTB 4 FSR0 FSR1 FSR2 Bank 0, F 12 inc/dec logic RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD 8 ROM Latch PORTC IR 8 Instruction Decode & Control Power-up Timer OSC2/CLKO OSC1/CLKI Timing Generation T1OSI T1OSO PRODH PRODL 3 Precision Band Gap Reference 8 x 8 Multiply 8 Oscillator Start-up Timer Power-on Reset 4x PLL RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1 RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO W 8 BITOP 8 8 8 ALU<8> Watchdog Timer 8 Brown-out Reset PORTE Power-Managed Mode Logic MCLR/VPP INTRC MCLR/VPP OSC VDD, VSS Timer0 Timer1 Timer2 Timer5 Data EE CCP1 CCP2 Synchronous Serial Port EUSART DS39616D-page 14 HS 10-Bit ADC PCPWM AVDD, AVSS MFM 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 1-2: PIC18F4331/4431 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Data RAM (768 bytes) inc/dec logic 21 Address Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 4 12 BSR 31 Level Stack 16 Decode Table Latch PORTB 4 FSR0 FSR1 FSR2 Bank 0, F 12 inc/dec logic RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD 8 ROM Latch PORTC IR 8 Instruction Decode & Control Power-up Timer OSC2/CLKO OSC1/CLKI Timing Generation T1OSI T1OSO PRODH PRODL 3 Power-on Reset 4x PLL Precision Band Gap Reference 8 x 8 Multiply 8 Oscillator Start-up Timer W 8 BITOP 8 PORTD 8 8 ALU<8> Watchdog Timer Brown-out Reset PORTE RE0/AN6 RE1/AN7 RE2/AN8 INTRC MCLR/VPP/RE3(1) OSC VDD, VSS Timer0 Timer1 Timer2 Timer5 Data EE CCP1 CCP2 Synchronous Serial Port EUSART Note 1: 2: 3: 4: RD0/IT0CKI/T5CKI RD1/SDO RD2/SDI/SDA RD3/SCK/SCL RD4/FLTA(2) RD5/PWM4(4) RD6/PWM6 RD7/PWM7 8 Power-Managed Mode Logic MCLR/VPP RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0(3) RC4/INT1/SDI/SDA(3) RC5/INT2/SCK/SCL(3) RC6/TX/CK/SS RC7/RX/DT/SDO HS 10-Bit ADC PCPWM AVDD, AVSS MFM RE3 is available only when MCLR is disabled. RD4 is the alternate pin for FLTA. RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 15 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR/VPP MCLR Pin Buffer SPDIP, Type Type QFN SOIC 1 26 I VPP OSC1/CLKI/RA7 OSC1 P 9 6 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 ST I/O 10 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSPTM programming enable pin. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. ST 7 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CAP1/INDX RA2 AN2 VREFCAP1 INDX 4 RA3/AN3/VREF+/CAP2/QEA RA3 AN3 VREF+ CAP2 QEA 5 RA4/AN4/CAP3/QEB RA4 AN4 CAP3 QEB 6 27 I/O TTL I Analog Digital I/O. Analog Input 0. I/O TTL I Analog Digital I/O. Analog Input 1. I/O TTL I Analog I Analog I ST I ST Digital I/O. Analog Input 2. A/D reference voltage (low) input. Input Capture Pin 1. Quadrature Encoder Interface index input pin. I/O TTL I Analog I Analog I ST I ST Digital I/O. Analog Input 3. A/D reference voltage (high) input. Input Capture Pin 2. Quadrature Encoder Interface Channel A input pin. I/O TTL I Analog I ST I ST Digital I/O. Analog Input 4. Input Capture Pin 3. Quadrature Encoder Interface Channel B input pin. 28 1 2 3 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39616D-page 16 CMOS = CMOS compatible input or output I = Input P = Power 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer SPDIP, Type Type QFN SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/PWM0 RB0 PWM0 21 RB1/PWM1 RB1 PWM1 22 RB2/PWM2 RB2 PWM2 23 RB3/PWM3 RB3 PWM3 24 RB4/KBI0/PWM5 RB4 KBI0 PWM5 25 RB5/KBI1/PWM4/PGM RB5 KBI1 PWM4 PGM 26 RB6/KBI2/PGC RB6 KBI2 PGC 27 RB7/KBI3/PGD RB7 KBI3 PGD 28 18 I/O O TTL TTL Digital I/O. PWM Output 0. I/O O TTL TTL Digital I/O. PWM Output 1. I/O O TTL TTL Digital I/O. PWM Output 2. I/O O TTL TTL Digital I/O. PWM Output 3. I/O I O TTL TTL TTL Digital I/O. Interrupt-on-change pin. PWM Output 5. I/O I O I/O TTL TTL TTL ST Digital I/O. Interrupt-on-change pin. PWM Output 4. Single-Supply ICSPTM Programming entry pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. 19 20 21 22 23 24 25 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output 2010 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power DS39616D-page 17 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer SPDIP, Type Type QFN SOIC Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 11 RC1/T1OSI/CCP2/FLTA RC1 T1OSI CCP2 FLTA 12 RC2/CCP1 RC2 CCP1 13 RC3/T0CKI/T5CKI/INT0 RC3 T0CKI T5CKI INT0 14 RC4/INT1/SDI/SDA RC4 INT1 SDI SDA 15 RC5/INT2/SCK/SCL RC5 INT2 SCK SCL 16 RC6/TX/CK/SS RC6 TX CK SS 17 RC7/RX/DT/SDO RC7 RX DT SDO 18 8 I/O O I ST -- ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. 9 I/O ST I Analog I/O ST I ST Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin. I/O I/O ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. I/O I I I ST ST ST ST Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External Interrupt 0. I/O I I I/O ST ST ST I2C Digital I/O. External Interrupt 1. SPI data in. I2CTM data I/O. I/O I I/O I/O ST ST ST I2C Digital I/O. External Interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O O I/O I ST -- ST TTL Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input. I/O I I/O O ST ST ST -- Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out. 10 11 12 13 14 15 VSS 8, 19 5, 16 P -- Ground reference for logic and I/O pins. VDD 7, 20 4, 17 P -- Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39616D-page 18 CMOS = CMOS compatible input or output I = Input P = Power 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number Pin Buffer Type Type PDIP TQFP QFN 1 18 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 30 I ST P I ST 32 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 31 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Available only when MCLR is disabled. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. TTL ST 33 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 19 PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CAP1/ INDX RA2 AN2 VREFCAP1 INDX 4 RA3/AN3/VREF+/ CAP2/QEA RA3 AN3 VREF+ CAP2 QEA 5 RA4/AN4/CAP3/QEB RA4 AN4 CAP3 QEB 6 RA5/AN5/LVDIN RA5 AN5 LVDIN 7 19 20 21 22 23 24 19 I/O I TTL Analog Digital I/O. Analog Input 0. I/O I TTL Analog Digital I/O. Analog Input 1. I/O I I I I TTL Analog Analog ST ST Digital I/O. Analog Input 2. A/D reference voltage (low) input. Input Capture Pin 1. Quadrature Encoder Interface index input pin. I/O I I I I TTL Analog Analog ST ST Digital I/O. Analog Input 3. A/D reference voltage (high) input. Input Capture Pin 2. Quadrature Encoder Interface Channel A input pin. I/O I I I TTL Analog ST ST Digital I/O. Analog Input 4. Input Capture Pin 3. Quadrature Encoder Interface Channel B input pin. I/O I I TTL Analog Analog Digital I/O. Analog Input 5. Low-Voltage Detect input. 20 21 22 23 24 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. DS39616D-page 20 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/PWM0 RB0 PWM0 33 RB1/PWM1 RB1 PWM1 34 RB2/PWM2 RB2 PWM2 35 RB3/PWM3 RB3 PWM3 36 RB4/KBI0/PWM5 RB4 KBI0 PWM5 37 RB5/KBI1/PWM4/ PGM RB5 KBI1 PWM4 PGM 38 RB6/KBI2/PGC RB6 KBI2 PGC 39 RB7/KBI3/PGD RB7 KBI3 PGD 40 8 9 10 11 14 15 16 17 9 I/O O TTL TTL Digital I/O. PWM Output 0. I/O O TTL TTL Digital I/O. PWM Output 1. I/O O TTL TTL Digital I/O. PWM Output 2. I/O O TTL TTL Digital I/O. PWM Output 3. I/O I O TTL TTL TTL Digital I/O. Interrupt-on-change pin. PWM Output 5. I/O I O I/O TTL TTL TTL ST Digital I/O. Interrupt-on-change pin. PWM Output 4. Single-Supply ICSPTM Programming entry pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. 10 11 12 14 15 16 17 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 21 PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2/ FLTA RC1 T1OSI CCP2 FLTA 16 RC2/CCP1/FLTB RC2 CCP1 FLTB 17 RC3/T0CKI/T5CKI/ INT0 RC3 T0CKI(1) T5CKI(1) INT0 18 RC4/INT1/SDI/SDA RC4 INT1 SDI(1) SDA(1) 23 RC5/INT2/SCK/SCL RC5 INT2 SCK(1) SCL(1) 24 RC6/TX/CK/SS RC6 TX CK SS 25 RC7/RX/DT/SDO RC7 RX DT SDO(1) 26 32 35 36 37 42 43 44 1 34 I/O O I ST -- ST I/O I I/O I ST CMOS ST ST Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM2 output. Fault interrupt input pin. I/O I/O I ST ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Fault interrupt input pin. I/O I I I ST ST ST ST Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External Interrupt 0. I/O I I I/O ST ST ST I2C Digital I/O. External Interrupt 1. SPI data in. I2CTM data I/O. I/O I I/O I/O ST ST ST I2C Digital I/O. External Interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O O I/O I ST -- ST ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). SPI slave select input. I/O I I/O O ST ST ST -- Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). SPI data out. Digital I/O. Timer1 oscillator output. Timer1 external clock input. 35 36 37 42 43 44 1 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. DS39616D-page 22 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTD is a bidirectional I/O port. RD0/T0CKI/T5CKI RD0 T0CKI T5CKI 19 RD1/SDO RD1 SDO(1) 20 RD2/SDI/SDA RD2 SDI(1) SDA(1) 21 RD3/SCK/SCL RD3 SCK(1) SCL(1) 22 RD4/FLTA RD4 FLTA(2) 27 RD5/PWM4 RD5 PWM4(3) 28 RD6/PWM6 RD6 PWM6 29 RD7/PWM7 RD7 PWM7 30 38 39 40 41 2 3 4 5 38 I/O I I ST ST ST Digital I/O. Timer0 external clock input. Timer5 input clock. I/O O ST -- Digital I/O. SPI data out. I/O I I/O ST ST ST Digital I/O. SPI data in. I2CTM data I/O. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O I ST ST Digital I/O. Fault interrupt input pin. I/O O ST TTL Digital I/O. PWM Output 4. I/O O ST TTL Digital I/O. PWM Output 6. I/O O ST TTL Digital I/O. PWM Output 7. 39 40 41 2 3 4 5 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 23 PIC18F2331/2431/4331/4431 TABLE 1-3: Pin Name PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTE is a bidirectional I/O port. RE0/AN6 RE0 AN6 8 RE1/AN7 RE1 AN7 9 RE2/AN8 RE2 AN8 10 VSS 12, 31 VDD NC 25 25 I/O I ST Analog Digital I/O. Analog Input 6. I/O I ST Analog Digital I/O. Analog Input 7. I/O I ST Analog Digital I/O. Analog Input 8. 6, 29 6, 30, 31 P -- Ground reference for logic and I/O pins. 11, 32 7, 28 7, 8, 28, 29 P -- Positive supply for logic and I/O pins. -- 12, 13, 33, 34 13 NC NC No connect. 26 27 26 27 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. DS39616D-page 24 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(1) MCLR VDD C1 Additionally, the following pins may be required: * VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: C3(1) PIC18FXXXX VSS VSS C6(1) VDD C5(1) These pins must also be connected if they are being used in the end application: * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.4 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.5 "External Oscillator Pins") VSS R2 VSS * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") R1 VDD The following pins must always be connected: VDD Getting started with the PIC18F2331/2431/4331/4431 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. VDD AVSS Basic Connection Requirements AVDD 2.1 C4(1) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic R1: 10 k R2: 100 to 470 Note 1: The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. DS39616D-page 25 PIC18F2331/2431/4331/4431 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. DS39616D-page 26 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. 2.2.3 CONSIDERATIONS WHEN USING BOR When the Brown-out Reset (BOR) feature is enabled, a sudden change in VDD may result in a spontaneous BOR event. This can happen when the microcontroller is operating under normal operating conditions, regardless of what the BOR set point has been programmed to, and even if VDD does not approach the set point. The precipitating factor in these BOR events is a rise or fall in VDD with a slew rate faster than 0.15V/s. An application that incorporates adequate decoupling between the power supplies will not experience such rapid voltage changes. Additionally, the use of an electrolytic tank capacitor across VDD and VSS, as described above, will be helpful in preventing high slew rate transitions. If the application has components that turn on or off, and share the same VDD circuit as the microcontroller, the BOR can be disabled in software by using the SBOREN bit before switching the component. Afterwards, allow a small delay before re-enabling the BOR. By doing this, it is ensured that the BOR is disabled during the interval that might cause high slew rate changes of VDD. Note: Not all devices incorporate software BOR control. See Section 5.0 "Reset" for device-specific information. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS 2.4 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes, and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGCx/PGDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 25.0 "Development Support". VDD R1 R2 MCLR JP PIC18FXXXX C1 Note 1: R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2010 Microchip Technology Inc. DS39616D-page 27 PIC18F2331/2431/4331/4431 2.5 External Oscillator Pins FIGURE 2-3: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 "Oscillator Configurations" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Single-Sided and In-Line Layouts: Copper Pour (tied to ground) For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" 2.6 Unused I/Os Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 OSC2 GND C2 T1OSO T1OS I Timer1 Oscillator Crystal Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application's routing and I/O assignments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low. DS39616D-page 28 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types FIGURE 3-1: C1(1) The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these 10 modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 3.2 Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL Enabled External Resistor/Capacitor with FOSC/4 Output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 Output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with FOSC/4 Output External Clock with I/O on RA6 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-1 shows the pin connections. The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of the crystal manufacturers' specifications. CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) OSC1 XTAL To Internal Logic RF(3) Sleep RS(2) C2(1) Note 1: PIC18FXXXX OSC2 See Table 3-1 and Table 3-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip resonant crystals. 3: RF varies with the oscillator mode chosen. TABLE 3-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 56 pF 47 pF 33 pF 56 pF 47 pF 33 pF HS 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 3-2 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz 2010 Microchip Technology Inc. DS39616D-page 29 PIC18F2331/2431/4331/4431 TABLE 3-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 4 MHz 200 kHz 8 MHz 1 MHz 20 MHz Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-2. FIGURE 3-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from Ext. System PIC18FXXXX OSC2 Open 3.3 (HS Mode) PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for those concerned with EMI from highfrequency crystals or users requiring higher clock speeds from an internal oscillator. 3.3.1 HSPLL OSCILLATOR MODE The HSPLL mode uses the HS Oscillator mode for frequencies up to 10 MHz. A PLL circuit then multiplies the oscillator output frequency by four to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC<3:0> Configuration bits are programmed for HSPLL mode (`0110'). FIGURE 3-3: PLL BLOCK DIAGRAM HS Osc Enable PLL Enable (from Configuration Register 1H) OSC2 HS Mode OSC1 Crystal Osc FIN Phase Comparator FOUT Loop Filter 4: Rs may be required to avoid overdriving crystals with low drive level specification. DS39616D-page 30 4 VCO MUX 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. SYSCLK 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-4 shows the pin connections for the EC Oscillator mode. FIGURE 3-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX FOSC/4 OSC2/CLKO The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 3-5 shows the pin connections for the ECIO Oscillator mode. 3.5 RC Oscillator For timing-insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The actual oscillator frequency is a function of several factors: * Supply voltage * Values of the external resistor (REXT) and capacitor (CEXT) * Operating temperature Given the same device, operating voltage and temperature, and component values, there will also be unit-to-unit frequency variations. These are due to factors, such as: * Normal manufacturing variation * Difference in lead frame capacitance between package types (especially for low CEXT values) * Variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode (Figure 3-6), the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. FIGURE 3-6: RC OSCILLATOR MODE VDD REXT FIGURE 3-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) CEXT PIC18FXXXX VSS OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) Internal Clock OSC1 FOSC/4 OSC2/CLKO Recommended values: 3 k REXT 100 k CEXT > 20 pF The RCIO Oscillator mode (Figure 3-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 3-7: RCIO OSCILLATOR MODE VDD REXT Internal Clock OSC1 CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 k REXT 100 k CEXT > 20 pF 2010 Microchip Technology Inc. DS39616D-page 31 PIC18F2331/2431/4331/4431 3.6 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system's clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 23.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 3-2). 3.6.1 INTIO MODES Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. DS39616D-page 32 3.6.2 INTRC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. 3.6.3 OSCTUNE REGISTER The internal oscillator's output has been calibrated at the factory, but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 3-1). Each increment may adjust the FRC frequency by varying amounts and may not be monotonic. The next closest frequency may be multiple steps apart. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. 3.6.4 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. This frequency, however, may drift as the VDD or temperature changes, which can affect the controller operation in a variety of ways. The INTOSC frequency can be adjusted by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make an adjustment, in which direction it should be made, and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 3.6.4.1 "Compensating with the EUSART", Section 3.6.4.2 "Compensating with the Timers" and Section 3.6.4.3 "Compensating with the CCP Module in Capture Mode", but other techniques may be used. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency * * * * 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 * * * * 100000 = Minimum frequency 3.6.4.1 Compensating with the EUSART An adjustment may be required when the EUSART begins generating framing errors or receives data with errors while in Asynchronous mode. Framing errors frequently indicate that the device clock frequency is too high. To adjust for this, decrement the value in the OSCTUNE register to reduce the clock frequency. Conversely, errors in data may suggest that the clock speed is too low; to compensate, increment the OSCTUNE register to increase the clock frequency. 3.6.4.2 Compensating with the Timers This technique compares the device clock speed to that of a reference clock. Two timers may be used: one timer clocked by the peripheral clock and the other by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2010 Microchip Technology Inc. 3.6.4.3 Compensating with the CCP Module in Capture Mode A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (such as the AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and recorded for later use. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate for this, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow and the OSCTUNE register should be incremented. DS39616D-page 33 PIC18F2331/2431/4331/4431 3.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F2331/2431/4331/4431 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T1CKI and RC1/T1OSI/ CCP2/FLTA pins. Like the LP Oscillator mode circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 13.2 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2331/2431/4331/4431 devices are shown in Figure 3-8. See Section 13.0 "Timer1 Module" for further details of the Timer1 oscillator. See Section 23.1 "Configuration Bits" for Configuration register details. 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the system clock's operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source that is used when the device is operating in power-managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power-managed mode of operation. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Select bits, IRCF<2:0>, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator's output. On device Resets, the default output frequency of the internal oscillator block is set at 32 kHz. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out, and the primary clock is providing the system clock in Primary Clock modes. The IOFS bit indicates when the internal oscillator block has stabilized, and is providing the system clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in Secondary Clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The IDLEN bit controls the selective shutdown of the controller's CPU in power-managed modes. The use of these bits is discussed in more detail in Section 4.0 "Power-Managed Modes" Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source, when executing a SLEEP instruction, will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts. DS39616D-page 34 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 CLOCK DIAGRAM CONFIG1H <3:0> Primary Oscillator OSC2 LP, XT, HS, RC, EC OSC1 Secondary Oscillator T1OSC T1OSO T1OSI OSCCON<1:0> HSPLL 4 x PLL Sleep Clock Control Clock Source Option for other Modules T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz OSCCON<6:4> MUX FIGURE 3-8: Peripherals Internal Oscillator CPU 111 4 MHz 8 MHz (INTOSC) Postscaler INTRC Source 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz 2010 Microchip Technology Inc. 110 IDLEN 101 100 011 MUX Internal Oscillator Block 010 001 000 WDT, FSCM DS39616D-page 35 PIC18F2331/2431/4331/4431 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-managed modes bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly)(2) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: 2: Depends on the state of the IESO bit in Configuration Register 1H. Default output frequency of INTOSC on Reset. DS39616D-page 36 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.7.2 OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking "glitches" when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Clock transitions are discussed in greater detail in Section 4.1.2 "Entering Power-Managed Modes". 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. When the device executes a SLEEP instruction, the system is switched to one of the power-managed modes, depending on the state of the IDLEN and SCS<1:0> bits of the OSCCON register. See Section 4.0 "Power-Managed Modes" for details. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 23.2 "Watchdog Timer (WDT)" through Section 23.4 "Fail-Safe Clock Monitor"). The INTOSC output at 8 MHz may be used TABLE 3-3: directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do not require a system clock source (i.e., SSP slave, INTx pins, A/D conversions and others). 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances, and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.3 "Power-on Reset (POR)" through Section 5.4 "Brown-out Reset (BOR)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 26-8), if enabled, in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 5-1 in Section 5.0 "Reset" for time-outs due to Sleep and MCLR Reset. 2010 Microchip Technology Inc. DS39616D-page 37 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 38 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.0 4.1.1 POWER-MANAGED MODES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F2331/2431/4331/4431 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). * the primary clock, as defined by the FOSC<3:0> Configuration bits * the secondary clock (the Timer1 oscillator) * the internal oscillator block (for RC modes) There are three categories of power-managed modes: 4.1.2 * Run modes * Idle modes * Sleep mode The power-managed modes include several powersaving features offered on previous PIC(R) devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. TABLE 4-1: ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 4.1.3 "Clock Transitions and Status Indicators" and subsequent sections. These categories define which portions of the device are clocked, and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. 4.1 CLOCK SOURCES POWER-MANAGED MODES OSCCON Bits<7,1:0> Module Clocking IDLEN(1) SCS<1:0> CPU Peripherals 0 N/A Off Off PRI_RUN N/A 00 Clocked Clocked SEC_RUN N/A 01 Clocked Clocked Secondary - Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary - LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary - Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Mode Sleep Note 1: 2: Available Clock and Oscillator Source None - All clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block.(2) This is the normal, full-power execution mode. IDLEN reflects its value when the SLEEP instruction is executed. Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2010 Microchip Technology Inc. DS39616D-page 39 PIC18F2331/2431/4331/4431 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: * OSTS (OSCCON<3>) * IOFS (OSCCON<2>) * T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable, 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC<3:0> Configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable, 8 MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. 4.1.4 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39616D-page 40 4.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 4.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 23.3 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 3.7.1 "Oscillator Control Register"). 4.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC PC + 2 PC + 4 Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note 1: 2: 4.2.3 PC + 2 PC PC + 4 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC. RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2010 Microchip Technology Inc. This mode is entered by setting the SCS1 bit to `1'. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. DS39616D-page 41 PIC18F2331/2431/4331/4431 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes, after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 INTRC 2 3 n-1 Clock Transition OSC1 Q3 Q4 Q1 Q2 Q3 n (1) CPU Clock Peripheral Clock Program Counter Note 1: PC PC + 2 PC + 4 Clock transition typically occurs within 2-4 TOSC. FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note 1: 2: DS39616D-page 42 PC + 2 PC PC + 4 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source, selected by the SCS<1:0> bits, becomes ready (see Figure 4-6), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor is enabled (see Section 23.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (Parameter 38, Table 26-8) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT timeout will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 4-6: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2010 Microchip Technology Inc. DS39616D-page 43 PIC18F2331/2431/4331/4431 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm-up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<3:0> Configuration bits. The OSTS bit remains set (see Figure 4-7). setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS<1:0> bits to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD, following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 4-8). Note: When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-8). 4.4.2 The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 4-8: PC PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39616D-page 44 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (Parameter 39, Table 26-8). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD, following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in more detail in each of the sections that relate to the power-managed modes (see Section 4.2 "Run Modes", Section 4.3 "Sleep Mode" and Section 4.4 "Idle Modes"). 4.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2010 Microchip Technology Inc. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 10.0 "Interrupts"). A fixed delay of interval, TCSD, following the wake event, is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 "Run Modes" and Section 4.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 23.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 4.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up, and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 4-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 23.4 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. DS39616D-page 45 PIC18F2331/2431/4331/4431 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode, where the primary clock source is not stopped; and * the primary clock source is not any of the LP, XT, HS or HSPLL modes. TABLE 4-2: In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval, TCSD, following the wake event, is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Clock Source After Wake-up Exit Delay Clock Ready Status Bit (OSCCON) LP, XT, HS Primary Device Clock (PRI_IDLE mode) HSPLL EC, RC TCSD(1) INTOSC(2) T1OSC INTOSC(3) None (Sleep mode) 2: 3: 4: IOFS LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC INTOSC(2) TCSD(1) TIOBST(4) IOFS LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) INTOSC(2) None LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) TIOBST(4) IOFS INTOSC(2) Note 1: OSTS IOFS TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concurrently with any other required delays (see Section 4.4 "Idle Modes"). Includes both the INTOSC 8 MHz source and postscaler derived frequencies. TOST is the Oscillator Start-up Timer (Parameter 32). trc is the PLL Lock-out Timer (Parameter F12); it is also designated as TPLL. Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period. DS39616D-page 46 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.0 RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset FIGURE 5-1: This section discusses Resets generated by MCLR, POR and BOR, and the operation of the various startup timers. Stack Reset events are covered in Section 6.1.2.4 "Stack Full/Underflow Resets". WDT Resets are covered in Section 23.2 "Watchdog Timer (WDT)". A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD POR Pulse Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles 10-Bit Ripple Counter OSC1 32 s INTRC PWRT R Q Chip_Reset 65.5 ms 11-Bit Ripple Counter Enable PWRT Enable OST(1) Note 1: See Table 5-1 for time-out situations. 2010 Microchip Technology Inc. DS39616D-page 47 PIC18F2331/2431/4331/4431 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.6 "Reset State of Registers". Note 1: If the BOREN Configuration bit is set (Brown-out Reset enabled), the BOR bit is `1' on a Power-on Reset. After a Brown-out Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 10.0 "Interrupts". BOR is covered in Section 5.4 "Brown-out Reset (BOR)". REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR(2) BOR(1) bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit(1) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 5.6 "Reset State of Registers" for additional information. Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset). DS39616D-page 48 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin can trigger an external Reset of the device by holding the pin low. These devices have a noise filter in the MCLR Reset path that detects and ignores small pulses. In PIC18F2331/2431/4331/4431 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. For more information, see Section 11.5 "PORTE, TRISE and LATE Registers". 5.3 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. D Power-on Reset events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a POR occurs and does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset. Note: The following decoupling method is recommended: 1. A 1 F capacitor should be connected across AVDD and AVSS. 2. A similar capacitor should be connected across VDD and VSS. 2010 Microchip Technology Inc. R R1 C MCLR PIC18FXXXX Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode, D, helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. The minimum rise rate for VDD is specified (Parameter D004). For a slow rise time, see Figure 5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (such as voltage, frequency and temperature) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. VDD VDD The MCLR pin is not driven low by any internal Resets, including the Watchdog Timer. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) 3: R1 1 k will limit any current flowing into MCLR from external capacitor, C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 5.4 Brown-out Reset (BOR) A Configuration bit, BOREN, can disable (if clear/ programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (Parameter D005A through D005F) for greater than TBOR (Parameter 35), the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay TPWRT (Parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling the Brown-out Reset does not automatically enable the PWRT. DS39616D-page 49 PIC18F2331/2431/4331/4431 5.5 5.5.3 Device Reset Timers PIC18F2331/2431/4331/4431 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out 5.5.1 With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL Lock Time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 5.5.4 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter that uses the INTRC source as the clock input. This yields an approximate time interval of 2,048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC Parameter 33 for details. The PWRT is enabled by clearing the PWRTEN Configuration bit. 5.5.2 PLL LOCK TIME-OUT OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1,024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (Parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 1. 2. After the POR pulse has cleared, the PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3 through Figure 5-7 depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figure 5-3 through Figure 5-6 also apply to devices operating in XT or LP modes. For devices in RC mode, and with the PWRT disabled, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes or synchronization of more than one PIC18FXXXX device operating in parallel. The OST time-out is invoked only for XT, LP, HS and HSPLL modes, and on Power-on Reset or on exit from most power-managed modes. TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration HSPLL HS, XT, LP Power-up(2) and Brown-out PWRTEN = 0 PWRTEN = 1 Exit From Power-Managed Mode 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) (1) 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) -- -- RC, RCIO 66 ms(1) -- -- (1) -- -- INTIO1, INTIO2 Note 1: 2: 66 ms + 1024 TOSC 66 ms 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the 4x PLL to lock. DS39616D-page 50 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. FIGURE 5-3: Status bits from the RCON register (RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-2. These bits are used in software to determine the nature of the Reset. Table 5-3 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets, and WDT wake-ups. TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR PWRT TIME-OUT TPWRT TOST OST TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. DS39616D-page 51 PIC18F2331/2431/4331/4431 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39616D-page 52 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 5-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. TABLE 5-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0 RESET Instruction 0000h 0--0 uuuu 0 u u u u u u Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u MCLR Reset during power-managed Run modes 0000h 0--u 1uuu u 1 u u u u u MCLR Reset during power-managed Idle and Sleep modes 0000h 0--u 10uu u 1 0 u u u u WDT Time-out during full power or power-managed Run modes 0000h 0--u 0uuu u 0 u u u u u u u 0000h 0--u uuuu u u u u u 1 u u 1 MCLR Reset during full-power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u--u uuuu u u u u u u 1 WDT time-out during power-managed Idle or Sleep modes PC + 2 u--u 00uu u 0 0 u u u u Interrupt exit from power-managed modes PC + 2(1) u--u u0uu u u 0 u u u u Legend: Note 1: u = unchanged, x = unknown, - = unimplemented bit, read as `0'. When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2010 Microchip Technology Inc. DS39616D-page 53 PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets TOSU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2331 2431 4331 4431 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu PCLATH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PCL 2331 2431 4331 4431 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu TBLPTRH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TABLAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PRODH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2331 2431 4331 4431 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2331 2431 4331 4431 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2331 2431 4331 4431 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2331 2431 4331 4431 N/A N/A N/A POSTINC0 2331 2431 4331 4431 N/A N/A N/A Register Wake-up via WDT or Interrupt POSTDEC0 2331 2431 4331 4431 N/A N/A N/A PREINC0 2331 2431 4331 4431 N/A N/A N/A PLUSW0 2331 2431 4331 4431 N/A N/A N/A FSR0H 2331 2431 4331 4431 ---- xxxx ---- uuuu ---- uuuu FSR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2331 2431 4331 4431 N/A N/A N/A POSTINC1 2331 2431 4331 4431 N/A N/A N/A POSTDEC1 2331 2431 4331 4431 N/A N/A N/A PREINC1 2331 2431 4331 4431 N/A N/A N/A PLUSW1 2331 2431 4331 4431 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. DS39616D-page 54 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 2331 2431 4331 4431 ---- 0000 ---- uuuu ---- uuuu FSR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu INDF2 2331 2431 4331 4431 N/A N/A N/A Register POSTINC2 2331 2431 4331 4431 N/A N/A N/A POSTDEC2 2331 2431 4331 4431 N/A N/A N/A PREINC2 2331 2431 4331 4431 N/A N/A N/A PLUSW2 2331 2431 4331 4431 N/A N/A N/A FSR2H 2331 2431 4331 4431 ---- 0000 ---- uuuu ---- uuuu FSR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2331 2431 4331 4431 ---x xxxx ---u uuuu ---u uuuu TMR0H 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TMR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu OSCCON 2331 2431 4331 4431 0000 q000 0000 q000 uuuu uuuu LVDCON 2331 2431 4331 4431 --00 0101 --00 0101 --uu uuuu WDTCON 2331 2431 4331 4431 0--- ---0 0--- ---0 u--- ---u RCON(4) 2331 2431 4331 4431 0--1 11q0 0--q qquu u--u qquu TMR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2331 2431 4331 4431 0000 0000 u0uu uuuu uuuu uuuu TMR2 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PR2 2331 2431 4331 4431 1111 1111 1111 1111 1111 1111 T2CON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu SSPBUF 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SSPCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. DS39616D-page 55 PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ADCON1 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu ADCON2 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu ADCON3 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu ADCHS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu CCPR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu CCPR2H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ANSEL1 2331 2431 4331 4431 ---- ---1 ---- ---1 ---- ---u ANSEL0 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu T5CON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu QEICON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SPBRGH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SPBRG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu RCREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TXREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TXSTA 2331 2431 4331 4431 0000 -010 0000 -010 uuuu -uuu RCSTA 2331 2431 4331 4431 0000 000x 0000 000x uuuu uuuu BAUDCON 2331 2431 4331 4431 -1-1 0-00 -1-1 0-00 -u-u u-uu EEADR 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu EEDATA 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu EECON2 2331 2431 4331 4431 0000 0000 0000 0000 0000 0000 EECON1 2331 2431 4331 4431 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 2331 2431 4331 4431 ---1 1111 ---1 1111 ---u uuuu PIE3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu PIR3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. DS39616D-page 56 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 2331 2431 4331 4431 1--1 -1-1 1--1 -1-1 u--u -u-u PIR2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u PIE2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u IPR1 2331 2431 4331 4431 -111 1111 -111 1111 -uuu uuuu PIR1 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu(1) 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu(1) 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu PIE1 OSCTUNE 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu TRISE(6) 2331 2431 4331 4431 ---- -111 ---- -111 ---- -uuu TRISD 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu TRISC 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu TRISB 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2331 2431 4331 4431 1111 1111(5) 1111 1111(5) uuuu uuuu(5) PR5H 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu PR5L 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu LATE(6) 2331 2431 4331 4431 ---- -xxx ---- -uuu ---- -uuu LATD 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu (5) LATA 2331 2431 4331 4431 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) TMR5H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu TMR5L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTE(6) 2331 2431 4331 4431 ---- xxxx ---- xxxx ---- uuuu PORTD 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2331 2431 4331 4431 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. DS39616D-page 57 PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt PTCON0 2331 2431 4331 4431 0000 0000 uuuu uuuu uuuu uuuu PTCON1 2331 2431 4331 4431 00-- ---- 00-- ---- uu-- ---- PTMRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PTMRH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu PTPERL 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu PTPERH 2331 2431 4331 4431 ---- 1111 ---- 1111 ---- uuuu PDC0L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC0H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC1L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC1H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC2L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC2H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC3L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC3H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu SEVTCMPL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SEVTCMPH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu PWMCON0 2331 2431 4331 4431 -111 0000 -111 0000 -uuu uuuu PWMCON1 2331 2431 4331 4431 0000 0-00 0000 0-00 uuuu u-uu DTCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu FLTCONFIG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu OVDCOND 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu OVDCONS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu CAP1BUFH/ VELRH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP1BUFL/ VELRL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP2BUFH/ POSCNTH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP2BUFL/ POSCNTL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP3BUFH/ MAXCNTH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. DS39616D-page 58 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices Power-on Reset, Brown-out Reset CAP3BUFL/ MAXCNTL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP1CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP2CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP3CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu DFLTCON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as `0'. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. DS39616D-page 59 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 60 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.0 MEMORY ORGANIZATION There are three memory types in enhanced MCU devices. These memory types are: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate buses, enabling concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 8.0 "Flash Program Memory". Data EEPROM is discussed separately in Section 7.0 "Data EEPROM Memory". FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2331/4331 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter that can address a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F2331/4331 devices each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F2431/4431 devices each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 000000h and the interrupt vector addresses are at 000008h and 000018h. The program memory maps for PIC18F2331/4331 and PIC18F2431/4431 devices are shown in Figure 6-1 and Figure 6-2, respectively. FIGURE 6-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F2431/4431 PC<20:0> PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 1 Stack Level 31 Stack Level 31 Reset Vector LSb High-Priority Interrupt Vector LSb 000008h High-Priority Interrupt Vector LSb 000008h Low-Priority Interrupt Vector LSb Low-Priority Interrupt Vector LSb 000018h 000018h On-Chip Flash Program Memory 001FFFh 002000h User Memory Space On-Chip Flash Program Memory 000000h Reset Vector LSb 000000h User Memory Space 003FFFh 004000h Unused Read `0's 1FFFFFh 2010 Microchip Technology Inc. Unused Read `0's 1FFFFFh DS39616D-page 61 PIC18F2331/2431/4331/4431 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte (PCH register) contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is the PCU register and contains the bits, PC<20:16>. This register is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to the PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.1.4.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of the PCL is fixed to a value of `0`. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 6.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, with the Stack Pointer initialized to 00000b after all Resets. There is no RAM associated with Stack Pointer, 00000b. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. DS39616D-page 62 The stack space is not part of either program or data space. The Stack Pointer is readable and writable, and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special Function Registers. Data can also be pushed to, or popped from, the stack using the Top-of-Stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed. 6.1.2.1 Top-of-Stack Access The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 6-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. 6.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 23.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. FIGURE 6-3: Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset as the contents of the SFRs are not affected. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack REGISTER 6-1: STKPTR<4:0> 00010 00011 001A34h 00010 000D58h 00001 00000 STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) -- SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as `0' bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: x = Bit is unknown Bit 7 and bit 6 are cleared by user software or by a POR. 2010 Microchip Technology Inc. DS39616D-page 63 PIC18F2331/2431/4331/4431 6.1.2.3 PUSH and POP Instructions Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 6.1.2.4 Stack Full/Underflow Resets These Resets are enabled by programming the STVREN bit in Configuration Register 4L. When the STVREN bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVREN bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.3 FAST REGISTER STACK A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a "fast return" option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high-priority interrupts are enabled, the stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. DS39616D-page 64 Example 6-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. EXAMPLE 6-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 RETURN FAST 6.1.4 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented two ways: * Computed GOTO * Table Reads 6.1.4.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value "nn" to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte can be stored in each instruction location and room on the return address stack is required. EXAMPLE 6-2: MOVFW CALL 0xnn00 ADDWF RETLW RETLW RETLW ORG TABLE COMPUTED GOTO USING AN OFFSET VALUE OFFSET TABLE PCL 0xnn 0xnn 0xnn . . . 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.1.4.2 Table Reads and Table Writes 6.2 A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored, two bytes per program word, by using table reads and writes. The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the Instruction Register (IR) in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-4. The Table Pointer register (TBLPTR) specifies the byte address and the Table Latch register (TABLAT) contains the data that is read from or written to program memory. Data is transferred to or from program memory, one byte at a time. Table read and table write operations are discussed further in Section 8.1 "Table Reads and Table Writes". FIGURE 6-4: Clocking Scheme/Instruction Cycle CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC OSC2/CLKO (RC mode) 6.3 Execute INST (PC - 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle, Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). INSTRUCTION PIPELINE FLOW 1. MOVLW 55h TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 3. BRA SUB_1 4. BSF Execute INST (PC + 2) Fetch INST (PC + 4) A fetch cycle begins with the Program Counter (PC) incrementing in Q1. Instruction Flow/Pipelining EXAMPLE 6-3: PC + 4 PC + 2 PC PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. 2010 Microchip Technology Inc. DS39616D-page 65 PIC18F2331/2431/4331/4431 6.4 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 6-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0'. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction 2 in Figure 6-5 shows how the instruction, `GOTO 000006h', is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 24.0 "Instruction Set Summary" provides further details of the instruction set. FIGURE 6-5: 6.4.1 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the four MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence, immediately after the first word, the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: For information on two-word instructions in the extended instruction set, see Section 24.2 "Instruction Set". INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations Instruction 1: Instruction 2: MOVLW GOTO 055h 000006h Instruction 3: MOVFF 123h, 456h EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 CASE 2: Object Code 0000 0011 0110 0000 0110 1100 1111 0010 0000 0011 0110 0000 0110 0001 0100 0100 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 0000 0010 0101 0000 DS39616D-page 66 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; No, skip this word ; Execute this word as a NOP REG3 ; continue code Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.5 The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. Data Memory Organization The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. PIC18F2331/2431/4331/4431 devices implement all 16 banks. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.5.2 "Access Bank" provides a detailed description of the Access RAM. Figure 6-6 shows the data memory organization for the PIC18F2331/2431/4331/4431 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. FIGURE 6-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES Data Memory Map BSR<3:0> = 0000 = 0001 = 0010 00h Access RAM FFh 00h GPR Bank 0 000h 05Fh 060h 0FFh 100h GPR Bank 1 1FFh 200h FFh 00h GPR Bank 2 FFh 00h 2FFh 300h Access Bank Access RAM Low = 0011 = 1110 Bank 3 to Bank 14 00h 5Fh Access RAM High 60h (SFRs) FFh Unused Read `00h' When a = 0: The BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). = 1111 00h Unused FFh SFR Bank 15 EFFh F00h F5Fh F60h FFFh The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction. 2010 Microchip Technology Inc. DS39616D-page 67 PIC18F2331/2431/4331/4431 6.5.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a four-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the four Most Significant bits of a location's address; the instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 6-6. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to the eight-bit address of F9h, while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39616D-page 68 6.5.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected; otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. This upper half is also where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 6-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. 6.5.3 GENERAL PURPOSE REGISTER (GPR) FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.5.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 6-1 and Table 6-2. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the TABLE 6-1: "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as `0's. SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES Address Name Address FFFh TOSU FDFh INDF2(1) Name Address FFEh TOSH FDEh POSTINC2(1) FFDh TOSL FDDh POSTDEC2(1) (1) Name FBFh CCPR1H FBEh CCPR1L FBDh CCP1CON Address Name Address Name F9Fh IPR1 F7Fh PTCON0 F9Eh PIR1 F7Eh PTCON1 F9Dh PIE1 F7Dh PTMRL (2) FFCh STKPTR FDCh PREINC2 FBCh CCPR2H F9Ch F7Ch PTMRH FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh PTPERL FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah ADCON3 F7Ah PTPERH FF9h PCL FD9h FSR2L FB9h F99h ADCHS F79h PDC0L F78h PDC0H F77h PDC1L (3) ANSEL1 -- FF8h TBLPTRU FD8h STATUS FB8h ANSEL0 F98h --(2) FF7h TBLPTRH FD7h TMR0H FB7h T5CON F97h --(2) FF6h TBLPTRL FD6h TMR0L FB6h QEICON F96h TRISE F76h PDC1H FF5h TABLAT FD5h T0CON FB5h --(2) F95h TRISD(3) F75h PDC2L FF4h PRODH FD4h --(2) FB4h --(2) F94h TRISC F74h PDC2H FF3h PRODL FD3h OSCCON FB3h --(2) F93h TRISB F73h PDC3L(3) FF2h INTCON FD2h LVDCON FB2h --(2) F92h TRISA F72h PDC3H(3) WDTCON FB1h --(2) F91h PR5H F71h SEVTCMPL FF1h INTCON2 FD1h FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h PR5L F70h SEVTCMPH FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh --(2) F6Fh PWMCON0 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh --(2) F6Eh PWMCON1 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) F6Dh DTCON FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch FLTCONFIG FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh OVDCOND FEAh FSR0H FCAh T2CON FAAh BAUDCON F8Ah LATB F6Ah OVDCONS FE9h FSR0L FC9h SSPBUF FA9h F89h LATA F69h CAP1BUFH EEADR FE8h WREG FC8h SSPADD FA8h EEDATA F88h TMR5H F68h CAP1BUFL FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2 F87h TMR5L F67h CAP2BUFH FE6h POSTINC1(1) FC6h SSPCON FA6h EECON1 F86h --(2) F66h CAP2BUFL FE5h POSTDEC1(1) FC5h --(2) FA5h IPR3 F85h --(2) F65h CAP3BUFH FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h CAP3BUFL FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD(3) F63h CAP1CON FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h CAP2CON FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h CAP3CON FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h DFLTCON Note 1: 2: 3: This is not a physical register. Unimplemented registers are read as `0'. This register is not available on 28-pin devices. 2010 Microchip Technology Inc. DS39616D-page 69 PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) Bit 7 Bit 6 Bit 5 -- -- -- TOSU TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKFUL STKUNF -- PCLATU -- -- bit 21(3) Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU -- -- Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 0000 0000 0000 0000 STKPTR PCLATH Bit 4 SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21(3) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 TABLAT Program Memory Table Latch 0000 0000 PRODH Product Register High Byte xxxx xxxx PRODL Product Register Low Byte INTCON xxxx xxxx GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP -- INT0IF RBIF INTEDG2 -- TMR0IP -- RBIP 1111 -1-1 INT2IE INT1IE -- INT2IF INT1IF 11-0 0-00 0000 000x INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register) FSR0H -- -- -- -- N/A Indirect Data Memory Address Pointer 0 High ---- xxxx FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx WREG Working Register xxxx xxxx INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) FSR1H -- FSR1L -- -- N/A -- Indirect Data Memory Address Pointer 1 High Byte -- Bank Select Register ---- 0000 Indirect Data Memory Address Pointer 1 Low Byte BSR -- -- -- xxxx xxxx ---- 0000 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) N/A POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) FSR2H FSR2L -- -- -- -- TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte Legend: Note 1: 2: 3: 4: 5: -- N/A Indirect Data Memory Address Pointer 2 High Byte ---- 0000 Indirect Data Memory Address Pointer 2 Low Byte STATUS T0CON -- TMR0ON T016BIT -- xxxx xxxx N OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented. RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as `0'. The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to `0'; otherwise, RE3 reads `0'. This bit is read-only. DS39616D-page 70 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 6 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 LVDCON -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 WDTCON WDTW -- -- -- -- -- -- SWDTEN 0--- ---0 IPEN -- -- RI TO PD POR BOR 0--1 11q0 RCON Bit 5 TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN TMR2 Timer2 Register PR2 Timer2 Period Register T2CON -- Bit 4 Bit 3 Bit 2 Bit 1 xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS 0000 0000 1111 1111 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 SSP Receive Buffer/Transmit Register SSPADD SSP Address Register in I2CTM Slave mode. SSP Baud Rate Reload Register in I2C Master mode. SSPCON TMR1ON 0000 0000 SSPBUF SSPSTAT Bit 0 Value on POR, BOR Bit 7 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 SMP CKE D/A P S R/W UA BF 0000 0000 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte xxxx xxxx xxxx xxxx ADCON0 -- -- ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000 ADCON1 VCFG1 VCFG0 -- FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 00-0 0000 ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 ADCON3 ADRS1 ADRS0 -- SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 ADCHS CCPR1H Capture/Compare/PWM Register 1 High Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCP1CON -- -- DC1B1 CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx xxxx xxxx DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 xxxx xxxx xxxx xxxx CCP2CON -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 ANSEL1 -- -- -- -- -- -- -- ANS8(4) ---- ---1 ANSEL0 ANS7(4) ANS6(4) ANS5(4) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 (4) T5CON T5SEN RESEN QEICON VELM QERR T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 0000 0000 UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0 0000 0000 SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 RCREG EUSART Receive Register 0000 0000 TXREG EUSART Transmit Register 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-1 0-00 BAUDCON Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented. RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as `0'. The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to `0'; otherwise, RE3 reads `0'. This bit is read-only. 2010 Microchip Technology Inc. DS39616D-page 71 PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR EEADR EEPROM Address Register 0000 0000 EEDATA EEPROM Data Register 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) EECON1 0000 0000 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 IPR3 -- -- -- PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 PIR3 -- -- -- PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 PIE3 -- -- -- PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 IPR2 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP 1--1 -1-1 PIR2 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF 0--0 -0-0 PIE2 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE 0--0 -0-0 IPR1 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 OSCTUNE -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 ADCON3 ADRS1 ADRS0 -- SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 TRISE(4) -- -- -- -- -- PORTE Data Direction Register(4) ---- -111 TRISD(4) PORTD Data Direction Register 1111 1111 TRISC PORTC Data Direction Register 1111 1111 TRISB PORTB Data Direction Register TRISA7(2) TRISA TRISA6(1) 1111 1111 PORTA Data Direction Register PR5H Timer5 Period Register High Byte PR5L Timer5 Period Register Low Byte LATE(4) -- -- 1111 1111 1111 1111 1111 1111 -- -- -- LATE Data Output Register ---- -xxx LATD(4) LATD Data Output Register xxxx xxxx LATC LATC Data Output Register xxxx xxxx LATB LATB Data Output Register LATA7(2) LATA LATA6(1) TMR5H Timer5 Register High Byte TMR5L Timer5 Register Low Byte PORTE -- xxxx xxxx LATA Data Output Register xxxx xxxx xxxx xxxx xxxx xxxx -- -- -- RE3(4,5) RE2(4) RE1(4) RE0(4) ---- xxxx PORTD(4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx PORTA RA7(2) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 PTCON1 PTEN PTDIR -- -- -- -- -- -- 00-- ---- PTMRL PWM Time Base Register (lower 8 bits) PTMRH PTPERL UNUSED PWM Time Base Period Register (lower 8 bits) PTPERH Legend: Note 1: 2: 3: 4: 5: 0000 0000 PWM Time Base Register (upper 4 bits) UNUSED ---- 0000 1111 1111 PWM Time Base Period Register (upper 4 bits) ---- 1111 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented. RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as `0'. The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to `0'; otherwise, RE3 reads `0'. This bit is read-only. DS39616D-page 72 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 6-2: File Name PDC0L REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM Duty Cycle #0L Register (lower 8 bits) PDC0H PDC1L 0000 0000 PWM Duty Cycle #0H Register (upper 6 bits) UNUSED --00 0000 PWM Duty Cycle #1L Register (lower 8 bits) PDC1H PDC2L 0000 0000 PWM Duty Cycle #1H Register (upper 6 bits) UNUSED --00 0000 PWM Duty Cycle #2L Register (lower 8 bits) PDC2H PDC3L(4) 0000 0000 PWM Duty Cycle #2H Register (upper 6 bits) UNUSED --00 0000 PWM Duty Cycle #3L Register (lower 8 bits) PDC3H(4) SEVTCMPL 0000 0000 PWM Duty Cycle #3H Register (upper 6 bits) UNUSED --00 0000 PWM Special Event Compare Register (lower 8 bits) SEVTCMPH Value on POR, BOR 0000 0000 PWM Special Event Compare Register (upper 4 bits) UNUSED ---- 0000 PWMCON0 -- PWMEN2 PWMEN1 PWMEN0 PMOD3 PMOD2 PMOD1 PMOD0 -111 0000 PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR -- UDIS OSYNC 0000 0-00 DTCON DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 0000 0000 FLTCONFIG BRFEN FLTBS(4) FLTBMOD(4) FLTBEN(4) FLTCON FLTAS FLTAMOD FLTAEN 0000 0000 OVDCOND POVD7(4) POVD6(4) POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 1111 1111 OVDCONS POUT7(4) POUT6(4) POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0000 0000 CAP1BUFH/ VELRH Capture 1 Register High Byte/Velocity Register High Byte xxxx xxxx CAP1BUFL/ VELRL Capture 1 Register Low Byte/Velocity Register Low Byte xxxx xxxx CAP2BUFH/ POSCNTH Capture 2 Register High Byte/QEI Position Counter Register High Byte xxxx xxxx CAP2BUFL/ POSCNTL Capture 2 Register Low Byte/QEI Position Counter Register Low Byte xxxx xxxx CAP3BUFH/ MAXCNTH Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte xxxx xxxx CAP3BUFL/ MAXCNTL Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte xxxx xxxx CAP1CON -- CAP1REN -- -- CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-- 0000 CAP2CON -- CAP2REN -- -- CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-- 0000 CAP3CON -- CAP3REN -- -- CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-- 0000 DFLTCON -- FLT4EN FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented. RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read `0' in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other modes. Bit 21 of the PC is only available in Test mode and Serial Programming modes. These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as `0'. The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to `0'; otherwise, RE3 reads `0'. This bit is read-only. 2010 Microchip Technology Inc. DS39616D-page 73 PIC18F2331/2431/4331/4431 6.6 STATUS Register The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see Table 24-2. Note: The C and DC bits operate as a Borrow and Digit Borrow bit respectively, in subtraction. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). REGISTER 6-2: U-0 STATUS REGISTER U-0 -- -- U-0 -- R/W-x N R/W-x R/W-x R/W-x R/W-x Z DC(1) C(2) OV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. DS39616D-page 74 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.7 Data Addressing Modes The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect 6.7.1 The destination of the operation's results is determined by the destination bit, `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 6.7.3 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all. They either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 6.7.2 A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their op codes. In these cases, the BSR is ignored entirely. DIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.5.4 "Special Function Registers") or a location in the Access Bank (Section 6.5.2 "Access Bank") as the data source for the instruction. INDIRECT ADDRESSING Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 6-5. EXAMPLE 6-5: NEXT LFSR CLRF BTFSS BRA CONTINUE HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue The Access RAM bit, `a', determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 6.5.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. 2010 Microchip Technology Inc. DS39616D-page 75 PIC18F2331/2431/4331/4431 6.7.3.1 FSR Registers and the INDF Operand 6.7.3.2 At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards * POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards * PREINC: increments the FSR value by 1, then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. Indirect Addressing is accomplished with a set of Indirect File Operands: INDF0 through INDF2. These can be thought of as "virtual" registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 6-7: FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). INDIRECT ADDRESSING 000h Using an instruction with one of the indirect addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 2 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory DS39616D-page 76 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.7.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contain FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. 2010 Microchip Technology Inc. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. DS39616D-page 77 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 78 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.0 DATA EEPROM MEMORY 7.2 EECON1 and EECON2 Registers The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. There are four SFRs used to read and write the program and data EEPROM memory. These registers are: The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. * * * * EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to Parameter D122 (Table 26-1 in Section 26.0 "Electrical Characteristics") for exact limits. 7.1 EEADR The Address register can address 256 bytes of data EEPROM. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either Flash program or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR bit is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 7.3 "Reading the Data EEPROM Memory" regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. 2010 Microchip Technology Inc. DS39616D-page 79 PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39616D-page 80 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).The basic process is shown in Example 7-1. 7.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. EXAMPLE 7-1: MOVLW MOVWF BCF BSF MOVF At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W EXAMPLE 7-2: Required Sequence After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BTFSC DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; GOTO BSF $-2 INTCON, GIE ; ; Enable interrupts 2010 Microchip Technology Inc. Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete DS39616D-page 81 PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 "Special Features of the CPU" for additional information. 7.8 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM memory are blocked during the Power-up Timer period (TPWRT, Parameter 33). 7.9 Using the Data EEPROM The data EEPROM is a high-endurance, byteaddressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than Specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See Specification D124. The write/initiate sequence, and the WREN bit together, help prevent an accidental write during Brown-out Reset, power glitch or software malfunction. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF BCF BCF BCF BSF EEADR EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN LOOP Required Sequence DS39616D-page 82 ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 7-1: Name INTCON REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 EEADR EEPROM Address Register 56 EEDATA EEPROM Data Register 56 EECON2 EEPROM Control Register 2 (not a physical register) 56 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 56 IPR2 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP 57 PIR2 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF 57 PIE2 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE 57 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. DS39616D-page 83 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 84 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 8.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. 8.1 Table Reads and Table Writes The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 8-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 8.5 "Writing to Flash Program Memory". Figure 8-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned, (TBLPTRL<0> = 0). In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) FIGURE 8-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer points to a byte in program memory. 2010 Microchip Technology Inc. DS39616D-page 85 PIC18F2331/2431/4331/4431 FIGURE 8-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 8.2 The Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 8.5 "Writing to Flash Program Memory". Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 8.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. A write operation is allowed when the WREN bit (EECON1<2>) is set. On power-up, the WREN bit is clear. The WRERR bit (EECON1<3>) is set in hardware when the WR bit (EECON1<1>) is set and cleared when the internal programming timer expires and the write operation is complete. Note: EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers, regardless of EEPGD. (See Section 23.0 "Special Features of the CPU".) When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. DS39616D-page 86 During normal operation, the WRERR may read as `1'. This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. The bit is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. DS39616D-page 87 PIC18F2331/2431/4331/4431 8.2.2 TABLAT - TABLE LATCH REGISTER 8.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 8.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 8.5 "Writing to Flash Program Memory". The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the Device ID, the User ID and the Configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The TBLPTR is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 8-1. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 8-1: TABLE POINTER BOUNDARIES Figure 8-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 8-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 TABLE ERASE/WRITE TBLPTR<21:6> 7 TBLPTRL 0 TABLE WRITE TBLPTR<5:0> TABLE READ - TBLPTR<21:0> DS39616D-page 88 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 8.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 8-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 8-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 8-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF TABLAT,W WORD_EVEN TABLAT,W WORD_ODD 2010 Microchip Technology Inc. ; read into TABLAT and increment TBLPTR ; get data ; read into TABLAT and increment TBLPTR ; get data DS39616D-page 89 PIC18F2331/2431/4331/4431 8.4 8.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Larger blocks of program memory can be bulk erased only through the use of an external programmer or ICSP control. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased; TBLPTR<5:0> are ignored. 2. The EECON1 register commands the erase operation. The EEPGD bit (EECON1<7>) must be set to point to the Flash program memory. The WREN bit (EECON1<2>) must be set to enable write operations. The FREE bit (EECON1<4>) is set to select an erase operation. 3. 4. 5. 6. For protection, the write initiate sequence using EECON2 must be used. 7. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. 8. 9. EXAMPLE 8-2: FLASH PROGRAM MEMORY ERASE SEQUENCE Load the Table Pointer with the address of the row being erased. Set the EECON1 register for the erase operation: - set the EEPGD bit to point to program memory; - clear the CFGS bit to access program memory; - set the WREN bit to enable writes; - set the FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for the duration of the erase (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON2, ; ; ; ; ; ERASE_ROW Required Sequence DS39616D-page 90 EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55H WR INTCON, GIE ; write 0AAH ; start erase (CPU stall) ; re-enable interrupts 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. 8.5 Writing to Flash Program Memory Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. FIGURE 8-5: Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the modification does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 8 TBLPTR = xxxxx2 Holding Register Holding Register 8 TBLPTR = xxxxx7 Holding Register Program Memory 2010 Microchip Technology Inc. DS39616D-page 91 PIC18F2331/2431/4331/4431 8.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE 7. The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 8.4.1 "Flash Program Memory Erase Sequence"). Load Table Pointer with the address of the first byte being written. Write the first 8 bytes into the holding registers with auto-increment. 8. 9. 10. 11. 12. 13. 14. 15. 16. Set the EECON1 register for the write operation by doing the following: * Set the EEPGD bit to point to program memory * Clear the CFGS bit to access program memory * Set the WREN bit to enable byte writes Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for the duration of the write (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Repeat Steps 6-14 seven times to write 64 bytes. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 8-3. DS39616D-page 92 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT,W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data and increment FSR0 done? repeat MODIFY_WORD ; point to buffer ; update buffer word and increment FSR0 ; update buffer word ERASE_BLOCK MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BCF EECON1, CFGS BSF EECON1, EEPGD BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE WRITE_BUFFER_BACK MOVLW 8 MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 MOVWF COUNTER WRITE_WORD_TO_HREGS MOVF POSTINC0,F MOVWF TABLAT TBLWT+* DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS 2010 Microchip Technology Inc. ; load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 ; ; ; ; ; ; ; point to PROG/EEPROM memory point to Flash program memory enable write to memory enable Row Erase operation disable interrupts Required sequence write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer ; number of bytes in holding register ; ; ; ; ; ; get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR loop until buffers are full DS39616D-page 93 PIC18F2331/2431/4331/4431 EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ GOTO BCF 8.5.2 INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR ; disable interrupts ; required sequence ; write 55h INTCON, GIE COUNTER_HI PROGRAM_LOOP EECON1, WREN ; re-enable interrupts ; loop until done ; write 0AAh ; start program (CPU stall) ; disable write to memory WRITE VERIFY reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 8.5.3 8.6 UNEXPECTED TERMINATION OF WRITE OPERATION See Section 23.5 "Program Verification and Code Protection" for details on code protection of Flash program memory. If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and TABLE 8-2: Flash Program Operation During Code Protection REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 TBLPTRU -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Reset Values on Page: 54 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 54 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 54 TABLAT Program Memory Table Latch 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EECON2 EEPROM Control Register 2 (not a physical register) 54 56 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 56 IPR2 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP 57 PIR2 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF 57 PIE2 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE 57 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. DS39616D-page 94 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction 9.2 Example 9-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Example 9-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms, and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. EXAMPLE 9-1: MOVF MULWF A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1. TABLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE ARG1, W ARG2 EXAMPLE 9-2: ; ; ARG1 * ARG2 -> ; PRODH:PRODL 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 PERFORMANCE COMPARISON Routine 8 x 8 Unsigned 8 x 8 Signed 16 x 16 Unsigned 16 x 16 Signed Operation Program Memory (Words) Cycles (Max) Without Hardware Multiply 13 Hardware Multiply 1 Without Hardware Multiply 33 Hardware Multiply 6 Without Hardware Multiply Hardware Multiply Without Hardware Multiply Hardware Multiply Multiply Method 2010 Microchip Technology Inc. Time @ 40 MHz @ 10 MHz @ 4 MHz 69 6.9 s 27.6 s 69 s 1 100 ns 400 ns 1 s 91 9.1 s 36.4 s 91 s 6 600 ns 2.4 s 6 s 21 242 24.2 s 96.8 s 242 s 24 24 2.4 s 9.6 s 24 s 52 254 25.4 s 102.6 s 254 s 36 36 3.6 s 14.4 s 36 s DS39616D-page 95 PIC18F2331/2431/4331/4431 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES<3:0>. EQUATION 9-1: RES<3:0> = = 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) EXAMPLE 9-3: EQUATION 9-2: RES<3:0> = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L)+ (-1 ARG2H<7> ARG1H:ARG1L 216) + (-1 ARG1H<7> ARG2H:ARG2L 216) EXAMPLE 9-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; MOVF MULWF 16 x 16 SIGNED MULTIPLY ROUTINE ARG1L, W ARG2L MOVFF MOVFF ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; MOVF MULWF ARG1H, W ARG2H ; MOVFF MOVFF ; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; MOVF MULWF ARG1L,W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers, RES<3:0>. To account for the sign bits of the arguments, each argument pair's Most Significant bit (MSb) is tested and the appropriate subtractions are done. DS39616D-page 96 Add cross products ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.0 INTERRUPTS The PIC18F2331/2431/4331/4431 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The highpriority interrupt vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority (most interrupt sources have priority bits) The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a lowpriority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the Interrupt Control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39616D-page 97 PIC18F2331/2431/4331/4431 FIGURE 10-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Power-Managed Mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP TXIF TXIE TXIP GIE/GIEH ADIF ADIE ADIP IPEN IPEN PEIE/GIEL RCIF RCIE RCIP IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Interrupt to CPU Vector to Location 0018h PEIE/GIEL INT0IF INT0IE INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS39616D-page 98 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all high-priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt for RB<7:4> pins 0 = Disables the RB port change interrupt for RB<7:4> pins bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state 2010 Microchip Technology Inc. DS39616D-page 99 PIC18F2331/2431/4331/4431 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as `0' bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as `0' bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39616D-page 100 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as `0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as `0' bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. DS39616D-page 101 PIC18F2331/2431/4331/4431 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) Registers (PIR1, PIR2 and PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow DS39616D-page 102 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6-5 Unimplemented: Read as `0' bit 4 EEIF: EEPROM or Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 Unimplemented: Read as `0' bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software) 0 = The supply voltage is greater than the specified LVD voltage bit 1 Unimplemented: Read as `0' bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Not used in this mode. 2010 Microchip Technology Inc. DS39616D-page 103 PIC18F2331/2431/4331/4431 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- PTIF IC3DRIF IC2QEIF IC1IF TMR5IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in the PTPER registers. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software. 0 = PWM time base has not matched the value in the PTPER registers bit 3 IC3DRIF: IC3 Interrupt Flag/Direction Change Interrupt Flag bit IC3 Enabled (CAP3CON<3:0>): 1 = TMR5 value was captured by the active edge on CAP3 input (must be cleared in software) 0 = TMR5 capture has not occurred QEI Enabled (QEIM<2:0>): 1 = Direction of rotation has changed (must be cleared in software) 0 = Direction of rotation has not changed bit 2 IC2QEIF: IC2 Interrupt Flag/QEI Interrupt Flag bit IC2 Enabled (CAP2CON<3:0>): 1 = TMR5 value was captured by the active edge on CAP2 input (must be cleared in software) 0 = TMR5 capture has not occurred QEI Enabled (QEIM<2:0>): 1 = The QEI position counter has reached the MAXCNT value, or the index pulse, INDX, has been detected. Depends on the QEI operating mode enabled. Must be cleared in software. 0 = The QEI position counter has not reached the MAXCNT value or the index pulse has not been detected bit 1 IC1 Enabled (CAP1CON<3:0>): 1 = TMR5 value was captured by the active edge on CAP1 input (must be cleared in software) 0 = TMR5 capture has not occurred QEI Enabled (QEIM<2:0>), Velocity Measurement Mode Enabled (VELM = 0 in QEICON register): 1 = Timer5 value was captured by the active velocity edge (based on PHA or PHB input). CAP1REN bit must be set in CAP1CON register. IC1IF must be cleared in software. 0 = Timer5 value was not captured by the active velocity edge bit 0 TMR5IF: Timer5 Interrupt Flag bit 1 = Timer5 time base matched the PR5 value (must be cleared in software) 0 = Timer5 time base did not match the PR5 value DS39616D-page 104 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable Registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. x = Bit is unknown DS39616D-page 105 PIC18F2331/2431/4331/4431 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as `0' bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as `0' bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 Unimplemented: Read as `0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39616D-page 106 x = Bit is unknown 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- PTIE IC3DRIE IC2QEIE IC1IE TMR5IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PTIF enabled 0 = PTIF disabled bit 3 IC3DRIE: IC3 Interrupt Enable/Direction Change Interrupt Enable bit IC3 Enabled (CAP3CON<3:0>): 1 = IC3 interrupt enabled 0 = IC3 interrupt disabled QEI Enabled (QEIM<2:0>): 1 = Change of direction interrupt enabled 0 = Change of direction interrupt disabled bit 2 IC2QEIE: IC2 Interrupt Flag/QEI Interrupt Flag Enable bit IC2 Enabled (CAP2CON<3:0>): 1 = IC2 interrupt enabled) 0 = IC2 interrupt disabled QEI Enabled (QEIM<2:0>): 1 = QEI interrupt enabled 0 = QEI interrupt disabled bit 1 IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled 2010 Microchip Technology Inc. x = Bit is unknown DS39616D-page 107 PIC18F2331/2431/4331/4431 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- ADIP RCIP TXIP SSPIP CCPIP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART Transmit Interrupt Priority bit x = Bit is unknown 1 = High priority 0 = Low priority bit 3 SSP1IP: Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39616D-page 108 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 U-0 R/W-1 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as `0' bit 4 EEIP: Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as `0' bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as `0' bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. x = Bit is unknown DS39616D-page 109 PIC18F2331/2431/4331/4431 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- -- PTIP IC3DRIP IC2QEIP IC1IP TMR5IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 IC3DRIP: IC3 Interrupt Priority/Direction Change Interrupt Priority bit IC3 Enabled (CAP3CON<3:0>): 1 = IC3 interrupt high priority 0 = IC3 interrupt low priority QEI Enabled (QEIM<2:0>): 1 = Change of direction interrupt high priority 0 = Change of direction interrupt low priority bit 2 IC2QEIP: IC2 Interrupt Priority/QEI Interrupt Priority bit IC2 Enabled (CAP2CON<3:0>): 1 = IC2 interrupt high priority 0 = IC2 interrupt low priority QEI Enabled (QEIM<2:0>): 1 = High priority 0 = Low priority bit 1 IC1IP: IC1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR5IP: Timer5 Interrupt Priority bit 1 = High priority 0 = Low priority DS39616D-page 110 x = Bit is unknown 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from a powermanaged mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register 5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2010 Microchip Technology Inc. x = Bit is unknown DS39616D-page 111 PIC18F2331/2431/4331/4431 10.6 INTx Pin Interrupts 10.7 External interrupts on the INT0, INT1 and INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Before re-enabling the interrupt, the flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from the Idle or Sleep modes if bit, INTxIE, was set prior to going into those modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. EXAMPLE 10-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit, TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h) in the TMR0H:TMR0L registers will set flag bit, TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 12.0 "Timer0 Module" for further details. 10.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 10.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 6.1.3 "Fast Register Stack"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS DS39616D-page 112 ; Restore BSR ; Restore WREG ; Restore STATUS 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Data Latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 11-1. FIGURE 11-1: GENERIC I/O PORT OPERATION RD LAT Data Bus D WR LAT or PORT Q I/O Pin(1) CK Data Latch D WR TRIS PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA<4:2> pins are multiplexed with three input capture pins and Quadrature Encoder Interface pins. Pins, RA6 and RA7, are multiplexed with the main oscillator pins. They are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 23.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins RA<3:0> and RA5 as A/D Converter inputs is selected by clearing/setting the control bits in the ANSEL0 and ANSEL1 registers. Note 1: On a Power-on Reset, RA<5:0> are configured as analog inputs and read as `0'. Q 2: RA5 I/F is available only on 40-pin devices (PIC18F4331/4431). CK TRIS Latch Input Buffer RD TRIS Q D ENEN The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 11-1: CLRF RD PORT CLRF Note 1: PORTA, TRISA and LATA Registers I/O pins have diode protection to VDD and VSS. MOVLW MOVWF MOVLW MOVWF 2010 Microchip Technology Inc. PORTA ; ; ; LATA ; ; ; 0x3F ; ANSEL0 ; 0xCF ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs DS39616D-page 113 PIC18F2331/2431/4331/4431 TABLE 11-1: PORTA I/O SUMMARY Pin RA0/AN0 RA1/AN1 RA2/AN2/VREF-/ CAP1/INDX RA3/AN3/VREF+/ CAP2/QEA RA4/AN4/CAP3/ QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Legend: Function TRIS Setting I/O I/O Type RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2 0 O DIG LATA<2> data output; not affected by analog input. Description LATA<0> data output; not affected by analog input. 1 I TTL PORTA<2> data input. Disabled when analog input is enabled. AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR. A/D voltage reference low input. VREF- 1 I ANA CAP1 1 I ST Input Capture Pin 1. Disabled when analog input is enabled. INDX 1 I ST Quadrature Encoder Interface index input pin. Disabled when analog input is enabled. RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D voltage reference high input. CAP2 1 I ST Input Capture Pin 2. Disabled when analog input is enabled. QEA 1 I ST Quadrature Encoder Interface Channel A input pin. Disabled when analog input is enabled. RA4 0 O DIG LATA<4> data output; not affected by analog input. 1 I ST AN4 1 I ANA PORTA<4> data input; disabled when analog input is enabled. CAP3 1 I ST Input Capture Pin 3. Disabled when analog input is enabled. QEB 1 I ST Quadrature Encoder Interface Channel B input pin. Disabled when analog input is enabled. RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input is enabled. A/D Input Channel 4. Default input configuration on POR. AN5 1 I ANA A/D Input Channel 5. Default configuration on POR. LVDIN 1 I ANA Low-Voltage Detect external trip point input. OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). DS39616D-page 114 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 11-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 57 (1) (1) LATA LATA7 LATA6 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register LATA Data Output Register 57 57 ADCON1 VCFG1 VCFG0 -- FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 56 ANSEL0 ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 56 ANSEL1 -- -- -- -- -- -- -- ANS8(2) 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. 2: ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. 2010 Microchip Technology Inc. DS39616D-page 115 PIC18F2331/2431/4331/4431 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 11-2: CLRF PORTB CLRF LATB MOVLW 0xCF MOVWF TRISB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. DS39616D-page 116 Four of the PORTB pins (RB<7:4>) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB<7:4>) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are ORed together to generate the RB port change interrupt with flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) c) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). NOP (or any 1 TCY delay). Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB and waiting 1 TCY will end the mismatch condition and allow flag bit, RBIF, to be cleared. Also, if the port pin returns to its original state, the mismatch condition will be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB<3:0> and RB4 pins are multiplexed with the 14-bit PWM module for PWM<3:0> and PWM5 output. The RB5 pin can be configured by the Configuration bit, PWM4MX, as the alternate pin for PWM4 output. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 11-3: Pin RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB0 0 O DIG LATB<0> data output; not affected by analog input. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. PWM0 0 O DIG PWM Output 0. RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. PWM1 0 O DIG PWM Output 1. RB2 0 O DIG LATB<2> data output; not affected by analog input. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. PWM2 0 O DIG PWM Output 2. RB3 0 O DIG LATB<3> data output; not affected by analog input. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. PWM3 0 O DIG PWM Output 3. RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. 1 I TTL Interrupt-on-change pin. KBI0 RB5/KBI1/ PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: 2: 3: Description PWM5 0 O DIG PWM Output 5. RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-change pin. PWM4(3) 0 O DIG PWM Output 4; takes priority over port data. PGM(2) x I ST Single-Supply Programming mode entry (ICSPTM). Enabled by LVP Configuration bit; all other pin functions are disabled. RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-change pin. PGC x I ST Serial execution (ICSPTM) clock input for ICSP and ICD operation.(1) RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(1) x I ST Serial execution data input for ICSP and ICD operation.(1) DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). All other pin functions are disabled when ICSP or ICD is enabled. Single-Supply Programming must be enabled. RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. DS39616D-page 117 PIC18F2331/2431/4331/4431 TABLE 11-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 57 LATB LATB Data Output Register 57 TRISB PORTB Data Direction Register 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP -- Legend: RBIE TMR0IF INT0IF RBIF 54 INTEDG2 -- TMR0IP -- RBIP 54 INT2IE INT1IE -- INT2IF INT1IF 54 -- = unimplemented, read as `0'. Shaded cells are not used by PORTB. DS39616D-page 118 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 11-5). The pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. External interrupts, IN0, INT1 and INT2, are placed on RC3, RC4 and RC5 pins, respectively. SSP alternate interface pins, SDI/SDA, SCK/SCL and SDO are placed on RC4, RC5 and RC7 pins, respectively. These pins are multiplexed on PORTC and PORTD by using the SSPMX bit in the CONFIG3L register. EUSART pins RX/DT and TX/CK are placed on RC7 and RC6 pins, respectively. The alternate Timer5 external clock input, T5CKI, and the alternate TMR0 external clock input, T0CKI, are placed on RC3 and are multiplexed with the PORTD (RD0) pin using the EXCLKMX Configuration bit in CONFIG3H. Fault inputs to the 14-bit PWM module, FLTA and FLTB, are located on RC1 and RC2. FLTA input on RC1 is multiplexed with RD4 using the FLTAMX bit. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: Note: On a Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. 2010 Microchip Technology Inc. CLRF PORTC CLRF LATC MOVLW 0xCF MOVWF TRISC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs DS39616D-page 119 PIC18F2331/2431/4331/4431 TABLE 11-5: Pin PORTC I/O SUMMARY Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST x O ANA RC0/T1OSO/ T1CKI T1OSO RC1/T1OSI/ CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/ T5CKI/INT0 RC4/INT1/SDI/ SDA 1 I ST Timer1/Timer3 counter input. 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. CCP2 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. FLTA 1 I ST Fault Interrupt Input Pin A. RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG CCP1 compare or PWM output; takes priority over port data. 1 I ST CCP1 capture input. FLTB 1 I ST Fault Interrupt Input Pin B. RC3 0 O DIG LATC<3> data output. Note 1: PORTC<1> data input. 1 I ST PORTC<3> data input. T0CKI(1) 1 I ST Timer0 alternate clock input. T5CKI(1) 1 I ST Timer5 alternate clock input. INT0 1 I ST External Interrupt 0. RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. INT1 1 I ST External Interrupt 1. SDI(1) 1 I ST SPI data input (SSP module). (1) 0 O DIG I2CTM data output (SSP module); takes priority over port data. 1 I 2 I C I2C data input (SSP module). 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. External Interrupt 2. RC5 INT2 1 I ST SCK(1) 0 O DIG SPI clock output (SSP module); takes priority over port data. 1 I ST SPI clock input (SSP module). 0 O DIG I2C clock output (SSP module); takes priority over port data. 1 I I2C I2C clock input (SSP module); input type depends on module setting. 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 0 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as an output. CK 0 O DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 I ST Synchronous serial clock input (EUSART module). 1 I ST SPI slave select input. RC6 SS Legend: PORTC<0> data input. Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. RC1 SCL(1) RC6/TX/CK/SS LATC<0> data output. T1CKI SDA RC5/INT2/SCK/ SCL Description DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). RD0 is the alternate pin for T0CKI/T5CKI; RD2 is the alternate pin for SDI/SDA; RD3 is the alternate pin for SCK/SCL; RD1 is the alternate pin for SDO. DS39616D-page 120 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 11-5: PORTC I/O SUMMARY (CONTINUED) Pin Function TRIS Setting I/O I/O Type RC7/RX/DT/SDO RC7 0 O DIG 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (EUSART module). DT 0 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. 0 O DIG SPI data out; takes priority over port data. SDO(1) Legend: Note 1: Description LATC<7> data output. DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). RD0 is the alternate pin for T0CKI/T5CKI; RD2 is the alternate pin for SDI/SDA; RD3 is the alternate pin for SCK/SCL; RD1 is the alternate pin for SDO. TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 57 LATC LATC Data Output Register 57 TRISC PORTC Data Direction Register 57 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP TMR0IE INT0IE INTEDG1 INTEDG2 -- INT2IE RBIE TMR0IF -- TMR0IP INT1IE -- INT0IF RBIF 54 -- RBIP 54 INT2IF INT1IF 54 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. DS39616D-page 121 PIC18F2331/2431/4331/4431 11.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4331/ 4431 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39616D-page 122 PORTD includes PWM<7:6> complementary fourth channel PWM outputs. PWM4 is the complementary output of PWM5 (the third channel), which is multiplexed with the RB5 pin. This output can be used as the alternate output using the PWM4MX Configuration bit in CONFIG3H when the Single-Supply Programming pin (PGM) is used on RB5. RD1, RD2 and RD3 can be used as the alternate output for SDO, SDI/SDA and SCK/SCL using the SSPMX Configuration bit in CONFIG3H. RD4 an be used as the alternate output for FLTA using the FLTAMX Configuration bit in CONFIG3H. EXAMPLE 11-4: CLRF PORTD CLRF LATD MOVLW 0xCF MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 11-7: Pin PORTD I/O SUMMARY Function TRIS Setting I/O I/O Type RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. T0CKI(1) 1 I ST Timer0 alternate clock input. T5CKI(1) 1 I ST Timer5 alternate clock input. RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. SDO(1) 0 O DIG SPI data out; takes priority over port data. RD2 0 O DIG LATD<2> data output. RD0/T0CKI/ T5CKI RD1/SDO RD2/SDI/SDA 1 I ST PORTD<2> data input. SDI(1) 1 I ST SPI data input (SSP module). SDA(1) 0 O DIG I2CTM data output (SSP module); takes priority over port data. 1 I 2 I C I2C data input (SSP module). 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. 0 O DIG SPI clock output (SSP module); takes priority over port data. 1 I ST SPI clock input (SSP module). 0 O DIG I2C clock output (SSP module); takes priority over port data. 1 I 2 I C I2C clock input (SSP module); input type depends on module setting. RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. FLTA(2) 1 I ST Fault Interrupt Input Pin A. RD5 0 O DIG LATD<5> data output. RD3/SCK/SCL RD3 SCK(1) SCL RD4/FLTA RD5/PWM4 (1) 1 I ST PORTD<5> data input. PWM4(3) 0 O DIG PWM Output 4; takes priority over port data. RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PWM6 0 O DIG PWM Output 6; takes priority over port data. RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. 0 O DIG PWM Output 7; takes priority over port data. RD6/PWM6 RD7/PWM7 PWM7 Legend: Note 1: 2: 3: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL; RC7 is the alternate pin for SDO. RC1 is the alternate pin for FLTA. RB5 is the alternate pin for PWM4. TABLE 11-8: Name PORTD Description SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 57 LATD LATD Data Output Register 57 TRISD PORTD Data Direction Register 57 2010 Microchip Technology Inc. DS39616D-page 123 PIC18F2331/2431/4331/4431 11.5 PORTE, TRISE and LATE Registers Note: PORTE is only available on PIC18F4331/ 4431 devices. PORTE is a 4-bit wide, bidirectional port. Three pins (RE0/AN6, RE1/AN7 and RE2/AN8) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE<2:0> are configured as analog inputs. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin available for PIC18F4331/4431 devices. Its operation is controlled by the MCLRE Configuration bit REGISTER 11-1: in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input-only pin. As such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's master clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. EXAMPLE 11-5: CLRF PORTE CLRF LATE MOVLW MOVWF BCF MOVLW 0x3F ANSEL0 ANSEL1, 0 0x03 MOVWF TRISE 11.5.1 INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as input RE<1> as output RE<2> as input PORTE IN 28-PIN DEVICES For PIC18F2331/2431 devices, PORTE is not available. It is only available for PIC18F4331/4431 devices. TRISE REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 -- -- -- -- -- TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39616D-page 124 x = Bit is unknown 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 11-9: PORTE I/O SUMMARY Pin Function TRIS Setting I/O I/O Type RE0 0 O DIG 1 I ST AN6 1 I ANA A/D Input Channel 6. Default input configuration on POR. RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST AN7 1 I ANA A/D Input Channel 7. Default input configuration on POR. RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input is enabled. RE0/AN6 RE1/AN7 RE2/AN8 MCLR/VPP/RE3(1) Legend: Note 1: 2: AN8 1 I ANA MCLR -- I ST VPP -- I ANA RE3 --(2) I ST Description LATE<0> data output; not affected by analog input. PORTE<0> data input; disabled when analog input is enabled. PORTE<1> data input; disabled when analog input is enabled. A/D Input Channel 8. Default input configuration on POR. External Master Clear input; enabled when MCLRE Configuration bit is set. High-Voltage Detection; used for ICSPTM mode entry detection. Always available, regardless of pin mode. PORTE<3> data input; enabled when MCLRE Configuration bit is clear. DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). All PORTE pins are only implemented on 40/44-pin devices. RE3 does not have a corresponding TRIS bit to control data direction. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: PORTE -- -- -- -- RE3(1) RE2 RE1 RE0 57 LATE -- -- -- -- -- LATE Data Output Register 57 TRISE -- -- -- -- -- PORTE Data Direction Register 57 ANS4 ANS3 ANS2 ANS1 ANS0 56 -- -- -- -- ANS8(2) 56 Name ANSEL0 ANSEL1 ANS7(2) ANS6(2) ANS5(2) -- -- -- Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). It is available for PIC18F4331/4431 devices only. 2: ANS5 through ANS8 are available only on PIC18F4331/4431 devices. 2010 Microchip Technology Inc. DS39616D-page 125 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 126 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.0 TIMER0 MODULE The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock REGISTER 12-1: Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 12-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T016BIT: Timer0 16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. DS39616D-page 127 PIC18F2331/2431/4331/4431 FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 Sync with Internal Clocks (2 TCY Delay) 8 3 T0PS<2:0> 8 PSA Note: Set TMR0IF on Overflow TMR0L Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: FOSC/4 TIMER0 BLOCK DIAGRAM (16-BIT MODE) 0 1 1 T0CKI pin T0SE T0CS Programmable Prescaler 0 Sync with Internal Clocks TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39616D-page 128 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.1 12.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin, RC3/T0CKI/T5CKI/INT0. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 12.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS<2:0> bits determine the prescaler assignment and prescale ratio. Clearing bit, PSA, will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x..., etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 12-1: Name The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). 12.3 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep mode, since the timer requires clock cycles, even when T0CS is set. 12.4 16-Bit Mode Timer Reads and Writes TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 12-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 TMR0L Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON SWITCHING PRESCALER ASSIGNMENT GIE/GIEH PEIE/GIEL T0CON TMR0ON T016BIT TRISA TRISA7(1) TRISA6(1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 55 55 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 T0CS T0SE PSA T0PS2 T0PS1 T0PS0 55 PORTA Data Direction Register 57 Legend: Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. 2010 Microchip Technology Inc. DS39616D-page 129 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 130 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.0 TIMER1 MODULE The Timer1 timer/counter module has the following features: * 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from CCP module Special Event Trigger * Status of system clock operation Figure 13-1 is a simplified block diagram of the Timer1 module. REGISTER 13-1: R/W-0 The Timer1 oscillator can be used as a secondary clock source in power-managed modes. When the T1RUN bit is set, the Timer1 oscillator provides the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. T1CON: TIMER1 CONTROL REGISTER R-0 RD16 Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). R/W-0 T1RUN T1CKPS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1 (External Clock): 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0 (Internal Clock): This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. DS39616D-page 131 PIC18F2331/2431/4331/4431 13.1 When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/ T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and the pins are read as `0'. The operating mode is determined by the Timer1 Clock Select bit, TMR1CS (T1CON<1>). FIGURE 13-1: Timer1 also has an internal "Reset input". This Reset can be generated by the CCP module (see Section 16.4.4 "Special Event Trigger"). TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off T1OSO/T1CKI 1 1 FOSC/4 Internal Clock T1OSI Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 T1OSCEN(1) Sleep Input TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 (CCP Special Event Trigger) Set TMR1IF on Overflow TMR1 High Byte TMR1L Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Clock Input Timer1 Oscillator 1 T1OSO/T1CKI 1 FOSC/4 Internal Clock T1OSI Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 T1OSCEN(1) Sleep Input TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 (CCP Special Event Trigger) TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39616D-page 132 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.2 Timer1 Oscillator 13.3 A crystal oscillator circuit is built in-between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 13-3. Table 13-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 13-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 27 pF The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode. During normal device operation, the oscillator draws full current. As high noise environments may cause excessive oscillator instability in Sleep mode, this option is best suited for low noise applications, where power conservation is an important design consideration. The low-power option is enabled by clearing the T1OSCMX bit (CONFIG3L<5>). By default, the option is disabled, which results in a more or less constant current draw for the Timer1 oscillator. T1OSI Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. T1OSO The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. Refer to Section 2.0 "Guidelines for Getting Started with PIC18F Microcontrollers" for additional information PIC18FXXXX XTAL 32.768 kHz C2 27 pF See the notes with Table 13-1 for additional information about capacitor selection. Note: TABLE 13-1: Osc Type LP Timer1 Oscillator Layout Considerations CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Freq 32 kHz C1 27 pF(1) C2 27 pF(1) Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 2010 Microchip Technology Inc. DS39616D-page 133 PIC18F2331/2431/4331/4431 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in Timer1 Interrupt Flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 13.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a "Special Event Trigger" (CCP1M<3:0> = 1011), this signal will reset Timer1 and start an A/D conversion if the A/D module is enabled (see Section 16.4.4 "Special Event Trigger" for more information). Note: The Special Event Triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the Period register for Timer1. 13.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. DS39616D-page 134 A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 13.7 Using Timer1 as a Real-Time Clock (RTC) Adding an external LP oscillator to Timer1 (such as the one described in Section 13.2 "Timer1 Oscillator") gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base, and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr TABLE 13-2: Name INTCON secs mins, F .59 mins mins hours, F .23 hours ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; No, done ; Reset hours to 1 .01 hours ; Done REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 IPR1 TMR1L Timer1 Register Low Byte 55 TMR1H Timer1 Register High Byte 55 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 55 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. DS39616D-page 135 PIC18F2331/2431/4331/4431 14.0 TIMER2 MODULE 14.1 The Timer2 module has the following features: * * * * * * * 8-bit Timer register (TMR2) 8-bit Period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register, shown in Register 14-1. TMR2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 14-1 is a simplified block diagram of the Timer2 module. Register 14-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2 are controlled by this register. Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS<1:0> (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt, latched in flag bit, TMR2IF (PIR1<1>). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 DS39616D-page 136 x = Bit is unknown 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.2 Timer2 Interrupt 14.3 Output of TMR2 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the SSP module operating in SPI mode. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). For additional information, see Section 19.0 "Synchronous Serial Port (SSP) Module". FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 T2OUTPS<3:0> 1:1 to 1:16 Postscaler Set TMR2IF 2 T2CKPS<1:0> TMR2/PR2 Match Reset 1:1, 1:4, 1:16 Prescaler FOSC/4 TMR2 TMR2 Output (to PWM or SSP) Comparator 8 PR2 8 8 Internal Data Bus TABLE 14-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 IPR1 TMR2 T2CON PR2 Timer2 Register -- 55 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register 55 55 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. 2010 Microchip Technology Inc. DS39616D-page 137 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 138 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.0 TIMER5 MODULE The Timer5 module implements these features: * * * * * * * * * * 16-bit timer/counter operation Synchronous and Asynchronous Counter modes Continuous Count and Single-Shot Operating modes Four programmable prescaler values (1:1 to 1:8) Interrupt generated on period match Special Event Trigger Reset function Double-buffered registers Operation during Sleep CPU wake-up from Sleep Selectable hardware Reset input with a wake-up feature REGISTER 15-1: R/W-0 T5SEN Timer5 is a general purpose timer/counter that incorporates additional features for use with the Motion Feedback Module (see Section 17.0 "Motion Feedback Module"). It may also be used as a general purpose timer or a Special Event Trigger delay timer. When used as a general purpose timer, it can be configured to generate a delayed Special Event Trigger (e.g., an ADC Special Event Trigger) using a preprogrammed period delay. Timer5 is controlled through the Timer5 Control register (T5CON), shown in Register 15-1. The timer can be enabled or disabled by setting or clearing the control bit TMR5ON (T5CON<0>). A block diagram of Timer5 is shown in Figure 15-1. T5CON: TIMER5 CONTROL REGISTER R/W-0 R/W-0 (1) T5MOD RESEN R/W-0 T5PS1 R/W-0 R/W-0 R/W-0 R/W-0 T5PS0 T5SYNC(2) TMR5CS TMR5ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 T5SEN: Timer5 Sleep Enable bit 1 = Timer5 is enabled during Sleep 0 = Timer5 is disabled during Sleep bit 6 RESEN: Special Event Trigger Reset Enable bit(1) 1 = Special Event Trigger Reset is disabled 0 = Special Event Trigger Reset is enabled bit 5 T5MOD: Timer5 Mode bit 1 = Single-Shot mode is enabled 0 = Continuous Count mode is enabled bit 4-3 T5PS<1:0>: Timer5 Input Clock Prescale Select bits 11 = 1:8 10 = 1:4 01 = 1:2 00 = 1:1 bit 2 T5SYNC: Timer5 External Clock Input Synchronization Select bit(2) When TMR5CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR5CS = 0: This bit is ignored. Timer5 uses the internal clock when TMR5CS = 0. bit 1 TMR5CS: Timer5 Clock Source Select bit 1 = External clock from the T5CKI pin 0 = Internal clock (TCY) bit 0 TMR5ON: Timer5 On bit 1 = Timer5 is enabled 0 = Timer5 is disabled Note 1: 2: x = Bit is unknown These bits are not implemented on PIC18F2331/2431 devices and read as `0'. For Timer5 to operate during Sleep mode, T5SYNC must be set. 2010 Microchip Technology Inc. DS39616D-page 139 PIC18F2331/2431/4331/4431 FIGURE 15-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) 1 Noise Filter T5CKI Internal Data Bus 1 FOSC/4 Internal Clock Synchronize Detect Prescaler 1, 2, 4, 8 0 0 2 Sleep Input Timer5 On/Off TMR5CS T5PS<1:0> T5SYNC TMR5ON 8 8 TMR5H 8 Write TMR5L Read TMR5L Special Event Trigger Input from IC1 Timer5 Reset (external) 8 TMR5 1 TMR5L Timer5 Reset 16 0 Reset Logic Comparator 16 PR5 8 PR5L Set TMR5IF Special Event Trigger Output 15.1 Special Event Logic Timer5 Operation Timer5 combines two 8-bit registers to function as a 16-bit timer. The TMR5L register is the actual low byte of the timer; it can be read and written to directly. The high byte is contained in an unmapped register; it is read and written to through TMR5H, which serves as a buffer. Each register increments from 00h to FFh. A second register pair, PR5H and PR5L, serves as the Period register; it sets the maximum count for the TMR5 register pair. When TMR5 reaches the value of PR5, the timer rolls over to 00h and sets the TMR5IF interrupt flag. A simplified block diagram of the Timer5 module is shown in Figure 2-1. Note: TMR5 High Byte PR5H 8 Timer5 supports three configurations: * 16-Bit Synchronous Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter In Synchronous Timer configuration, the timer is clocked by the internal device clock. The optional Timer5 prescaler divides the input by 2, 4, 8 or not at all (1:1). The TMR5 register pair increments on Q1. Clearing TMR5CS (= 0) selects the internal device clock as the timer sampling clock. The Timer5 may be used as a general purpose timer and as the time base resource to the Motion Feedback Module (Input Capture or Quadrature Encoder Interface). DS39616D-page 140 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 In Synchronous Counter mode configuration, the timer is clocked by the external clock (T5CKI) with the optional prescaler. The external T5CKI is selected by setting the TMR5CS bit (TMR5CS = 1); the internal clock is selected by clearing TMR5CS. The external clock is synchronized to the internal clock by clearing the T5SYNC bit. The input on T5CKI is sampled on every Q2 and Q4 of the internal clock. The low to rise transition is decoded on three adjacent samples and the Timer5 is incremented on the next Q1. The T5CKI minimum pulse-width high and low time must be greater than TCY/2. In Asynchronous Counter mode configuration, Timer5 is clocked by the external clock (T5CKI) with the optional prescaler. In this mode, T5CKI is not synchronized to the internal clock. By setting TMR5CS, the external input clock (T5CKI) can be used as the counter sampling clock. When T5SYNC is set, the external clock is not synchronized to the internal device clock. The timer count is not reset automatically when the module is disabled. The user may write the Counter register to initialize the counter. Note: 15.1.1 The Timer5 module does NOT prevent writes to the PR5 registers (PR5H:PR5L) while the timer is enabled. Writing to PR5 while the timer is enabled may result in unexpected period match events. CONTINUOUS COUNT AND SINGLE-SHOT OPERATION Timer5 has two operating modes: Continuous Count and Single-Shot. Continuous Count mode is selected by clearing the T5MOD control bit (= 0). In this mode, the Timer5 time base will start incrementing according to the prescaler settings until a TMR5/PR5 match occurs, or until TMR5 rolls over (FFFFh to 0000h). The TMR5IF interrupt flag is set, the TMR5 register is reset on the following input clock edge and the timer continues to count for as long as the TMR5ON bit remains set. Single-Shot mode is selected by setting T5MOD (= 1). In this mode, the Timer5 time base begins to increment according to the prescaler settings until a TMR5/PR5 match occurs. This causes the TMR5IF interrupt flag to be set, the TMR5 register pair to be cleared on the following input clock edge and the TMR5ON bit to be cleared by the hardware to halt the timer. 15.2 16-Bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer. Reading TMR5L will load the contents of the high byte of the register pair into the TMR5H register. This allows the user to accurately read all 16 bits of the register pair without having to determine whether a read of the high byte, followed by the low byte, is valid due to a rollover between reads. Since the actual high byte of the Timer5 register pair is not directly readable or writable, it must be read and written to through the Timer5 High Byte Buffer register (TMR5H). The T5 high byte is updated with the contents of TMR5H when a write occurs to TMR5L. This allows a user to write all 16 bits to both the high and low bytes of Timer5 at once. Writes to TMR5H do not clear the Timer5 prescaler. The prescaler is only cleared on writes to TMR5L. 15.2.1 16-BIT READ-MODIFY-WRITE Read-modify-write instructions, like BSF and BCF, will read the contents of a register, make the appropriate changes and place the result back into the register. The write portion of a read-modify-write instruction of TMR5H will not update the contents of the high byte of TMR5 until a write of TMR5L takes place. Only then will the contents of TMR5H be placed into the high byte of TMR5. 15.3 Timer5 Prescaler The Timer5 clock input (either TCY or the external clock) may be divided by using the Timer5 programmable prescaler. The prescaler control bits, T5PS<1:0> (T5CON<4:3>), select a prescale factor of 2, 4, 8 or no prescale. The Timer5 prescaler is cleared by any of the following: * A write to the Timer5 register * Disabling Timer5 (TMR5ON = 0) * A device Reset such as Master Clear, POR or BOR Note: Writing to the T5CON register does not clear the Timer5. The Timer5 time base can only start incrementing in Single-Shot mode under two conditions: 1. 2. Timer5 is enabled (TMR5ON is set), or Timer5 is disabled and a Special Event Trigger Reset is present on the Timer5 Reset input. (See Section 15.7 "Timer5 Special Event Trigger Reset Input" for additional information.) 2010 Microchip Technology Inc. DS39616D-page 141 PIC18F2331/2431/4331/4431 15.4 Noise Filter The Timer5 module includes an optional input noise filter, designed to reduce spurious signals in noisy operating environments. The filter ensures that the input is not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The noise filter is part of the input filter network associated with the Motion Feedback Module (see Section 17.0 "Motion Feedback Module"). All of the filters are controlled using the Digital Filter Control (DFLTCON) register (Register 17-3). The Timer5 filter can be individually enabled or disabled by setting or clearing the FLT4EN bit (DFLTCON<6>). It is disabled on all Brown-out Resets. For additional information, refer to Section 17.3 "Noise Filters" in the Motion Feedback Module. 15.5 Timer5 Interrupt Timer5 has the ability to generate an interrupt on a period match. When the PR5 register is loaded with a new period value (00FFh), the Timer5 time base increments until its value is equal to the value of PR5. When a match occurs, the Timer5 interrupt is generated on the rising edge of Q4; TMR5IF is set on the next TCY. 15.7.1 WAKE-UP ON IC1 EDGE The Timer5 Special Event Trigger Reset input can act as a Timer5 wake-up and a start-up pulse. Timer5 must be in Single-Shot mode and disabled (TMR5ON = 0). An active edge on the CAP1 input pin will set TMR5ON. The timer is subsequently incremented on the next following clock according to the prescaler and the Timer5 clock settings. A subsequent hardware time-out (such as TMR5/PR5 match) will clear the TMR5ON bit and stop the timer. 15.7.2 DELAYED ACTION EVENT TRIGGER An active edge on CAP1 can also be used to initiate some later action delayed by the Timer5 time base. In this case, Timer5 increments as before after being triggered. When the hardware time-out occurs, the Special Event Trigger output is generated and used to trigger another action, such as an A/D conversion. This allows a given hardware action to be referenced from a capture edge on CAP1 and delayed by the timer. The event timing for the delayed action event trigger is discussed further in Section 17.1 "Input Capture". 15.7.3 SPECIAL EVENT TRIGGER RESET WHILE TIMER5 IS INCREMENTING The interrupt latency (i.e., the time elapsed from the moment Timer5 rolls over until TMR5IF is set) will not exceed 1 TCY. When the Timer5 clock input is prescaled and a TMR5/PR5 match occurs, the interrupt will be generated on the first Q4 rising edge after TMR5 resets. In the event that a bus write to Timer5 coincides with a Special Event Trigger Reset, the bus write will always take precedence over the Special Event Trigger Reset. 15.6 When Timer5 is configured for asynchronous operation, it will continue to increment each timer clock (or prescale multiple of clocks). Executing the SLEEP instruction will either stop the timer or let the timer continue, depending on the setting of the Timer5 Sleep Enable bit, T5SEN. If T5SEN is set (= 1), the timer continues to run when the SLEEP instruction is executed and the external clock is selected (TMR5CS = 1). If T5SEN is cleared, the timer stops when a SLEEP instruction is executed, regardless of the state of the TMR5CS bit. Timer5 Special Event Trigger Output A Timer5 Special Event Trigger is generated on a TMR5/PR5 match. The Special Event Trigger is generated on the falling edge of Q3. Timer5 must be configured for either Synchronous mode (Counter or Timer) to take advantage of the Special Event Trigger feature. If Timer5 is running in Asynchronous Counter mode, the Special Event Trigger may not work and should not be used. 15.7 Timer5 Special Event Trigger Reset Input In addition to the Special Event Trigger output, Timer5 has a Special Event Trigger Reset input that may be used with Input Capture Channel 1 (IC1) of the Motion Feedback Module. To use the Special Event Trigger Reset, the Capture 1 Control register, CAP1CON, must be configured for one of the Special Event Trigger modes (CAP1M<3:0> = 1110 or 1111). The Special Event Trigger Reset can be disabled by setting the RESEN control bit (T5CON<6>). The Special Event Trigger Reset resets the Timer5 time base. This Reset occurs in either Continuous Count or Single-Shot modes. DS39616D-page 142 15.8 Operation in Sleep Mode To summarize, Timer5 will continue to increment when a SLEEP instruction is executed only if all of these bits are set: * * * * TMR5ON T5SEN TMR5CS T5SYNC 15.8.1 INTERRUPT DETECT IN SLEEP MODE When configured as described above, Timer5 will continue to increment on each rising edge on T5CKI while in Sleep mode. When a TMR5/PR5 match occurs, an interrupt is generated which can wake the part. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 15-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER5 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 IPR3 -- -- -- PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 -- -- -- PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 -- -- -- PTIF IC3DRIF IC2QEIF IC1IF TMR5IF 56 PIR3 TMR5H Timer5 Register High Byte 57 TMR5L TImer5 Register Low Byte 57 PR5H Timer5 Period Register High Byte 57 PR5L Timer5 Period Register Low Byte 57 T5SEN RESEN T5MOD T5PS1 CAP1CON -- CAP1REN -- -- DFLTCON -- FLT4EN FLT3EN FLT2EN T5CON T5PS0 T5SYNC TMR5CS TMR5ON 56 CAP1M3 CAP1M2 CAP1M1 CAP1M0 59 FLT1EN FLTCK0 59 FLTCK2 FLTCK1 Legend: -- = unimplemented. Shaded cells are not used by the Timer5 module. 2010 Microchip Technology Inc. DS39616D-page 143 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 144 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES TABLE 16-1: The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. Table 16-1 shows the timer resources required for each of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the Special Event Trigger. Therefore, operation of a CCP module is described with respect to CCP1, except where noted. 16.1 CCP1 Module 16.2 CCP MODE - TIMER RESOURCES CCP Mode Timer Resources Capture Compare PWM Timer1 Timer1 Timer2 CCP2 Module Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSBs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode; Special Event Trigger (CCPxIF bit is set) 11xx = PWM mode 2010 Microchip Technology Inc. DS39616D-page 145 PIC18F2331/2431/4331/4431 16.3 16.3.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 16.3.2 If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition. TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode to be used with the capture feature. In Asynchronous Counter mode, the capture operation may not work. FIGURE 16-1: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit, CCP1IE (PIE1<2>), clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode. 16.3.4 The event is selected by control bits, CCP1M<3:0> (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. 16.3.1 SOFTWARE INTERRUPT CCP PRESCALER There are four prescaler settings specified by bits CCP1M<3:0>. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 16-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 16-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON NEW_CAPT_PS MOVWF CCP1CON ; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF Flag bit CCPR1H Prescaler 1, 4, 16 CCPR1L TMR1 Enable CCP1 Pin and Edge Detect TMR1H TMR1L CCPR2H CCPR2L CCP1CON<3:0> Qs Set CCP2IF Flag bit Prescaler 1, 4, 16 TMR1 Enable CCP2 Pin and Edge Detect Qs DS39616D-page 146 TMR1H TMR1L CCP2CON<3:0> 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.4 16.4.2 Compare Mode TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/ CCP1 (RC1/CCP2) pin: Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. * * * * 16.4.3 is driven high is driven low toggles output (high-to-low or low-to-high) remains unchanged (interrupt only) When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). The action on the pin is based on the value of control bits, CCP1M<3:0> (CCP2M<3:0>). At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. 16.4.1 16.4.4 CCP PIN CONFIGURATION The Special Event Trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Clearing the CCPxCON register will force the RC1 or RC2 compare output latch to the default low level. This is not the PORTC I/O data latch. The Special Event Trigger output of CCP2 resets the TMR1 register pair. Additionally, the CCP2 Special Event Trigger will start an A/D conversion if the A/D module is enabled. Note: FIGURE 16-2: SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. The user must configure the CCP1 pin as an output by clearing the appropriate TRISC bit. Note: SOFTWARE INTERRUPT MODE The Special Event Trigger from the CCP2 module will not set the Timer1 interrupt flag bit. COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1, but not set Timer1 interrupt flag bit and set bit, GO/DONE (ADCON0<1>), which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag CCP1IF bit CCPR1H CCPR1L Q RC2/CCP1 Pin S R TRISC<2> Output Enable Output Logic Match Comparator CCP1CON<3:0> Mode Select TMR1H TMR1L Special Event Trigger Set Flag CCP2IF bit Q RC1/CCP2 Pin TRISC<1> Output Enable 2010 Microchip Technology Inc. S R Output Logic CCP2CON<3:0> Mode Select Match Comparator CCPR2H CCPR2L DS39616D-page 147 PIC18F2331/2431/4331/4431 TABLE 16-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 IPR1 TRISC PORTC Data Direction Register 57 TMR1L Timer1 Register Low Byte 55 TMR1H Timer1 Register High Byte 55 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 55 CCPR1L Capture/Compare/PWM Register 1 Low Byte 56 CCPR1H Capture/Compare/PWM Register 1 High Byte 56 CCP1CON -- -- DC1B1 DC1B0 CCPR2L Capture/Compare/PWM Register 2 Low Byte CCPR2H Capture/Compare/PWM Register 2 High Byte -- -- DC2B1 PIR2 OSCFIF -- PIE2 OSCFIE -- IPR2 OSCFIP -- CCP2CON CCP1M3 CCP1M2 CCP1M1 CCP1M0 56 56 56 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 56 -- EEIF -- LVDIF -- CCP2IF 57 -- EEIE -- LVDIE -- CCP2IE 57 -- EEIP -- LVDIP -- CCP2IP 57 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Capture, Compare and Timer1. DS39616D-page 148 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.5 16.5.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Note: Figure 16-3 shows a simplified block diagram of the CCP1 module in PWM mode. For a step-by-step procedure on how to set up the CCP1 module for PWM operation, see Section 16.5.3 "Setup for PWM Operation". FIGURE 16-3: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 16-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: CCP1CON<5:4> Duty Cycle Registers CCPR1L 16.5.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Comparator Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base. A PWM output (Figure 16-4) has a time base (period) and a time that the output is high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 16-4: PWM PERIOD The Timer2 postscaler (see Section 14.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation: EQUATION 16-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2010 Microchip Technology Inc. DS39616D-page 149 PIC18F2331/2431/4331/4431 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation: 16.5.3 EQUATION 16-3: 4. log FOSC FPWM PWM Resolution (max) = bits log(2) Note: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. 3. 5. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 16-4: INTCON The following steps should be taken when configuring the CCP1 module for PWM operation: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. TABLE 16-3: Name SETUP FOR PWM OPERATION REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 IPR1 TRISC PORTC Data Direction Register 57 TMR2 Timer2 Register 55 PR2 Timer2 Period Register 55 T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR1H Capture/Compare/PWM Register 1 High Byte CCP1CON -- -- DC1B1 DC1B0 55 56 56 CCP1M3 CCP1M2 CCP1M1 CCP1M0 56 CCPR2L Capture/Compare/PWM Register 2 Low Byte 56 CCPR2H Capture/Compare/PWM Register 2 High Byte 56 CCP2CON -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 56 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2. DS39616D-page 150 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.0 MOTION FEEDBACK MODULE The Motion Feedback Module (MFM) is a special purpose peripheral designed for motion feedback applications. Together with the Power Control PWM (PCPWM) module (see Section 18.0 "Power Control PWM Module"), it provides a variety of control solutions for a wide range of electric motors. The module actually consists of two hardware submodules: Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses. An overview of the available features is presented in Table 17-1. A simplified block diagram of the entire Motion Feedback Module is shown in Figure 17-1. Note: * Input Capture (IC) * Quadrature Encoder Interface (QEI) Because the same input pins are common to the IC and QEI submodules, only one of these two submodules may be used at any given time. If both modules are on, the QEI submodule will take precedence. Together with Timer5 (see Section 15.0 "Timer5 Module"), these modules provide a number of options for motion and control applications. TABLE 17-1: SUMMARY OF MOTION FEEDBACK MODULE FEATURES Submodule Mode(s) Features IC (3x) * Synchronous * Input Capture * * * * QEI QEI * * * * Velocity Measurement * 2x and 4x Update modes * Velocity Event Postscaler * Counter Overflow Flag for Low Rotation Speed * Utilizes Input Capture 1 Logic (IC1) * High and Low Velocity Support 2010 Microchip Technology Inc. Flexible Input Capture modes Available Prescaler Selectable Time Base Reset Special Event Trigger for ADC Sampling/Conversion or Optional TMR5 Reset Feature (CAP1 only) * Wake-up from Sleep function * Selectable Interrupt Frequency * Optional Noise Filter Detect Position Detect Direction of Rotation Large Bandwidth (FCY/16) Optional Noise Filter Timer TMR5 Function * 3x Input Capture (edge capture, pulse width, period measurement, capture on change) * Special Event Triggers the A/D Conversion on the CAP1 Input 16-Bit * Position Measurement Position * Direction of Rotation Status Counter TMR5 * Precise Velocity Measurement * Direction of Rotation Status DS39616D-page 151 PIC18F2331/2431/4331/4431 FIGURE 17-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Event Trigger Reset TMR5IF TMR5 Reset Control Timer Reset Special Event Trigger Output Timer5 TMR5<15:0> 8 Filter Data Bus<7:0> TCY T5CKI 3x Input Capture Logic Filter Prescaler IC3 Filter CAP2/QEA Prescaler IC2 Filter CAP1/INDX Prescaler TMR5<15:0> CAP3/QEB TCY IC3IF 8 IC2IF IC1 Clock Divider 8 IC1IF Special Event Trigger Reset 8 8 Postscaler QEB Velocity Event Timer Reset QEA 8 Direction Position Counter Clock QEIF QEI Control Logic INDX CHGIF 8 QEI Logic CHGIF IC3DRIF IC3IF QEI Mode Decoder QEIF 8 IC2QEIF IC2IF DS39616D-page 152 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.1 Input Capture The Input Capture (IC) submodule implements the following features: * Three channels of independent input capture (16-bits/channel) on the CAP1, CAP2 and CAP3 pins * Edge-Trigger, Period or Pulse-Width Measurement Operating modes for each channel * Programmable prescaler on every input capture channel * Special Event Trigger output (IC1 only) * Selectable noise filters on each capture input FIGURE 17-2: Input Channel 1 (IC1) includes a Special Event Trigger that can be configured for use in Velocity Measurement mode. Its block diagram is shown in Figure 17-2. IC2 and IC3 are similar, but lack the Special Event Trigger features or additional velocity measurement logic. A representative block diagram is shown in Figure 17-3. Please note that the time base is Timer5. INPUT CAPTURE BLOCK DIAGRAM FOR IC1 CAP1 Pin Noise Filter Prescaler 1, 4, 16 and Mode Select CAP1BUF/VELR(1) Clock 3 FLTCK<2:0> 4 CAP1M<3:0> Q Clocks IC1IF IC1_TR 1 MUX 0 Clock/ Reset/ Interrupt Decode Logic Special Event Trigger Reset Reset Control Timer5 Logic CAP1BUF_clk First Event Reset velcap(2) VELM Timer Reset Control Timer5 Reset CAP1M<3:0> CAPxREN Q Clocks Reset TMR5 Note 1: 2: CAP1BUF register is reconfigured as VELR register when QEI mode is active. QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2010 Microchip Technology Inc. DS39616D-page 153 PIC18F2331/2431/4331/4431 FIGURE 17-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 CAPxBUF(1,2,3) CAP2/3 Pin Noise Filter Prescaler 1, 4, 16 and Mode Select Capture Clock TMR5 Enable 3 FLTCK<2:0> 4 CAP1M<3:0>(1) Q Clocks TMR5 ICxIF(1) Capture Clock/ Reset/ Interrupt Decode Logic Q Clocks CAPxBUF_clk(1) Reset Timer Reset Control TMR5 Reset CAPxM<3:0>(1) CAPxREN(2) Note 1: IC2 and IC3 are denoted as x = 2 and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active. 3: CAP3BUF is enabled as MAXCNT when QEI mode is active. DS39616D-page 154 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The three input capture channels are controlled through the Input Capture Control registers, CAP1CON, CAP2CON and CAP3CON. Each channel is configured independently with its dedicated register. The implementation of the registers is identical except for the Special Event Trigger (see Section 17.1.8 "Special Event Trigger (CAP1 Only)"). The typical Capture Control register is shown in Register 17-1. REGISTER 17-1: Note: Throughout this section, references to registers and bit names that may be associated with a specific capture channel will be referred to generically by the use of the term `x' in place of the channel number. For example, `CAPxREN' may refer to the Capture Reset Enable bit in CAP1CON, CAP2CON or CAP3CON. CAPxCON: INPUT CAPTURE x CONTROL REGISTER U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CAPxREN -- -- CAPxM3 CAPxM2 CAPxM1 CAPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 CAPxREN: Time Base Reset Enable bit 1 = Enabled 0 = Disable selected time base Reset on capture bit 5-4 Unimplemented: Read as `0' bit 3-0 CAPxM<3:0>: Input Capture x (ICx) Mode Select bits 1111 = Special Event Trigger mode; the trigger occurs on every rising edge on CAP1 input(1) 1110 = Special Event Trigger mode; the trigger occurs on every falling edge on CAP1 input(1) 1101 = Unused 1100 = Unused 1011 = Unused 1010 = Unused 1001 = Unused 1000 = Capture on every CAPx input state change 0111 = Pulse-Width Measurement mode, every rising to falling edge 0110 = Pulse-Width Measurement mode, every falling to rising edge 0101 = Frequency Measurement mode, every rising edge 0100 = Capture mode, every 16th rising edge 0011 = Capture mode, every 4th rising edge 0010 = Capture mode, every rising edge 0001 = Capture mode, every falling edge 0000 = Input Capture x (ICx) off Note 1: Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. 2010 Microchip Technology Inc. DS39616D-page 155 PIC18F2331/2431/4331/4431 When in Counter mode, the counter must be configured as the synchronous counter only (T5SYNC = 0). When configured in Asynchronous mode, the IC module will not work properly. Note 1: Input capture prescalers are reset (cleared) when the input capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is changed, without first disabling the module and entering the new Input Capture mode, a false interrupt (or Special Event Trigger on IC1) may be generated. The user should either: (1) disable the input capture before entering another mode, or (2) disable IC interrupts to avoid false interrupts during IC mode changes. 17.1.1 EDGE CAPTURE MODE In this mode, the value of the time base is captured either on every rising edge, every falling edge, every 4th rising edge, or every 16th rising edge. The edge present on the input capture pin (CAP1, CAP2 or CAP3) is sampled by the synchronizing latch. The signal is used to load the Input Capture Buffer (ICxBUF register) on the following Q1 clock (see Figure 17-4). Consequently, Timer5 is either reset to `0' (Q1 immediately following the capture event) or left free running, depending on the setting of the Capture Reset Enable bit, CAPxREN, in the CAPxCON register. On the first capture edge following the setting of the Input Capture mode (i.e., MOVWF CAP1CON), Timer5 contents are always captured into the corresponding Input Capture Buffer (i.e., CAPxBUF). Timer5 can optionally be reset; however, this is dependent on the setting of the Capture Reset Enable bit, CAPxREN (see Figure 17-4). Note: 3: During IC mode changes, the prescaler count will not be cleared, therefore, the first capture in the new IC mode may be from the non-zero prescaler. FIGURE 17-4: EDGE CAPTURE MODE TIMING Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC 0012 TMR5(1) 0013 0014 0015 0000 0001 0002 0000 0001 0002 CAP1 Pin(2) ABCD CAP1BUF(3) 0016 0003 Note 5 TMR5 Reset(4) Instruction Execution Note 1: MOVWF CAP1CON 0002 BCF CAP1CON, CAP1REN TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on the Q1 rising edge. 2: IC1 is configured in Edge Capture mode (CAP1M<3:0> = 0010) with the time base reset upon edge capture (CAP1REN = 1) and no noise filter. 3: TMR5 value is latched by CAP1BUF on TCY. In the event that a write to TMR5 coincides with an input capture event, the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated with the incremented value of the time base on the next TCY clock edge when the capture event takes place (see Note 4 when Reset occurs). 4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used with the input capture, it is active immediately after the time base value is captured. 5: TMR5 Reset pulse is disabled by clearing the CAP1REN bit (e.g., BCF CAP1CON, CAP1REN). DS39616D-page 156 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.1.2 PERIOD MEASUREMENT MODE The Period Measurement mode is selected by setting CAPxM<3:0> = 0101. In this mode, the value of Timer5 is latched into the CAPxBUF register on the rising edge of the input capture trigger and Timer5 is subsequently reset to 0000h (optional by setting CAPxREN = 1) on the next TCY (see capture and Reset relationship in Figure 17-4). 17.1.3 Timer5 is always reset on the edge when the measurement is first initiated. For example, when the measurement is based on the falling to rising edge, Timer5 is first reset on the falling edge, and thereafter, the timer value is captured on the rising edge. Upon entry into the Pulse-Width Measurement mode, the very first edge detected on the CAPx pin is always captured. The TMR5 value is reset on the first active edge (see Figure 17-5). PULSE-WIDTH MEASUREMENT MODE The Pulse-Width Measurement mode can be configured for two different edge sequences, such that the pulse width is based on either the falling to rising edge of the CAPx input pin (CAPxM<3:0> = 0110), or on the rising to falling edge (CAPxM<3:0> = 0111). FIGURE 17-5: PULSE-WIDTH MEASUREMENT MODE TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0012 TMR5(1) 0013 0014 0015 0000 0001 0002 0000 0001 0002 CAP1 Pin(2) CAP1BUF(3) 0015 0001 0002 TMR5 Reset(4,5) Instruction Execution(2) Note 1: MOVWF CAP1CON TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on every Q1 rising edge. 2: IC1 is configured in Pulse-Width Measurement mode (CAP1M<3:0> = 0111, rising to falling pulse-width measurement). No noise filter on CAP1 input is used. The MOVWF instruction loads CAP1CON when W = 0111. 3: TMR5 value is latched by CAP1BUF on TCY rising edge. In the event that a write to TMR5 coincides with an input capture event, the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated with the incremented value of the time base on the next TCY clock edge when the capture event takes place (see Note 4 when Reset occurs). 4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used in Pulse-Width Measurement mode, it is always present on the edge that first initiates the pulse-width measurement (i.e., when configured in the rising to falling Pulse-Width Measurement mode); it is active on each rising edge detected. In the falling to rising Pulse-Width Measurement mode, it is active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. The CAP1REN bit has no bearing in this mode. 2010 Microchip Technology Inc. DS39616D-page 157 PIC18F2331/2431/4331/4431 17.1.3.1 Pulse-Width Measurement Timing 17.1.4 Pulse-width measurement accuracy can only be ensured when the pulse-width high and low present on the CAPx input exceeds one TCY clock cycle. The limitations depend on the mode selected: INPUT CAPTURE ON STATE CHANGE When CAPxM<3:0> = 1000, the value is captured on every signal change on the CAPx input. If all three capture channels are configured in this mode, the three input captures can be used as the Hall effect sensor state transition detector. The value of Timer5 can be captured, Timer5 reset and the interrupt generated. Any change on CAP1, CAP2 or CAP3 is detected and the associated time base count is captured. * When CAPxM<3:0> = 0110 (rising to falling edge delay), the CAPx input high pulse width (TCCH) must exceed TCY + 10 ns. * When CAPxM<3:0> = 0111 (falling to rising edge delay), the CAPx input low pulse width (TCCL) must exceed TCY + 10 ns. For position and velocity measurement in this mode, the timer can be optionally reset (see Section 17.1.6 "Timer5 Reset" for Reset options). Note 1: The Period Measurement mode will produce valid results upon sampling of the second rising edge of the input capture. CAPxBUF values latched during the first active edge after initialization are invalid. 2: The Pulse-Width Measurement mode will latch the value of the timer upon sampling of the first input signal edge by the input capture. State 2 State 3 State 4 State 5 State 6 INPUT CAPTURE ON STATE CHANGE (HALL EFFECT SENSOR MODE) State 1 FIGURE 17-6: CAP1 1 1 1 0 0 0 CAP2 0 0 1 1 1 0 1 0 0 0 1 1 CAP3 0FFFh Time Base(1) 0000h CAP1BUF(2) CAP2BUF(2) CAP3BUF(2) Time Base Reset(1) Note 1: TMR5 can be selected as the time base for input capture. The time base can be optionally reset when the Capture Reset Enable bit is set (CAPxREN = 1). 2: Detailed CAPxBUF event timing (all modes reflect the same capture and Reset timing) is shown in Figure 17-4. There are six commutation BLDC Hall effect sensor states shown. The other two remaining states (i.e., 000h and 111h) are invalid in the normal operation. They remain to be decoded by the CPU firmware in BLDC motor application. DS39616D-page 158 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.1.5 ENTERING INPUT CAPTURE MODE AND CAPTURE TIMING 17.1.6 Every input capture trigger can optionally reset (TMR5). The Capture Reset Enable bit, CAPxREN, gates the automatic Reset of the time base of the capture event with this enable Reset signal. All capture events reset the selected timer when CAPxREN is set. Resets are disabled when CAPxREN is cleared (see Figure 17-4, Figure 17-5 and Figure 17-6). The following is a summary of functional operation upon entering any of the Input Capture modes: 1. 2. After the module is configured for one of the Capture modes by setting the Capture Mode Select bits (CAPxM<3:0>), the first detected edge captures the Timer5 value and stores it in the CAPxBUF register. The timer is then reset (depending on the setting of CAPxREN bit) and starts to increment according to its settings (see Figure 17-4, Figure 17-5 and Figure 17-6). On all edges, the capture logic performs the following: a) Input Capture mode is decoded and the active edge is identified. b) The CAPxREN bit is checked to determine whether Timer5 is reset or not. c) On every active edge, the Timer5 value is recorded in the Input Capture Buffer (CAPxBUF). d) Reset Timer5 after capturing the value of the timer when the CAPxREN bit is enabled. Timer5 is reset on every active capture edge in this case. e) On all continuing capture edge events, repeat steps (a) through (d) until the operational mode is terminated, either by user firmware, POR or BOR. f) The timer value is not affected when switching into and out of various Input Capture modes. FIGURE 17-7: TIMER5 RESET Note: 17.1.7 The CAPxREN bit has no effect in Pulse-Width Measurement mode. IC INTERRUPTS There are four operating modes for which the IC module can generate an interrupt and set one of the Interrupt Capture Flag bits (IC1IF, IC2QEIF or IC3DRIF). The interrupt flag that is set depends on the channel in which the event occurs. The modes are: * Edge Capture (CAPxM<3:0> = 0001, 0010, 0011 or 0100) * Period Measurement Event (CAPxM<3:0> = 0101) * Pulse-Width Measurement Event (CAPxM<3:0> = 0110 or 0111) * State Change Event (CAPxM<3:0> = 1000) Note: The Special Event Trigger is generated only in the Special Event Trigger mode on the CAP1 input (CAP1M<3:0> = 1110 and 1111). IC1IF interrupt is not set in this mode. The timing of interrupt and Special Event Trigger events is shown in Figure 17-7. Any active edge is detected on the rising edge of Q2 and propagated on the rising edge of Q4 rising edge. If an active edge happens to occur any later than this (on the falling edge of Q2, for example), then it will be recognized on the next Q2 rising edge. CAPx INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC CAP1 Pin IC1IF TMR5 Reset TMR5 XXXX 0000 0001 TMR5ON(1) Note 1: Timer5 is only reset and enabled (assuming TMR5ON = 0 and T5MOD = 1) when the Special Event Trigger Reset is enabled for the Timer5 Reset input. The TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the event capture. With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). 2010 Microchip Technology Inc. DS39616D-page 159 PIC18F2331/2431/4331/4431 17.1.8 SPECIAL EVENT TRIGGER (CAP1 ONLY) 17.1.9 The Special Event Trigger mode of IC1 (CAP1M<3:0> = 1110 or 1111) enables the Special Event Trigger signal. The trigger signal can be used as the Special Event Trigger Reset input to TMR5, resetting the timer when the specific event happens on IC1. The events are summarized in Table 17-2. TABLE 17-2: SPECIAL EVENT TRIGGER CAP1M<3:0> Description 1110 The trigger occurs on every falling edge on the CAP1 input. 1111 The trigger occurs on every rising edge on the CAP1 input. OPERATING MODES SUMMARY Table 17-3 shows a summary of the input capture configuration when used in conjunction with the TMR5 timer resource. 17.1.10 OTHER OPERATING MODES Although the IC and QEI submodules are mutually exclusive, the IC can be reconfigured to work with the QEI module to perform specific functions. In effect, the QEI "borrows" hardware from the IC to perform these operations. For velocity measurement, the QEI uses dedicated hardware in channel IC1. The CAP1BUF registers are remapped, becoming the VELR registers. Its operation and use are described in Section 17.2.6 "Velocity Measurement". While in QEI mode, the CAP2BUF and CAP3BUF registers of channel IC2 and IC3 are used for position determination. They are remapped as the POSCNT and MAXCNT Buffer registers, respectively. TABLE 17-3: INPUT CAPTURE TIME BASE RESET SUMMARY Mode Timer Reset Timer on Capture CAP1 0001-0100 Edge Capture TMR5 optional(1) Simple Edge Capture mode (includes a selectable prescaler). TMR5 optional(1) Captures Timer5 on period boundaries. TMR5 always Captures Timer5 on pulse boundaries. Input Capture on State Change TMR5 optional(1) Captures Timer5 on state change. 1110-1111 Special Event Trigger (rising or falling edge) TMR5 optional(2) Used as a Special Event Trigger to be used with the Timer5 or other peripheral modules. TMR5 optional(1) Simple Edge Capture mode (includes a selectable prescaler). TMR5 optional(1) Captures Timer5 on period boundaries. TMR5 always Captures Timer5 on pulse boundaries. TMR5 optional(1) Captures Timer5 on state change. TMR5 optional(1) Simple Edge Capture mode (includes a selectable prescaler). TMR5 optional(1) Captures Timer5 on period boundaries. TMR5 always Captures Timer5 on pulse boundaries. TMR5 optional(1) Pin CAPxM 0101 Period Measurement 0110-0111 Pulse-Width Measurement 1000 CAP2 0001-0100 Edge Capture 0101 Period Measurement 0110-0111 Pulse-Width Measurement 1000 Input Capture on State Change CAP3 0001-0100 Edge Capture 0101 Period Measurement 0110-0111 Pulse-Width Measurement 1000 Note 1: 2: Input Capture on State Change Description Captures Timer5 on state change. Timer5 may be reset on capture events only when CAPxREN = 1. Trigger mode will not reset Timer5 unless RESEN = 0 in the T5CON register. DS39616D-page 160 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Quadrature Encoder Interface The Quadrature Encoder Interface (QEI) decodes speed and motion sensor information. It can be used in any application that uses a quadrature encoder for feedback. The interface implements these features: * Three QEI inputs: two phase signals (QEA and QEB) and one index signal (INDX) * Direction of movement detection with a direction change interrupt (IC3DRIF) * 16-bit up/down position counter * Standard and High-Precision Position Tracking modes * Two Position Update modes (x2 and x4) * Velocity measurement with a programmable postscaler for high-speed velocity measurement * Position counter interrupt (IC2QEIF in the PIR3 register) * Velocity control interrupt (IC1IF in the PIR3 register) The position counter acts as an integrator for tracking distance traveled. The QEA and QEB input edges serve as the stimulus to create the input clock which advances the Position Counter register (POSCNT). The register is incremented on either the QEA input edge, or the QEA and QEB input edges, depending on the operating mode. It is reset either by a rollover on match to the Period register, MAXCNT, or on the external index pulse input signal (INDX). An interrupt is generated on a Reset of POSCNT if the position counter interrupt is enabled. The QEI submodule has three main components: the QEI control logic block, the position counter and velocity postscaler. FIGURE 17-8: The QEI control logic detects the leading edge on the QEA or QEB phase input pins and generates the count pulse, which is sent to the position counter logic. It also samples the index input signal (INDX) and generates the direction of the rotation signal (up/down) and the velocity event signals. The velocity postscaler down samples the velocity pulses used to increment the velocity counter by a specified ratio. It essentially divides down the number of velocity pulses to one output per so many inputs, preserving the pulse width in the process. A simplified block-diagram of the QEI module is shown in Figure 17-8. QEI BLOCK DIAGRAM Data Bus 17.2 QEI Module Direction Change Timer Reset Velocity Event Set CHGIF Reset Timer5 Velocity Capture Postscaler 8 Set UP/DOWN Filter QEB QEA CAP3/QEB Direction Clock CAP2BUF/POSCNT 8 Reset on Match INDX Comparator Filter Set IC2QEIF CAP2/QEA CAP3BUF/MAXCNT Filter QEI Control Logic 8 Position Counter CAP1/INDX 8 8 2010 Microchip Technology Inc. DS39616D-page 161 PIC18F2331/2431/4331/4431 17.2.1 QEI CONFIGURATION The operation of the QEI is controlled by the QEICON Configuration register (see Register 17-2). The QEI module shares its input pins with the Input Capture (IC) module. The inputs are mutually exclusive; only the IC module or the QEI module (but not both) can be enabled at one time. Also, because the IC and QEI are multiplexed to the same input pins, the programmable noise filters can be dedicated to one module only. REGISTER 17-2: R/W-0 VELM Note: In the event that both QEI and IC are enabled, QEI will take precedence and IC will remain disabled. QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER R/W-0 QERR (1) R-0 UP/DOWN R/W-0 QEIM2 R/W-0 (2,3) QEIM1 (2,3) R/W-0 QEIM0 (2,3) R/W-0 R/W-0 PDEC1 PDEC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 VELM: Velocity Mode bit 1 = Velocity mode disabled 0 = Velocity mode enabled bit 6 QERR: QEI Error bit(1) 1 = Position counter overflow or underflow(4) 0 = No overflow or underflow bit 5 UP/DOWN: Direction of Rotation Status bit 1 = Forward 0 = Reverse bit 4-2 QEIM<2:0>: QEI Mode bits(2,3) 111 = Unused 110 = QEI enabled in 4x Update mode; position counter is reset on period match (POSCNT = MAXCNT) 101 = QEI enabled in 4x Update mode; INDX resets the position counter 100 = Unused 010 = QEI enabled in 2x Update mode; position counter is reset on period match (POSCNT = MAXCNT) 001 = QEI enabled in 2x Update mode; INDX resets the position counter 000 = QEI off bit 1-0 PDEC<1:0>: Velocity Pulse Reduction Ratio bits 11 = 1:64 10 = 1:16 01 = 1:4 00 = 1:1 Note 1: 2: 3: 4: QEI must be enabled and in Index mode. QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and IC modules are both enabled, QEI will take precedence. Enabling one of the QEI operating modes remaps the IC Buffer registers, CAP1BUFH, CAP1BUFL, CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL, as the VELRH, VELRL, POSCNTH, POSCNTL, MAXCNTH and MAXCNTL registers (respectively) for the QEI. The QERR bit must be cleared in software. DS39616D-page 162 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.2 QEI MODES 17.2.3 Position measurement resolution depends on how often the Position Counter register, POSCNT, is incremented. There are two QEI Update modes to measure the rotor's position: QEI x2 and QEI x4. TABLE 17-4: QEI MODES QEIM<2:0> Mode/ Reset 000 -- 001 010 Description QEI disabled.(1) x2 update/ Two clocks per QEA index pulse pulse. INDX resets POSCNT. x2 update/ Two clocks per QEA pulse. period POSCNT is reset by the match period match (MAXCNT). 011 -- Unused. 100 -- Unused. 101 x4 update/ Four clocks per QEA and index pulse QEB pulse pair. INDX resets POSCNT. 110 x4 update/ Four clocks per QEA and period QEB pulse pair. match POSCNT is reset by the period match (MAXCNT). 111 Note 1: 17.2.2.1 -- Unused. QEI module is disabled. The position counter and the velocity measurement functions are fully disabled in this mode. QEI x2 Update Mode QEI x2 Update mode is selected by setting the QEI Mode Select bits (QEIM<2:0>) to `001' or `010'. In this mode, the QEI logic detects every edge on the QEA input only. Every rising and falling edge on the QEA signal clocks the position counter. The position counter can be reset by either an input on the INDX pin (QEIM<2:0> = 001), or by a period match, even when the POSCNT register pair equals MAXCNT (QEIM<2:0> = 010). 17.2.2.2 QEI x4 Update Mode QEI x4 Update mode provides for a finer resolution of the rotor position, since the counter increments or decrements more frequently for each QEA/QEB input pulse pair than in QEI x2 mode. This mode is selected by setting the QEI mode select bits to `101' or `110'. In QEI x4, the phase measurement is made on the rising and the falling edges of both QEA and QEB inputs. The position counter is clocked on every QEA and QEB edge. Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM<2:0> = 101), or by the period match event (QEIM<2:0> = 010). 2010 Microchip Technology Inc. QEI OPERATION The Position Counter register pair (POSCNTH: POSCNTL) acts as an integrator, whose value is proportional to the position of the sensor rotor that corresponds to the number of active edges detected. POSCNT can either increment or decrement, depending on a number of selectable factors which are decoded by the QEI logic block. These include the Count mode selected, the phase relationship of QEA to QEB ("lead/lag"), the direction of rotation and if a Reset event occurs. The logic is detailed in the sections that follow. 17.2.3.1 Edge and Phase Detect In the first step, the active edges of QEA and QEB are detected, and the phase relationship between them is determined. The position counter is changed based on the selected QEI mode. In QEI x2 Update mode, the position counter increments or decrements on every QEA edge based on the phase relationship of the QEA and QEB signals. In QEI x4 Update mode, the position counter increments or decrements on every QEA and QEB edge based on the phase relationship of the QEA and QEB signals. For example, if QEA leads QEB, the position counter is incremented by `1'. If QEB lags QEA, the position counter is decremented by `1'. 17.2.3.2 Direction of Count The QEI control logic generates a signal that sets the UP/DOWN bit (QEICON<5>); this, in turn, determines the direction of the count. When QEA leads QEB, UP/DOWN is set (= 1) and the position counter increments on every active edge. When QEA lags QEB, UP/DOWN is cleared and the position counter decrements on every active edge. TABLE 17-5: Current Signal Detected DIRECTION OF ROTATION Previous Signal Detected Rising Falling Pos. Cntrl.(1) QEA QEB QEA QEB QEA Rising x x DEC QEA Falling x x QEB Rising x Note 1: DEC INC x QEB Falling INC INC x DEC x INC DEC When UP/DOWN = 1, the position counter is incremented. When UP/DOWN = 0, the position counter is decremented. DS39616D-page 163 PIC18F2331/2431/4331/4431 17.2.3.3 Reset and Update Events The position counter will continue to increment or decrement until one of the following events takes place. The type of event and the direction of rotation when it happens determines if a register Reset or update occurs. 1. An index pulse is detected on the INDX input (QEIM<2:0> = 001). If the encoder is traveling in the forward direction, POSCNT is reset (00h) on the next clock edge after the index marker, INDX, has been detected. The position counter resets on the QEA or QEB edge once the INDX rising edge has been detected. If the encoder is traveling in the reverse direction, the value in the MAXCNT register is loaded into POSCNT on the next quadrature pulse edge (QEA or QEB) after the falling edge on INDX has been detected. 2. A POSTCNT/MAXCNT period match occurs (QEIM<2:0> = 010). If the encoder is traveling in the forward direction, POSCNT is reset (00h) on the next clock edge when POSCNT = MAXCNT. An interrupt event is triggered on the next TCY after the Reset (see Figure 17-10) If the encoder is traveling in the reverse direction and the value of POSCNT reaches 00h, POSCNT is loaded with the contents of the MAXCNT register on the next clock edge. An interrupt event is triggered on the next TCY after the load operation (see Figure 17-10). The value of the position counter is not affected during QEI mode changes, nor when the QEI is disabled altogether. 17.2.4 QEI INTERRUPTS The position counter interrupt occurs and the interrupt flag (IC2QEIF) is set, based on the following events: * A POSCNT/MAXCNT period match event (QEIM<2:0> = 010 or 110) * A POSCNT rollover (FFFFh to 0000h) in Period mode only (QEIM<2:0> = 010 or 110) * An index pulse detected on INDX The interrupt timing diagrams for IC2QEIF are shown in Figure 17-10 and Figure 17-11. When the direction has changed, the direction change interrupt flag (IC3DRIF) is set on the following TCY clock (see Figure 17-10). If the position counter rolls over in Index mode, the QERR bit will be set. 17.2.5 QEI SAMPLE TIMING The quadrature input signals, QEA and QEB, may vary in quadrature frequency. The minimum quadrature input period, TQEI, is 16 TCY. The position count rate, FPOS, is directly proportional to the rotor's RPM, line count D and QEI Update mode (x2 versus x4); that is, EQUATION 17-1: FPOS = 4D * RPM 60 Note: The number of incremental lines in the position encoder is typically set at D = 1024 and the QEI Update mode = x4. The maximum position count rate (i.e., x4 QEI Update mode, D = 1024) with F CY = 10 MIPS is equal to 2.5 MHz, which corresponds to FQEI of 625 kHz. Figure 17-9 shows QEA and QEB quadrature input timing when sampled by the noise filter. DS39616D-page 164 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-9: QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1:1) TCY QEA Pin TQEI = 16 TCY(1) QEB Pin QEA Input TGD = 3 TCY QEB Input Note 1: The module design allows a quadrature frequency of up to FQEI = FCY/16. FIGURE 17-10: QEI MODULE RESET TIMING ON PERIOD MATCH Forward Reverse QEA QEB Count (+/-) +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 MAXCNT 1517 1516 1515 1514 1519 1518 1520 1522 1521 1523 1525 1524 1526 1527 0003 0002 0001 0000 0004 0003 0002 0000 0001 1525 1526 1527 1524 1521 1522 1523 1520 POSCNT(1) MAXCNT=1527 Note 6 IC2QEIF Note 2 Note 2 UP/DOWN Q4(3) Q4(3) Position Counter Load Q1(5) Q1(4) IC3DRIF Q1(5) Note 1: The POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals). Asynchronous external QEA and QEB inputs are synchronized to the TCY clock by the input sampling FF in the noise filter (see Figure 17-14). 2: When POSCNT = MAXCNT, POSCNT is reset to `0' on the next QEA rising edge. POSCNT is set to MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEIF is generated on the Q4 rising edge. 4: Position counter is loaded with `0' (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. 2010 Microchip Technology Inc. DS39616D-page 165 PIC18F2331/2431/4331/4431 FIGURE 17-11: QEI MODULE RESET TIMING WITH THE INDEX INPUT Forward Reverse Note 2 Note 2 QEA QEB Count (+/-) -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 MAXCNT 1515 1514 1517 1516 1519 1518 1520 1522 1521 1525 1524 1523 1527 1526 0001 0000 0002 0003 0004 0003 0000 0001 0002 1526 1527 1524 1525 1521 1522 1523 1520 POSCNT(1) MAXCNT = 1527 INDX Note 6 IC2QEIF UP/DOWN Q4(3) Position Counter Load Q1(4) Q4(3) Q1(5) Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals). 2: When an INDX Reset pulse is detected, POSCNT is reset to `0' on the next QEA or QEB edge. POSCNT is set to MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA or QEB edge. a similar Reset sequence occurs for the reverse direction, except that the INDX signal is recognized on its falling edge. The Reset is generated on the next QEA or QEB edge. 3: IC2QEIF is enabled for one TCY clock cycle. 4: The position counter is loaded with 0000h (i.e., Reset) on the next QEA or QEB edge when the INDX is high. 5: The position counter is loaded with a MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the INDX falling edge input signal detect). 6: IC2QEIF must be cleared in software. DS39616D-page 166 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.6 17.2.6.1 VELOCITY MEASUREMENT The velocity pulse generator, in conjunction with the IC1 and the synchronous TMR5 (in synchronous operation), provides a method for high accuracy speed measurements at both low and high mechanical motor speeds. The Velocity mode is enabled when the VELM bit is cleared (= 0) and QEI is set to one of its operating modes (see Table 17-6). The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i.e., distance travelled) for a given time interval. Time is measured by utilizing the TMR5 time base. To optimize register space, the Input Capture Channel 1 (IC1) is used to capture TMR5 counter values. Input Capture Buffer register, CAP1BUF, is redefined in Velocity Measurement mode, VELM = 0, as the Velocity Register Buffer (VELRH, VELRL). TABLE 17-6: Each velocity pulse serves as a capture pulse. With the TMR5 in Synchronous Timer mode, the value of TMR5 is captured on every output pulse of the postscaler. The counter is subsequently reset to `0'. TMR5 is reset upon a capture event. VELOCITY PULSES QEIM<2:0> Velocity Event Mode 001 010 x2 Velocity Event mode. The velocity pulse is generated on every QEA edge. 101 110 x4 Velocity Event mode. The velocity pulse is generated on every QEA and QEB active edge. FIGURE 17-12: Velocity Event Timing Figure 17-13 shows the velocity measurement timing diagram. VELOCITY MEASUREMENT BLOCK DIAGRAM Reset Logic QEI Control Logic TMR5 Reset TMR5 Clock TCY 16 CAP3/QEB Noise Filters Velocity Mode Velocity Event Velocity Capture IC1 (VELR Register) QEB QEA CAP2/QEA Postscaler INDX Direction Clock Position Counter CAP1/INDX 2010 Microchip Technology Inc. DS39616D-page 167 PIC18F2331/2431/4331/4431 FIGURE 17-13: VELOCITY MEASUREMENT TIMING(1) Forward Reverse QEA QEB vel_out velcap VELR(2) Old Value 1529 0003 0004 0001 0002 0008 0009 0000 0006 0007 0005 0003 0004 0001 0002 0000 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1525 1526 1523 1524 1522 1520 1521 TMR5(2) 1537 cnt_reset(3) Q1 Q1 Q1 IC1IF(4) CAP1REN Instr. Execution BCF T5CON, VELM BCF PIE2, IC1IE BSF PIE2, IC1IE MOVWF QEICON(5) Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio is set to divide-by-4 (PDEC<1:0> = 01). 2: The VELR register latches the TMR5 count on the "velcap" capture pulse. Timer5 must be set to the Synchronous Timer or Counter mode. In this example, it is set to the Synchronous Timer mode, where the TMR5 prescaler divide ratio = 1 (i.e., Timer5 Clock = TCY). 3: The TMR5 counter is reset on the next Q1 clock cycle following the "velcap" pulse. The TMR5 value is unaffected when the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be reconfigured to their previous settings when re-entering Velocity Measurement mode. While making speed measurements of very slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode may not provide sufficient precision. The Pulse-Width Measurement mode may have to be used to provide the additional precision. In this case, the input pulse is measured on the CAP1 input pin. 4: IC1IF interrupt is enabled by setting IC1IE as follows: BSF PIE2, IC1IE. Assume IC1E bit is placed in the PIE2 (Peripheral Interrupt Enable 2) register in the target device. The actual IC1IF bit is written on the Q2 rising edge. 5: The post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1). 17.2.6.2 Velocity Postscaler The velocity event pulse (velcap, see Figure 17-12) serves as the TMR5 capture trigger to IC1 while in the Velocity mode. The number of velocity events are reduced by the velocity postscaler before they are used as the input capture clock. The velocity event reduction ratio can be set with the PDEC<1:0> control bits (QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1). 17.2.6.3 CAP1REN in Velocity Mode The TMR5 value can be reset (TMR5 register pair = 0000h) on a velocity event capture by setting the CAP1REN bit (CAP1CON<6>). When CAP1REN is cleared, the TMR5 time base will not be reset on any velocity event capture pulse. The VELR register pair, however, will continue to be updated with the current TMR5 value. The velocity postscaler settings are automatically reloaded from their previous values as the Velocity mode is re-enabled. DS39616D-page 168 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.3 Noise Filters The Motion Feedback Module includes three noise rejection filters on RA2/AN2/VREF-/CAP1/INDX, RA3/AN3/VREF+/CAP2/QEA and RA4/AN4/CAP3/QEB. The filter block also includes a fourth filter for the T5CKI pin. They are intended to help reduce spurious noise spikes which may cause the input signals to become corrupted at the inputs. The filter ensures that the input signals are not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The filters are controlled using the Digital Filter Control (DFLTCON) register (see Register 17-3). The filters can be individually enabled or disabled by setting or clearing the corresponding FLTxEN bit in the DFLTCON register. The sampling frequency, which must be the same for all three noise filters, can be REGISTER 17-3: programmed by the FLTCK<2:0> Configuration bits. TCY is used as the clock reference to the clock divider block. The noise filters can either be added or removed from the input capture, or QEI signal path, by setting or clearing the appropriate FLTxEN bit, respectively. Each capture channel provides for individual enable control of the filter output. The FLT4EN bit enables or disables the noise filter available on the T5CKI input in the Timer5 module. The filter network for all channels is disabled on Power-on and Brown-out Resets, as the DFLTCON register is cleared on Resets. The operation of the filter is shown in the timing diagram in Figure 17-14. DFLTCON: DIGITAL FILTER CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- FLT4EN FLT3EN(1) FLT2EN(1) FLT1EN(1) FLTCK2 FLTCK1 FLTCK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 FLT4EN: Noise Filter Output Enable bit (T5CKI input) 1 = Enabled 0 = Disabled bit 5 FLT3EN: Noise Filter Output Enable bit (CAP3/QEB input)(1) 1 = Enabled 0 = Disabled bit 4 FLT2EN: Noise Filter Output Enable bit (CAP2/QEA input)(1) 1 = Enabled 0 = Disabled bit 3 FLT1EN: Noise Filter Output Enable bit (CAP1/INDX Input)(1) 1 = Enabled 0 = Disabled bit 2-0 FLTCK<2:0>: Noise Filter Clock Divider Ratio bits 111 = Unused 110 = 1:128 101 = 1:64 100 = 1:32 011 = 1:16 010 = 1:4 001 = 1:2 000 = 1:1 Note 1: Note: x = Bit is unknown The noise filter output enables are functional in both QEI and IC Operating modes. The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering. 2010 Microchip Technology Inc. DS39616D-page 169 PIC18F2331/2431/4331/4431 FIGURE 17-14: NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1) TQEI = 16 TCY TCY Noise Glitch(3) Noise Glitch(3) Pin(1) CAP1/INDX (input to filter) CAP1/INDX Input(2) (output from filter) TGD = 3 TCY Note 1: 17.4 Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and CAP3/QEB pins. 2: Noise filtering occurs in the shaded portions of the CAP1 input. 3: Filter's group delay: TGD = 3 TCY. IC and QEI Shared Interrupts The IC and QEI submodules can each generate three distinct interrupt signals; however, they share the use of the same three interrupt flags in register, PIR3. The meaning of a particular interrupt flag at any given time depends on which module is active at the time the interrupt is set. The meaning of the flags in context are summarized in Table 17-7. When the IC submodule is active, the three flags (IC1IF, IC2QEIF and IC3DRIF) function as interrupt-on-capture event flags for their respective input capture channels. The channel must be configured for one of the events that will generate an interrupt (see Section 17.1.7 "IC Interrupts" for more information). When the QEI is enabled, the IC1IF interrupt flag indicates an interrupt caused by a velocity measurement event, usually an update of the VELR register. The IC2QEIF interrupt indicates that a position measurement event has occurred. IC3DRIF indicates that a direction change has been detected. TABLE 17-7: Interrupt Flag IC1IF 17.5 17.5.1 Operation in Sleep Mode 3x INPUT CAPTURE IN SLEEP MODE Since the input capture can operate only when its time base is configured in a Synchronous mode, the input capture will not capture any events. This is because the device's internal clock has been stopped and any internal timers in Synchronous modes will not increment. The prescaler will continue to count the events (not synchronized). When the specified capture event occurs, the CAPx interrupt will be set. The Capture Buffer register will be updated upon wake-up from sleep to the current TMR5 value. If the CAPx interrupt is enabled, the device will wake-up from Sleep. This effectively enables all input capture channels to be used as the external interrupts. 17.5.2 QEI IN SLEEP MODE All QEI functions are halted in Sleep mode. MEANING OF IC AND QEI INTERRUPT FLAGS Meaning IC Mode QEI Mode IC1 Capture Event Velocity Register Update IC2QEIF IC2 Capture Event Position Measurement Update IC3DRIF IC3 Capture Event Direction Change DS39616D-page 170 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 17-8: Name INTCON REGISTERS ASSOCIATED WITH THE MOTION FEEDBACK MODULE Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 Bit 6 GIE/GIEH PEIE/GIEL IPR3 -- -- -- PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 -- -- -- PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 -- -- -- PTIF IC3DRIF IC2QEIF IC1IF TMR5IF 56 PIR3 TMR5H Timer5 Register High Byte 57 TMR5L Timer5 Register Low Byte 57 PR5H Timer5 Period Register High Byte 57 PR5L Timer5 Period Register Low Byte 57 T5CON T5SEN RESEN T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 57 CAP1BUFH/ VELRH Capture 1 Register High Byte/Velocity Register High Byte(1) 58 CAP1BUFL/ VELRL Capture 1 Register Low Byte/Velocity Register Low Byte(1) 58 CAP2BUFH/ POSCNTH Capture 2 Register High Byte/QEI Position Counter Register High Byte(1) 58 CAP2BUFL/ POSCNTL Capture 2 Register Low Byte/QEI Position Counter Register Low Byte(1) 58 CAP3BUFH/ MAXCNTH Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte(1) 58 CAP3BUFL/ MAXCNTL Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte(1) 58 CAP1CON -- CAP1REN -- -- CAP1M3 CAP1M2 CAP1M1 CAP1M0 59 CAP2CON -- CAP2REN -- -- CAP2M3 CAP2M2 CAP2M1 CAP2M0 59 CAP3CON -- CAP3REN -- -- CAP3M3 CAP3M2 CAP3M1 CAP3M0 59 DFLTCON -- FLT4EN FLT3EN VELM QERR QEICON FLT2EN FLT1EN UP/DOWN QEIM2 QEIM1 FLTCK2 FLTCK1 FLTCK0 59 QEIM0 PDEC1 PDEC0 56 Legend: -- = unimplemented. Shaded cells are not used by the Motion Feedback Module. Note 1: Register name and function determined by which submodule is selected (IC/QEI, respectively). See Section 17.1.10 "Other Operating Modes" for more information. 2010 Microchip Technology Inc. DS39616D-page 171 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 172 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.0 POWER CONTROL PWM MODULE The Power Control PWM module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs for use in the control of motor controllers and power conversion applications. In particular, the following power and motion control applications are supported by the PWM module: * Three-Phase and Single-Phase AC Induction Motors * Switched Reluctance Motors * Brushless DC (BLDC) Motors * Uninterruptible Power Supplies (UPS) * Multiple DC Brush Motors The PWM module has the following features: * Up to eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control. * Up to 14-bit resolution, depending upon the PWM period. * "On-the-fly" PWM frequency changes. * Edge and Center-Aligned Output modes. * Single-Pulse Generation mode. * Programmable dead-time control between paired PWMs. * Interrupt support for asymmetrical updates in Center-Aligned mode. * Output override for Electrically Commutated Motor (ECM) operation; for example, BLDC. * Special Event Trigger comparator for scheduling other peripheral events. * PWM outputs disable feature sets PWM outputs to their inactive state when in Debug mode. The Power Control PWM module supports three PWM generators and six output channels on PIC18F2331/2431 devices, and four generators and eight channels on PIC18F4331/4431 devices. A simplified block diagram of the module is shown in Figure 18-1. Figure 18-2 and Figure 18-3 show how the module hardware is configured for each PWM output pair for the Complementary and Independent Output modes. Each functional unit of the PWM module will be discussed in subsequent sections. 2010 Microchip Technology Inc. DS39616D-page 173 PIC18F2331/2431/4331/4431 FIGURE 18-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 PWM Enable and Mode 8 PWMCON1 8 DTCON Dead-Time Control 8 FLTCONFIG Fault Pin Control 8 OVDCON<D/S> PWM Manual Control PWM Generator #3(1) 8 PDC3 Buffer PDC3 Comparator 8 PWM Generator 2 PTMR Channel 3 Dead-Time Generator and Override Logic(2) PWM7(2) Channel 2 Dead-Time Generator and Override Logic PWM5 Comparator PWM Generator 1 PTPER PWM Generator 0 8 PTPER Buffer Channel 1 Dead-Time Generator and Override Logic PWM6(2) Output Driver Block Channel 0 Dead-Time Generator and Override Logic PWM4 PWM3 PWM2 PWM1 PWM0 8 FLTA PTCON FLTB(2) Comparator SEVTDIR 8 SEVTCMP Note 1: 2: Special Event Postscaler Special Event Trigger PTDIR Only PWM Generator 3 is shown in detail. The other generators are identical; their details are omitted for clarity. PWM Generator 3 and its logic, PWM Channels 6 and 7, and FLTB and its associated logic are not implemented on PIC18F2331/2431 devices. DS39616D-page 174 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-2: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE VDD Dead-Band Generator PWM1 Duty Cycle Comparator HPOL PWM Duty Cycle Register PWM0 LPOL Fault Override Values Channel Override Values Fault A Pin Fault Pin Assignment Logic Fault B Pin Note: In Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active. The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd channel is driven to its active state. FIGURE 18-3: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE VDD PWM Duty Cycle Register PWM1 Duty Cycle Comparator VDD HPOL PWM0 Fault Override Values LPOL Channel Override Values Fault A Pin Fault B Pin Fault Pin Assignment Logic This module contains four duty cycle generators, numbered 0 through 3. The module has eight PWM output pins, numbered 0 through 7. The eight PWM outputs are grouped into output pairs of even and odd numbered outputs. In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3 and so on. The dead-time 2010 Microchip Technology Inc. generator inserts an OFF period called "dead time" between the going OFF of one pin to the going ON of the complementary pin of the paired pins. This is to prevent damage to the power switching devices that will be connected to the PWM output pins. The time base for the PWM module is provided by its own 12-bit timer, which also incorporates selectable prescaler and postscaler options. DS39616D-page 175 PIC18F2331/2431/4331/4431 18.1 Control Registers The operation of the PWM module is controlled by a total of 22 registers. Eight of these are used to configure the features of the module: * * * * * * * * PWM Timer Control Register 0 (PTCON0) PWM Timer Control Register 1 (PTCON1) PWM Control Register 0 (PWMCON0) PWM Control Register 1 (PWMCON1) Dead-Time Control Register (DTCON) Output Override Control Register (OVDCOND) Output State Register (OVDCONS) Fault Configuration Register (FLTCONFIG) There are also 14 registers that are configured as seven register pairs of 16 bits. These are used for the configuration values of specific features. They are: * PWM Time Base Registers (PTMRH and PTMRL) * PWM Time Base Period Registers (PTPERH and PTPERL) * PWM Special Event Trigger Compare Registers (SEVTCMPH and SEVTCMPL) * PWM Duty Cycle #0 Registers (PDC0H and PDC0L) * PWM Duty Cycle #1 Registers (PDC1H and PDC1L) * PWM Duty Cycle #2 Registers (PDC2H and PDC2L) * PWM Duty Cycle #3 Registers (PDC3H and PDC3L) 18.2 Module Functionality The PWM module supports several modes of operation that are beneficial for specific power and motor control applications. Each mode of operation is described in subsequent sections. The PWM module is composed of several functional blocks. The operation of each is explained separately in relation to the several modes of operation: * * * * * * * * PWM Time Base PWM Time Base Interrupts PWM Period PWM Duty Cycle Dead-Time Generators PWM Output Overrides PWM Fault Inputs PWM Special Event Trigger 18.3 PWM Time Base The PWM time base is provided by a 12-bit timer with prescaler and postscaler functions. A simplified block diagram of the PWM time base is shown in Figure 18-4. The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software. All of these register pairs are double-buffered. DS39616D-page 176 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-4: PWM TIME BASE BLOCK DIAGRAM PTMR Register PTMR Clock Timer Reset Up/Down Comparator Zero Match Period Match Comparator PTMOD1 Timer Direction Control PTDIR Duty Cycle Load PTPER Period Load PTPER Buffer Update Disable (UDIS) FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 Zero Match Zero Match Period Match PTMOD1 PTMOD0 Clock Control PTMR Clock PTEN Postscaler 1:1-1:16 Interrupt Control PTIF Period Match PTMOD1 PTMOD0 The PWM time base can be configured for four different modes of operation: * * * * Free-Running mode Single-Shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double updates 2010 Microchip Technology Inc. These four modes are selected by the PTMOD<1:0> bits in the PTCON0 register. The Free-Running mode produces edge-aligned PWM generation. The Continuous Up/Down Count modes produce center-aligned PWM generation. The Single-Shot mode allows the PWM module to support pulse control of certain Electronically Commutated Motors (ECMs) and produces edge-aligned operation. DS39616D-page 177 PIC18F2331/2431/4331/4431 REGISTER 18-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . . 1111 = 1:16 Postscale bit 3-2 PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits 00 = PWM time base input clock is FOSC/4 (1:1 prescale) 01 = PWM time base input clock is FOSC/16 (1:4 prescale) 10 = PWM time base input clock is FOSC/64 (1:16 prescale) 11 = PWM time base input clock is FOSC/256 (1:64 prescale) bit 1-0 PTMOD<1:0>: PWM Time Base Mode Select bits 11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base configured for Single-Shot mode 00 = PWM time base operates in a Free-Running mode REGISTER 18-2: PTCON1: PWM TIMER CONTROL REGISTER 1 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 PTEN PTDIR -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is off bit 6 PTDIR: PWM Time Base Count Direction Status bit 1 = PWM time base counts down 0 = PWM time base counts up bit 5-0 Unimplemented: Read as `0' DS39616D-page 178 x = Bit is unknown 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 18-3: U-0 -- PWMCON0: PWM CONTROL REGISTER 0 R/W-1(1) R/W-1(1) PWMEN2 PWMEN1 R/W-1(1) PWMEN0 R/W-0 (3) PMOD3 R/W-0 R/W-0 R/W-0 PMOD2 PMOD1 PMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6-4 PWMEN<2:0>: PWM Module Enable bits(1) 111 = All odd PWM I/O pins are enabled for PWM output(2) 110 = PWM1, PWM3 pins are enabled for PWM output 101 = All PWM I/O pins are enabled for PWM output(2) 100 = PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5 pins are enabled for PWM output 011 = PWM0, PWM1, PWM2 and PWM3 I/O pins are enabled for PWM output 010 = PWM0 and PWM1 pins are enabled for PWM output 001 = PWM1 pin is enabled for PWM output 000 = PWM module is disabled; all PWM I/O pins are general purpose I/O bit 3-0 PMOD<3:0>: PWM Output Pair Mode bits For PMOD0: 1 = PWM I/O pin pair (PWM0, PWM1) is in the Independent mode 0 = PWM I/O pin pair (PWM0, PWM1) is in the Complementary mode For PMOD1: 1 = PWM I/O pin pair (PWM2, PWM3) is in the Independent mode 0 = PWM I/O pin pair (PWM2, PWM3) is in the Complementary mode For PMOD2: 1 = PWM I/O pin pair (PWM4, PWM5) is in the Independent mode 0 = PWM I/O pin pair (PWM4, PWM5) is in the Complementary mode For PMOD3:(3) 1 = PWM I/O pin pair (PWM6, PWM7) is in the Independent mode 0 = PWM I/O pin pair (PWM6, PWM7) is in the Complementary mode Note 1: 2: 3: Reset condition of the PWMEN bits depends on the PWMPIN Configuration bit. When PWMEN<2:0> = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0> outputs are enabled for PIC18F4331/4431 devices. When PWMEN<2:0> = 111, PWM Outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM Outputs 1, 3, 5 and 7 are enabled in PIC18F4331/4431 devices. Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. 2010 Microchip Technology Inc. DS39616D-page 179 PIC18F2331/2431/4331/4431 REGISTER 18-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR -- UDIS OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-4 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . . 1111 = 1:16 Postscale bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit 1 = A Special Event Trigger will occur when the PWM time base is counting downwards 0 = A Special Event Trigger will occur when the PWM time base is counting upwards bit 2 Unimplemented: Read as `0' bit 1 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled bit 0 OSYNC: PWM Output Override Synchronization bit 1 = Output overrides via the OVDCON register are synchronized to the PWM time base 0 = Output overrides via the OVDCON register are asynchronous 18.3.1 FREE-RUNNING MODE In the Free-Running mode, the PWM Time Base registers (PTMRL and PTMRH) will begin counting upwards until the value in the PWM Time Base Period register, PTPER (PTPERL and PTPERH), is matched. The PTMR registers will be reset on the following input clock edge and the time base will continue counting upwards as long as the PTEN bit remains set. 18.3.2 SINGLE-SHOT MODE In the Single-Shot mode, the PWM time base will begin counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt the time base. 18.3.3 CONTINUOUS UP/DOWN COUNT MODES In Continuous Up/Down Count modes, the PWM time base counts upwards until the value in the PTPER register matches with the PTMR register. On the following input clock edge, the timer counts downwards. The PTDIR bit in the PTCON1 register is read-only and indicates the counting direction. The PTDIR bit is set when the timer counts downwards. DS39616D-page 180 Note: 18.3.4 Since the PWM compare outputs are driven to the active state when the PWM time base is counting downwards and matches the duty cycle value, the PWM outputs are held inactive during the first half of the first period of the Continuous Up/Down Count mode until PTMR begins to count down from the PTPER value. PWM TIME BASE PRESCALER The input clock to PTMR (FOSC/4) has prescaler options of 1:1, 1:4, 1:16 or 1:64. These are selected by control bits, PTCKPS<1:0>, in the PTCON0 register. The prescaler counter is cleared when any of the following occurs: * Write to the PTMR register * Write to the PTCON (PTCON0 or PTCON1) register * Any device Reset Note: The PTMR register is not cleared when PTCONx is written. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.3.5 Table 18-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. An operating frequency of 40 MHz (FCYC = 10 MHz) and PTPER = 0xFFF is assumed in the table. The PWM module must be capable of generating PWM signals at the line frequency (50 Hz or 60 Hz) for certain power control applications. TABLE 18-1: The match output of PTMR can optionally be postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt. The postscaler counter is cleared when any of the following occurs: * Write to the PTMR register * Write to the PTCON register * Any device Reset MINIMUM PWM FREQUENCY Minimum PWM Frequencies vs. Prescaler Value for FCYC = 10 MIPS (PTPER = 0FFFh) Prescale PWM Frequency Edge-Aligned PWM Frequency Center-Aligned 1:1 2441 Hz 1221 Hz 1:4 610 Hz 305 Hz 1:16 153 Hz 76 Hz 1:64 38 Hz 19 Hz PWM TIME BASE POSTSCALER The PTMR register is not cleared when PTCON is written. 18.4 PWM Time Base Interrupts The PWM timer can generate interrupts based on the modes of operation selected by the PTMOD<1:0> bits and the postscaler bits (PTOPS<3:0>). 18.4.1 INTERRUPTS IN FREE-RUNNING MODE When the PWM time base is in the Free-Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs. The PTMR register is reset to zero in the following clock edge. Using a postscaler selection other than 1:1 will reduce the frequency of interrupt events. FIGURE 18-5: PWM TIME BASE INTERRUPT TIMING, FREE-RUNNING MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 1 PTMR FFEh FFFh 000h 001h 002h PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 1 PTMR FFEh FFFh 000h 001h 002h PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value, FFFh, for this example. 2010 Microchip Technology Inc. DS39616D-page 181 PIC18F2331/2431/4331/4431 18.4.2 INTERRUPTS IN SINGLE-SHOT MODE 18.4.3 When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM Time Base register (PTMR) is reset to zero on the following input clock edge and the PTEN bit is cleared. The postscaler selection bits have no effect in this Timer mode. FIGURE 18-6: INTERRUPTS IN CONTINUOUS UP/DOWN COUNT MODE In the Continuous Up/Down Count mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM time base begins to count upwards. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. Figure 18-7 shows the interrupts in Continuous Up/Down Count mode. PWM TIME BASE INTERRUPT TIMING, SINGLE-SHOT MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 2 PTMR FFEh FFFh 000h 1 1 000h 000h 1 PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 2 PTMR FFEh 1 000h FFFh 1 000h 000h 1 PTMR_INT_REQ PTIF bit Note 1: 2: Interrupt flag bit, PTIF, is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value, FFFh, for this example. DS39616D-page 182 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-7: PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 PTMR 002h 001h 000h 001h 002h PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit B: PRESCALER = 1:4 Qc Qc Q4 Qc Qc Qc 002h PTMR Qc Qc Qc Qc 001h Q4 Qc Qc Qc Qc Qc Qc 001h 000h Qc Qc Qc Qc Qc 002h PTDIR bit 1 1 PTMR_INT_REQ 1 1 PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2010 Microchip Technology Inc. DS39616D-page 183 PIC18F2331/2431/4331/4431 18.4.4 INTERRUPTS IN DOUBLE UPDATE MODE Note: This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 18-8 shows the interrupts in Continuous Up/Down Count mode with double updates. Do not change the PTMOD bits while PTEN is active; it will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load the PTMOD bits with the required data and then set PTEN. The Double Update mode provides two additional functions to the user in Center-Aligned mode. 1. 2. The control loop bandwidth is doubled because the PWM duty cycles can be updated twice per period. Asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. FIGURE 18-8: PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES A: PRESCALER = 1:1 Case 1: PTMR Counting Upwards Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 2 PTMR 3FDh 3FEh 3FFh 3FEh 3FDh PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit Case 2: PTMR Counting Downwards Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PTMR 002h 001h 000h 001h 002h PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit Note 1: 2: Interrupt flag bit, PTIF, is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value, 3FFh, for this example. DS39616D-page 184 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.5 PWM Period The PWM period is defined by the PTPER register pair (PTPERL and PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH and 8 bits of PTPERL. PTPER is a double-buffered register used to set the counting period for the PWM time base. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 18-4: FOSC log FPWM Resolution = log(2) The PTPER register contents are loaded into the PTPER register at the following times: * Free-Running and Single-Shot modes: When the PTMR register is reset to zero after a match with the PTPER register. * Continuous Up/Down Count modes: When the PTMR register is zero. The value held in the PTPER register is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). Figure 18-9 and Figure 18-10 indicate the times when the contents of the PTPER register are loaded into the actual PTPER register. The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 18-2. The PWM frequencies in Table 18-2 are calculated for Edge-Aligned PWM mode. For Center-Aligned mode, the PWM frequencies will be approximately one-half the values indicated in this table. TABLE 18-2: PWM PERIOD FOR FREE-RUNNING MODE (PTPER + 1) x PTMRPS TPWM = FOSC/4 EQUATION 18-2: TPWM = PWM PERIOD FOR UP/DOWN COUNT MODE (2 x PTPER) x PTMRPS FOSC 4 The PWM frequency is the inverse of period; or: EQUATION 18-3: PWM FREQUENCY 1 PWM Frequency = PWM Period PTPER PWM PWM Value Resolution Frequency FOSC MIPS 40 MHz 10 0FFFh 14 bits 2.4 kHz 40 MHz 10 07FFh 13 bits 4.9 kHz 40 MHz 10 03FFh 12 bits 9.8 kHz 40 MHz 10 01FFh 11 bits 19.5 kHz 40 MHz 10 FFh 10 bits 39.0 kHz 40 MHz 10 7Fh 9 bits 78.1 kHz 40 MHz 10 3Fh 8 bits 156.2 kHz 40 MHz 10 1Fh 7 bits 312.5 kHz 40 MHz 10 0Fh 6 bits 625 kHz 25 MHz 6.25 0FFFh 14 bits 1.5 kHz 25 MHz 6.25 03FFh 12 bits 6.1 kHz 25 MHz 6.25 FFh 10 bits 24.4 kHz 10 MHz 2.5 0FFFh 14 bits 610 Hz 10 MHz 2.5 03FFh 12 bits 2.4 kHz 10 MHz 2.5 FFh 10 bits 9.8 kHz 5 MHz 1.25 0FFFh 14 bits 305 Hz 5 MHz 1.25 03FFh 12 bits 1.2 kHz 5 MHz 1.25 FFh 10 bits 4.9 kHz 4 MHz 1 0FFFh 14 bits 244 Hz 4 MHz 1 03FFh 12 bits 976 Hz 4 MHz 1 FFh 10 bits 3.9 kHz Note: 2010 Microchip Technology Inc. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS PWM Frequency = 1/TPWM The PWM period can be calculated from the following formulas: EQUATION 18-1: PWM RESOLUTION For center-aligned operation, PWM frequencies will be approximately 1/2 the value indicated in the table. DS39616D-page 185 PIC18F2331/2431/4331/4431 FIGURE 18-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE Period Value Loaded from PTPER Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 4 3 4 3 3 2 2 2 1 1 1 0 0 0 New Value Written to PTPER Register FIGURE 18-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE Period Value Loaded from PTPER Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 3 2 1 0 4 3 3 2 2 1 1 0 6 5 4 3 2 1 0 New Value Written to PTPER Register DS39616D-page 186 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.6 PWM Duty Cycle PWM duty cycle is defined by the PDCx (PDCxL and PDCxH) registers. There are a total of four PWM Duty Cycle registers for four pairs of PWM channels. The Duty Cycle registers have 14-bit resolution by combining six LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a double-buffered register used to set the counting period for the PWM time base. 18.6.1 PWM DUTY CYCLE REGISTERS There are four 14-bit Special Function Registers used to specify duty cycle values for the PWM module: * * * * PDC0 (PDC0L and PDC0H) PDC1 (PDC1L and PDC1H) PDC2 (PDC2L and PDC2H) PDC3 (PDC3L and PDC3H) The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx holds the actual duty cycle value from PTMRH/L<11:0>, while the lower 2 bits control which internal Q clock the duty cycle match will occur. This 2-bit value is decoded from the Q clocks as shown in Figure 18-11 (when the prescaler is 1:1 or PTCKPS<1:0> = 00). In Edge-Aligned mode, the PWM period starts at Q1 and ends when the Duty Cycle register matches the PTMR register as follows. The duty cycle match is considered when the upper 12 bits of the PDCx are equal to the PTMR and the lower 2 bits are equal to Q1, Q2, Q3 or Q4, depending on the lower two bits of the PDCx (when the prescaler is 1:1 or PTCKPS<1:0> = 00). Note: When the prescaler is not 1:1 (PTCKPS<1:0> ~00), the duty cycle match occurs at the Q1 clock of the instruction cycle when the PTMR and PDCx match occurs. Each compare unit has logic that allows override of the PWM signals. This logic also ensures that the PWM signals will complement each other (with dead-time insertion) in Complementary mode (see Section 18.7 "Dead-Time Generators"). FIGURE 18-11: DUTY CYCLE COMPARISON PTMRH<7:0> PTMRL<7:0> PTMR<11:0> PTMRH<3:0> PTMRL<7:0> Unused Q Clocks(1) <1:0> Comparator Unused PDCxH<5:0> PDCxL<7:0> PDCx<13:0> PDCxH<7:0> PDCxL<7:0> Note 1: This value is decoded from the Q clocks: 00 = duty cycle match occurs on Q1 01 = duty cycle match occurs on Q2 10 = duty cycle match occurs on Q3 11 = duty cycle match occurs on Q4 2010 Microchip Technology Inc. DS39616D-page 187 PIC18F2331/2431/4331/4431 18.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period. In Edge-Aligned PWM Output mode, a new duty cycle value will be updated whenever a PTMR match with the PTPER register occurs and PTMR is reset as shown in Figure 18-12. Also, the contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). When the PWM time base is in the Continuous Up/Down Count mode, new duty cycle values will be updated when the value of the PTMR register is zero and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). Figure 18-13 shows the timings when the duty cycle update occurs for the Continuous Up/Down Count mode. In this mode, up to one entire PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. When the PWM time base is in the Continuous Up/Down Count mode with double updates, new duty cycle values will be updated when the value of the PTMR register is zero and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers during both of the previously described conditions. Figure 18-14 shows the duty cycle updates for Continuous Up/Down Count mode with double updates. In this mode, only up to half of a PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. FIGURE 18-13: 18.6.3 EDGE-ALIGNED PWM Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free-Running mode or the Single-Shot mode. For edge-aligned PWM outputs, the output for a given PWM channel has a period specified by the value loaded in PTPER and a duty cycle specified by the appropriate Duty Cycle register (see Figure 18-12). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the Duty Cycle register matches PTMR. A new cycle is started when PTMR matches the PTPER as explained in the PWM period section. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is greater than the value held in the PTPER register. FIGURE 18-12: EDGE-ALIGNED PWM New Duty Cycle Latched PTPER PDCx (old) PTMR Value PDCx (new) 0 Duty Cycle Active at Beginning of Period Period DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE Duty Cycle Value Loaded from Buffer Register PWM Output PTMR Value New Value Written to Duty Cycle Buffer DS39616D-page 188 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-14: DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES Duty Cycle Value Loaded from Buffer Register PWM Output PTMR Value New Values Written to Duty Cycle Buffer 18.6.4 CENTER-ALIGNED PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see Figure 18-15). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output will be driven to the inactive state when the PWM time base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be FIGURE 18-15: inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register. Note: When the PWM is started in Center-Aligned mode, the PWM Time Base Period register (PTPER) is loaded into the PWM Time Base register (PTMR) and the PTMR is configured automatically to start down counting. This is done to ensure that all the PWM signals don't start at the same time. START OF CENTER-ALIGNED PWM Period/2 PTPER Duty Cycle PTMR Value 0 Start of First PWM Period Duty Cycle Period 2010 Microchip Technology Inc. Period DS39616D-page 189 PIC18F2331/2431/4331/4431 PWM5 3-Phase Load PWM4 PWM3 Each upper/lower power switch pair is fed by a complementary PWM signal. Dead time may be optionally inserted during device switching, where both outputs are inactive for a short period (see Section 18.7 "Dead-Time Generators"). TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS +V PWM2 The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 18-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or a 3-phase Uninterruptible Power Supply (UPS) control applications. FIGURE 18-16: PWM1 COMPLEMENTARY PWM OPERATION PWM0 18.6.5 In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: * * * * PDC0 register controls PWM1/PWM0 outputs PDC1 register controls PWM3/PWM2 outputs PDC2 register controls PWM5/PWM4 outputs PDC3 register controls PWM7/PWM6 outputs PWM1/3/5/7 are the main PWMs that are controlled by the PDCx registers and PWM0/2/4/6 are the complemented outputs. When using the PWMs to control the half bridge, the odd numbered PWMs can be used to control the upper power switch and the even numbered PWMs used for the lower switches. DS39616D-page 190 The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.7 18.7.1 Dead-Time Generators In power inverter applications, where the PWMs are used in Complementary mode to control the upper and lower switches of a half-bridge, a dead-time insertion is highly recommended. The dead-time insertion keeps both outputs in inactive state for a brief time. This avoids any overlap in the switching during the state change of the power devices due to TON and TOFF characteristics. Because the power output devices cannot switch instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. The PWM module allows dead time to be programmed. The following sections explain the dead-time block in detail. FIGURE 18-17: Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead-time insertion. As shown in Figure 18-17, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. The dead time is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. A timing diagram, indicating the dead-time insertion for one pair of PWM outputs, is shown in Figure 18-18. DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR Dead Time Select Bits FOSC DEAD-TIME INSERTION Zero Compare Clock Control and Prescaler 6-Bit Down Counter Odd PWM Signal to Output Control Block Dead Time Prescale Even PWM Signal to Output Control Block Dead-Time Register Duty Cycle Compare Input FIGURE 18-18: DEAD-TIME INSERTION FOR COMPLEMENTARY PWM td td PDC1 Compare Output PWM1 PWM0 2010 Microchip Technology Inc. DS39616D-page 191 PIC18F2331/2431/4331/4431 REGISTER 18-5: DTCON: DEAD-TIME CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 DTPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit is FOSC/16 10 = Clock source for dead-time unit is FOSC/8 01 = Clock source for dead-time unit is FOSC/4 00 = Clock source for dead-time unit is FOSC/2 bit 5-0 DT<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit bits 18.7.2 DEAD-TIME RANGES The amount of dead time provided by the dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value defined in the DTCON register. Four input clock prescaler selections have been provided to allow a suitable range of dead times based on the device operating frequency. FOSC/2, FOSC/4, FOSC/8 and FOSC/16 are the clock prescaler options available using the DTPS<1:0> control bits in the DTCON register. After selecting an appropriate prescaler value, the dead time is adjusted by loading a 6-bit unsigned value into DTCON<5:0>. The dead-time unit prescaler is cleared on any of the following events: * On a load of the down timer due to a duty cycle comparison edge event; * On a write to the DTCON register; or * On any device Reset. 18.7.3 DECREMENTING THE DEAD-TIME COUNTER The dead-time counter is clocked from any of the Q clocks based on the following conditions. 1. 2. 3. 4. DS39616D-page 192 x = Bit is unknown The dead-time counter is clocked on Q1 when: * The DTPS bits are set to any of the following dead-time prescaler settings: FOSC/4, FOSC/8, FOSC/16 * The PWM Time Base Prescale bits (PTCKPS) are set to any of the following prescale ratios: FOSC/16, FOSC/64, FOSC/256 The dead-time counter is clocked by a pair of Q clocks when the PWM Time Base Prescale bits are set to 1:1 (PTCKPS<1:0> = 00, FOSC/4) and the dead-time counter is clocked by the FOSC/2 (DTPS<1:0> = 00). The dead-time counter is clocked using every other Q clock, depending on the two LSbs in the Duty Cycle registers: * If the PWM duty cycle match occurs on Q1 or Q3, then the dead-time counter is clocked using every Q1 and Q3. * If the PWM duty cycle match occurs on Q2 or Q4, then the dead-time counter is clocked using every Q2 and Q4. When the DTPS<1:0> bits are set to any of the other dead-time prescaler settings (i.e., FOSC/4, FOSC/8 or FOSC/16) and the PWM time base prescaler is set to 1:1, the dead-time counter is clocked by the Q clock corresponding to the Q clocks on which the PWM duty cycle match occurs. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The actual dead time is calculated from the DTCON register as follows: Dead Time = Dead-Time Value/(FOSC/Prescaler) Table 18-3 shows example dead-time ranges as a function of the input clock prescaler selected and the device operating frequency. TABLE 18-3: EXAMPLE DEAD-TIME RANGES Prescaler Dead-Time Dead-Time FOSC MIPS (MHz) Selection Min Max 40 10 FOSC/2 50 ns 3.2 s 40 10 FOSC/4 100 ns 6.4 s 40 10 FOSC/8 200 ns 12.8 s 40 10 FOSC/16 400 ns 25.6 s 32 8 FOSC/2 62.5 ns 4 s 32 8 FOSC/4 125 ns 8 s 32 8 FOSC/8 250 ns 16 s 32 8 FOSC/16 500 ns 32 s 25 6.25 FOSC/2 80 ns 5.12 s 25 6.25 FOSC/4 160 ns 10.2 s 25 6.25 FOSC/8 320 ns 20.5 s 25 6.25 FOSC/16 640 ns 41 s 20 5 FOSC/2 100 ns 6.4 s 20 5 FOSC/4 200 ns 12.8 s 20 5 FOSC/8 400 ns 25.6 s 20 5 FOSC/16 800 ns 51.2 s 18.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM module. The user can ensure that dead-time distortion is minimized by keeping the PWM duty cycle at least three times larger than the dead time. A similar effect occurs for duty cycles at or near 100%. The maximum duty cycle used in the application should be chosen such that the minimum inactive time of the signal is at least three times larger than the dead time. If the dead time is greater or equal to the duty cycle of one of the PWM output pairs, then that PWM pair will be inactive for the whole period. 2: Changing the dead-time values in DTCON when the PWM is enabled may result in an undesired situation. Disable the PWM (PTEN = 0) before changing the dead-time value 18.8 Independent PWM Output 10 2.5 FOSC/2 200 ns 12.8 s 10 2.5 FOSC/4 400 ns 25.6 s 10 2.5 FOSC/8 800 ns 51.2 s 10 2.5 FOSC/16 1.6 s 102.4 s Independent PWM mode is used for driving the loads (as shown in Figure 18-19) for driving one winding of a switched reluctance motor. A particular PWM output pair is configured in the Independent Output mode when the corresponding PMOD bit in the PWMCON0 register is set. No dead-time control is implemented between the PWM I/O pins when the module is operating in the Independent PWM mode and both I/O pins are allowed to be active simultaneously. This mode can also be used to drive stepper motors. 5 1.25 FOSC/2 400 ns 25.6 s 1.25 FOSC/4 800 ns 51.2 s 18.8.1 5 5 1.25 FOSC/8 1.6 s 102.4 s 5 1.25 FOSC/16 3.2 s 204.8 s 4 1 FOSC/2 0.5 s 32 s 4 1 FOSC/4 1 s 64 s 4 1 FOSC/8 2 s 128 s 4 1 FOSC/16 4 s 256 s 2010 Microchip Technology Inc. DUTY CYCLE ASSIGNMENT IN THE INDEPENDENT PWM MODE In the Independent PWM mode, each duty cycle generator is connected to both PWM output pins in a given PWM output pair. The odd and even PWM output pins are driven with a single PWM duty cycle generator. PWM1 and PWM0 are driven by the PWM channel which uses the PDC0 register to set the duty cycle, PWM3 and PWM2 with PDC1, PWM5 and PWM4 with PDC2, and PWM7 and PWM6 with PDC3 (see Figure 18-3 and Register 18-4). DS39616D-page 193 PIC18F2331/2431/4331/4431 18.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: * I/O pin outputs PWM signal * I/O pin inactive * I/O pin active Refer to Section 18.10 "PWM Output Override" for details for all the override functions. FIGURE 18-19: CENTER CONNECTED LOAD +V PWM1 Load PWM0 18.9 Single-Pulse PWM Operation The single-pulse PWM operation is available only in Edge-Aligned mode. In this mode, the PWM module will produce single-pulse output. Single-pulse operation is configured when the PTMOD<1:0> bits are set to `01' in the PTCON0 register. This mode of operation is useful for driving certain types of ECMs. In Single-Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When the PWM timer match with the Duty Cycle register occurs, the PWM I/O pin is driven to the inactive state. When the PWM timer match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated if the corresponding interrupt bit is set. Note: PTPER and PDCx values are held as they are after the single-pulse output. To have another cycle of single pulse, only PTEN has to be enabled. 18.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units. The PWM override bits are useful when controlling various types of ECMs like a BLDC motor. DS39616D-page 194 OVDCOND and OVDCONS registers are used to define the PWM override options. The OVDCOND register contains eight bits, POVD<7:0>, that determine which PWM I/O pins will be overridden. The OVDCONS register contains eight bits, POUT<7:0>, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. The POVD bits are active-low control bits. When the POVD bits are set, the corresponding POUT bit will have no effect on the PWM output. In other words, the pins corresponding to POVD bits that are set will have the duty PWM cycle set by the PDCx registers. When one of the POVD bits is cleared, the output on the corresponding PWM I/O pin will be determined by the state of the POUT bit. When a POUT bit is set, the PWM pin will be driven to its active state. When the POUT bit is cleared, the PWM pin will be driven to its inactive state. 18.10.1 COMPLEMENTARY OUTPUT MODE The even numbered PWM I/O pins have override restrictions when a pair of PWM I/O pins are operating in the Complementary mode (PMODx = 0). In Complementary mode, if the even numbered pin is driven active by clearing the corresponding POVD bit and by setting POUT bits in the OVDCOND and OVDCONS registers, the output signal is forced to be the complement of the odd numbered I/O pin in the pair (see Figure 18-2 for details). 18.10.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMCON1 register is set, all output overrides performed via the OVDCOND and OVDCONS registers will be synchronized to the PWM time base. Synchronous output overrides will occur on the following conditions: * When the PWM is in Edge-Aligned mode, synchronization occurs when PTMR is zero. * When the PWM is in Center-Aligned mode, synchronization occurs when PTMR is zero and when the value of PTMR matches PTPER. Note 1: In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active. The even channel is always the complement of the odd channel with dead time inserted, before the odd channel can be driven to its active state, as shown in Figure 18-20. 2: Dead time is inserted in the PWM channels even when they are in Override mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-20: PWM OVERRIDE BITS IN COMPLEMENTARY MODE 1 POUT0 POUT1 4 5 3 6 PWM1 2 PWM0 7 Assume: POVD0 = 0; POVD1 = 0; PMOD0 = 0 1. 2. 3. 4. 5. 6. 7. Even override bits have no effect in Complementary mode. Odd override bit is activated, which causes the even PWM to deactivate. Dead-time insertion. Odd PWM activated after the dead time. Odd override bit is deactivated, which causes the odd PWM to deactivate. Dead-time insertion. Even PWM is activated after the dead time. 2010 Microchip Technology Inc. DS39616D-page 195 PIC18F2331/2431/4331/4431 18.10.3 OUTPUT OVERRIDE EXAMPLES Figure 18-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 18-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In this example, the PWM outputs are driven to specific logic states. The OVDCOND and OVDCONS register values used to generate the signals in Figure 18-21 are given in Table 18-4. REGISTER 18-6: The PWM Duty Cycle registers may be used in conjunction with the OVDCOND and OVDCONS registers. The Duty Cycle registers control the average voltage across the load and the OVDCOND and OVDCONS registers control the commutation sequence. Figure 18-22 shows the waveforms, while Table 18-4 and Table 18-5 show the OVDCOND and OVDCONS register values used to generate the signals. OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 POVD7(1) POVD6(1) POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown POVD<7:0>: PWM Output Override bits 1 = Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM time base 0 = Output on PWM I/O pin is controlled by the value in the corresponding POUT bit Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. REGISTER 18-7: OVDCONS: OUTPUT STATE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POUT7(1) POUT6(1) POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: 2: x = Bit is unknown POUT<7:0>: PWM Manual Output bits 1 = Output on PWM I/O pin is active when the corresponding PWM output override bit is cleared 0 = Output on PWM I/O pin is inactive when the corresponding PWM output override bit is cleared Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. With PWMs configured in Complementary mode, the output of even numbered PWM (PM0,2,4) will be complementary of the output of odd PWM (PWM1,3,5), irrespective of the POUT bit setting. DS39616D-page 196 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-21: 1 PWM OUTPUT OVERRIDE EXAMPLE #1 2 3 4 5 FIGURE 18-22: 6 PWM OUTPUT OVERRIDE EXAMPLE #2 1 2 3 4 PWM5 PWM4 PWM7 PWM3 PWM2 PWM6 PWM1 PWM0 PWM5 PWM4 TABLE 18-4: State PWM OUTPUT OVERRIDE EXAMPLE #1 PWM3 OVDCOND (POVD) OVDCONS (POUT) 1 00000000b 00100100b 2 00000000b 00100001b 3 00000000b 00001001b 4 00000000b 00011000b 5 00000000b 00010010b 6 00000000b 00000110b TABLE 18-5: PWM2 PWM1 PWM0 PWM OUTPUT OVERRIDE EXAMPLE #2 State OVDCOND (POVD) OVDCONS (POUT) 1 11000011b 00000000b 2 11110000b 00000000b 3 00111100b 00000000b 4 00001111b 00000000b 2010 Microchip Technology Inc. DS39616D-page 197 PIC18F2331/2431/4331/4431 18.11 PWM Output and Polarity Control 18.11.2 There are three device Configuration bits associated with the PWM module that provide PWM output pin control defined in the CONFIG3L Configuration register. They are: The polarity of the PWM I/O pins is set during device programming via the HPOL and LPOL Configuration bits in the CONFIG3L Configuration register. The HPOL Configuration bit sets the output polarity for the high side PWM outputs: PWM1, PWM3, PWM5 and PWM7. The polarity is active-low when HPOL is cleared (= 0), and active-high when it is set (= 1). * HPOL * LPOL * PWMPIN The LPOL Configuration bit sets the output polarity for the low side PWM outputs: PWM0, PWM2, PWM4 and PWM6. As with HPOL, they are active-low when LPOL is cleared and active-high when it is set. These three Configuration bits work in conjunction with the three PWM Enable bits (PWMEN<2:0>) in the PWMCON0 register. The Configuration bits and PWM enable bits ensure that the PWM pins are in the correct states after a device Reset occurs. 18.11.1 All output signals generated by the PWM module are referenced to the polarity control bits, including those generated by Fault inputs or manual override (see Section 18.10 "PWM Output Override"). OUTPUT PIN CONTROL The PWMEN<2:0> control bits enable each PWM output pin as required in the application. The default polarity Configuration bits have the PWM I/O pins in active-high output polarity. All PWM I/O pins are general purpose I/O. When a pair of pins are enabled for PWM output, the PORT and TRIS registers controlling the pins are disabled. Refer to Figure 18-23 for details. FIGURE 18-23: OUTPUT POLARITY CONTROL PWM I/O PIN BLOCK DIAGRAM PWM Signal from Module 1 0 PWM Pin Enable Data Bus WR PORT D CK Q VDD Q P Data Latch D WR TRIS CK I/O Pin Q N Q VSS TRIS Latch TTL or Schmitt Trigger RD TRIS Q D EN RD PORT Note: DS39616D-page 198 I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.11.3 PWM OUTPUT PIN RESET STATES The PWMPIN Configuration bit determines the PWM output pins to be PWM output pins or digital I/O pins, after the device comes out of Reset. If the PWMPIN Configuration bit is unprogrammed (default), the PWMEN<2:0> control bits will be cleared on a device Reset. Consequently, all PWM outputs will be tri-stated and controlled by the corresponding PORT and TRIS registers. If the PWMPIN Configuration bit is programmed low, the PWMEN<2:0> control bits will be set, as follows, on a device Reset: * PWMEN<2:0> = 101 if device has 8 PWM pins (PIC18F4331/4431 devices) * PWMEN<2:0> = 100 if device has 6 PWM pins (PIC18F2331/2431 devices) All PWM pins will be enabled for PWM output and will have the output polarity defined by the HPOL and LPOL Configuration bits. 18.12 PWM Fault Inputs There are two Fault inputs associated with the PWM module. The main purpose of the input Fault pins is to disable the PWM output signals and drive them into an inactive state. The action of the Fault inputs is performed directly in hardware so that when a Fault occurs, it can be managed quickly and the PWM outputs are put into an inactive state to save the power devices connected to the PWMs. The PWM Fault inputs are FLTA and FLTB, which can come from I/O pins, the CPU or another module. The FLTA and FLTB pins are active-low inputs so it is easy to "OR" many sources to the same input. FLTB and its associated logic are not implemented on PIC18F2331/2431 devices. 18.12.1 FAULT PIN ENABLE BITS By setting the bits, FLTAEN and FLTBEN in the FLTCONFIG register, the corresponding Fault inputs are enabled. If both bits are cleared, then the Fault inputs have no effect on the PWM module. 18.12.2 MFAULT INPUT MODES The FLTAMOD and FLTBMOD bits in the FLTCONFIG register determine the modes of PWM I/O pins that are deactivated when they are overridden by Fault input. The FLTAS and FLTBS bits in the FLTCONFIG register give the status of Fault A and Fault B inputs. Each of the Fault inputs have two modes of operation: * Inactive Mode (FLTxMOD = 0) This is a Catastrophic Fault Management mode. When the Fault occurs in this mode, the PWM outputs are deactivated. The PWM pins will remain in Inactivate mode until the Fault is cleared (Fault input is driven high) and the corresponding Fault Status bit has been cleared in software. The PWM outputs are enabled immediately at the beginning of the following PWM period, after the Fault Status bit (FLTxS) is cleared. * Cycle-by-Cycle Mode (FLTxMOD = 1) When the Fault occurs in this mode, the PWM outputs are deactivated. The PWM outputs will remain in the defined Fault states (all PWM outputs inactive) for as long as the Fault pin is held low. After the Fault pin is driven high, the PWM outputs will return to normal operation at the beginning of the following PWM period and the FLTxS bit is automatically cleared. The FLTCONFIG register (Register 18-8) defines the settings of FLTA and FLTB inputs. Note: The inactive state of the PWM pins are dependent on the HPOL and LPOL Configuration bit settings, which define the active and inactive state for PWM outputs. 2010 Microchip Technology Inc. DS39616D-page 199 PIC18F2331/2431/4331/4431 18.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., one or both FLTA and FLTB inputs are active), the PWM output signals are driven into their inactive states. The selection of which PWM outputs are deactivated (while in the Fault state) is determined by the FLTCON bit in the FLTCONFIG register as follows: * FLTCON = 1: When FLTA or FLTB is asserted, the PWM outputs (i.e., PWM<7:0>) are driven into their inactive state. * FLTCON = 0: When FLTA or FLTB is asserted, only PWM<5:0> outputs are driven inactive, leaving PWM<7:6> activated. Note: Disabling only three PWM channels and leaving one PWM channel enabled when in the Fault state, allows the flexibility to have at least one PWM channel enabled. None of the PWM outputs can be enabled (driven with the PWM Duty Cycle registers) while FLTCON = 1 and the Fault condition is present. DS39616D-page 200 18.12.4 PWM OUTPUTS IN DEBUG MODE The BRFEN bit in the FLTCONFIG register controls the simulation of a Fault condition, when a breakpoint is hit, while debugging the application using an In-Circuit Emulator (ICE) or an In-Circuit Debugger (ICD). Setting the BRFEN to high, enables the Fault condition on breakpoint, thus driving the PWM outputs to the inactive state. This is done to avoid any continuous keeping of status on the PWM pin, which may result in damage of the power devices connected to the PWM outputs. If BRFEN = 0, the Fault condition on breakpoint is disabled. Note: It is highly recommended to enable the Fault condition on breakpoint if a debugging tool is used while developing the firmware and high-power circuitry. When the device is ready to program after debugging the firmware, the BRFEN bit can be disabled. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 18-8: R/W-0 BRFEN FLTCONFIG: FAULT CONFIGURATION REGISTER R/W-0 (1) FLTBS R/W-0 R/W-0 (1) FLTBMOD (1) FLTBEN R/W-0 (2) FLTCON R/W-0 R/W-0 R/W-0 FLTAS FLTAMOD FLTAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 BRFEN: Breakpoint Fault Enable bit 1 = Enable Fault condition on a breakpoint (i.e., only when PWMPIN = 1) 0 = Disable Fault condition bit 6 FLTBS: Fault B Status bit(1) 1 = FLTB is asserted: if FLTBMOD = 0, cleared by the user; if FLTBMOD = 1, cleared automatically at beginning of the new period when FLTB is deasserted 0 = No Fault bit 5 FLTBMOD: Fault B Mode bit(1) 1 = Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTB is deasserted; FLTBS is cleared automatically when FLTB is inactive (no Fault present) 0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTB is deasserted and FLTBS is cleared by the user only bit 4 FLTBEN: Fault B Enable bit(1) 1 = Enable Fault B 0 = Disable Fault B bit 3 FLTCON: Fault Configuration bit(2) 1 = FLTA, FLTB or both deactivates all PWM outputs 0 = FLTA or FLTB deactivates PWM<5:0> bit 2 FLTAS: Fault A Status bit 1 = FLTA is asserted: if FLTAMOD = 0, cleared by the user; if FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is deasserted 0 = No Fault bit 1 FLTAMOD: Fault A Mode bit 1 = Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTA is deasserted; FLTAS is cleared automatically 0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is cleared by the user only bit 0 FLTAEN: Fault A Enable bit 1 = Enable Fault A 0 = Disable Fault A Note 1: 2: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. PWM<7:6> are implemented only on PIC18F4331/4431 devices. On PIC18F2331/2431 devices, setting or clearing FLTCON has no effect. 2010 Microchip Technology Inc. DS39616D-page 201 PIC18F2331/2431/4331/4431 18.13 PWM Update Lockout For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. A PWM update lockout feature may optionally be enabled so the user may specify when new duty cycle buffer values are valid. The PWM update lockout feature is enabled by setting the control bit, UDIS, in the PWMCON1 register. This bit affects all Duty Cycle Buffer registers and the PWM Time Base Period register, PTPER. To perform a PWM update lockout: 1. 2. 3. 4. Set the UDIS bit. Write all Duty Cycle registers and PTPER, if applicable. Clear the UDIS bit to re-enable updates. With this, when UDIS bit is cleared, the buffer values will be loaded to the actual registers. This makes a synchronous loading of the registers. 18.14 PWM Special Event Trigger The PWM module has a Special Event Trigger capability that allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The Special Event Trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. The PTMR value for which a Special Event Trigger should occur is loaded into the SEVTCMP register pair. The SEVTDIR bit in the PWMCON1 register specifies the counting phase when the PWM time base is in a Continuous Up/Down Count mode. If the SEVTDIR bit is cleared, the Special Event Trigger will occur on the upward counting cycle of the PWM time base. If SEVTDIR is set, the Special Event Trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR bit has effect only when the PWM timer is in the Continuous Up/Down Count mode. 18.14.1 SPECIAL EVENT TRIGGER ENABLE The PWM module will always produce Special Event Trigger pulses. This signal may optionally be used by the A/D module. Refer to Section 21.0 "10-Bit High-Speed Analog-to-Digital Converter (A/D) Module" for details. 18.14.2 SPECIAL EVENT TRIGGER POSTSCALER The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS<3:0> control bits in the PWMCON1 register. The Special Event Trigger output postscaler is cleared on any write to the SEVTCMP register pair, or on any device Reset. The PWM 16-bit Special Event Trigger register, SEVTCMP (high and low), and five control bits in the PWMCON1 register are used to control its operation. DS39616D-page 202 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 18-6: Name INTCON REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 IPR3 -- -- -- PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 -- -- -- PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 IC3DRIF IC2QEIF IC1IF TMR5IF 56 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 58 -- -- -- PTIF PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCON1 PTEN PTDIR -- -- PIR3 PTMRL(1) -- -- -- -- PWM Time Base Register (lower 8 bits) PTMRH(1) 58 UNUSED PTPERL(1) PWM Time Base Register (upper 4 bits) 58 PWM Time Base Period Register (upper 4 bits) 58 PWM Time Base Period Register (lower 8 bits) PTPERH(1) UNUSED 58 SEVTCMPL(1) PWM Special Event Compare Register (lower 8 bits) (1) SEVTCMPH PWMCON0 PWMCON1 DTCON 58 PWM Special Event Compare Register (upper 4 bits) UNUSED 58 PWMEN2 PWMEN1 PWMEN0 PMOD3(2) PMOD2 PMOD1 PMOD0 58 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR -- UDIS OSYNC 58 DT5 DT4 DT3 DT2 DT1 DT0 58 FLTBMOD(2) FLTBEN(2) -- DTPS1 DTPS0 (2) FLTCONFIG BRFEN FLTCON FLTAS OVDCOND POVD7(2) POVD6(2) POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 OVDCONS POUT7(2) POUT6(2) POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 (1) PDC0L PDC0H(1) (1) PDC1L PDC1H(1) PDC2L(1) PDC2H(1) PDC3L(1,2) PDC3H(1,2) Legend: Note 1: 2: 58 FLTBS FLTAMOD FLTAEN PWM Duty Cycle #0L Register (lower 8 bits) UNUSED PWM Duty Cycle #0H Register (upper 6 bits) 58 58 PWM Duty Cycle #1H Register (upper 6 bits) 58 PWM Duty Cycle #2L Register (lower 8 bits) UNUSED 58 PWM Duty Cycle #2H Register (upper 6 bits) 58 PWM Duty Cycle #3L Register (lower 8 bits) UNUSED 58 58 PWM Duty Cycle #1L register (lower 8 bits) UNUSED 58 58 58 PWM Duty Cycle #3H Register (upper 6 bits) 58 -- = Unimplemented, read as `0'. Shaded cells are not used with the power control PWM. Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Reset values shown are for PIC18F4331/4431 devices. 2010 Microchip Technology Inc. DS39616D-page 203 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 204 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.0 19.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) An overview of information on the "PIC(R) Mid-Range (DS33023). I2C operations and additional SSP module can be found in the MCU Family Reference Manual" Refer to application note AN578, "Use of the SSP Module in the I 2CTM Multi-Master Environment" (DS00578). 19.2 SPI Mode This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON (SSPCON<5:0>) and SSPSTAT<7:6> registers. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock rate (Master mode only) * Slave Select mode (Slave mode only) 2010 Microchip Technology Inc. DS39616D-page 205 PIC18F2331/2431/4331/4431 REGISTER 19-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Edge Select bit (Figure 19-2, Figure 19-3 and Figure 19-4) SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK I2 CTM mode: This bit must be maintained clear. bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled or when the Start bit is detected last; SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled or when the Stop bit is detected last; SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-Bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS39616D-page 206 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 19-2: R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER R/W-0 SSPOV(1) R/W-0 SSPEN(2) W = Writable bit `1' = Bit is set R/W-0 CKP R/W-0 SSPM3(3) R/W-0 SSPM2(3) R/W-0 SSPM1(3) R/W-0 SSPM0(3) bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2CTM mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit(2) In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode: SCK release control. 1 = Enables clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 6 bit 5 bit 4 Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as inputs or outputs. Bit combinations not specifically listed here are either reserved or implemented in I2CTM mode only. 2010 Microchip Technology Inc. DS39616D-page 207 PIC18F2331/2431/4331/4431 REGISTER 19-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (CONTINUED) SSPM<3:0>: Synchronous Serial Port Mode Select bits(3) 0000 = SPI Master mode, Clock = FOSC/4 0001 = SPI Master mode, Clock = FOSC/16 0010 = SPI Master mode, Clock = FOSC/64 0011 = SPI Master mode, Clock = TMR2 output/2 0100 = SPI Slave mode, Clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, Clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C Firmware Controlled Master mode (slave Idle) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled bit 3-0 Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as inputs or outputs. Bit combinations not specifically listed here are either reserved or implemented in I2CTM mode only. DS39616D-page 208 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 19-1: SSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read Write SSPBUF Reg * Serial Data Out (SDO) - RC7/RX/DT/SDO or RD1/SDO * SDI must have TRISC<4> or TRISD<2> set * SDO must have TRISC<7> or TRISD<1> cleared * SCK (Master mode) must have TRISC<5> or TRISD<3> cleared * SCK (Slave mode) must have TRISC<5> or TRISD<3> set * SS must have TRISA<6> set SSPSR Reg SDI SDO Shift Clock bit 0 Peripheral OE SS Control Enable SS Note 1: When the SPI is in Slave mode, with the SS pin control enabled, (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. Edge Select 2 Clock Select SSPM<3:0> 4 Edge Select SCK TRISC<3> 2010 Microchip Technology Inc. To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear bit SSPEN, reinitialize the SSPCON register and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: TMR2 Output 2 Prescaler 4, 16, 64 TCY 2: If the SPI is used in Slave mode with CKE = 1, then the SS pin control must be enabled. 3: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the state of the SS pin can affect the state read back from the TRISC<6> bit. The peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<6> bit (see Section 11.3 "PORTC, TRISC and LATC Registers" for information on PORTC). If Read-Modify-Write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<6> bit to be set, thus disabling the SDO output. DS39616D-page 209 PIC18F2331/2431/4331/4431 FIGURE 19-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SDI (SMP = 1) bit 0 bit 7 SSPIF FIGURE 19-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF DS39616D-page 210 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 19-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 SSPIF TABLE 19-1: Name INTCON PIR1 PIE1 REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE -- ADIF RCIF -- ADIE RCIE TRISC PORTC Data Direction Register SSPBUF SSP Receive Buffer/Transmit Register SSPCON TRISA SSPSTAT WCOL (1) TRISA7 SMP SSPOV TRISA6(2) CKE SSPEN Bit 0 Reset Values on Page: INT0IF RBIF 54 TMR2IF TMR1IF 57 TMR1IE 57 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TMR2IE 57 55 CKP SSPM3 SSPM2 SSPM1 SSPM0 PORTA Data Direction Register D/A P S 55 57 R/W UA BF 55 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode. Note 1: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read `0' in all other oscillator modes. 2: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read `0' in all other oscillator modes. 2010 Microchip Technology Inc. DS39616D-page 211 PIC18F2331/2431/4331/4431 19.3 SSP I2 C Operation The SSP module, in I2C mode, fully implements all slave functions except general call support and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the SCK/ SCL pin, which is the clock (SCL), and the SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<5:4> or TRISD<3:2> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). FIGURE 19-5: SSP BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read MSb LSb Match Detect Addr Match SSPADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT Reg) When SSPMX = 1 in CONFIG3H: SCK/SCL is multiplexed to the RC5 pin, SDA/ SDI is multiplexed to the RC4 pin and SDO is multiplexed to pin, RC7. When SSPMX = 0 in CONFIG3H: SCK/SCL is multiplexed to the RD3 pin, SDA/ SDI is multiplexed to the RD2 pin and SDO is multiplexed to pin, RD1. The SSP module has five registers for I2C operation. These are the: * * * * SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) DS39616D-page 212 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<5:4> or TRISD<3:2> set). The SSP module will override the input state with the output data when required (slave-transmitter). SSPSR Reg Note 1: Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISC or TRISD bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. 19.3.1 Shift Clock SDI/SDA(1) * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled to support Firmware Controlled Master mode * I 2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled to support Firmware Controlled Master mode * I 2C Start and Stop bit interrupts enabled to support Firmware Controlled Master mode; Slave is Idle Additional information on SSP I 2C operation can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). Write SSPBUF Reg SCK/SCL(1) The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): a) b) The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received. The SSP Overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF (PIR1<3>), is set. Table 19-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit, BF, is cleared by reading the SSPBUF register, while bit, SSPOV, is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirements of the SSP module, are shown in timing Parameter 100 and Parameter 101. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.3.1.1 Addressing Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. In 10-Bit Addressing mode, two address bytes need to be received by the slave (Figure 19-7). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. TABLE 19-2: The sequence of events for 10-Bit Addressing mode is as follows, with Steps 7-9 for slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of address (SSPIF, BF and UA bits are set). Update the SSPADD register with second (low) byte of address (clears bit, UA, and releases the SCL line). Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. Receive second (low) byte of address (SSPIF, BF and UA bits are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit, UA. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (SSPIF and BF bits are set). Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR SSPBUF Generate ACK Pulse Set SSPIF Bit (SSP interrupt occurs if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 1 No No Yes 0 Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 2010 Microchip Technology Inc. DS39616D-page 213 PIC18F2331/2431/4331/4431 19.3.1.2 Reception When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user's firmware. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. I 2CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 19-6: Receiving Address SDA SCL R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 S 1 2 3 SSPIF (PIR1<3>) BF (SSPSTAT<0>) 4 5 6 7 8 9 Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 Cleared in software 8 9 P Bus master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) SSPOV bit is set because the SSPBUF register is still full ACK is not sent DS39616D-page 214 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.3.1.3 Transmission An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF, must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit, SSPIF, is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin, SCK/SCL, is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin, SCK/SCL, should be enabled by setting bit, CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 19-7). I 2CTM WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 19-7: Receiving Address SDA SCL A7 S As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin, SCK/SCL, should be enabled by setting bit CKP. R/W = 1 A6 A5 A4 A3 A2 A1 1 2 Data in sampled 3 4 5 6 7 SSPIF (PIR1<3>) Transmitting Data ACK 8 9 D7 1 SCL held low while CPU responds to SSPIF ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Cleared in software BF (SSPSTAT<0>) SSPBUF is written in software From SSP Interrupt Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (SSPBUF must be written to before the CKP bit can be set) 2010 Microchip Technology Inc. DS39616D-page 215 PIC18F2331/2431/4331/4431 19.3.2 MASTER MODE 19.3.3 Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle and both the S and P bits are clear. In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is Idle and both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<5:4> or TRISD<3:2> bits. The output level is always low, regardless of the value(s) in PORTC<5:4> or PORTD<3:2>. So when transmitting data, a `1' data bit must have the TRISC<4> bit set (input) and a `0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<4> or TRISD<2> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. In Multi-Master mode, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<5:4> or TRISD<3:2>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt will occur if enabled): When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time. * Start condition * Stop condition * Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode Idle (SSPM<3:0> = 1011) or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 19-3: Name INTCON PIR1 PIE1 SSPBUF SSPADD MULTI-MASTER MODE REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE -- ADIF RCIF -- ADIE RCIE Bit 1 Bit 0 Reset Values on Page: Bit 3 Bit 2 INT0IE RBIE TMR0IF INT0IF RBIF 54 TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 SSP Receive Buffer/Transmit Register SSP Address Register (I2 55 C mode) 55 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 55 SSPSTAT (1) CKE(1) D/A P S R/W UA BF 55 SMP TRISC(2) PORTC Data Direction Register TRISD(2) PORTD Data Direction Register 57 57 2C mode. Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the SSP module in I Note 1: Maintain these bits clear in I2C mode. 2: Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD. DS39616D-page 216 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules available in the PIC18F2331/ 2431/4331/4431 family of microcontrollers. EUSART is also known as a Serial Communications Interface or SCI. 20.1 The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The EUSART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The EUSART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network (LIN/J2602) bus systems. The EUSART can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half-duplex) with selectable clock polarity * Synchronous - Slave (half-duplex) with selectable clock polarity In order to configure pins, TX and RX, as the Enhanced Universal Synchronous Asynchronous Receiver Transmitter: These are detailed on the following pages in Register 20-1, Register 20-2 and Register 20-3, respectively. Asynchronous Operation in Power-Managed Modes The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 26-6). However, this frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6.4 "INTOSC Frequency Drift" for more information). The other method adjusts the value in the Baud Rate Generator (BRG). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. * SPEN (RCSTA<7>) bit must be set ( = 1), * TRISC<6> bit must be set ( = 1), and * TRISC<7> bit must be set ( = 1). Note: The EUSART control will automatically reconfigure the pin from input to output as needed. 2010 Microchip Technology Inc. DS39616D-page 217 PIC18F2331/2431/4331/4431 REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th Bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39616D-page 218 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-Bit (RX9 = 0): Don't care. bit 2 FERR: Framing Error bit 1 = Framing error (can be cleared by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th Bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2010 Microchip Technology Inc. DS39616D-page 219 PIC18F2331/2431/4331/4431 REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-1 R/W-0 U-0 R/W-0 R/W-0 -- RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receive in progress bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39616D-page 220 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.2 20.2.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 20-1 shows the formula for computation of the baud rate for different EUSART modes, which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 20-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 20-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 20-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG, to reduce the baud rate error or achieve a slow baud rate for a fast oscillator frequency. POWER-MANAGED MODE OPERATION The system clock is used to generate the desired baud rate. However, when a power-managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode, no clocks are present and in PRI_IDLE, the primary clock source continues to provide clocks to the Baud Rate Generator. However, in other powermanaged modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit and make sure that the receive operation is Idle before changing the system clock. 20.2.2 SAMPLING The data on the RC7/RX/DT/SDO pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 8-Bit/Asynchronous FOSC/[64 (n + 1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-Bit/Asynchronous 0 1 0 16-Bit/Asynchronous 0 1 1 16-Bit/Asynchronous 1 0 x 8-Bit/Synchronous 1 1 x 16-Bit/Synchronous FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair 2010 Microchip Technology Inc. DS39616D-page 221 PIC18F2331/2431/4331/4431 EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 BAUDCON SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- 1.221 2.441 1.73 255 9.615 0.16 64 19.2 19.531 1.73 57.6 56.818 115.2 125.000 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- -- -- 1.73 255 1.202 2.404 0.16 129 9.766 1.73 31 31 19.531 1.73 -1.36 10 62.500 8.51 4 104.167 Actual Rate (K) % Error 0.3 -- -- 1.2 -- 2.4 9.6 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- 0.16 129 1.201 -0.16 103 2.404 0.16 64 2.403 -0.16 51 9.766 1.73 15 9.615 -0.16 12 15 19.531 1.73 7 -- -- -- 8.51 4 52.083 -9.58 2 -- -- -- -9.58 2 78.125 -32.18 1 -- -- -- SPBRG value SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz (decimal) Actual Rate (K) 0.16 207 0.300 -0.16 103 0.300 -0.16 51 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.404 0.16 25 2.403 -0.16 12 -- -- -- 9.6 8.929 -6.99 6 -- -- -- -- -- -- 19.2 20.833 8.51 2 -- -- -- -- -- -- Actual Rate (K) % Error 0.3 0.300 1.2 1.202 2.4 SPBRG value % Error (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 57.6 62.500 8.51 0 -- -- -- -- -- -- 115.2 62.500 -45.75 0 -- -- -- -- -- -- DS39616D-page 222 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 2.4 -- -- -- -- -- -- 2.441 1.73 255 2.403 -0.16 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 207 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error -- -- -- 0.16 207 1.201 0.16 103 2.403 9.615 0.16 25 19.2 19.231 0.16 57.6 62.500 115.2 125.000 FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -- 0.300 -0.16 207 -0.16 103 1.201 -0.16 51 -0.16 51 2.403 -0.16 25 9.615 -0.16 12 -- -- -- 12 -- -- -- -- -- -- 8.51 3 -- -- -- -- -- -- 8.51 1 -- -- -- -- -- -- Actual Rate (K) % Error 0.3 -- -- 1.2 1.202 2.4 2.404 9.6 SPBRG value SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 1665 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 0.04 0.16 832 207 0.300 1.201 2.404 0.16 103 9.615 0.16 25 19.2 19.231 0.16 57.6 62.500 8.51 115.2 125.000 8.51 Actual Rate (K) % Error 0.3 1.2 0.300 1.202 2.4 9.6 2010 Microchip Technology Inc. FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -0.16 -0.16 415 103 0.300 1.201 -0.16 -0.16 207 51 2.403 -0.16 51 2.403 -0.16 25 9.615 -0.16 12 -- -- -- 12 -- -- -- -- -- -- 3 -- -- -- -- -- -- 1 -- -- -- -- -- -- SPBRG value SPBRG value SPBRG value (decimal) DS39616D-page 223 PIC18F2331/2431/4331/4431 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 33332 0.300 0.00 8332 1.200 2.400 0.02 4165 9.6 9.606 0.06 19.2 19.193 57.6 57.803 115.2 114.943 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 16665 0.300 0.02 4165 1.200 2.400 0.02 2082 1040 9.596 -0.03 -0.03 520 19.231 0.35 172 57.471 -0.22 86 116.279 0.94 Actual Rate (K) % Error 0.3 0.300 1.2 1.200 2.4 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 0.00 8332 0.300 -0.01 6665 0.02 2082 1.200 -0.04 1665 2.402 0.06 1040 2.400 -0.04 832 520 9.615 0.16 259 9.615 -0.16 207 0.16 259 19.231 0.16 129 19.230 -0.16 103 -0.22 86 58.140 0.94 42 57.142 0.79 34 42 113.636 -1.36 21 117.647 -2.12 16 SPBRG value SPBRG value SPBRG value (decimal) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 3332 0.300 -0.04 0.04 832 1.201 0.16 415 2.403 Actual Rate (K) % Error 0.3 0.300 0.01 1.2 1.200 2.4 2.404 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 1665 0.300 -0.04 832 -0.16 415 1.201 -0.16 207 -0.16 207 2.403 -0.16 103 SPBRG value SPBRG value (decimal) 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 -- -- -- 115.2 111.111 -3.55 8 -- -- -- -- -- -- DS39616D-page 224 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.2.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 20-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. This allows the user to verify that no carry occurred for 8bit modes by checking for 00h in the SPBRGH register. Refer to Table 20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character (see Section 20.3.4 "Auto-Wake-up on Sync Break Character"). In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Detect must receive a byte with the value of 55h (ASCII "U", which is also the LIN/J2602 bus Sync character) in order to calculate the proper bit rate. The measurement takes over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. Once the 5th edge is seen (should correspond to the Stop bit), the ABDEN bit is automatically cleared. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. 3: To maximize baud rate range, setting the BRG16 bit is recommended if the auto-baud feature is used. TABLE 20-4: While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. The BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG and SPBRGH as a 16-bit counter. BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/256 1 0 FOSC/128 1 1 FOSC/32 AUTOMATIC BAUD RATE CALCULATION(1) FIGURE 20-1: BRG Value BRG COUNTER CLOCK RATES XXXXh 0000h 001Ch Start RX Pin Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by user ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. 2010 Microchip Technology Inc. DS39616D-page 225 PIC18F2331/2431/4331/4431 20.3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. Asynchronous mode is available in all Low-Power modes; it is available in Sleep mode only when AutoWake-up on Sync Break is enabled. When in PRI_IDLE mode, no changes to the Baud Rate Generator values are required; however, other Low-Power mode clocks may operate at another frequency than the primary clock. Therefore, the Baud Rate Generator values may need to be adjusted. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection 20.3.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 20-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). DS39616D-page 226 Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. Flag bit, TXIF, is not cleared immediately upon loading the Transmit Buffer register, TXREG. TXIF becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit, TRMT, is a readonly bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXIF, is set when enable bit, TXEN, is set. To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. Enable the transmission by setting bit, TXEN, which will also set bit, TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 20-2: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register RC6/TX/CK/SS Pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPEN SPBRG TX9 Baud Rate Generator TX9D FIGURE 20-3: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 RC6/TX/CK/SS (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 20-4: 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX/CK/SS (pin) TXIF bit (Interrupt Reg. Flag) Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. 2010 Microchip Technology Inc. DS39616D-page 227 PIC18F2331/2431/4331/4431 TABLE 20-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 IPR1 RCSTA TXREG TXSTA EUSART Transmit Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 BAUDCON SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for asynchronous transmission. DS39616D-page 228 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.3.2 EUSART ASYNCHRONOUS RECEIVER 20.3.3 The receiver block diagram is shown in Figure 20-5. The data is received on the RC7/RX/DT/SDO pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 3. If interrupts are desired, set enable bit, RCIE. 4. If 9-bit reception is desired, set bit, RX9. 5. Enable the reception by setting bit, CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE, was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-5: SETTING UP 9-BIT MODE WITH ADDRESS DETECT EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator 64 or 16 or 4 MSb RSR Register LSb Stop Start (8) 7 1 0 RX9 Pin Buffer and Control Data Recovery RX9D RC7/RX/DT/SDO RCREG Register FIFO SPEN 8 Interrupt RCIF RCIE 2010 Microchip Technology Inc. Data Bus DS39616D-page 229 PIC18F2331/2431/4331/4431 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit, BRGH (see Section 20.2 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. FIGURE 20-6: 6. 7. Enable the transmission by setting bit, TXEN, which will also set bit, TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. ASYNCHRONOUS RECEPTION Start bit bit 0 RX (Pin) bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun) bit to be set. Note: TABLE 20-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 IPR1 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 INTCON RCSTA RCREG TXSTA BAUDCON EUSART Receive Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for asynchronous reception. DS39616D-page 230 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 20-7), and asynchronously if the device is in Sleep mode (Figure 20-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 20.3.4.1 Special Considerations Using Auto-Wake-up Since Auto-Wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-of-character FIGURE 20-7: and cause data or framing errors. To work properly, therefore, the initial characters in the transmission must be all `0's. This can be 00h (8 bits) for standard RS-232 devices, or 000h (12 bits) for LIN/J2602 bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 20.3.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set), and the RCIF flag is set, should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit(1) Auto-Cleared Bit Set by User RX/DT Line RCIF Cleared Due to User Read of RCREG Note 1: The EUSART remains in Idle while the WUE bit is set. FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit(2) Auto-Cleared Bit Set by User RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared Due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2010 Microchip Technology Inc. DS39616D-page 231 PIC18F2331/2431/4331/4431 20.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN/J2602 specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 20-9 for the timing of the Break character sequence. 20.3.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN/J2602 bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to setup the Break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 20.3.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 of the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 20.3.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit before placing the EUSART in its Sleep mode. FIGURE 20-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (Pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (Transmit Shift Reg. Empty Flag) DS39616D-page 232 SENDB sampled here Auto-Cleared 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.4 Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/ CK/SS and RC7/RX/DT/SDO I/O pins to CK (clock) and DT (data) lines, respectively. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>). Setting SCKP sets the Idle state on CK as high, while clearing the bit, sets the Idle state low. This option is provided to support Microwire devices with this module. 20.4.1 To set up a Synchronous Master Transmission: 1. EUSART SYNCHRONOUS MASTER TRANSMISSION 2. The EUSART transmitter block diagram is shown in Figure 20-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). FIGURE 20-10: 3. 4. 5. 6. 7. 8. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT/ SDO Pin bit 0 bit 1 Word 1 RC6/TX/CK/ SS Pin (SCKP = 0) bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 bit 1 bit 7 Word 2 RC6/TX/CK/ SS pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. 2010 Microchip Technology Inc. DS39616D-page 233 PIC18F2331/2431/4331/4431 FIGURE 20-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDO Pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK/SS Pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit TABLE 20-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 IPR1 RCSTA TXREG TXSTA BAUDCON EUSART Transmit Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. DS39616D-page 234 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT/SDO pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. FIGURE 20-12: 3. 4. 5. 6. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT/SDO Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK/SS Pin (SCKP = 0) RC6/TX/CK/SS Pin (SCKP = 1) Write to SREN bit SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0. 2010 Microchip Technology Inc. DS39616D-page 235 PIC18F2331/2431/4331/4431 TABLE 20-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 IPR1 RCSTA RCREG TXSTA BAUDCON EUSART Receive Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. DS39616D-page 236 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.5 To set up a Synchronous Slave Transmission: EUSART Synchronous Slave Mode 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RC6/TX/CK/SS pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 20.5.1 2. 3. 4. 5. 6. EUSART SYNCHRONOUS SLAVE TRANSMIT 7. The operation of the Synchronous Master and Slave modes are identical, except in the case of Sleep mode. 8. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit, TXIF, will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 20-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 IPR1 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 CREN ADDEN FERR OERR RX9D 56 INTCON RCSTA TXREG TXSTA BAUDCON SPEN TMR0IE INT0IE Bit 3 RX9 SREN EUSART Transmit Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 56 -- RCIDL -- SCKP BRG16 -- WUE ABDEN 56 SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. 2010 Microchip Technology Inc. DS39616D-page 237 PIC18F2331/2431/4331/4431 20.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this Low-Power mode. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the chip from Low-Power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. 6. 7. 8. 9. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. If interrupts are desired, set enable bit, RCIE. If 9-bit reception is desired, set bit, RX9. To enable reception, set enable bit, CREN. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit, CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 TMR2IF PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP SPEN RX9 SREN CREN ADDEN FERR OERR RX9D IPR1 RCSTA RCREG TXSTA EUSART Receive Register 56 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D -- RCIDL -- SCKP BRG16 -- WUE ABDEN BAUDCON 57 56 56 56 SPBRGH EUSART Baud Rate Generator Register High Byte 56 SPBRG EUSART Baud Rate Generator Register Low Byte 56 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. DS39616D-page 238 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.0 10-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The high-speed Analog-to-Digital (A/D) Converter module allows conversion of an analog signal to a corresponding 10-bit digital number. The A/D module supports up to 5 input channels on PIC18F2331/2431 devices, and up to 9 channels on the PIC18F4331/4431 devices. This high-speed 10-bit A/D module offers the following features: * Up to 200K samples per second * Two sample and hold inputs for dual-channel simultaneous sampling * Selectable Simultaneous or Sequential Sampling modes * 4-word data buffer for A/D results * Selectable data acquisition timing * Selectable A/D event trigger * Operation in Sleep using internal oscillator 2010 Microchip Technology Inc. These features lend themselves to many applications including motor control, sensor interfacing, data acquisition and process control. In many cases, these features will reduce the software overhead associated with standard A/D modules. The module has 9 registers: * * * * * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) A/D Control Register 3 (ADCON3) A/D Channel Select Register (ADCHS) Analog I/O Select Register 0 (ANSEL0) Analog I/O Select Register 1 (ANSEL1) DS39616D-page 239 PIC18F2331/2431/4331/4431 REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5 ACONV: Auto-Conversion Continuous Loop or Single-Shot Mode Select bit 1 = Continuous Loop mode enabled 0 = Single-Shot mode enabled bit 4 ACSCH: Auto-Conversion Single or Multi-Channel Mode bit 1 = Multi-Channel mode enabled, Single Channel mode disabled 0 = Single Channel mode enabled, Multi-Channel mode disabled bit 3-2 ACMOD<1:0>: Auto-Conversion Mode Sequence Select bits If ACSCH = 1: 00 = Sequential Mode 1 (SEQM1); two samples are taken in sequence: 1st sample: Group A(1) 2nd sample: Group B(1) 01 = Sequential Mode 2 (SEQM2); four samples are taken in sequence: 1st sample: Group A(1) 2nd sample: Group B(1) 3rd sample: Group C(1) 4th sample: Group D(1) 10 = Simultaneous Mode 1 (STNM1); two samples are taken simultaneously: 1st sample: Group A and Group B(1) 11 = Simultaneous Mode 2 (STNM2); two samples are taken simultaneously: 1st sample: Group A and Group B(1) 2nd sample: Group C and Group D(1) If ACSCH = 0, Auto-Conversion Single Channel Sequence Mode Enabled: 00 = Single Channel Mode 1 (SCM1); Group A is taken and converted(1) 01 = Single Channel Mode 2 (SCM2); Group B is taken and converted(1) 10 = Single Channel Mode 3 (SCM3); Group C is taken and converted(1) 11 = Single Channel Mode 4 (SCM4); Group D is taken and converted(1) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts the A/D conversion cycle. If AutoConversion Single-Shot mode is enabled (ACONV = 0), this bit is automatically cleared by hardware when the A/D conversion (single or multi-channel depending on ACMOD settings) has completed. If Auto-Conversion Continuous Loop mode is enabled (ACONV = 1), this bit remains set after the user/trigger has set it (continuous conversions). It may be cleared manually by the user to stop the conversions. 0 = A/D conversion or multiple conversions completed/not in progress bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled (after brief power-up delay, starts continuous sampling) 0 = A/D Converter module is disabled Note 1: Groups A, B, C, and D refer to the ADCHS register. DS39616D-page 240 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 VCFG1 VCFG0 -- FIFOEN BFEMT BFOVL ADPNT1 ADPNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 VCFG<1:0>: A/D VREF+ and A/D VREF- Source Selection bits 00 = VREF+ = AVDD, VREF- = AVSS (AN2 and AN3 are analog inputs or digital I/O) 01 = VREF+ = External VREF+, VREF- = AVSS (AN2 is an analog input or digital I/O) 10 = VREF+ = AVDD, VREF- = External VREF- (AN3 is an analog input or digital I/O) 11 = VREF+ = External VREF-, VREF- = External VREF- bit 5 Unimplemented: Read as `0' bit 4 FIFOEN: FIFO Buffer Enable bit 1 = FIFO is enabled 0 = FIFO is disabled bit 3 BFEMT: Buffer Empty bit 1 = FIFO is empty 0 = FIFO is not empty (at least one of four locations has unread A/D result data) bit 2 BFOVFL: Buffer Overflow bit 1 = A/D result has overwritten a buffer location that has unread data 0 = A/D result has not overflowed bit 1-0 ADPNT<1:0>: Buffer Read Pointer Location bits Designates the location to be read next. 00 = Buffer Address 0 01 = Buffer Address 1 10 = Buffer Address 2 11 = Buffer Address 3 2010 Microchip Technology Inc. DS39616D-page 241 PIC18F2331/2431/4331/4431 REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 ACQT<3:0>: A/D Acquisition Time Select bits 0000 = No delay (conversion starts immediately when GO/DONE is set)(1) 0001 = 2 TAD 0010 = 4 TAD 0011 = 6 TAD 0100 = 8 TAD 0101 = 10 TAD 0110 = 12 TAD 0111 = 16 TAD 1000 = 20 TAD 1001 = 24 TAD 1010 = 28 TAD 1011 = 32 TAD 1100 = 36 TAD 1101 = 40 TAD 1110 = 48 TAD 1111 = 64 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC/4 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (Internal A/D RC Oscillator) Note 1: If the A/D RC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. DS39616D-page 242 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 21-4: R/W-0 ADCON3: A/D CONTROL REGISTER 3 R/W-0 ADRS1 U-0 -- ADRS0 R/W-0 SSRC4 (1) R/W-0 SSRC3 (1) R/W-0 SSRC2 (1) R/W-0 SSRC1 (1) R/W-0 SSRC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 ADRS<1:0>: A/D Result Buffer Depth Interrupt Select Control for Continuous Loop Mode bits The ADRS bits are ignored in Single-Shot mode. 00 = Interrupt is generated when each word is written to the buffer 01 = Interrupt is generated when the 2nd and 4th words are written to the buffer 10 = Interrupt is generated when the 4th word is written to the buffer 11 = Unimplemented bit 5 Unimplemented: Read as `0' bit 4-0 SSRC<4:0>: A/D Trigger Source Select bits(1) 00000 = All triggers disabled xxxx1 = External interrupt RC3/INT0 starts A/D sequence xxx1x = Timer5 starts A/D sequence xx1xx = Input Capture 1 (IC1) starts A/D sequence x1xxx = CCP2 compare match starts A/D sequence 1xxxx = Power Control PWM module rising edge starts A/D sequence Note 1: The SSRC<4:0> bits can be set such that any of the triggers will start a conversion (e.g., SSRC<4:0> = 00101 will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs). 2010 Microchip Technology Inc. DS39616D-page 243 PIC18F2331/2431/4331/4431 REGISTER 21-5: ADCHS: A/D CHANNEL SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 GDSEL<1:0>: Group D Select bits S/H-2 positive input. 00 = AN3 01 = AN7(1) 1x = Reserved bit 5-4 GBSEL<1:0>: Group B Select bits S/H-2 positive input. 00 = AN1 01 = AN5(1) 1x = Reserved bit 3-2 GCSEL<1:0>: Group C Select bits S/H-1 positive input. 00 = AN2 01 = AN6(1) 1x = Reserved bit 1-0 GASEL<1:0>: Group A Select bits S/H-1 positive input. 00 = AN0 01 = AN4 10 = AN8(1) 11 = Reserved Note 1: x = Bit is unknown AN5 through AN8 are available only in PIC18F4331/4431 devices. DS39616D-page 244 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 21-6: R/W-1 ANS7 ANSEL0: ANALOG SELECT REGISTER 0(1) R/W-1 (2) R/W-1 (2) ANS6 ANS5 (2) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown ANS<7:0>: Analog Input Function Select bits Correspond to pins, AN<7:0>. 1 = Analog input 0 = Digital I/O Note 1: 2: Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins (e.g., ANS0 = AN0, ANS1 = AN1, etc.). Unused ANSx bits are read as `0'. ANS7 through ANS5 are available only on PIC18F4331/4431 devices. REGISTER 21-7: ANSEL1: ANALOG SELECT REGISTER 1(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 -- -- -- -- -- -- -- ANS8(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 ANS8: Analog Input Function Select bit(2) 1 = Analog input 0 = Digital I/O Note 1: 2: x = Bit is unknown Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins (e.g., ANS8 = AN8, ANS9 = AN9, etc.). Unused ANSx bits are read as `0'. ANS8 is available only on PIC18F4331/4431 devices. 2010 Microchip Technology Inc. DS39616D-page 245 PIC18F2331/2431/4331/4431 The A/D channels are grouped into four sets of 2 or 3 channels. For the PIC18F2331/2431 devices, AN0 and AN4 are in Group A, AN1 is in Group B, AN2 is in Group C and AN3 is in Group D. For the PIC18F4331/ 4431 devices, AN0, AN4 and AN8 are in Group A, AN1 and AN5 are in Group B, AN2 and AN6 are in Group C and AN3 and AN7 are in Group D. The selected channel in each group is selected by configuring the A/D Channel Select Register, ADCHS. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can individually be configured as an analog input or digital I/O using the ANSEL0 and ANSEL1 registers. The ADRESH and ADRESL registers contain the value in the result buffer pointed to by ADPNT<1:0> (ADCON1<1:0>). The result buffer is a 4-deep circular buffer that has a Buffer Empty status bit, BFEMT (ADCON1<3>), and a Buffer Overflow status bit, BFOVFL (ADCON1<2>). The analog voltage reference is software selectable to either the device's positive and negative analog supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+/CAP2/QEA and RA2/AN2/VREF-/ CAP1/INDX, or some combination of supply and external sources. Register ADCON1 controls the voltage reference settings. FIGURE 21-1: A/D BLOCK DIAGRAM AVDD(2) VCFG<1:0> AVSS(2) VREF+ VREF- VREFH VREFL ADC AN0 AN4 Analog MUX AN8(1) ADRESH, ADRESL 10 AN2/VREF- MUX AN6(1) ACMOD<1:0>, GxSEL<1:0> + - 00 01 10 11 1 2 3 4 S/H-1 S/H ADPNT<1:0> 4x10-Bit FIFO AVSS ACONV ACSCH ACMODx AN1 AN5(1) Analog MUX AN3/VREF+ S/H-2 AN7(1) + S/H ACMOD<1:0>, GxSEL<1:0> Note 1: 2: AVSS(2) Seq. Cntrl. AN5 through AN8 are available only on PIC18F4331/4431 devices. I/O pins have diode protection to VDD and VSS. DS39616D-page 246 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.1 Continuous Loop mode allows the defined sequence to be executed in a continuous loop when ACONV = 1. In this mode, either the user can trigger the start of conversion by setting the GO/DONE bit, or one of the A/D triggers can start the conversion. The interrupt flag, ADIF, is set based on the configuration of the bits, ADRS<1:0> (ADCON3<7:6>). In Simultaneous modes, STNM1 and STNM2 acquisition time must be configured to ensure proper conversion of the analog input signals. Configuring the A/D Converter The A/D Converter has two types of conversions, two modes of operation and eight different Sequencing modes. These features are controlled by the ACONV bit (ADCON0<5>), ACSCH bit (ADCON0<4>) and ACMOD<1:0> bits (ADCON0<3:2>). In addition, the A/D channels are divided into four groups as defined in the ADCHS register. Table 21-1 shows the sequence configurations as controlled by the ACSCH and ACMOD<1:0> bits. 21.1.1 21.1.2 CONVERSION TYPE The ACSCH bit (ADCON0<4>) controls how many channels are used in the configured sequence. When clear, the A/D is configured for single channel conversion and will convert the group selected by the ACMOD<1:0> bits and the channel selected by the GxSEL<1:0> bits (ADCHS register). When ACSCH = 1, the A/D is configured for multiple channel conversion and the sequence is defined by ACMOD<1:0>. Two types of conversions exist in the high-speed 10-bit A/D Converter module that are selected using the ACONV bit. Single-Shot mode allows a single conversion or sequence to be enabled when ACONV = 0. At the end of the sequence, the GO/DONE bit will be automatically cleared and the interrupt flag, ADIF, will be set. When using Single-Shot mode and configured for Simultaneous mode, STNM2, acquisition time must be used to ensure proper conversion of the analog input signals. TABLE 21-1: CONVERSION MODE AUTO-CONVERSION SEQUENCE CONFIGURATIONS Mode ACSCH ACMOD<1:0> Description Multi-Channel Sequential Mode 1 (SEQM1) 1 00 Groups A and B are sampled and converted sequentially. Multi-Channel Sequential Mode 2 (SEQM2) 1 01 Groups A, B, C and D are sampled and converted sequentially. Multi-Channel Simultaneous Mode 1 (STNM1) 1 10 Groups A and B are sampled simultaneously and converted sequentially. Multi-Channel Simultaneous Mode 2 (STNM2) 1 11 Groups A and B are sampled simultaneously, then converted sequentially. Then, Group C and D are sampled simultaneously, then converted sequentially. Single Channel Mode 1 (SCM1) 0 00 Group A is sampled and converted. Single Channel Mode 2 (SCM2) 0 01 Group B is sampled and converted. Single Channel Mode 3 (SCM3) 0 10 Group C is sampled and converted. Single Channel Mode 4 (SCM4) 0 11 Group D is sampled and converted. 2010 Microchip Technology Inc. DS39616D-page 247 PIC18F2331/2431/4331/4431 21.1.3 CONVERSION SEQUENCING The ACMOD<1:0> bits control the sequencing of the A/D conversions. When ACSCH = 0, the A/D is configured to sample and convert a single channel. The ACMOD bits select which group to perform the conversions and the GxSEL<1:0> bits select which channel in the group is to be converted. If Single-Shot mode is enabled, the A/D interrupt flag will be set after the channel is converted. If Continuous Loop mode is enabled, the A/D interrupt flag will be set according to the ADRS<1:0> bits. When ACSCH = 1, multiple channel sequencing is enabled and two submodes can be selected. The first mode is Sequential mode with two settings. The first setting is called SEQM1, and first samples and converts the selected Group A channel, and then samples and converts the selected Group B channel. The second mode is called SEQM2, and it samples and converts a Group A channel, Group B channel, Group C channel and finally, a Group D channel. The second multiple channel sequencing submode is Simultaneous Sampling mode. In this mode, there are also two settings. The first setting is called STNM1, and uses the two sample and hold circuits on the A/D module. The selected Group A and B channels are simultaneously sampled and then the Group A channel is converted followed by the conversion of the Group B channel. The second setting is called STNM2, and starts the same as STNM1, but follows it with a simultaneous sample of Group C and D channels. The A/D module will then convert the Group C channel followed by the Group D channel. 21.1.4 1. 2. 3. 4. 5. RC3/INT0 Pin Timer5 Overflow Input Capture 1 (IC1) CCP2 Compare Match Power Control PWM Rising Edge These triggers are enabled using the SSRC<4:0> bits (ADCON3<4:0>). Any combination of the five sources can trigger a conversion by simply setting the corresponding bit in ADCON3. When the trigger occurs, the GO/DONE bit is automatically set by the hardware and then cleared once the conversion completes. DS39616D-page 248 A/D MODULE INITIALIZATION STEPS The following steps should be followed to initialize the A/D module: TRIGGERING A/D CONVERSIONS The PIC18F2331/2431/4331/4431 devices are capable of triggering conversions from many different sources. The same method used by all other microcontrollers of setting the GO/DONE bit still works. The other trigger sources are: * * * * * 21.1.5 6. Configure the A/D module: a) Configure the analog pins, voltage reference and digital I/O. b) Select the A/D input channels. c) Select the A/D Auto-Conversion mode (Single-Shot or Continuous Loop). d) Select the A/D conversion clock. e) Select the A/D conversion trigger. Configure the A/D interrupt (if required): a) Set the GIE bit. b) Set the PEIE bit. c) Set the ADIE bit. d) Clear the ADIF bit. e) Select the A/D trigger setting. f) Select the A/D interrupt priority. Turn on ADC: a) Set the ADON bit in the ADCON0 register. b) Wait the required power-up setup time, about 5-10 s. Start the sample/conversion sequence: a) Sample for a minimum of 2 TAD and start the conversion by setting the GO/DONE bit. The GO/DONE bit is set by the user in software or by the module if initiated by a trigger. b) If TACQ is assigned a value (multiple of TAD), then setting the GO/DONE bit starts a sample period of the TACQ value, then starts a conversion. Wait for A/D conversion/conversions to complete using one of the following options: a) Poll for the GO/DONE bit to be cleared if in Single-Shot mode. b) Wait for the A/D Interrupt Flag (ADIF) to be set. c) Poll for the BFEMT bit to be cleared to signify that at least the first conversion has completed. Read the A/D results, clear the ADIF flag, reconfigure the trigger. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.2 A/D Result Buffer The A/D module has a 4-level result buffer with an address range of 0 to 3, enabled by setting the FIFOEN bit in the ADCON1 register. This buffer is implemented in a circular fashion, where the A/D result is stored in one location and the address is incremented. If the address is greater than 3, the pointer is wrapped back around to 0. The result buffer has a Buffer Empty Flag, BFEMT, indicating when any data is in the buffer. It also has a Buffer Overflow Flag, BFOVFL, which indicates when a new sample has overwritten a location that was not previously read. Associated with the buffer is a pointer to the address for the next read operation. The ADPNT<1:0> bits configure the address for the next read operation. These bits are read-only. The Result Buffer also has a configurable interrupt trigger level that is configured by the ADRS<1:0> bits. The user has three selections: interrupt flag set on every write to the buffer, interrupt on every second write to the buffer, or interrupt on every fourth write to the buffer. ADPNT<1:0> are reset to `00' every time a conversion sequence is started (either by setting the GO/DONE bit or on a trigger). When right justified, reading ADRESL increments the ADPNT<1:0> bits. When left justified, reading ADRESH increments the ADPNT<1:0> bits. Note: 21.3 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 21-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 21-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 21-1 shows the calculation of the minimum required acquisition time TACQ. In this case, the converter module is fully powered up at the outset and therefore, the amplifier settling time, TAMP, is negligible. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD EQUATION 21-1: TACQ 9 pF 100 1/2 LSb 5V Rss = 6 k 50C (system max.) 0V @ time = 0 ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: VHOLD or TC = = = = = MINIMUM A/D HOLDING CAPACITOR CHARGING TIME = (VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) = -(CHOLD)(RIC + RSS + RS) ln(1/2048) 2010 Microchip Technology Inc. DS39616D-page 249 PIC18F2331/2431/4331/4431 EXAMPLE 21-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = Negligible TCOFF = (Temp - 25C)(0.005 s/C) (50C - 25C)(0.005 s/C) = .13 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. TC = -(CHOLD) (RIC + RSS + RS) ln(1/2047) s -(9 pF) (1 k + 6 k + 100) ln(0.0004883) s = .49 s TACQ = 0 + .49 s + .13 s = .62 s Note: If the converter module has been in Sleep mode, TAMP is 2.0 s from the time the part exits Sleep mode. FIGURE 21-2: ANALOG INPUT MODEL VDD Rs ANx RIC 1k CPIN VAIN 5 pF Sampling Switch VT = 0.6V VT = 0.6V SS RSS ILEAKAGE 100 nA CHOLD = 9 pF VSS Legend: Note: DS39616D-page 250 CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) For VDD < 2.7V and temperatures below 0C, VAIN should be restricted to range: VAIN < VDD/2. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.4 A/D Voltage References If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. When using external references, the source impedance of the external voltage references must be less than 75 in order to achieve the specified ADC resolution. A higher reference source impedance will increase the ADC offset and gain errors. Resistive voltage dividers will not provide a low enough source impedance. To ensure the best possible ADC performance, external VREF inputs should be buffered with an op amp or other low-impedance circuit. Note: 21.5 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time an A/D conversion is triggered. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and the start of conversion. This occurs when the ACQT<3:0> bits (ADCON2<6:3>) remain in their Reset state (`0000'). TABLE 21-2: AD Clock Source (TAD) 4: 21.6 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are eight possible options for TAD: * * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator Internal RC Oscillator/4 For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 416 ns, see parameter A11 for more information). Table 21-2 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TAD vs. DEVICE OPERATING FREQUENCIES Operation Note 1: 2: 3: If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When triggered, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and triggering the A/D. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. ADCS<2:0> Maximum Device Frequency PIC18FXX31 PIC18LFXX31(4) 000 4.8 MHz 666 kHz 2 TOSC 100 9.6 MHz 1.33 MHz 4 TOSC 8 TOSC 001 19.2 MHz 2.66 MHz 16 TOSC 101 38.4 MHz 5.33 MHz 010 40.0 MHz 10.65 MHz 32 TOSC 64 TOSC 110 40.0 MHz 21.33 MHz (3) (1) RC/4 011 1.00 MHz 1.00 MHz(2) (3) (2) RC 111 4.0 MHz 4.0 MHz(2) The RC source has a typical TAD time of 2-6 s. The RC source has a typical TAD time of 0.5-1.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification unless in Single-Shot mode. Low-power devices only. 2010 Microchip Technology Inc. DS39616D-page 251 PIC18F2331/2431/4331/4431 21.7 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<3:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. 21.8 Configuring Analog Port Pins The ANSEL0, ANSEL1, TRISA and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the ANSEL0, ANSEL1 and TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. Operation in Sleep mode requires the A/D RC clock to be selected. If bits, ACQT<3:0>, are set to `0000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. Note: The A/D can operate in Sleep mode only when configured for Single-Shot mode. If the part is in Sleep mode, and it is possible for a source other than the A/D module to wake the part, the user must poll ADCON0<GO/DONE> to ensure it is clear before reading the result. DS39616D-page 252 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.9 A/D Conversions Figure 21-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. The internal A/D RC oscillator must be selected to perform a conversion in Sleep. Figure 21-4 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<3:0> bits are set to `010' and a 4 TAD acquisition time is selected before the conversion starts. FIGURE 21-3: Clearing the GO/DONE bit during a conversion will abort the current conversion. The resulting buffer location will contain the partially completed A/D conversion sample. This will not set the ADIF flag, therefore, the user must read the buffer location before a conversion sequence overwrites it. After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) GO/DONE bit is TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 set and holding b6 b3 b2 b8 b9 b4 b5 b7 b0 b1 cap is disconnected Conversion Starts from analog input GO/DONE bit cleared on the rising edge of Q1 after the first Q3 following TAD11 and result buffer is loaded.(1) Conversion time is a minimum of 11 TAD + 2 TCY and a maximum of 11 TAD + 6 TCY. Note 1: A/D CONVERSION TAD CYCLES (ACQT<3:0> = 0010, TACQ = 4 TAD) FIGURE 21-4: TACQT Cycles 1 2 3 TAD Cycles 4 Automatic Acquisition Time TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b6 b3 b2 b8 b9 b4 b5 b7 b0 b1 Conversion Starts (Holding capacitor is disconnected) A/D Triggered GO/DONE bit cleared on the rising edge of Q1 after the first Q3 following TAD11 and result buffer is loaded.(1) Note 1: In Continuous modes, next conversion starts at the end of TAD12. 2010 Microchip Technology Inc. DS39616D-page 253 PIC18F2331/2431/4331/4431 21.9.1 A/D RESULT REGISTER The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D FIGURE 21-5: Format Select bit (ADFM) controls this justification. Figure 21-5 shows the operation of the A/D result justification. The extra bits are loaded with `0's. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers. A/D RESULT JUSTIFICATION 10-Bit Result ADFM = 0 ADFM = 1 7 0 2107 7 0765 0000 00 ADRESH 0000 00 ADRESL 10-Bit Result Right Justified EQUATION 21-3: 0 ADRESH ADRESL 10-Bit Result Left Justified CONVERSION TIME FOR MULTI-CHANNEL MODES Sequential Mode: T = (TACQ)A + (TCON)A + [(TACQ)B - 12 TAD] + (TCON)B + [(TACQ)C - 12 TAD] + (TCON)C + [(TACQ)D - 12 TAD] + (TCON)D Simultaneous Mode: T = TACQ + (TCON)A + (TCON)B + TACQ + (TCON)C + (TCON)D DS39616D-page 254 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 21-3: Name INTCON SUMMARY OF A/D REGISTERS Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 -- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 -- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 IPR1 -- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 PIR2 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF 57 PIE2 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE 57 IPR2 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP 57 ADRESH A/D Result Register High Byte 56 ADRESL A/D Result Register Low Byte 56 ADCON0 -- -- ACONV ADCON1 VCFG1 VCFG0 -- FIFOEN BFEMT ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 -- SSRC4 SSRC3 GO/DONE ADON 56 BFOVFL ADPNT1 ADPNT0 56 ADCS2 ADCS1 ADCS0 56 SSRC2 SSRC1 SSRC0 56 GASEL1 GASEL0 56 ACSCH ACMOD1 ACMOD0 ADCON3 ADRS1 ADRS0 ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 ANSEL0 ANS7(6) ANS6(6) ANS5(6) ANS4 ANS3 ANS2 ANS1 ANS0 56 ANSEL1 -- -- -- -- -- -- -- ANS8(5) 56 PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 TRISA TRISA7(4) TRISA6(4) PORTA Data Direction Register 57 57 PORTE(2) -- -- -- -- RE3(1,3) TRISE(3) -- -- -- -- -- PORTE Data Direction Register 57 -- -- -- -- -- LATE Data Output Register 57 LATE(3) Legend: Note 1: 2: 3: 4: 5: 6: RA2(3) RA1(3) RA0(3) 57 -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. The RE3 port bit is available only as an input pin when the MCLRE bit in the CONFIG3H register is `0'. This register is not implemented on PIC18F2331/2431 devices. These bits are not implemented on PIC18F2331/2431 devices. These pins may be configured as port pins depending on the oscillator mode selected. ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. Not available on 28-pin devices. 2010 Microchip Technology Inc. DS39616D-page 255 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 256 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.0 LOW-VOLTAGE DETECT (LVD) PIC18F2331/2431/4331/4431 devices have a LowVoltage Detect module (LVD), a programmable circuit that enables the user to specify a device voltage trip point. If the device experiences an excursion below the trip point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The block diagram for the LVD module is shown in Figure 22-1. The module is enabled by setting the LVDEN bit, but the circuitry requires some time to stabilize each time that it is enabled. The IRVST bit is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and the IRVST bit is set. The module monitors for drops in VDD below a predetermined set point. The Low-Voltage Detect Control register (Register 22-1) completely controls the operation of the LVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. REGISTER 22-1: U-0 -- LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3(1) R/W-1 LVDL2(1) R/W-0 LVDL1(1) R/W-1 LVDL0(1) bit 7 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL<3:0>: Low-Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = Maximum setting . . . 0010 = Minimum setting 0001 = Reserved 0000 = Reserved bit 3-0 Note 1: LVDL<3:0> bit modes, which result in a trip point below the valid operating voltage of the device, are not tested. 2010 Microchip Technology Inc. DS39616D-page 257 PIC18F2331/2431/4331/4431 FIGURE 22-1: VDD LVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD LVDCON Register LVDEN LVDIN 16-to-1 MUX LVDIN LVDL<3:0> VDIRMAG Set LVDIF LVDEN BOREN DS39616D-page 258 Internal Voltage Reference 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.1 Operation When the LVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a low-voltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the LVDIF bit. The trip point voltage is software programmable to any one of 16 values, selected by programming the LVDL<3:0> bits (LVDCON<3:0>). The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, LVDL<3:0>, are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, LVDIN. This gives users flexibility because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. 2010 Microchip Technology Inc. 22.2 LVD Setup The following steps are needed to set up the LVD module: 1. 2. 3. 4. 5. Disable the module by clearing the LVDEN bit (LVDCON<4>). Write the value to the LVDL<3:0> bits that selects the desired LVD trip point. Enable the LVD module by setting the LVDEN bit. Clear the LVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt. Enable the LVD interrupt, if interrupts are desired, by setting the LVDIE and GIE bits (PIE<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. 22.3 Current Consumption When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification Parameter D022B. Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. DS39616D-page 259 PIC18F2331/2431/4331/4431 22.4 start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification Parameter 36. LVD Start-up Time The internal reference voltage of the LVD module, specified in electrical specification Parameter D420, may be used by other internal circuitry, such as the Programmable Brown-out Reset. If the LVD, or other circuits using the voltage reference, are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low-voltage condition can be reliably detected. This FIGURE 22-2: The LVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (refer to Figure 22-2). LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIRVST LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIRVST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS39616D-page 260 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.5 Operation During Sleep 22.7 When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 22.6 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off. Voltage FIGURE 22-3: Applications Figure 22-3 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage, VA, the LVD logic generates an interrupt. This occurs at time, TA. The application software then has the time, until the device voltage is no longer in valid operating range, to perform "housekeeping tasks" and to shut down the system. Voltage point, VB, is the minimum valid operating voltage specification. This occurs at time, TB. The difference, TB - TA, is the total time for shutdown. TYPICAL LOW-VOLTAGE DETECT APPLICATION VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage TA TB Time TABLE 22-1: Name REGISTERS ASSOCIATED WITH LOW-VOLTAGE DETECT MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVDCON -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR2 OSCFIP -- -- EEIP -- LVDIP -- CCP2IP PIR2 OSCFIF -- -- EEIF -- LVDIF -- CCP2IF PIE2 OSCFIE -- -- EEIE -- LVDIE -- CCP2IE Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the LVD module. 2010 Microchip Technology Inc. DS39616D-page 261 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 262 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 23.0 SPECIAL FEATURES OF THE CPU PIC18F2331/2431/4331/4431 devices include several features intended to maximize system reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM (ICSPTM) The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 3.0 "Oscillator Configurations". 23.1 Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the Configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 8.5 "Writing to Flash Program Memory". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2331/2431/4331/ 4431 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits, or software-controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. 2010 Microchip Technology Inc. DS39616D-page 263 PIC18F2331/2431/4331/4431 TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300000h CONFIG1L -- -- -- -- -- -- -- -- ---- ---- 300001h CONFIG1H IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 BORV0 BOREN PWRTEN ---- 1111 WDTEN --11 1111 300002h CONFIG2L -- -- -- -- BORV1 300003h CONFIG2H -- -- WINEN WDTPS3 WDTPS2 300004h CONFIG3L -- HPOL LPOL -- T1OSCMX 300005h CONFIG3H MCLRE(1) -- -- 300006h CONFIG4L DEBUG -- -- -- -- 300007h CONFIG4H -- -- -- -- -- 300008h CONFIG5L -- -- -- -- 300009h CONFIG5H CPD CPB -- 30000Ah CONFIG6L -- -- 30000Bh CONFIG6H WRTD 30000Ch CONFIG7L WDTPS1 WDTPS0 PWMPIN -- -- --11 11-- EXCLKMX(1) PWM4MX(1) SSPMX(1) -- FLTAMX(1) 1--1 11-1 LVP -- STVREN 1--- -1-1 -- -- -- ---- ---- CP3(1) CP2(1) CP1 CP0 ---- 1111 -- -- -- -- -- 11-- ---- -- -- WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 WRTB WRTC -- -- -- -- -- 111- ---- -- -- -- -- EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0101 3FFFFFh Legend: Note 1: 2: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F2331/4331 devices; maintain this bit set. See Register 23-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as `0' bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6 and port function on RA7 (INTIO1) 1000 = Internal oscillator block, port function on RA6 and port function on RA7 (INTIO2) 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 (ECIO) 0100 = EC oscillator, CLKO function on RA6 (EC) 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39616D-page 264 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 -- U-0 -- -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 R/P-1 (1) BOREN bit 7 PWRTEN(1) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as `0' bit 3-2 BORV<1:0>: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset is enabled 0 = Brown-out Reset is disabled bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT is disabled 0 = PWRT is enabled Note 1: U = Unimplemented bit, read as `0' U = Unchanged from programmed state Having BOREN = 1 does not automatically override the PWRTEN to `0', nor automatically enables the Power-up Timer. 2010 Microchip Technology Inc. DS39616D-page 265 PIC18F2331/2431/4331/4431 REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 -- -- WINEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7-6 Unimplemented: Read as `0' bit 5 WINEN: Watchdog Timer Window Enable bit 1 = WDT window is disabled 0 = WDT window is enabled bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) DS39616D-page 266 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-4: U-0 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U -- R/P-1 -- T1OSCMX R/P-1 HPOL (1) R/P-1 LPOL (1) R/P-1 (3) PWMPIN U U -- -- bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7-6 Unimplemented: Read as `0' bit 5 T1OSCMX: Timer1 Oscillator Mode bit 1 = Low-power Timer1 operation when microcontroller is in Sleep mode 0 = Standard (legacy) Timer1 oscillator operation bit 4 HPOL: High Side Transistors Polarity bit (i.e., Odd PWM Output Polarity Control bit)(1) 1 = PWM1, 3, 5 and 7 are active-high (default)(2) 0 = PWM1, 3, 5 and 7 are active-low(2) bit 3 LPOL: Low Side Transistors Polarity bit (i.e., Even PWM Output Polarity Control bit)(1) 1 = PWM0, 2, 4 and 6 are active-high (default)(2) 0 = PWM0, 2, 4 and 6 are active-low(2) bit 2 PWMPIN: PWM Output Pins Reset State Control bit(3) 1 = PWM outputs are disabled upon Reset (default) 0 = PWM outputs drive active states upon Reset bit 1-0 Unimplemented: Read as `0' Note 1: 2: 3: Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states; PWM states generated by the Fault inputs or PWM manual override. PWM6 and PWM7 output channels are only available on PIC18F4331/4431 devices. When PWMPIN = 0, PWMEN<2:0> = 101 if the device has eight PWM output pins (40 and 44-pin devices) and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin devices). PWM output polarity is defined by HPOL and LPOL. 2010 Microchip Technology Inc. DS39616D-page 267 PIC18F2331/2431/4331/4431 REGISTER 23-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U U MCLRE(1) -- -- R/P-1 R/P-1 EXCLKMX(1) PWM4MX(1) R/P-1 U R/P-1 SSPMX(1) -- FLTAMX(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin is enabled; RE3 input pin is disabled 0 = RE3 input pin is enabled; MCLR is disabled bit 6-5 Unimplemented: Read as `0' bit 4 EXCLKMX: TMR0/T5CKI External Clock MUX bit(1) 1 = TMR0/T5CKI external clock input is multiplexed with RC3 0 = TMR0/T5CKI external clock input is multiplexed with RD0 bit 3 PWM4MX: PWM4 MUX bit(1) 1 = PWM4 output is multiplexed with RB5 0 = PWM4 output is multiplexed with RD5 bit 2 SSPMX: SSP I/O MUX bit(1) 1 = SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7. 0 = SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1. bit 1 Unimplemented: Read as `0' bit 0 FLTAMX: FLTA MUX bit(1) 1 = FLTA input is multiplexed with RC1 0 = FLTA input is multiplexed with RD4 Note 1: Unimplemented in PIC18F2331/2431 devices; maintain this bit set. DS39616D-page 268 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG -- -- -- -- LVP -- STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6-3 Unimplemented: Read as `0' bit 2 LVP: Single-Supply ICSPTM Enable bit 1 = Single-Supply ICSP is enabled 0 = Single-Supply ICSP is disabled bit 1 Unimplemented: Read as `0' bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset 2010 Microchip Technology Inc. DS39616D-page 269 PIC18F2331/2431/4331/4431 REGISTER 23-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 -- -- -- -- CP3(1,2) CP2(1,2) CP1(2) CP0(2) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as `0' bit 3 CP3: Code Protection bit(1,2) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected bit 2 CP2: Code Protection bit(1,2) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected bit 1 CP1: Code Protection bit(2) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected bit 0 CP0: Code Protection bit(2) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected Note 1: 2: U = Unchanged from programmed state Unimplemented in PIC18F2331/4331 devices; maintain this bit set. Refer to Figure 23-5 for block boundary addresses. REGISTER 23-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD(1) CPB(1) -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed bit 7 CPD: Data EEPROM Code Protection bit(1) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit(1) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected bit 5-0 Unimplemented: Read as `0' Note 1: U = Unimplemented bit, read as `0' U = Unchanged from programmed state Refer to Figure 23-5 for block boundary addresses. DS39616D-page 270 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-9: U-0 CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 -- U-0 -- -- U-0 R/P-1 -- WRT3 (1,2) R/P-1 WRT2 (1,2) R/P-1 R/P-1 (2) WRT1 WRT0(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as `0' bit 3 WRT3: Write Protection bit(1,2) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected bit 2 WRT2: Write Protection bit(1,2) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected bit 1 WRT1: Write Protection bit(2) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected bit 0 WRT0: Write Protection bit(2) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected Note 1: 2: U = Unimplemented bit, read as `0' U = Unchanged from programmed state Unimplemented in PIC18F2331/4331 devices; maintain this bit set. Refer to Figure 23-5 for block boundary addresses. REGISTER 23-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD(2) WRTB(2) WRTC(1,2) -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7 WRTD: Data EEPROM Write Protection bit(2) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection bit(2) 1 = Boot block is not write-protected 0 = Boot block is write-protected bit 5 WRTC: Configuration Register Write Protection bit(1,2) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected bit 4-0 Unimplemented: Read as `0' Note 1: 2: This bit is read-only in normal execution mode; it can be written only in Program mode. Refer to Figure 23-5 for block boundary addresses. 2010 Microchip Technology Inc. DS39616D-page 271 PIC18F2331/2431/4331/4431 REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 -- -- U-0 -- U-0 -- R/P-1 EBTR3 (1,2,3) R/P-1 R/P-1 (1,2,3) EBTR2 EBTR1 (2,3) R/P-1 EBTR0(2,3) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7-4 Unimplemented: Read as `0' bit 3 EBTR3: Table Read Protection bit(1,2,3) 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1,2,3) 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit(2,3) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit(2,3) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks Note 1: 2: 3: Unimplemented in PIC18F2331/4331 devices; maintain this bit set. Refer to Figure 23-5 for block boundary addresses. Enabling the corresponding CPx bit is recommended to protect the block from external read operations. REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 -- EBTRB(1,2) -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7 Unimplemented: Read as `0' bit 6 EBTRB: Boot Block Table Read Protection bit(1,2) 1 = Boot block is not protected from table reads executed in other blocks 0 = Boot block is protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as `0' Note 1: 2: Enabling the corresponding CPx bit is recommended to protect the block from external read operations. Refer to Figure 23-5 for block boundary addresses. DS39616D-page 272 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2331/2431/4331/4431 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' U = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number. 000 = PIC18F4331 001 = PIC18F4431 100 = PIC18F2331 101 = PIC18F2431 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 23-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2331/2431/4331/4431 DEVICES R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-0 Note 1: U = Unimplemented bit, read as `0' U = Unchanged from programmed state DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number 0000 0101 = PIC18F2331/2431/4331/4431 devices These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. 2010 Microchip Technology Inc. DS39616D-page 273 PIC18F2331/2431/4331/4431 23.2 Watchdog Timer (WDT) For PIC18F2331/2431/4331/4431 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H (see Register 23-3). Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred (see Section 23.4.1 "FSCM and the Watchdog Timer"). Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. FIGURE 23-1: Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. 4: If WINEN = 0, then CLRWDT must be executed only when WDTW = 1; otherwise, a device Reset will result. 23.2.1 CONTROL REGISTER Register 23-15 shows the WDTCON register. This is a readable and writable register. The SWDTEN bit allows software to enable or disable the WDT, but only if the Configuration bit has disabled the WDT. The WDTW bit is a read-only bit that indicates when the WDT count is in the fourth quadrant (i.e., when the 8-bit WDT value is b'11000000' or greater). WDT BLOCK DIAGRAM SWDTEN WDTEN Enable WDT INTRC Control WDT Counter INTRC Source Wake-up from Sleep 125 Change on IRCF bits Programmable Postscaler 1:1 to 1:32,768 CLRWDT All Device Resets WDTPS<3:0> Reset WDT Reset WDT 4 Sleep DS39616D-page 274 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 23-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER R-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 WDTW -- -- -- -- -- -- SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 WDTW: Watchdog Timer Window bit 1 = WDT count is in fourth quadrant 0 = WDT count is not in fourth quadrant bit 6-1 Unimplemented: Read as `0' bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off Note 1: If the WDTEN Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTEN Configuration bit = 0, then it is possible to turn WDT on/off with this control bit. TABLE 23-2: Name CONFIG2H RCON WDTCON x = Bit is unknown SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- WINEN WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN IPEN -- -- RI TO PD POR BOR WDTW -- -- -- -- -- -- SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. 2010 Microchip Technology Inc. DS39616D-page 275 PIC18F2331/2431/4331/4431 23.3 In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO Configuration bit is ignored. Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). 23.3.1 Two-Speed Start-up is available only if the primary oscillator mode is LP, XT, HS or HSPLL (Crystal-Based modes). Other sources do not require a OST start-up delay; for these, Two-Speed Start-up is disabled. While using the INTRC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 4.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS<1:0> bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF<2:0> immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IRCF<2:0> prior to entering Sleep mode. FIGURE 23-2: SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: PC + 2 PC + 4 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39616D-page 276 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 23-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. FIGURE 23-3: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source (32 s) / 64 S Q C Q 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while the CM is still set, a clock failure has been detected (Figure 23-4). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition); and * the WDT is reset. Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power-managed mode (see Section 23.3.1 "Special Considerations for Using Two-Speed Start-up" and Section 4.1.4 "Multiple Sleep Commands" for more details). This can be done to attempt a partial recovery or execute a controlled shutdown. 2010 Microchip Technology Inc. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF<2:0>, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF<2:0> bits prior to entering Sleep mode. Adjustments to the internal oscillator block using the OSCTUNE register also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 23.4.1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock Monitor events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 23.4.2 EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset, or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power-managed mode is entered. Entering a power-managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the fail-safe condition. When the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. DS39616D-page 277 PIC18F2331/2431/4331/4431 FIGURE 23-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 23.4.3 CM Test CM Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES As previously mentioned, entering a power-managed mode clears the fail-safe condition. By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-safe monitoring of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the power-managed mode on oscillator failure. Instead, the device will continue to operate as before, but clocked by the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the fail-safe condition is cleared. 23.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 23.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration, and enter an alternate power-managed mode, while waiting for the primary system clock to become stable. When the new powered-managed mode is selected, the primary clock is disabled. DS39616D-page 278 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 23.5 Each of the five blocks has three code protection bits associated with them. They are: Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC(R) devices. * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a Boot Block of 512 bytes. The remainder of the memory is divided into four blocks on binary boundaries. Figure 23-5 shows the program memory organization for 8 and 16-Kbyte devices, and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 23-3. FIGURE 23-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431 MEMORY SIZE/DEVICE Block Code Protection Controlled By: 8 Kbytes (PIC18F2331/4331) Address Range 16 Kbytes (PIC18F2431/4431) 0000h 0FFFh Boot Block Address Range 0000h 01FFh Boot Block 0200h CPB, WRTB, EBTRB 0200h Block 0 Block 0 CP0, WRT0, EBTR0 0FFFh 0FFFh 1000h 1000h Block 1 Block 1 CP1, WRT1, EBTR1 1FFFh 1FFFh 2000h CP2, WRT2, EBTR2 Block 2 2FFFh Unimplemented Read `0's 3000h Block 3 CP3, WRT3, EBTR3 3FFFh TABLE 23-3: 3FFFh SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L -- -- -- -- CP3(1) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB -- -- -- -- -- -- WRT1 WRT0 -- -- EBTR1 EBTR0 -- -- 30000Ah CONFIG6L -- -- -- -- 30000Bh CONFIG6H WRTD WRTB WRTC -- 30000Ch CONFIG7L -- -- -- -- 30000Dh CONFIG7H -- EBTRB -- -- WRT3 (1) -- EBTR3 -- WRT2 (1) -- (1) (1) EBTR2 -- Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F2331/4331 devices; maintain this bit set. 2010 Microchip Technology Inc. DS39616D-page 279 PIC18F2331/2431/4331/4431 23.5.1 PROGRAM MEMORY CODE PROTECTION Note: The program memory may be read to, or written from, any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn Configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read, and will result in reading `0's. Figures 23-6 through 23-8 illustrate table write and table read protection. FIGURE 23-6: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 0007FEh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLWT * 0007FFh 000800h WRT1, EBTR1 = 11 000FFFh 001000h PC = 0017FEh WRT2, EBTR2 = 11 TBLWT * 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table writes are disabled to Blockn whenever WRTn = 0. DS39616D-page 280 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Configuration Bit Settings Program Memory 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 000FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 0007FFh 000800h TBLRD * 000FFFh 001000h WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. The TABLAT register returns a value of `0'. FIGURE 23-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Configuration Bit Settings Program Memory 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 0007FEh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 TBLRD * 0007FFh 000800h WRT1, EBTR1 = 11 000FFFh 001000h WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. The TABLAT register returns the value of the data at the location TBLPTR. 2010 Microchip Technology Inc. DS39616D-page 281 PIC18F2331/2431/4331/4431 23.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 23.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 23.6 Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected. In-Circuit Serial Programming PIC18F2331/2431/4331/4431 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 23.8 In-Circuit Debugger When the DEBUG bit in the CONFIG4L Configuration register is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 23-4 shows which resources are required by the background debugger. TABLE 23-4: 23.9 Single-Supply ICSPTM Programming The LVP bit in Configuration Register 4L (CONFIG4L<2>) enables Single-Supply ICSP Programming. When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP pin, but the RB5/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. ID Locations 23.7 To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. While programming, using Single-Supply Programming, VDD is applied to the MCLR/VPP pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Single-Supply Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 3: When LVP is enabled externally, pull the PGM pin to VSS to allow normal program execution. If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared and RB5/PGM becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/ VPP pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Single-Supply Programming, the device must be supplied with VDD of 4.5V to 5.5V. DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: 2 levels Program Memory: <1 Kbytes Data Memory: 16 bytes DS39616D-page 282 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 24.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC(R) instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 24-2 lists byte-oriented, bit-oriented, literal and control operations. Table 24-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator, `f', specifies which file register is to be used by the instruction. The destination designator, `d', specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the WREG register. If `d' is `1', the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator, `b', selects the number of the bit affected by the operation, while the file register designator, `f', represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') 2010 Microchip Technology Inc. The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the call or return instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 24-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 24-2, lists the instructions recognized by the Microchip Assembler (MPASMTM Assembler). Section 24.2 "Instruction Set" provides a description of each instruction. 24.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator, `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a "BCF PORTB, 1" instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch. DS39616D-page 283 PIC18F2331/2431/4331/4431 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file locations. f 8-bit register file address (0x00 to 0xFF). fs 12-bit register file address (0x000 to 0xFFF). This is the source address. fd 12-bit register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes). *+ Post-Increment register (such as TBLPTR with table reads and writes). *- Post-Decrement register (such as TBLPTR with table reads and writes). Pre-Increment register (such as TBLPTR with table reads and writes). +* n The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return Mode Select bit: s = 0: do not update into/from Shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged. WREG Working register (accumulator). x Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-Down bit. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents. Assigned to. < > Register bit field. In the set of. italics User-defined term (font is Courier New). DS39616D-page 284 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE 15 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 S OPCODE 15 0 n<7:0> (literal) 12 11 CALL MYFUNC 0 n<19:8> (literal) S = Fast bit 15 11 10 OPCODE 15 0 n<10:0> (literal) 8 7 OPCODE 2010 Microchip Technology Inc. BRA MYFUNC 0 n<7:0> (literal) BC MYFUNC DS39616D-page 285 PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s, f d MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 11da 0101 10da ffff ffff ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da ffff ffff ffff ffff None ffff None ffff Z, N 4 1, 2 1 1 1 (2 or 3) 1 (2 or 3) 1 ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1, 2 1, 2 3, 4 3, 4 1, 2 None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS BTG Note 1: 2: 3: 4: 5: f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39616D-page 286 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO -- -- n NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n RETLW RETURN SLEEP Note 1: 2: 3: 4: 5: 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call Subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to Address 1st word 2nd word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable k s -- Return with Literal in WREG Return from Subroutine Go into Standby mode 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 2 2 1 0000 1100 0000 0000 0000 0000 kkkk 0001 0000 1 1 2 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C, DC None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. 2010 Microchip Technology Inc. DS39616D-page 287 PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Load Literal (12-bit) 2nd word to FSRx 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS Table Read 2 Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment Table Write 2 (5) Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: 5: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39616D-page 288 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 24.2 Instruction Set ADDLW ADD Literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW Syntax: [ label ] ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 k 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 Encoding: 0010 Q1 Q2 Q3 Q4 Words: 1 Read literal `k' Process Data Write to W Cycles: 1 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 2010 Microchip Technology Inc. ffff ffff Add W to register, `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR is used. Decode ADDLW 01da Description: Q Cycle Activity: Example: f [,d [,a]] Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWF Before Instruction W = REG = 0x17 0xC2 After Instruction W = REG = 0xD9 0xC2 REG, W DS39616D-page 289 PIC18F2331/2431/4331/4431 ADDWFC ADD W and Carry bit to f ANDLW Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f [,d [,a]] Operation: (W) + (f) + (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the Carry flag and data memory location, `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location, `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination ADDWFC Before Instruction Carry bit = REG = W = 1 0x02 0x4D After Instruction Carry bit = REG = W = 0 0x02 0x50 DS39616D-page 290 0000 k 1011 kkkk kkkk Description: The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: Q Cycle Activity: Example: AND Literal with W ANDLW Before Instruction W = After Instruction W = 0x5F 0xA3 0x03 REG, W 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 01da ffff ffff The contents of W are ANDed with register, `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination ANDWF Before Instruction W = REG = After Instruction W = REG = Branch if Carry Syntax: [ label ] BC Operands: -128 n 127 Operation: if Carry bit is `1', (PC) + 2 + 2n PC Status Affected: None Encoding: Description: Example: BC REG, W 0x17 0xC2 0x02 0xC2 1110 Description: 0010 nnnn nnnn If the Carry bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: 2010 Microchip Technology Inc. n HERE BC JUMP Before Instruction PC = address (HERE) After Instruction If Carry PC If Carry PC = = = = 1; address (JUMP) 0; address (HERE + 2) DS39616D-page 291 PIC18F2331/2431/4331/4431 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f<b> Status Affected: None Encoding: 1001 f,b[,a] bbba ffff ffff Bit `b' in register, `f', is cleared. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' BCF Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 Branch if Negative Syntax: [ label ] BN Operands: -128 n 127 Operation: if Negative bit is `1', (PC) + 2 + 2n PC Status Affected: None Encoding: Description: Example: BN FLAG_REG, 7 1110 Description: 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: DS39616D-page 292 n HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative PC If Negative PC = = = = 1; address (Jump) 0; address (HERE + 2) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is `0', (PC) + 2 + 2n PC Operation: if Negative bit is `0', (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0011 nnnn nnnn Encoding: 1110 If the Carry bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: n 0111 nnnn nnnn If the Negative bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Carry PC If Carry PC = = = = = BNC Jump Example: HERE BNN Jump address (HERE) Before Instruction PC = address (HERE) 0; address (Jump) 1; address (HERE + 2) After Instruction If Negative PC If Negative PC = = = = 0; address (Jump) 1; address (HERE + 2) 2010 Microchip Technology Inc. DS39616D-page 293 PIC18F2331/2431/4331/4431 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is `0', (PC) + 2 + 2n PC Operation: if Zero bit is `0', (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: n 0001 nnnn nnnn If the Zero bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC DS39616D-page 294 = = = = = BNOV Jump Example: HERE BNZ Jump address (HERE) Before Instruction PC = address (HERE) 0; address (Jump) 1; address (HERE + 2) After Instruction If Zero PC If Zero PC = = = = 0; address (Jump) 1; address (HERE + 2) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BRA Unconditional Branch BSF Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2's complement number, `2n', to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation HERE BRA Example: Bit Set f Operation: 1 f<b> Status Affected: None Encoding: Before Instruction PC = address (HERE) After Instruction PC = address (Jump) 2010 Microchip Technology Inc. bbba ffff ffff Description: Bit `b' in register, `f', is set. If `a' is `0', Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: Jump 1000 f,b[,a] BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS39616D-page 295 PIC18F2331/2431/4331/4431 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit `b' in register, `f', is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Description: If bit `b' in register, `f', is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSC : : FLAG, 1 Example: HERE FALSE TRUE BTFSS : : FLAG, 1 Before Instruction PC = address (HERE) Before Instruction PC = address (HERE) After Instruction If FLAG<1> PC If FLAG<1> PC = = = = 0; address (TRUE) 1; address (FALSE) After Instruction If FLAG<1> PC If FLAG<1> PC = = = = 0; address (FALSE) 1; address (TRUE) DS39616D-page 296 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is `1', (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: Encoding: 0111 bbba ffff ffff Description: Bit `b' in data memory location, `f', is inverted. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, 4 Before Instruction: PORTC = 0111 0101 [0x75] After Instruction: PORTC = 0110 0101 [0x65] 1110 Description: 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: 2010 Microchip Technology Inc. n HERE BOV JUMP Before Instruction PC = address (HERE) After Instruction If Overflow PC If Overflow PC = = = = 1; address (JUMP) 0; address (HERE + 2) DS39616D-page 297 PIC18F2331/2431/4331/4431 BZ Branch if Zero CALL Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is `1', (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>; if s = 1: (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n Subroutine Call None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE BZ Subroutine call of entire 2-Mbyte memory range. First, the return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs. Then, the 20-bit value, `k', is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 = address (HERE) After Instruction If Zero PC If Zero PC = = = = 1; address (Jump) 0; address (HERE + 2) DS39616D-page 298 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, Push PC to Stack Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Jump Before Instruction PC kkkk0 kkkk8 Description: Q Cycle Activity: If Jump: Decode k7kkk kkkk 110s k19kkk Example: HERE CALL THERE,FAST Before Instruction PC = address (HERE) After Instruction PC = TOS = WS = BSRS = STATUSS = address (THERE) address (HERE + 4) W BSR STATUS 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Clears the contents of the specified register. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Encoding: Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Description: Q Cycle Activity: 0000 0000 0000 0100 Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Decode No operation Process Data No operation Example: CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 2010 Microchip Technology Inc. Example: CLRWDT Before Instruction WDT Counter = ? After Instruction WDT Counter WDT Postscaler TO PD = = = = 0x00 0 1 1 DS39616D-page 299 PIC18F2331/2431/4331/4431 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: 0001 Description: CPFSEQ f [,d [,a]] 11da ffff ffff The contents of register, `f', are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Compare f with W, Skip if f = W Syntax: [ label ] CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Read register `f' Process Data Write to destination Cycles: 1(2) Note: COMF Before Instruction REG = After Instruction REG = W = ffff ffff Compares the contents of data memory location, `f', to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Decode Example: 001a f [,a] REG, W 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 0x13 0x13 0xEC Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: DS39616D-page 300 HERE NEQUAL EQUAL CPFSEQ REG : : Before Instruction PC Address W REG = = = HERE ? ? After Instruction If REG PC If REG PC = = = W; Address (EQUAL) W; Address (NEQUAL) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CPFSGT Compare f with W, Skip if f > W CPFSLT Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) W), skip if (f) > (W) (unsigned comparison) Operation: (f) -W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a f [,a] ffff ffff Description: Compares the contents of data memory location, `f', to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a twocycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Encoding: Q2 Q3 Q4 Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 No operation No operation No operation No operation 1 Cycles: 1(2) Note: Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation HERE NGREATER GREATER CPFSGT REG : : Before Instruction PC W = = Address (HERE) ? After Instruction If REG PC If REG PC = = W; Address (GREATER) W; Address (NGREATER) 2010 Microchip Technology Inc. ffff ffff 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation HERE NLESS LESS CPFSLT REG : : Example: Example: 000a Q Cycle Activity: If skip and followed by 2-word instruction: Q2 f [,a] Compares the contents of data memory location, `f', to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. Words: If skip: Q1 0110 Description: Q Cycle Activity: Q1 Compare f with W, Skip if f < W Before Instruction PC W = = Address (HERE) ? After Instruction If REG PC If REG PC < = = W; Address (LESS) W; Address (NLESS) DS39616D-page 301 PIC18F2331/2431/4331/4431 DAW Decimal Adjust W Register DECF Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> 9] or [C = 1] then, (W<7:4>) + 6 W<7:4>; else, (W<7:4>) W<7:4> Status Affected: Decrement f 0000 0000 Description: 0000 0000 Words: 1 Cycles: 1 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1: DAW Before Instruction W = C = DC = 0xA5 0 0 After Instruction W = C = DC = 0x05 1 0 ffff Words: 0111 DAW adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. The Carry bit may be set by DAW regardless of its setting prior to the DAW instruction. ffff Decrement register, `f',. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. C, DC Encoding: 01da Description: DECF Before Instruction CNT = Z = 0x01 0 After Instruction CNT = Z = 0x00 1 CNT, Example 2: Before Instruction W = C = DC = 0xCE 0 0 After Instruction W = C = DC = 0x34 1 0 DS39616D-page 302 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff Decrement f, Skip if Not 0 Encoding: 0100 The contents of register, `f', are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If the result is `0', the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Description: Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: 11da f [,d [,a]] ffff ffff The contents of register, `f', are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If the result is not `0', the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ GOTO CNT LOOP Example: CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = HERE ZERO NZERO DCFSNZ : : TEMP Address (HERE) Before Instruction TEMP = ? CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) After Instruction TEMP If TEMP PC If TEMP PC = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) 2010 Microchip Technology Inc. DS39616D-page 303 PIC18F2331/2431/4331/4431 GOTO Unconditional Branch INCF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value, `k', is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation No operation Increment f Encoding: 0010 GOTO THERE After Instruction PC = Address (THERE) DS39616D-page 304 f [,d [,a]] 10da ffff ffff Description: The contents of register, `f', are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination No operation Example: Example: INCF INCF Before Instruction CNT = Z = C = DC = 0xFF 0 ? ? After Instruction CNT = Z = C = DC = 0x00 1 1 1 CNT, 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: INCFSZ f [,d [,a]] 11da ffff ffff Increment f, Skip if Not 0 Encoding: 0100 The contents of register, `f', are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If the result is `0', the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Description: Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: INFSNZ f [,d [,a]] 10da ffff ffff The contents of register, `f', are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If the result is not `0', the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : CNT Example: HERE ZERO NZERO INFSNZ REG Address (HERE) Before Instruction PC = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) After Instruction REG = If REG PC = If REG = PC = REG + 1 0; Address (NZERO) 0; Address (ZERO) 2010 Microchip Technology Inc. DS39616D-page 305 PIC18F2331/2431/4331/4431 IORLW Inclusive OR Literal with W IORWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: IORLW k 1001 kkkk kkkk The contents of W are ORed with the 8-bit literal, `k'. The result is placed in W. Words: 1 Cycles: 1 Inclusive OR W with f Encoding: 0001 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example: IORLW Before Instruction W = 0x9A After Instruction W = 0xBF 0x35 00da ffff ffff Inclusive OR W with register, `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: DS39616D-page 306 f [,d [,a]] Description: Q Cycle Activity: Decode IORWF IORWF Before Instruction RESULT = W = 0x13 0x91 After Instruction RESULT = W = 0x13 0x93 RESULT, W 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LFSR Load FSR MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the file select register pointed to by `f'. Words: 2 Cycles: 2 Move f Encoding: 0101 Q1 Q2 Q3 Q4 Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Process Data Write literal `k' to FSRfL Example: After Instruction FSR2H FSR2L LFSR 2, 0x3AB = = 0x03 0xAB 00da ffff ffff The contents of register, `f', are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. Location, `f', can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W Example: 2010 Microchip Technology Inc. f [,d [,a]] Description: Q Cycle Activity: Decode MOVF MOVF REG, W Before Instruction REG W = = 0x22 0xFF After Instruction REG W = = 0x22 0x22 DS39616D-page 307 PIC18F2331/2431/4331/4431 MOVFF Move f to f MOVLB Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operation: (fs) fd Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) MOVFF fs,fd 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register, `fs', are moved to destination register, `fd'. Location of source, `fs', can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination, `fd', can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see the note on page 97). Words: 2 Cycles: 2 (3) Move Literal to Low Nibble in BSR Syntax: [ label ] Operands: 0 k 255 MOVLB k Operation: k BSR Status Affected: None 0000 0001 0000 kkkk Description: The 8-bit literal, `k', is loaded into the Bank Select Register (BSR). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write literal `k' to BSR Example: MOVLB 5 Before Instruction BSR register = 0x02 After Instruction BSR register = 0x05 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No operation Write register `f' (dest) No dummy read Example: MOVFF REG1, REG2 Before Instruction REG1 REG2 = = 0x33 0x11 After Instruction REG1 REG2 = = 0x33 0x33 DS39616D-page 308 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MOVLW Move Literal to W MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 MOVLW k 1110 kkkk kkkk Description: The 8-bit literal, `k', is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example: After Instruction W = MOVLW 0x5A 0x5A ffff ffff Move data from W to register, `f'. Location, `f', can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF Before Instruction W = REG = After Instruction W = REG = 2010 Microchip Technology Inc. 111a f [,a] Description: Q Cycle Activity: Decode MOVWF REG 0x4F 0xFF 0x4F 0x4F DS39616D-page 309 PIC18F2331/2431/4331/4431 MULLW Multiply Literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: MULLW MULWF k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal, `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Words: 1 Cycles: 1 Multiply W with f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write registers PRODH: PRODL Example: MULLW 0xC4 Before Instruction W PRODH PRODL = = = 0xE2 ? ? After Instruction W PRODH PRODL = = = 0xE2 0xAD 0x08 DS39616D-page 310 001a f [,a] ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the register file location, `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a'= 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Decode MULWF Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write registers PRODH: PRODL Example: MULWF REG Before Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 ? ? After Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 0x8A 0x94 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: NEGF f [,a] 1 Cycles: 1 No Operation Syntax: [ label ] Operands: None ffff NOP Operation: No operation Status Affected: None Encoding: 110a 0000 1111 ffff Location, `f', is negated using two's complement. The result is placed in the data memory location, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: NOP 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: NEGF None. REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] 2010 Microchip Technology Inc. DS39616D-page 311 PIC18F2331/2431/4331/4431 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 POP 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW Before Instruction TOS Stack (1 level down) DS39616D-page 312 0000 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, and then push it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 After Instruction TOS PC 0000 Description: Q Cycle Activity: Example: PUSH Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: = = = = 0x0031A2 0x014332 0x014332 NEW PUSH Before Instruction TOS PC = = 0x00345A 0x000124 After Instruction PC TOS Stack (1 level down) = = = 0x000126 0x000126 0x00345A 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RCALL Relative Call Syntax: [ label ] RCALL Operands: -1024 n 1023 Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: n 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 RESET Reset Syntax: [ label ] Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: 0000 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: Q Cycle Activity: RESET After Instruction Registers = Flags* = RESET Reset Value Reset Value PUSH PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) 2010 Microchip Technology Inc. DS39616D-page 313 PIC18F2331/2431/4331/4431 RETFIE Return from Interrupt RETLW Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1: (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: RETFIE [s] Encoding: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: 1100 kkkk kkkk W is loaded with the 8-bit literal, `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs. RETLW k Description: GIE/GIEH, PEIE/GIEL. Encoding: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data POP PC from stack, Write to W No operation No operation No operation No operation Example: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation Return Literal to W No operation Example: RETFIE After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39616D-page 314 No operation No operation 1 = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value W = offset Begin table End of table Before Instruction W = 0x07 After Instruction W = value of kn 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RETURN Return from Subroutine RLCF Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1: (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: RETURN [s] Rotate Left f through Carry Encoding: 0000 0001 001s 0011 Description: f [,d [,a]] 01da ffff ffff The contents of register, `f', are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs. register f C Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: RLCF Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack Decode Read register `f' Process Data Write to destination No operation No operation No operation No operation Example: RETURN After Interrupt PC = TOS 2010 Microchip Technology Inc. Example: RLCF Before Instruction REG = C = 1110 0110 0 After Instruction REG = W = C = 1110 0110 1100 1100 1 REG, W DS39616D-page 315 PIC18F2331/2431/4331/4431 RLNCF Rotate Left f (No Carry) RRCF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register, `f', are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Rotate Right f through Carry Encoding: 0011 Description: RRCF 00da Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: RLNCF Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG Example: Before Instruction REG = 1010 1011 After Instruction REG = 0101 0111 DS39616D-page 316 ffff register f C 1 ffff The contents of register, `f', are rotated one bit to the right through the Carry Flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. register f Words: f [,d [,a]] RRCF REG, W Before Instruction REG = C = 1110 0110 0 After Instruction REG = W = C = 1110 0110 0111 0011 0 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RRNCF Rotate Right f (No Carry) SETF Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> Status Affected: None Status Affected: RRNCF f [,d [,a]] Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register, `f', are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. register f Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination RRNCF 1101 0111 After Instruction REG = 1110 1011 RRNCF f [,a] 100a ffff ffff Description: The contents of the specified register are set to FFh. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' SETF REG Before Instruction REG = 0x5A After Instruction REG = 0xFF REG, 1, 0 Before Instruction REG = Example 2: 0110 Example: Q Cycle Activity: Example 1: Set f REG, W Before Instruction W = REG = ? 1101 0111 After Instruction W = REG = 1110 1011 1101 0111 2010 Microchip Technology Inc. DS39616D-page 317 PIC18F2331/2431/4331/4431 SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z SLEEP Operands: None Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? ? PD = After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared. 0101 01da f [,d [,a]] ffff ffff Description: Subtract register, `f', and the Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = DS39616D-page 318 SUBFWB SUBFWB REG 0x03 0x02 0x01 0xFF 0x02 0x00 0x00 0x01 SUBFWB ; result is negative REG, 0, 0 2 5 1 2 3 1 0 0 ; result is positive SUBFWB REG, 1, 0 1 2 0 0 2 1 1 0 ; result is zero 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z SUBLW k Operands: 0 k 255 Operation: k - (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the 8-bit literal, `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0101 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: SUBLW 1 ? 1 1 0 0 SUBLW Before Instruction W = C = 2 ? After Instruction W = C = Z = N = 0 1 1 0 Example 3: 0x02 SUBLW 11da f [,d [,a]] ffff ffff Description: Subtract W from register, `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If = `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Decode SUBWF Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination ; result is positive Example 1: 0x02 ; result is zero 0x02 Before Instruction W = C = 3 ? After Instruction W = C = Z = N = FF ; (2's complement) ; result is negative 0 0 1 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = 2010 Microchip Technology Inc. SUBWF REG 3 2 ? 1 2 1 0 0 SUBWF ; result is positive REG, W 2 2 ? 2 0 1 1 0 SUBWF ; result is zero REG 0x01 0x02 ? 0xFFh ; (2's complement) 0x02 0x00 ; result is negative 0x00 0x01 DS39616D-page 319 PIC18F2331/2431/4331/4431 SUBWFB Subtract W from f with Borrow SWAPF Syntax: [ label ] Syntax: [ label ] 0 f 255 d [0,1] a [0,1] SUBWFB f [,d [,a]] Swap f SWAPF f [,d [,a]] Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) - (W) - (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 10da ffff ffff Description: Subtract W and the Carry flag (borrow) from register, `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: SUBWFB Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: 0011 10da ffff ffff Description: The upper and lower nibbles of register, `f', are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 Example: 0x19 0x0D 0x01 (0001 1001) (0000 1101) 0x0C 0x0D 0x01 0x00 0x00 (0000 1011) (0000 1101) SWAPF Before Instruction REG = 0x53 After Instruction REG = 0x35 REG ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 0x1B 0x1A 0x00 (0001 1011) (0001 1010) 0x1B 0x00 0x01 0x01 0x00 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Encoding: = = = = DS39616D-page 320 ; result is zero REG, 1, 0 0x03 0x0E 0x01 (0000 0011) (0000 1101) 0xF5 (1111 0100) ; [2's comp] (0000 1101) 0x0E 0x00 0x00 0x01 ; result is negative 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TBLRD Table Read TBLRD Table Read (cont'd) Syntax: [ label ] Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT TBLRD ( *; *+; *-; +*) Encoding: 0000 0000 0000 = = = 0x55 0x00A356 0x34 After Instruction TABLAT TBLPTR = = 0x34 0x00A357 Example 2: Status Affected: None 10nn nn = 0 *+ ; Before Instruction TABLAT TBLPTR MEMORY(0x00A356) TBLRD +* ; Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) = = = = 0xAA 0x01A357 0x12 0x34 After Instruction TABLAT TBLPTR = = 0x34 0x01A358 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) 2010 Microchip Technology Inc. DS39616D-page 321 PIC18F2331/2431/4331/4431 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Words: Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) Holding Register, TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register Q Cycle Activity: Status Affected: Encoding: Description: TBLWT ( *; *+; *-; +*) Example 1: None 0000 0000 0000 11nn nn = 0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 8.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment DS39616D-page 322 1 Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) TBLWT *+; Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x00A356) = = 0x55 0x00A356 = 0xFF After Instructions (table write completion) TABLAT = 0x55 TBLPTR = 0x00A357 HOLDING REGISTER (0x00A356) = 0x55 Example 2: TBLWT +*; Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) = = 0x34 0x01389A = 0xFF = 0xFF After Instruction (table write completion) TABLAT = 0x34 TBLPTR = 0x01389B HOLDING REGISTER (0x01389A) = 0xFF HOLDING REGISTER (0x01389B) = 0x34 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] TSTFSZ f [,a] Operation: skip if f = 0 Status Affected: None Encoding: Description: Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Encoding: 0110 011a ffff ffff If `f' = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation XORLW k 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal, `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: XORLW Before Instruction W = 0xB5 After Instruction W = 0x1A 0xAF If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO TSTFSZ : CNT : Before Instruction PC = Address (HERE) After Instruction If CNT PC If CNT PC = = = 0x00, Address (ZERO) 0x00, Address (NZERO) 2010 Microchip Technology Inc. DS39616D-page 323 PIC18F2331/2431/4331/4431 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 XORWF 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register, `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register, `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = 0xAF 0xB5 After Instruction REG = W = 0x1A 0xB5 DS39616D-page 324 REG 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 25.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2010 Microchip Technology Inc. DS39616D-page 325 PIC18F2331/2431/4331/4431 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 25.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 25.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 25.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS39616D-page 326 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 25.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2010 Microchip Technology Inc. 25.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 25.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. DS39616D-page 327 PIC18F2331/2431/4331/4431 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 25.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39616D-page 328 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byall ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. DS39616D-page 329 PIC18F2331/2431/4331/4431 FIGURE 26-1: PIC18F2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2X31/4X31 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 26-2: PIC18LF2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2X31/4X31 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC(R) device in the application. DS39616D-page 330 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D001 Symbol VDD Characteristic Min Typ Max Units Conditions Supply Voltage PIC18LF2X31/4X31 2.0 -- 5.5 V PIC18F2X31/4X31 4.2 -- 5.5 V D001C AVDD Analog Supply Voltage VDD - 0.3 -- VDD + 0.3 V D001D AVSS Analog Ground Voltage VSS - 0.3 -- VSS + 0.3 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal -- -- 0.7 V D004 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 -- -- D005A VBOR Brown-out Reset Voltage See section on Power-on Reset for details V/ms See section on Power-on Reset for details PIC18LF2X31/4X31 Industrial Low Voltage (-10C to +85C) D005B D005C D005D D005E D005F Legend: Note 1: 2: BORV<1:0> = 11 N/A N/A N/A V BORV<1:0> = 10 2.50 2.72 2.94 V BORV<1:0> = 01 3.88 4.22 4.56 V BORV<1:0> = 00 4.18 4.54 4.90 V Reserved PIC18LF2X31/4X31 Industrial Low Voltage (-40C to -10C) BORV<1:0> = 11 N/A N/A N/A V BORV<1:0>= 10 2.34 2.72 3.10 V BORV<1:0> = 01 3.63 4.22 4.81 V BORV<1:0> = 00 3.90 4.54 5.18 V Reserved PIC18F2X31/4X31 Industrial (-10C to +85C) BORV<1:0>= 1x N/A N/A N/A V Reserved BORV<1:0> = 01 3.88 4.22 4.56 V (Note 2) BORV<1:0> = 00 4.18 4.54 4.90 V (Note 2) PIC18F2X31/4X31 Industrial (-40C to -10C) BORV<1:0>= 1x N/A N/A N/A V Reserved BORV<1:0> = 01 N/A N/A N/A V Reserved BORV<1:0> = 00 3.90 4.54 5.18 V (Note 2) PIC18F2X31/4X31 Extended (-10C to +85C) BORV<1:0> = 1x N/A N/A N/A V Reserved BORV<1:0> = 01 3.88 4.22 4.56 V (Note 2) BORV<1:0> = 00 4.18 4.54 4.90 V (Note 2) PIC18F2X31/4X31 Extended (-40C to -10C, +85C to +125C) BORV<1:0> = 1x N/A N/A N/A V Reserved BORV<1:0> = 01 N/A N/A N/A V Reserved BORV<1:0> = 00 3.90 4.54 5.18 V (Note 2) Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows execution. 2010 Microchip Technology Inc. DS39616D-page 331 PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Power-Down Current (IPD)(1) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 0.1 0.5 A -40C 0.1 0.5 A +25C 0.2 1.9 A +85C 0.1 0.5 A -40C 0.1 0.5 A +25C 0.3 1.9 A +85C 0.1 2.0 A -40C 0.1 2.0 A +25C 0.4 6.5 A +85C 5 33 A +125C VDD = 2.0V (Sleep mode) VDD = 3.0V (Sleep mode) VDD = 5.0V (Sleep mode) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39616D-page 332 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 8 40 A -40C 9 40 A +25C 11 40 A +85C 25 68 A -40C 25 68 A +25C 20 68 A +85C 55 180 A -40C 55 180 A +25C 50 180 A +85C 0.25 1 mA +125C 140 220 A -40C 145 220 A +25C 155 220 A +85C Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 215 330 A -40C 225 330 A +25C 235 330 A +85C 385 550 A -40C 390 550 A +25C 405 550 A +85C +125C 0.7 2.8 mA 410 600 A -40C 425 600 A +25C 435 600 A +85C 650 900 A -40C 670 900 A +25C 680 900 A +85C 1.2 1.8 mA -40C 1.2 1.8 mA +25C 1.2 1.8 mA +85C 2.2 6 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2010 Microchip Technology Inc. DS39616D-page 333 PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 4.7 8 A -40C 5.0 8 A +25C 5.8 11 A +85C 7.0 11 A -40C 7.8 11 A +25C 8.7 15 A +85C 12 16 A -40C 14 16 A +25C 14 22 A +85C 200 850 A +125C 75 150 A -40C 85 150 A +25C 95 150 A +85C 110 180 A -40C 125 180 A +25C 135 180 A +85C 180 300 A -40C 195 300 A +25C 200 300 A +85C 300 750 A +125C 175 275 A -40C 185 275 A +25C 195 275 A +85C 265 375 A -40C 280 375 A +25C 300 375 A +85C 475 800 A -40C 500 800 A +25C 505 800 A +85C 0.7 1.6 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 31 KHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39616D-page 334 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices 150 250 A -40C 150 250 A +25C 160 250 A +85C 340 350 A -40C 300 350 A +25C +85C 280 350 A 0.72 1.0 mA -40C 0.63 1.0 mA +25C 0.57 1.0 mA +85C +125C 0.9 2.1 mA 440 600 A -40C 450 600 A +25C 460 600 A +85C 0.80 1.0 mA -40C 0.78 1.0 mA +25C 0.77 1.0 mA +85C 1.6 2.0 mA -40C 1.5 2.0 mA +25C 1.5 2.0 mA +85C 2.0 4.2 mA +125C 10 28 mA +125C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 2.0V VDD = 3.0V All devices Legend: Note 1: 2: 3: 4: 9.5 12 mA -40C 9.7 12 mA +25C 9.9 12 mA +85C 11.9 15 mA -40C 12.1 15 mA +25C 12.3 15 mA +85C FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 5.0V All devices All devices FOSC = 1 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 4.2V VDD = 5.0V FOSC = 25 MHz (PRI_RUN, EC oscillator) FOSC = 40 MHZ (PRI_RUN, EC oscillator) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2010 Microchip Technology Inc. DS39616D-page 335 PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices 35 50 A -40C 35 50 A +25C 35 60 A +85C 55 80 A -40C 50 80 A +25C 60 100 A +85C 105 150 A -40C 110 150 A +25C 115 150 A +85C 300 400 A +125C 135 180 A -40C 140 180 A +25C 140 180 A +85C 215 280 A -40C 225 280 A +25C 230 280 A +85C 410 525 A -40C 420 525 A +25C 430 525 A +85C 1.2 1.7 mA +125C 18 22 mA +125C 3.2 4.1 mA -40C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 2.0V VDD = 3.0V All devices Legend: Note 1: 2: 3: 4: 3.2 4.1 mA +25C 3.3 4.1 mA +85C 4.0 5.1 mA -40C 4.1 5.1 mA +25C 4.1 5.1 mA +85C FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V All devices All devices FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39616D-page 336 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 5.1 9 A -10C 5.8 9 A +25C 7.9 11 A +70C 7.9 12 A -10C 8.9 12 A +25C 10.5 14 A +70C 12.5 20 A -10C 16.3 20 A +25C 18.9 25 A +70C 150 850 A +125C 9.2 15 A -10C 9.6 15 A +25C 12.7 18 A +70C 22.0 30 A -10C 21.0 30 A +25C 20.0 35 A +70C 30 80 A -10C 45 80 A +25C 45 85 A +70C 250 850 A +125C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. 2010 Microchip Technology Inc. DS39616D-page 337 PIC18F2331/2431/4331/4431 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) D022A (IBOR) D022B (ILVD) Watchdog Timer Brown-out Reset Low-Voltage Detect D025 (IOSCB) Timer1 Oscillator D026 (IAD) A/D Converter Legend: Note 1: 2: 3: 4: 1.5 4.0 A -40C 2.2 4.0 A +25C 3.1 5.0 A +85C 2.5 6.0 A -40C 3.3 6.0 A +25C 4.7 7.0 A +85C 3.7 10.0 A -40C 4.5 10.0 A +25C 6.1 13.0 A +85C 22 44 A +125C 19 35.0 A -40C to +85C 24 45.0 A -40C to +85C 40 75 A +125C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V 8.5 25.0 A -40C to +85C VDD = 2.0V 16 35.0 A -40C to +85C VDD = 3.0V 20 45.0 A -40C to +85C 35 66 A +125C 1.7 3.5 A -40C 1.8 3.5 A +25C 2.1 4.5 A +85C 2.2 4.5 A -40C 2.6 4.5 A +25C 2.8 5.5 A +85C 3.0 6.0 A -40C 3.3 6.0 A +25C 3.6 7.0 A +85C VDD = 5.0V VDD = 2.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 5.0V 32 kHz on Timer1(4) 42 70 A +125C 1.0 3.0 A -40C to +85C VDD = 2.0V 1.0 4.0 A -40C to +85C VDD = 3.0V 2.0 10.0 A -40C to +85C 150 950 A +125C A/D on, not converting VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in k. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39616D-page 338 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V -- 0.8 V 4.5V VDD 5.5V VSS VSS 0.2 VDD 0.3 VDD V V I2CTM enabled Input Low Voltage I/O Ports: D030 with TTL Buffer D030A D031 with Schmitt Trigger Buffer RC3 and RC4 D032 MCLR VSS 0.2 VDD V D032A OSC1 and T1OSI VSS 0.3 VDD V LP, XT, HS, HSPLL modes(1) D033 OSC1 VSS 0.2 VDD V EC mode(1) 0.25 VDD + 0.8V VDD V VDD < 4.5V VIH Input High Voltage I/O Ports: D040 with TTL Buffer D040A D041 with Schmitt Trigger Buffer RC3 and RC4 2.0 VDD V 4.5V VDD 5.5V 0.8 VDD 0.7 VDD VDD VDD V V I2CTM enabled D042 MCLR 0.8 VDD VDD V D042A OSC1 and T1OSI 0.7 VDD VDD V LP, XT, HS, HSPLL modes(1) D043 OSC1 0.8 VDD VDD V EC mode(1) -- +200 nA A VDD < 5.5V, VSS VPIN VDD, Pin at high-impedance -- +50 nA MCLR -- 1 A Vss VPIN VDD OSC1 -- 1 A Vss VPIN VDD 50 400 A VDD = 5V, VPIN = VSS IIL D060 Input Leakage Current(2,3) I/O Ports D061 D063 D070 Note 1: 2: 3: IPU Weak Pull-up Current IPURB PORTB Weak Pull-up Current VDD < 3V, VSS VPIN VDD, Pin at high-impedance In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. 2010 Microchip Technology Inc. DS39616D-page 339 PIC18F2331/2431/4331/4431 26.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O Ports -- 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) -- 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage(3) D090 I/O Ports VDD - 0.7 -- V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO (RC, RCIO, EC, ECIO modes) VDD - 0.7 -- V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin -- 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 (in RC mode) -- 50 pF To meet the AC Timing Specifications D102 CB SCL, SDA -- 400 pF I2CTM Specification Note 1: 2: 3: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. DS39616D-page 340 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ Max Units V Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 -- 13.25 D112 IPP Current into MCLR/VPP pin -- -- 300 A D113 IDDP Supply Current during Programming -- -- 1 mA E/W -40C to +85C (Note 3) Data EEPROM Memory D120 ED Byte Endurance 100K 1M -- D121 VDRW VDD for Read/Write VMIN -- 5.5 V D122 TDEW Erase/Write Cycle Time -- 4 -- ms D123 TRETD Characteristic Retention 40 -- -- Year Provided no other specifications are violated D124 TREF 1M 10M -- E/W -40C to +85C E/W -40C to +85C Number of Total Erase/Write Cycles before Refresh(2) Using EECON to read/write VMIN = Minimum operating voltage Program Flash Memory D130 EP Cell Endurance 10K 100K -- D131 VPR VDD for Read VMIN -- 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 -- 5.5 V Using ICSPTM port D132A VIW VDD for Externally Timed Erase or Write 4.5 -- 5.5 V Using ICSP port D132B VPEW VDD for Self-Timed Write VMIN -- 5.5 V VMIN = Minimum operating voltage D133 TIE ICSPTM Block Erase Cycle Time -- 4 -- ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 -- -- ms VDD > 4.5V D133A TIW Self-Timed Write Cycle Time -- 2 -- ms 40 100 -- D134 TRETD Characteristic Retention Year Provided no other specifications are violated Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 7.9 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. 2010 Microchip Technology Inc. DS39616D-page 341 PIC18F2331/2431/4331/4431 FIGURE 26-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 26-2: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D420A Symbol VLVD Legend: Characteristic LVD Voltage on VDD Transition High-to-Low Min Typ Max Units Conditions Industrial Low Voltage (-10C to +85C) PIC18LF2X31/4X31 LVDL<3:0> = 0000 N/A N/A N/A V Reserved LVDL<3:0> = 0001 N/A N/A N/A V Reserved LVDL<3:0> = 0010 2.08 2.26 2.44 V LVDL<3:0> = 0011 2.26 2.45 2.65 V LVDL<3:0> = 0100 2.35 2.55 2.76 V LVDL<3:0> = 0101 2.55 2.77 2.99 V LVDL<3:0> = 0110 2.64 2.87 3.10 V LVDL<3:0> = 0111 2.82 3.07 3.31 V LVDL<3:0> = 1000 3.09 3.36 3.63 V LVDL<3:0> = 1001 3.29 3.57 3.86 V LVDL<3:0> = 1010 3.38 3.67 3.96 V LVDL<3:0> = 1011 3.56 3.87 4.18 V LVDL<3:0> = 1100 3.75 4.07 4.40 V LVDL<3:0> = 1101 3.93 4.28 4.62 V LVDL<3:0> = 1110 4.23 4.60 4.96 V Shading of rows is to assist in readability of the table. Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization. DS39616D-page 342 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 26-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D420B D420C Symbol VLVD VLVD Characteristic LVD Voltage on VDD Transition High-to-Low D420F VLVD Legend: Conditions Industrial Low Voltage (-40C to -10C) N/A N/A V Reserved N/A N/A N/A V Reserved LVDL<3:0> = 0010 1.99 2.26 2.53 V LVDL<3:0> = 0011 2.16 2.45 2.75 V LVDL<3:0> = 0100 2.25 2.55 2.86 V LVDL<3:0> = 0101 2.43 2.77 3.10 V LVDL<3:0> = 0110 2.53 2.87 3.21 V LVDL<3:0> = 0111 2.70 3.07 3.43 V LVDL<3:0> = 1000 2.96 3.36 3.77 V LVDL<3:0> = 1001 3.14 3.57 4.00 V LVDL<3:0> = 1010 3.23 3.67 4.11 V LVDL<3:0> = 1011 3.41 3.87 4.34 V LVDL<3:0> = 1100 3.58 4.07 4.56 V LVDL<3:0> = 1101 3.76 4.28 4.79 V LVDL<3:0> = 1110 4.04 4.60 5.15 V LVD Voltage on VDD Transition High-to-Low LVD Voltage on VDD Transition High-to-Low LVDL<3:0> = 1110 VLVD Units N/A PIC18F2X31/4X31 LVDL<3:0> = 1101 D420E Max LVDL<3:0> = 0001 LVDL<3:0> = 1110 VLVD Typ PIC18LF2X31/4X31 LVDL<3:0> = 0000 PIC18F2X31/4X31 LVDL<3:0> = 1101 D420D Min LVD Voltage on VDD Transition High-to-Low Industrial (-10C to +85C) 3.93 4.28 4.62 V 4.23 4.60 4.96 V Industrial (-40C to -10C) 3.76 4.28 4.79 V 4.04 4.60 5.15 V Extended (-10C to +85C) PIC18F2X31/4X31 LVDL<3:0> = 1101 3.94 4.28 4.62 V LVDL<3:0> = 1110 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low Reserved Extended (-40C to -10C, +85C to +125C) PIC18F2X31/4X31 LVDL<3:0> = 1101 3.77 4.28 4.79 V LVDL<3:0> = 1110 4.05 4.60 5.15 V Reserved Shading of rows is to assist in readability of the table. Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization. 2010 Microchip Technology Inc. DS39616D-page 343 PIC18F2331/2431/4331/4431 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition DS39616D-page 344 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-Impedance High Low High Low SU Setup STO Stop condition 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 26-3 apply to all timing specifications unless otherwise noted. Figure 26-4 specifies the load conditions for the timing specifications. TABLE 26-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 26-4: Because of space limitations, the generic terms "PIC18FXX31" and "PIC18LFXX31" are used throughout this section to refer to the PIC18F2331/2431/4331/4431 and PIC18LF2331/2431/4331/4431 families of devices specifically, and only those devices. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 26.1 and Section 26.3. LF parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 Load Condition 1 VDD/2 RL CL Pin VSS CL Pin VSS 2010 Microchip Technology Inc. RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports DS39616D-page 345 PIC18F2331/2431/4331/4431 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-4: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 40 MHz EC, ECIO DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc 5 200 kHz LP Osc mode 25 -- ns EC, ECIO 250 -- ns RC osc 250 10,000 ns XT osc 25 100 250 250 ns ns HS osc HS + PLL osc 25 -- s LP osc 100 -- ns TCY = 4/FOSC 30 -- ns XT osc 2.5 -- s LP osc 10 -- ns HS osc -- 20 ns XT osc -- 50 ns LP osc -- 7.5 ns HS osc Oscillator Frequency 1 TOSC (1) External CLKI Period(1) (1) Oscillator Period Time(1) 2 TCY Instruction Cycle 3 TosL, TosH External Clock in (OSC1) High or Low Time 4 Note 1: TosR, TosF External Clock in (OSC1) Rise or Fall Time Conditions Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. DS39616D-page 346 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 26-5: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ Max 4 16 -- -- 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 TPLL PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKO Stability (Jitter) -2 -- +2 % F13 Conditions MHz HS mode only MHz HS mode only Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 26-6: INTERNAL RC ACCURACY PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) F2 PIC18LF2331/2431/4331/4431 -15 +/-5 +15 % 25C VDD = 3.0V F3 All devices -15 +/-5 +15 % 25C VDD = 5.0V -- 35.938 kHz 25C VDD = 3.0V -- 35.938 kHz 25C VDD = 5.0V INTRC Accuracy @ Freq = 31 F5 F6 Legend: Note 1: 2: kHz(2) PIC18LF2331/2431/4331/4431 26.562 All devices 26.562 Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration. 2010 Microchip Technology Inc. DS39616D-page 347 PIC18F2331/2431/4331/4431 FIGURE 26-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 TABLE 26-7: Param No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 to CLKO -- 75 200 ns (Note 1) 11 TosH2ckH OSC1 to CLKO -- 75 200 ns (Note 1) 12 TckR CLKO Rise Time -- 35 100 ns (Note 1) 13 TckF CLKO Fall Time -- 35 100 ns (Note 1) CLKO to Port Out Valid -- -- 0.5 TCY + 20 ns (Note 1) 0.25 TCY + 25 -- -- ns (Note 1) (Note 1) 14 TckL2ioV 15 TioV2ckH Port In Valid before CLKO 16 TckH2ioI 17 TosH2ioV OSC1 (Q1 cycle) to Port Out Valid 18 TosH2ioI 18A Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) 0 -- -- ns -- 50 150 ns PIC18FXX31 100 -- -- ns PIC18LFXX31 200 -- -- ns 0 -- -- ns PIC18FXX31 -- 10 25 ns PIC18LFXX31 -- -- 60 ns PIC18FXX31 -- 10 25 ns PIC18LFXX31 -- -- 60 ns 19 TioV2osH Port Input Valid to OSC1 (I/O in setup time) 20 TioR Port Output Rise Time 20A 21 TioF 21A Port Output Fall Time 22 TINP INTx Pin High or Low Time TCY -- -- ns 23 TRBP RB<7:4> Change INTx High or Low Time TCY -- -- ns These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39616D-page 348 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins FIGURE 26-8: BROWN-OUT RESET TIMING VDD BVDD 35 VIRVST VBGAP = 1.2V (nominal) Enable Internal Reference Voltage Internal Reference Voltage Stable 2010 Microchip Technology Inc. 36 DS39616D-page 349 PIC18F2331/2431/4331/4431 TABLE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. 30 31 TMCL TWDT 32 33 TOST TPWRT 34 TIOZ 35 36 TBOR TIRVST 37 38 39 TLVD TCSD TIOBST Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become Stable Low-Voltage Detect Pulse Width CPU Start-up Time Time for INTOSC to Stabilize DS39616D-page 350 Min Typ Max Units 2 -- -- 4.00 -- s ms -- 1024 TOSC -- 1024 TOSC -- 65.5 -- -- ms Conditions TOSC = OSC1 period -- 2 -- s 200 -- -- 20 -- 50 s s VDD BVDD (see D005) 200 -- -- -- 10 1 -- -- -- s s ms VDD VLVD 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 TABLE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 Tt0H T0CKI High Pulse Width No prescaler 41 Tt0L T0CKI Low Pulse Width No prescaler With prescaler With prescaler 42 Tt0P T0CKI Period No prescaler With prescaler 45 Tt1H T1CKI High Synchronous, no prescaler Time Synchronous, PIC18FXX31 with prescaler PIC18LFXX31 Asynchronous 46 Tt1L T1CKI Low Time Asynchronous 47 Tt1P Ft1 0.5 TCY + 20 -- ns ns 10 -- 0.5 TCY + 20 -- ns 10 -- ns TCY + 10 -- ns Greater of: 20 ns or TCY + 40 N -- ns 0.5 TCY + 20 -- ns 10 -- ns ns 25 -- -- ns PIC18LFXX31 50 -- ns 0.5 TCY + 5 -- ns PIC18FXX31 10 -- ns PIC18LFXX31 25 -- ns PIC18FXX31 30 -- ns PIC18LFXX31 50 -- ns Greater of: 20 ns or TCY + 40 N -- ns 60 -- ns DC 50 kHz 2 TOSC 7 TOSC -- T1CKI Input Synchronous Period T1CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment 2010 Microchip Technology Inc. Units 30 Asynchronous 48 Max PIC18FXX31 Synchronous, no prescaler Synchronous, with prescaler Min Conditions VDD = 2V N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) DS39616D-page 351 PIC18F2331/2431/4331/4431 FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 26-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TccL TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With PIC18FXX31 prescaler PIC18LFXX31 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns CCPx Input High No prescaler Time With PIC18FXX31 prescaler PIC18LFXX31 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns 3 TCY + 40 N -- ns 52 TccP CCPx Input Period 53 TccR CCPx Output Fall Time 54 TccF DS39616D-page 352 CCPx Output Fall Time PIC18FXX31 -- 25 ns PIC18LFXX31 -- 45 ns PIC18FXX31 -- 25 ns PIC18LFXX31 -- 45 ns Conditions N = prescale value (1, 4 or 16) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 26-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCK (CKP = 0) 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 26-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 75 TdoR SDO Data Output Rise Time 76 TdoF SDO Data Output Fall Time 78 TscR SCK Output Rise Time PIC18FXX31 PIC18LFXX31 79 TscF SCK Output Fall Time 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge 2010 Microchip Technology Inc. Min Max Units 20 -- ns 1.5 TCY + 40 -- ns 40 -- ns -- 25 ns -- 45 ns -- 25 ns PIC18FXX31 -- 25 ns PIC18LFXX31 -- 45 ns -- 25 ns PIC18FXX31 -- 50 ns PIC18LFXX31 -- 100 ns Conditions DS39616D-page 353 PIC18F2331/2431/4331/4431 FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 TABLE 26-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 75 TdoR SDO Data Output Rise Time 76 TdoF SDO Data Output Fall Time 78 TscR SCK Output Rise Time 79 TscF SCK Output Fall Time 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge 20 -- ns 1.5 TCY + 40 -- ns 40 -- ns PIC18FXX31 -- 25 ns -- 45 ns -- 25 ns -- 25 ns PIC18FXX31 -- 45 ns -- 25 ns PIC18FXX31 -- 50 ns PIC18LFXX31 -- 100 ns TCY -- ns TdoV2scH, SDO Data Output Setup to SCK Edge TdoV2scL DS39616D-page 354 Max Units PIC18LFXX31 PIC18LFXX31 81 Min Conditions 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 26-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 0) Param No. Symbol Characteristic 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH SCK Input High Time 71A 72 TscL SCK Input Low Time 72A 73 Min TCY Max Units Conditions -- ns Continuous 1.25 TCY + 30 -- ns Single byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single byte 40 -- ns 20 -- ns TdiV2scH, Setup Time of SDI Data Input to SCK Edge TdiV2scL 73A TB2B -- ns 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge TscL2diL Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 40 -- ns 75 TdoR PIC18FXX31 -- 25 ns PIC18LFXX31 -- 45 ns SDO Data Output Rise Time 76 TdoF -- 25 ns 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXX31 TscL2doV PIC18LFXX31 -- 50 ns -- 100 ns 1.5 TCY + 40 -- ns 83 Note 1: 2: SDO Data Output Fall Time TscH2ssH, SS after SCK Edge TscL2ssH (Note 1) (Note 1) (Note 2) Requires the use of Parameter 73A. Only if Parameter 71A and 72A are used. 2010 Microchip Technology Inc. DS39616D-page 355 PIC18F2331/2431/4331/4431 FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI 77 bit 6 - - - -1 MSb In LSb In 74 TABLE 26-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH SCK Input High Time TscL SCK Input Low Time 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge TscL2diL 75 TdoR SDO Data Output Rise Time 76 TdoF SDO Data Output Fall Time 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 80 TscH2doV, SDO Data Output Valid after SCK TscL2doV Edge PIC18FXX31 -- 50 ns PIC18LFXX31 -- 100 ns TssL2doV SDO Data Output Valid after SS Edge PIC18FXX31 -- 50 ns PIC18LFXX31 -- 100 ns 1.5 TCY + 40 -- ns 71A 72 72A TCY -- ns 1.25 TCY + 30 -- ns Single byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single byte 40 -- ns (Note 1) -- ns (Note 2) 40 -- ns -- 25 ns -- 45 ns -- 25 ns Continuous PIC18FXX31 PIC18LFXX31 82 83 Note 1: 2: TscH2ssH, SS after SCK Edge TscL2ssH (Note 1) Requires the use of Parameter 73A. Only if Parameter 71A and 72A are used. DS39616D-page 356 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 26-15: I2CTM BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition TABLE 26-15: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. Characteristic 90 TSU:STA Start Condition 91 THD:STA 92 TSU:STO 93 THD:STO Stop Condition Max Units 4700 -- ns Only relevant for repeated Start condition ns After this period, the first clock pulse is generated Setup Time 400 kHz mode 600 -- Start Condition 100 kHz mode 4000 -- Hold Time 400 kHz mode 600 -- Stop Condition 100 kHz mode 4000 -- Setup Time Hold Time FIGURE 26-16: 100 kHz mode Min 400 kHz mode 600 -- 100 kHz mode 4700 -- 400 kHz mode 600 -- Conditions ns ns I2CTM BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out 2010 Microchip Technology Inc. DS39616D-page 357 PIC18F2331/2431/4331/4431 TABLE 26-16: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 -- s PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s PIC18FXX31 must operate at a minimum of 10 MHz 1.5 TCY -- 100 kHz mode 4.7 -- s PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s PIC18FXX31 must operate at a minimum of 10 MHz SSP module 101 TLOW Clock Low Time 1.5 TCY -- SDA and SCL Rise Time 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns SDA and SCL Fall Time 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF Start Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Only relevant for Repeated Start condition Start Condition Hold Time 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Data Input Hold Time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data Input Setup Time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Stop Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Output Valid From Clock 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns Bus Free Time 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF SSP Module 102 TR 103 TF 90 TSU:STA 91 THD:STA 106 THD:DAT 107 TSU:DAT 92 TSU:STO 109 TAA 110 TBUF D102 CB Note 1: 2: Bus Capacitive Loading CB is specified to be from 10 to 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,. TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS39616D-page 358 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 26-17: SSP I2CTM BUS DATA REQUIREMENTS Param. No. Symbol Characteristic Min Max Units 2(TOSC)(BRG + 1) -- ms 100 THIGH Clock High Time 100 kHz mode 400 kHz mode 2(TOSC)(BRG + 1) -- ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 102 TR SDA and SCL Rise Time 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 103 TF SDA and SCL Fall Time 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 90 TSU:STA Start Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 100 kHz mode 2(TOSC)(BRG + 1) -- ms 91 THD:STA Start Condition Hold Time 400 kHz mode 2(TOSC)(BRG + 1) -- ms 106 THD:DAT Data Input Hold Time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 ms 107 TSU:DAT 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 109 TAA Output Valid from Clock 100 kHz mode -- 3500 ns 400 kHz mode -- 1000 ns 110 TBUF Bus Free Time 100 kHz mode 4.7 -- ms 400 kHz mode 1.3 -- ms -- 400 pF D102 CB Data Input Setup Time Bus Capacitive Loading 2010 Microchip Technology Inc. Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated Time the bus must be free before a new transmission can start DS39616D-page 359 PIC18F2331/2431/4331/4431 FIGURE 26-17: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK/SS Pin 121 121 RC7/RX/DT/SDO Pin 120 122 TABLE 26-18: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol No. 120 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid 121 Tckrf 122 Tdtrf FIGURE 26-18: Min Max Units PIC18FXX31 -- 40 ns PIC18LFXX31 -- 100 ns Clock Out Rise Time and Fall Time (Master mode) PIC18FXX31 -- 20 ns PIC18LFXX31 -- 50 ns Data Out Rise Time and Fall Time PIC18FXX31 -- 20 ns PIC18LFXX31 -- 50 ns Conditions EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK/SS Pin 125 RC7/RX/DT/SDO Pin 126 TABLE 26-19: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol TdtV2ckl TckL2dtl DS39616D-page 360 Characteristic Min Max Units SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) 10 -- ns Data Hold after CK (DT hold time) 15 -- ns Conditions 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 26-20: A/D CONVERTER CHARACTERISTICS PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param Symbol No. Characteristic Min Typ Max Units -- VDD + 0.3 V Conditions Device Supply AVDD Analog VDD Supply VDD - 0.3 AVSS Analog VSS Supply VSS - 0.3 -- VSS + 0.3 V IAD Module Current (during conversion) -- -- 500 250 -- -- A A IADO Module Current Off -- -- 1.0 A VDD = 5V VDD = 2.5V AC Timing Parameters A10 FTHR Throughput Rate -- -- -- -- 200 75 ksps ksps VDD = 5V, single channel VDD < 3V, single channel A11 TAD A/D Clock Period 385 1000 -- -- 20,000 20,000 ns ns VDD = 5V VDD = 3V A12 TRC A/D Internal RC Oscillator Period -- -- -- 500 750 10000 1500 2250 20000 ns ns ns PIC18F parts PIC18LF parts AVDD < 3.0V A13 TCNV Conversion Time(1) 12 12 12 TAD A14 TACQ Acquisition Time(2) 2(2) -- -- TAD A16 TTC Conversion Start from External 1/4 TCY -- -- 1.5 1.8 -- -- AVDD - AVSS AVDD - AVSS Reference Inputs A20 VREF Reference Voltage for 10-Bit Resolution (VREF+ - VREF-) V V VDD 3V VDD < 3V VDD 3V A21 VREFH Reference Voltage High (AVDD or VREF+) 1.5V -- AVDD V A22 VREFL Reference Voltage Low (AVSS or VREF-) AVSS -- VREFH - 1.5V V A23 IREF Reference Current -- -- 150 A 75 A -- -- VDD = 5V VDD = 2.5V Analog Input Characteristics A26 VAIN Input Voltage(3) AVSS - 0.3 -- AVDD + 0.3 V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 2.5 k A31 ZCHIN Analog Channel Input Impedance -- -- 10.0 k VDD = 3.0V DC Performance A41 NR Resolution A42 EIL Integral Nonlinearity -- -- <1 LSb VDD 3.0V VREFH 3.0V A43 EIL Differential Nonlinearity -- -- <1 LSb VDD 3.0V VREFH 3.0V A45 EOFF Offset Error -- 0.5 <1.5 LSb VDD 3.0V VREFH 3.0V A46 EGA Gain Error -- 0.5 <1.5 LSb VDD 3.0V VREFH 3.0V A47 -- Monotonicity(4) -- VDD 3.0V VREFH 3.0V Note 1: 2: 3: 4: 10 bits guaranteed -- Conversion time does not include acquisition time. See Section 21.0 "10-Bit High-Speed Analog-to-Digital Converter (A/D) Module" for a full discussion of acquisition time requirements. In Sequential modes, TACQ should be 12 TAD or greater. For VDD < 2.7V and temperature below 0C, VAIN should be limited to range < VDD/2. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2010 Microchip Technology Inc. DS39616D-page 361 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 362 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead SPDIP (Skinny PDIP) Example PIC18F2331-I/SP e3 1010017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F2431 -I/ML e3 1010017 Legend: XX...X Y YY WW NNN e3 * Note: PIC18F2431-E/SO e3 1010017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. DS39616D-page 363 PIC18F2331/2431/4331/4431 27.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39616D-page 364 PIC18F4331-I/P e3 1010017 Example PIC18F4431 -I/PT e3 1010017 Example PIC18F4431 -I/ML e3 1010017 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 27.2 Package Details The following sections give the technical details of the packages. !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; < & & & = = ##4 4!! - 1!& & = = "#& "#>#& . - -- ##4>#& . < : 9& - -? & & 9 - 9# 4!! < ) ) < 1 = = 6 9#>#& 9 *9#>#& : * + 1, - !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/ !# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,1 2010 Microchip Technology Inc. DS39616D-page 365 PIC18F2331/2431/4331/4431 # #$ %&'( #) !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 D N E E1 NOTE 1 1 2 3 e b h A2 A h c L A1 6&! '! 9'&! 7"') %! L1 99. . 7 7 7: ; < & : 8& = 1, = ##4 4!! = = &# %%+ = - : >#& . ##4>#& . 1, : 9& 1, ? -1, ,'%@ & A = 3 &9& 9 = 3 & & 9 .3 3 & I B = <B 9# 4!! < = -- 9#>#& ) - = #%& D B = B #%&1 && ' E B = B !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#'' !# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 DS39616D-page 366 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. DS39616D-page 367 PIC18F2331/2431/4331/4431 *+%!,-./.*+! 0 1'(() ,1 !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6&! '! 9'&! 7"') %! 99. . 7 7 7: ; < & : 8& < &# %% , && 4!! - : >#& . .$ !##>#& . : 9& .$ !##9& ?1, .3 ?1, -? - ?1, -? - , &&>#& ) - - - , &&9& 9 , &&& .$ !## C = !" !"#$%&"' ()"&'"!&) &#*&&&# 4!!*!"&# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! = * ,1 DS39616D-page 368 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 *+%!,-./.*+! 0 1'(() ,1 !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 2010 Microchip Technology Inc. DS39616D-page 369 PIC18F2331/2431/4331/4431 2 . !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; & & & = = ##4 4!! = 1!& & = = "#& "#>#& . = ? ##4>#& . < = < : 9& < = & & 9 = 9# 4!! < = ) - = ) = - 1 = = 6 9#>#& 9 *9#>#& : * + 1, !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/ !# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,?1 DS39616D-page 370 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22 31 *+435/5/5%'3*+ !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 A c A2 A1 L L1 6&! '! 9'&! 7"') %9#! 99. . 7 7 7: ; 9#& : 8& = <1, = ##4 4!! &# %% = 3 &9& 9 ? 3 & & 9 .3 3 & I : >#& . B 1, -B : 9& 1, ##4>#& . 1, ##49& 1, B 9# 4!! = 9#>#& ) - - #%& D B B -B #%&1 && ' E B B -B !" !"#$%&"' ()"&'"!&) &#*&&&# ,'%!& ! & D!E' - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#'' !# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,?1 2010 Microchip Technology Inc. DS39616D-page 371 PIC18F2331/2431/4331/4431 22 31 *+435/5/5%'3*+ !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 DS39616D-page 372 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22 *+%!,-/*+! !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6&! '! 9'&! 7"') %! 99. . 7 7 7: ; & : 8& < &# %% , && 4!! - : >#& . .$ !##>#& . : 9& .$ !##9& ?1, .3 <1, ?- ? ?< <1, ?- ? , &&>#& ) - -< , &&9& 9 - , &&& .$ !## C = !" !"#$%&"' ()"&'"!&) &#*&&&# 4!!*!"&# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! ?< = * ,-1 2010 Microchip Technology Inc. DS39616D-page 373 PIC18F2331/2431/4331/4431 22 *+%!,-/*+! !" 3 &' !&"& 4#*!( !!& 4 %& &#& && 255***' '5 4 DS39616D-page 374 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 APPENDIX A: REVISION HISTORY Revision A (June 2003) Original data sheet for PIC18F2331/2431/4331/4431 devices. Revision B (December 2003) The Electrical Specifications in Section 26.0 "Electrical Characteristics" have been updated and there have been minor corrections to the data sheet text. Revision D (September 2010) Section 2.0 "Guidelines for Getting Started with PIC18F Microcontrollers" has been updated with more detailed explanations. Changes have been made to the port summary tables in Section 11.0 "I/O Ports". Section 26.0 "Electrical Characteristics" has been updated to include extended temperature data. Packaging diagrams have been replaced with new diagrams in Section 27.0 "Packaging Information". There have been minor text edits throughout the document. Revision C (June 2007) The data sheet has been updated with all known Data Sheet Errata items and there have been minor corrections made to the data sheet text. Also, the packaging diagrams have been updated in Section 27.0 "Packaging Information". TABLE B-1: APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. DEVICE DIFFERENCES Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 Program Memory (Bytes) 4096 8192 4096 8192 Program Memory (Instructions) 2048 4096 2048 4096 22 22 34 34 Interrupt Sources I/O Ports Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/ PWM Modules 1 1 1 1 5 Input Channels 5 Input Channels 9 Input Channels 9 Input Channels 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN 40-Pin PDIP 44-Pin TQFP 44-Pin QFN 40-Pin PDIP 44-Pin TQFP 44-Pin QFN 10-Bit Analog-to-Digital Module Packages 2010 Microchip Technology Inc. DS39616D-page 375 PIC18F2331/2431/4331/4431 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39616D-page 376 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to an enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18F442." The changes discussed, while devicespecific, are generally applicable to all mid-range to enhanced device migrations. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18FXXX Migration." This Application Note is available on Microchip's web site: www.Microchip.com. This Application Note is available on Microchip's web site: www.Microchip.com. 2010 Microchip Technology Inc. DS39616D-page 377 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 378 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 INDEX A A/D .................................................................................... 239 Acquisition Requirements ......................................... 249 Associated Registers ................................................ 255 Calculating the Minimum Required Acquisition Time ............................................... 250 Configuring................................................................ 247 Configuring Analog Port Pins.................................... 252 Conversions .............................................................. 253 Converter Characteristics ......................................... 361 Operation in Power-Managed Modes ....................... 252 Result Buffer ............................................................. 249 Selecting and Configuring Automatic Acquisition Time ............................................... 251 Selecting the Conversion Clock ................................ 251 Special Event Trigger (CCP)..................................... 147 Voltage References .................................................. 251 Absolute Maximum Ratings .............................................. 329 AC (Timing) Characteristics .............................................. 344 Load Conditions for Device Timing Specifications ........................................ 345 Parameter Symbology .............................................. 344 Temperature and Voltage Specifications .................. 345 Timing Conditions ..................................................... 345 ACK Pulse................................................................. 212, 214 ADDLW ............................................................................. 289 ADDWF ............................................................................. 289 ADDWFC .......................................................................... 290 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................. 290 ANDWF ............................................................................. 291 Application Notes AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ......................... 205 Assembler MPASM Assembler................................................... 326 Auto-Wake-up on Sync Break Character .......................... 231 B BC ..................................................................................... 291 BCF ................................................................................... 292 BF Bit ................................................................................ 206 Block Diagrams A/D ............................................................................ 246 Analog Input Model ................................................... 250 Capture Mode Operation .......................................... 146 Center Connected Load............................................ 194 Compare Mode Operation ........................................ 147 Dead-Time Control Unit for One PWM Output Pair .............................................. 191 EUSART Receive ..................................................... 229 EUSART Transmit .................................................... 227 External Clock Input, EC............................................. 31 External Components for Timer1 LP Oscillator......... 133 External Power-on Reset Circuit (Slow VDD Power-up).......................................... 49 Fail-Safe Clock Monitor............................................. 277 Generic I/O Port ........................................................ 113 Input Capture for IC1 ................................................ 153 Input Capture for IC2 and IC3................................... 154 Interrupt Logic ............................................................. 98 Low-Voltage Detect with External Input .................... 258 Motion Feedback Module.......................................... 152 2010 Microchip Technology Inc. On-Chip Reset Circuit................................................. 47 PIC18F2331/2431 ...................................................... 14 PIC18F4331/4431 ...................................................... 15 PLL ............................................................................. 30 Power Control PWM Module .................................... 174 PWM (Standard)....................................................... 149 PWM I/O Pin............................................................. 198 PWM Module, One Output Pair, Complementary Mode ...................................... 175 PWM Module, One Output Pair, Independent Mode ........................................... 175 PWM Time Base....................................................... 177 QEI ........................................................................... 161 RC Oscillator .............................................................. 31 RCIO Oscillator........................................................... 31 Reads from Flash Program Memory .......................... 89 Recommended Minimum Connections....................... 25 SSP (I2C Mode)........................................................ 212 SSP (SPI Mode) ....................................................... 209 System Clock.............................................................. 35 Table Read Operation ................................................ 85 Table Write Operation ................................................ 86 Table Writes to Flash Program Memory ..................... 91 Timer0 in 16-Bit Mode .............................................. 128 Timer0 in 8-Bit Mode ................................................ 128 Timer1 ...................................................................... 132 Timer1 (16-Bit Read/Write Mode)............................. 132 Timer2 ...................................................................... 137 Timer5 ...................................................................... 140 Velocity Measurement .............................................. 167 Watchdog Timer ....................................................... 274 BN..................................................................................... 292 BNC .................................................................................. 293 BNN .................................................................................. 293 BNOV ............................................................................... 294 BNZ .................................................................................. 294 BOR. See Brown-out Reset. BOV .................................................................................. 297 BRA .................................................................................. 295 Brown-out Reset (BOR).............................................. 49, 263 BSF................................................................................... 295 BTFSC .............................................................................. 296 BTFSS .............................................................................. 296 BTG .................................................................................. 297 BZ ..................................................................................... 298 C C Compilers MPLAB C18.............................................................. 326 CALL................................................................................. 298 Capture (CCP Module) ..................................................... 146 Associated Registers................................................ 148 CCP Pin Configuration ............................................. 146 CCPR1H:CCPR1L Registers ................................... 146 Prescaler .................................................................. 146 Software Interrupt ..................................................... 146 Timer1 Mode Selection............................................. 146 Capture/Compare/PWM (CCP) ........................................ 145 Capture Mode. See Capture. CCP1 ........................................................................ 145 CCPR1H Register ............................................ 145 CCPR1L Register ............................................. 145 DS39616D-page 379 PIC18F2331/2431/4331/4431 CCP2 ........................................................................ 145 CCPR2H Register............................................. 145 CCPR2L Register ............................................. 145 Compare Mode. See Compare. Timer Resources....................................................... 145 CKE Bit.............................................................................. 206 CKP Bit.............................................................................. 207 Clock Sources ..................................................................... 34 Effects of Power-Managed Modes .............................. 37 Selection Using OSCCON Register ............................ 34 Clocking Scheme/Instruction Cycle..................................... 65 CLRF................................................................................. 299 CLRWDT........................................................................... 299 Code Examples Changing Between Capture Prescalers .................... 146 Computed GOTO Using an Offset Value .................... 64 Data EEPROM Read .................................................. 81 Data EEPROM Refresh Routine ................................. 82 Data EEPROM Write .................................................. 81 Erasing a Flash Program Memory Row ...................... 90 Fast Register Stack..................................................... 64 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................. 75 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ................................... 135 Initializing PORTA ..................................................... 113 Initializing PORTB ..................................................... 116 Initializing PORTC..................................................... 119 Initializing PORTD..................................................... 122 Initializing PORTE ..................................................... 124 Reading a Flash Program Memory Word ................... 89 Saving STATUS, WREG and BSR Registers in RAM .............................................. 112 Writing to Flash Program Memory ........................ 93-94 16 x 16 Signed Multiply Routine ................................. 96 16 x 16 Unsigned Multiply Routine ............................. 96 8 x 8 Signed Multiply Routine ..................................... 95 8 x 8 Unsigned Multiply Routine ................................. 95 Code Protection ........................................................ 263, 279 Associated Registers ................................................ 279 Data EEPROM .......................................................... 282 Program Memory ...................................................... 280 COMF................................................................................ 300 Compare (CCP Module).................................................... 147 Associated Registers ................................................ 148 CCP Pin Configuration .............................................. 147 CCPR1 Register ....................................................... 147 CCPR2 Register ....................................................... 147 Software Interrupt Mode ........................................... 147 Special Event Trigger................................................ 147 Timer1 Mode Selection ............................................. 147 Configuration Bits.............................................................. 263 Configuration Register Protection ..................................... 282 Conversion Considerations ............................................... 376 CPFSEQ ........................................................................... 300 CPFSGT............................................................................ 301 CPFSLT ............................................................................ 301 Crystal Oscillator/Ceramic Resonators ............................... 29 Customer Change Notification Service ............................. 387 Customer Notification Service........................................... 387 Customer Support ............................................................. 387 DS39616D-page 380 D D/A Bit............................................................................... 206 Data Addressing Modes ..................................................... 75 Direct .......................................................................... 75 Indirect ........................................................................ 75 Inherent and Literal..................................................... 75 Data EEPROM Memory...................................................... 79 Associated Registers .................................................. 83 EEADR Register ......................................................... 79 EECON1 and EECON2 Registers .............................. 79 Operation During Code-Protect .................................. 82 Protection Against Spurious Write .............................. 81 Reading ...................................................................... 81 Using .......................................................................... 82 Write Verify ................................................................. 81 Writing ........................................................................ 81 Data Memory ...................................................................... 67 Access Bank ............................................................... 68 Bank Select Register (BSR) ....................................... 68 General Purpose Register (GPR) File ........................ 68 Map for PIC18F2331/2431/4331/4431 ....................... 67 Special Function Registers (SFRs)............................. 69 DAW ................................................................................. 302 DC Characteristics............................................................ 339 Power-Down and Supply Current ............................. 332 Supply Voltage ......................................................... 331 DCFSNZ ........................................................................... 303 DECF ................................................................................ 302 DECFSZ ........................................................................... 303 Development Support ....................................................... 325 Device Differences............................................................ 375 Device Overview................................................................. 11 Features (table) .......................................................... 13 New Core Features..................................................... 11 Other Special Features............................................... 12 Device Reset Timers Oscillator Start-up Timer (OST) .................................. 50 PLL Lock Time-out...................................................... 50 Power-up Timer (PWRT) ............................................ 50 Time-out Sequence .................................................... 50 Direct Addressing ............................................................... 76 E Electrical Characteristics .................................................. 329 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................. 217 Equations A/D Acquisition Time ................................................ 249 Conversion Time for Multi-Channel Modes .............. 254 Minimum A/D Holding Capacitor Charging Time ...... 249 PWM Period for Free-Running Mode ....................... 185 PWM Period for Up/Down Count Mode .................... 185 PWM Resolution ....................................................... 185 16 x 16 Signed Multiplication Algorithm...................... 96 16 x 16 Unsigned Multiplication Algorithm.................. 96 Errata .................................................................................... 9 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 EUSART Asynchronous Mode ................................................. 226 Associated Registers, Receive ......................... 230 Associated Registers, Transmit ........................ 228 Auto-Wake-up on Sync Break .......................... 231 Receiver............................................................ 229 Receiving a Break Character ............................ 232 Setting Up 9-Bit Mode with Address Detect...... 229 Transmitter........................................................ 226 12-Bit Break Character Sequence .................... 232 Baud Rate Generator (BRG)..................................... 221 Associated Registers ........................................ 222 Auto-Baud Rate Detect ..................................... 225 Baud Rate Error, Calculating ............................ 222 Baud Rates, Asynchronous Modes .................. 222 High Baud Rate Select (BRGH Bit) .................. 221 Power-Managed Mode Operation..................... 221 Sampling ........................................................... 221 Serial Port Enable (SPEN Bit)................................... 217 Synchronous Master Mode ....................................... 233 Associated Registers, Receive ......................... 236 Associated Registers, Transmit ........................ 234 Reception.......................................................... 235 Transmission .................................................... 233 Synchronous Slave Mode ......................................... 237 Associated Registers, Receive ......................... 238 Associated Registers, Transmit ........................ 237 Reception.......................................................... 238 Transmission .................................................... 237 External Clock Input ............................................................ 31 F Fail-Safe Clock Monitor............................................. 263, 277 Exiting ....................................................................... 277 Interrupts in Power-Managed Modes........................ 278 POR or Wake From Sleep ........................................ 278 WDT During Oscillator Failure .................................. 277 Fail-Safe Clock Monitor (FSCM) ....................................... 263 Fast Register Stack............................................................. 64 Flash Program Memory ...................................................... 85 Associated Registers .................................................. 94 Control Registers ........................................................ 86 EECON1 and EECON2 ...................................... 86 Erase Sequence ......................................................... 90 Erasing........................................................................ 90 Operation During Code-Protect .................................. 94 Reading....................................................................... 89 TABLAT Register ........................................................ 88 Table Pointer............................................................... 88 Boundaries Based on Operation......................... 88 Table Pointer Boundaries ........................................... 88 Table Reads and Table Writes ................................... 85 Unexpected Termination of Write Operation............... 94 Write Sequence .......................................................... 92 Write Verify ................................................................. 94 Writing......................................................................... 91 FSCM. See Fail-Safe Clock Monitor. G Getting Started .................................................................... 25 GOTO ............................................................................... 304 2010 Microchip Technology Inc. H Hardware Multiplier............................................................. 95 Introduction................................................................. 95 Operation.................................................................... 95 Performance Comparison........................................... 95 I I/O Ports ........................................................................... 113 ID Locations.............................................................. 263, 282 INCF ................................................................................. 304 INCFSZ............................................................................. 305 In-Circuit Debugger........................................................... 282 In-Circuit Serial Programming (ICSP)....................... 263, 282 Independent PWM Mode .................................................. 193 Duty Cycle Assignment ............................................ 193 Indirect Addressing ............................................................. 76 INFSNZ............................................................................. 305 Initialization Conditions for All Registers....................... 54-59 Instruction Flow/Pipelining .................................................. 65 Instruction Set ADDLW..................................................................... 289 ADDWF .................................................................... 289 ADDWFC.................................................................. 290 ANDLW..................................................................... 290 ANDWF .................................................................... 291 BC............................................................................. 291 BCF .......................................................................... 292 BN............................................................................. 292 BNC .......................................................................... 293 BNN .......................................................................... 293 BNOV ....................................................................... 294 BNZ .......................................................................... 294 BOV .......................................................................... 297 BRA .......................................................................... 295 BSF........................................................................... 295 BTFSC...................................................................... 296 BTFSS ...................................................................... 296 BTG .......................................................................... 297 BZ ............................................................................. 298 CALL......................................................................... 298 CLRF ........................................................................ 299 CLRWDT .................................................................. 299 COMF ....................................................................... 300 CPFSEQ ................................................................... 300 CPFSGT ................................................................... 301 CPFSLT.................................................................... 301 DAW ......................................................................... 302 DCFSNZ ................................................................... 303 DECF........................................................................ 302 DECFSZ ................................................................... 303 General Format ........................................................ 285 GOTO ....................................................................... 304 INCF ......................................................................... 304 INCFSZ..................................................................... 305 INFSNZ..................................................................... 305 IORLW ...................................................................... 306 IORWF...................................................................... 306 LFSR ........................................................................ 307 MOVF ....................................................................... 307 MOVFF ..................................................................... 308 MOVLB ..................................................................... 308 DS39616D-page 381 PIC18F2331/2431/4331/4431 MOVLW .................................................................... 309 MOVWF .................................................................... 309 MULLW ..................................................................... 310 MULWF ..................................................................... 310 NEGF ........................................................................ 311 NOP .......................................................................... 311 POP .......................................................................... 312 PUSH ........................................................................ 312 RCALL ...................................................................... 313 Read-Modify-Write Operations ................................. 283 RESET ...................................................................... 313 RETFIE ..................................................................... 314 RETLW ..................................................................... 314 RETURN ................................................................... 315 RLCF......................................................................... 315 RLNCF ...................................................................... 316 RRCF ........................................................................ 316 RRNCF ..................................................................... 317 SETF ......................................................................... 317 SLEEP ...................................................................... 318 SUBFWB................................................................... 318 SUBLW ..................................................................... 319 SUBWF ..................................................................... 319 SUBWFB................................................................... 320 Summary................................................................... 283 Summary Table......................................................... 286 SWAPF ..................................................................... 320 TBLRD ...................................................................... 321 TBLWT ...................................................................... 322 TSTFSZ .................................................................... 323 XORLW ..................................................................... 323 XORWF..................................................................... 324 INTCON Register RBIF Bit..................................................................... 116 INTCON Registers .............................................................. 99 Inter-Integrated Circuit (I2C). See I2C Mode. Internal Oscillator Block ...................................................... 32 Adjustment .................................................................. 32 INTIO Modes............................................................... 32 INTRC Output Frequency ........................................... 32 OSCTUNE Register .................................................... 32 Internal RC Oscillator Use with WDT ........................................................... 274 Internet Address................................................................ 387 Interrupt Sources............................................................... 263 Capture Complete (CCP) .......................................... 146 Interrupt-on-Change (RB7:RB4) ............................... 116 INTx Pin .................................................................... 112 PORTB, Interrupt-on-Change ................................... 112 TMR0 ........................................................................ 112 TMR1 Overflow ......................................................... 131 TMR2 to PR2 Match (PWM) ............................. 136, 149 Interrupts ............................................................................. 97 Context Saving, During ............................................. 112 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit)....................................... 146 Interrupts, Flag Bits CCP1 Flag (CCP1IF Bit) ........................................... 146 CCP1IF Flag (CCP1IF Bit) ........................................ 147 CCP2IF Flag (CCP2IF Bit) ........................................ 147 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .......................................................... 116 INTOSC, INTRC. See Internal Oscillator Block. IORLW .............................................................................. 306 IORWF .............................................................................. 306 IPR Registers .................................................................... 108 DS39616D-page 382 I2C Mode Operation .................................................................. 212 I2C Mode (SSP) Addressing................................................................ 213 Associated Registers ................................................ 216 Master Mode............................................................. 216 Mode Selection ......................................................... 212 Multi-Master Mode .................................................... 216 Operation .................................................................. 212 Reception ................................................................. 214 Slave Mode............................................................... 212 SCL and SDA Pins ........................................... 212 Transmission ............................................................ 215 L LFSR................................................................................. 307 Low-Voltage Detect .......................................................... 257 Applications .............................................................. 261 Associated Registers ................................................ 261 Characteristics .......................................................... 342 Current Consumption................................................ 259 Effects of a Reset ..................................................... 261 Operation .................................................................. 259 Operation During Sleep ............................................ 261 Setup ........................................................................ 259 Start-up Time ............................................................ 260 LVD. See Low-Voltage Detect. M Master Clear (MCLR).......................................................... 49 Memory Organization ......................................................... 61 Data Memory .............................................................. 67 Program Memory ........................................................ 61 Memory Programming Requirements............................... 341 MFM Input Capture Edge Capture Mode ......................................... 156 Entering and Timing ......................................... 159 IC Interrupts...................................................... 159 Pulse-Width Measurement Mode ..................... 157 Special Event Trigger (CAP1 Only) .................. 160 State Change.................................................... 158 Time Base Reset Summary.............................. 160 Timer5 Reset .................................................... 159 Input Capture (IC) Submode..................................... 153 Input Capture Mode Period Measurement Mode .............................. 157 Noise Filters.............................................................. 169 Microchip Internet Web Site.............................................. 387 Migration From Baseline to Enhanced Devices................ 376 Migration From High-End to Enhanced Devices............... 377 Migration From Mid-Range to Enhanced Devices ............ 377 Motion Feedback Module (MFM) ...................................... 151 Associated Registers ................................................ 171 Summary of Features ............................................... 151 MOVF ............................................................................... 307 MOVFF ............................................................................. 308 MOVLB ............................................................................. 308 MOVLW ............................................................................ 309 MOVWF ............................................................................ 309 MPLAB ASM30 Assembler, Linker, Librarian ................... 326 MPLAB Integrated Development Environment Software .............................................. 325 MPLAB PM3 Device Programmer .................................... 328 MPLAB REAL ICE In-Circuit Emulator System ................ 327 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MPLINK Object Linker/MPLIB Object Librarian ................ 326 MULLW ............................................................................. 310 MULWF ............................................................................. 310 N NEGF ................................................................................ 311 NOP .................................................................................. 311 O Opcode Field Descriptions ................................................ 284 Oscillator Configuration....................................................... 29 EC ............................................................................... 29 ECIO ........................................................................... 29 HS ............................................................................... 29 HSPLL......................................................................... 29 Internal Oscillator Block .............................................. 32 INTIO1 ........................................................................ 29 INTIO2 ........................................................................ 29 LP................................................................................ 29 RC............................................................................... 29 RCIO ........................................................................... 29 XT ............................................................................... 29 Oscillator Selection ........................................................... 263 Oscillator Start-up Timer (OST) .................................. 37, 263 Oscillator Switching............................................................. 34 Oscillator Transitions .......................................................... 37 Oscillator, Timer1 .............................................................. 131 P P (Stop) Bit........................................................................ 206 Packaging Information ...................................................... 363 Details ....................................................................... 365 Marking ..................................................................... 363 PIE Registers .................................................................... 105 Pin Diagrams ........................................................................ 4 Pin Functions MCLR/VPP................................................................... 16 MCLR/VPP/RE3........................................................... 19 OSC1/CLKI/RA7 ................................................... 16, 19 OSC2/CLKO/RA6 ................................................. 16, 19 RA0/AN0 ............................................................... 16, 20 RA1/AN1 ............................................................... 16, 20 RA2/AN2/VREF-/CAP1/INDX................................. 16, 20 RA3/AN3/VREF+/CAP2/QEA................................. 16, 20 RA4/AN4/CAP3/QEB ............................................ 16, 20 RA5/AN5/LVDIN ......................................................... 20 RB0/PWM0 ........................................................... 17, 21 RB1/PWM1 ........................................................... 17, 21 RB2/PWM2 ........................................................... 17, 21 RB3/PWM3 ........................................................... 17, 21 RB4/KBIO/PWM5........................................................ 17 RB4/KBI0/PWM5 ........................................................ 21 RB5/KBI1/PWM4/PGM ......................................... 17, 21 RB6/KBI2/PGC ..................................................... 17, 21 RB7/KBI3/PGD ..................................................... 17, 21 RC0/T1OSO/T1CKI .............................................. 18, 22 RC1/T1OSI/CCP2/FLTA ....................................... 18, 22 RC2/CCP1 .................................................................. 18 RC2/CCP1/FLTB ........................................................ 22 RC3/T0CKI/T5CKI/INT0........................................ 18, 22 RC4/INT1/SDI/SDA............................................... 18, 22 RC5/INT2/SCK/SCL.............................................. 18, 22 RC6/TX/CK/SS ..................................................... 18, 22 RC7/RX/DT/SDO .................................................. 18, 22 RD0/T0CKI/T5CKI ...................................................... 23 RD1/SDO .................................................................... 23 2010 Microchip Technology Inc. RD2/SDI/SDA ............................................................. 23 RD3/SCK/SCL ............................................................ 23 RD4/FLTA................................................................... 23 RD5/PWM4................................................................. 23 RD6/PWM6................................................................. 23 RD7/PWM7................................................................. 23 RE0/AN6..................................................................... 24 RE1/AN7..................................................................... 24 RE2/AN8..................................................................... 24 VDD ....................................................................... 18, 24 VSS ....................................................................... 24, 18 Pinout I/O Descriptions PIC18F2331/2431 ...................................................... 16 PIC18F4331/4431 ...................................................... 19 PIR Registers.................................................................... 102 PLL HSPLL Mode .............................................................. 30 Multiplier ..................................................................... 30 POP .................................................................................. 312 POR. See Power-on Reset. PORTA Associated Registers................................................ 115 LATA Register .......................................................... 113 PORTA Register....................................................... 113 TRISA Register......................................................... 113 PORTB Associated Registers................................................ 118 LATB Register .......................................................... 116 PORTB Register....................................................... 116 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 116 TRISB Register......................................................... 116 PORTC Associated Registers................................................ 121 LATC Register .......................................................... 119 PORTC Register....................................................... 119 TRISC Register ........................................................ 119 PORTD Associated Registers................................................ 123 LATD Register .......................................................... 122 PORTD Register....................................................... 122 TRISD Register ........................................................ 122 PORTE Associated Registers................................................ 125 LATE Register .......................................................... 124 PORTE Register....................................................... 124 TRISE Register......................................................... 124 Postscaler, WDT Assignment (PSA Bit) ............................................... 129 Rate Select (T0PS2:T0PS0 Bits).............................. 129 Power-Managed Modes...................................................... 39 Clock Sources ............................................................ 39 Clock Transitions and Status Indicators ..................... 40 Entering ...................................................................... 39 Exiting Idle and Sleep Modes ..................................... 45 By Interrupt ......................................................... 45 By Reset ............................................................. 45 By WDT Time-out ............................................... 45 Without an Oscillator Start-up Delay .................. 46 Idle Modes .................................................................. 43 PRI_IDLE ........................................................... 44 RC_IDLE ............................................................ 45 SEC_IDLE .......................................................... 44 Multiple Sleep Commands.......................................... 40 DS39616D-page 383 PIC18F2331/2431/4331/4431 Run Modes.................................................................. 40 PRI_RUN ............................................................ 40 RC_RUN ............................................................. 41 SEC_RUN........................................................... 40 Selecting ..................................................................... 39 Sleep Mode ................................................................. 43 Summary (table) ......................................................... 39 Power-on Reset (POR) ............................................... 49, 263 Power-up Delays................................................................. 37 Power-up Timer (PWRT)............................................. 37, 263 Prescaler, Timer0.............................................................. 129 Assignment (PSA Bit) ............................................... 129 Rate Select (T0PS2:T0PS0 Bits) .............................. 129 Prescaler, Timer2.............................................................. 150 PRI_IDLE Mode .................................................................. 44 PRI_RUN Mode .................................................................. 40 Program Counter (PC) ........................................................ 62 Program Memory Instructions.................................................................. 66 Two-Word ........................................................... 66 Interrupt Vector ........................................................... 61 Map and Stack PIC18F2331/4331............................................... 61 PIC18F2431/4431............................................... 61 Reset Vector ............................................................... 61 Program Verification.......................................................... 279 Pulse-Width Modulation. See PWM (CCP Module). PUSH ................................................................................ 312 PUSH and POP Instructions ............................................... 64 PWM Associated Registers ................................................ 203 Complementary Operation ........................................ 190 Control Registers ...................................................... 176 Dead-Time Generators ............................................. 191 Duty Cycle................................................................. 187 Center-Aligned .................................................. 189 Comparison....................................................... 187 Edge-Aligned .................................................... 188 Register Buffers ................................................ 188 Registers........................................................... 187 Fault Inputs ............................................................... 199 Functionality .............................................................. 176 Modes Continuous Up/Down Count ............................. 180 Free-Running .................................................... 180 Single-Shot ....................................................... 180 Output and Polarity Control....................................... 198 Output Override ........................................................ 194 Single-Pulse Operation ............................................. 194 Special Event Trigger................................................ 202 Time Base ................................................................. 176 Interrupts........................................................... 181 Continuous Up/Down Count Mode ...................................... 182 Double Update Mode ................................ 184 Free-Running Mode .................................. 181 Single-Shot Mode ..................................... 182 Postscaler ......................................................... 181 Prescaler........................................................... 180 Update Lockout ......................................................... 202 DS39616D-page 384 PWM (CCP Module) Associated Registers ................................................ 150 CCPR1H:CCPR1L Registers.................................... 149 Duty Cycle ................................................................ 149 Example Frequencies/Resolutions ........................... 150 Period ....................................................................... 149 PR2 Register, Writing ............................................... 149 Setup for PWM Operation......................................... 150 TMR2 to PR2 Match ......................................... 136, 149 PWM Period...................................................................... 185 Q Q Clock ............................................................................. 150 QEI and IC Shared Interrupts .......................................... 170 Configuration ............................................................ 162 Direction of Rotation ................................................. 163 Interrupts .................................................................. 164 Operation .................................................................. 163 Operation in Sleep Mode .......................................... 170 3x Input Capture ............................................... 170 Sampling Modes ....................................................... 163 Velocity Measurement .............................................. 167 Quadrature Encoder Interface (QEI)................................. 161 R R/W Bit...................................................... 206, 213, 214, 215 RAM. See Data Memory. RC Oscillator....................................................................... 31 RCIO Oscillator Mode................................................. 31 RC_IDLE Mode................................................................... 45 RC_RUN Mode................................................................... 41 RCALL .............................................................................. 313 RCSTA Register SPEN Bit................................................................... 217 Reader Response............................................................. 388 Registers ADCHS (A/D Channel Select) .................................. 244 ADCON0 (A/D Control 0).......................................... 240 ADCON1 (A/D Control 1).......................................... 241 ADCON2 (A/D Control 2).......................................... 242 ADCON3 (A/D Control 3).......................................... 243 ANSEL0 (Analog Select 0) ....................................... 245 ANSEL1 (Analog Select 1) ....................................... 245 BAUDCON (Baud Rate Control)............................... 220 CAPxCON (Input Capture x Control) ........................ 155 CCPxCON (CCPx Control) ....................................... 145 CONFIG1H (Configuration 1 High) ........................... 264 CONFIG2H (Configuration 2 High) ........................... 266 CONFIG2L (Configuration 2 Low) ............................ 265 CONFIG3H (Configuration 3 High) ........................... 268 CONFIG3L (Configuration 3 Low) ............................ 267 CONFIG4L (Configuration 4 Low) ............................ 269 CONFIG5H (Configuration 5 High) ........................... 270 CONFIG5L (Configuration 5 Low) ............................ 270 CONFIG6H (Configuration 6 High) ........................... 271 CONFIG6L (Configuration 6 Low) ............................ 271 CONFIG7H (Configuration 7 High) ........................... 272 CONFIG7L (Configuration 7 Low) ............................ 272 DEVID1 (Device ID 1)............................................... 273 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DEVID2 (Device ID 2) ............................................... 273 DFLTCON (Digital Filter Control) .............................. 169 DTCON (Dead-Time Control) ................................... 192 EECON1 (Data EEPROM Control 1) .......................... 87 EECON1 (EEPROM Control 1)................................... 80 FLTCONFIG (Fault Configuration)............................ 201 INTCON (Interrupt Control)......................................... 99 INTCON2 (Interrupt Control 2).................................. 100 INTCON3 (Interrupt Control 3).................................. 101 IPR1 (Peripheral Interrupt Priority 1)......................... 108 IPR2 (Peripheral Interrupt Priority 2)......................... 109 IPR3 (Peripheral Interrupt Priority 3)......................... 110 LVDCON (Low-Voltage Detect Control).................... 257 OSCCON (Oscillator Control) ..................................... 36 OSCTUNE (Oscillator Tuning) .................................... 33 OVDCOND (Output Override Control) ...................... 196 OVDCONS (Output State) ........................................ 196 PIE1 (Peripheral Interrupt Enable 1)......................... 105 PIE2 (Peripheral Interrupt Enable 2)......................... 106 PIE3 (Peripheral Interrupt Enable 3)......................... 107 PIR1 (Peripheral Interrupt Request (Flag) 1) ............ 102 PIR2 (Peripheral Interrupt Request (Flag) 2) ............ 103 PIR3 (Peripheral Interrupt Request (Flag) 3) ............ 104 PTCON0 (PWM Timer Control 0) ............................. 178 PTCON1 (PWM Timer Control 1) ............................. 178 PWMCON0 (PWM Control 0) ................................... 179 PWMCON1 (PWM Control 1) ................................... 180 QEICON (QEI Control).............................................. 162 RCON (Reset Control) ........................................ 48, 111 RCSTA (Receive Status and Control)....................... 219 SSPCON (SSP Control)............................................ 207 SSPSTAT (SSP Status)............................................ 206 STATUS...................................................................... 74 STKPTR (Stack Pointer) ............................................. 63 Summary............................................................... 70-73 TRISE ....................................................................... 124 TXSTA (Transmit Status and Control) ...................... 218 T0CON (Timer0 Control)........................................... 127 T1CON (Timer1 Control)........................................... 131 T2CON (Timer2 Control)........................................... 136 T5CON (Timer5 Control)........................................... 139 WDTCON (Watchdog Timer Control) ....................... 275 RESET .............................................................................. 313 Reset................................................................................... 47 Resets ............................................................................... 263 RETFIE ............................................................................. 314 RETLW ............................................................................. 314 RETURN ........................................................................... 315 Return Address Stack ......................................................... 62 Return Stack Pointer (STKPTR) ......................................... 62 Revision History ................................................................ 375 RLCF................................................................................. 315 RLNCF .............................................................................. 316 RRCF ................................................................................ 316 RRNCF ............................................................................. 317 S S (Start) Bit ....................................................................... 206 SCK................................................................................... 205 SCL ................................................................................... 212 SDI .................................................................................... 205 SDO .................................................................................. 205 SEC_IDLE Mode................................................................. 44 SEC_RUN Mode ................................................................. 40 Serial Clock (SCK) Pin ...................................................... 205 Serial Data In (SDI) Pin..................................................... 205 2010 Microchip Technology Inc. Serial Data Out (SDO) Pin................................................ 205 SETF ................................................................................ 317 Single-Supply ICSP Programming.................................... 282 Slave Select (SS) Pin ....................................................... 205 SLEEP .............................................................................. 318 Sleep OSC1 and OSC2 Pin States....................................... 37 Software Simulator (MPLAB SIM) .................................... 327 Special Event Trigger. See Compare (CCP Module). Special Features of the CPU ............................................ 263 Special Function Registers Map............................................................................. 69 SPI Mode (SSP) ............................................................... 205 Associated Registers................................................ 211 Serial Clock .............................................................. 205 Serial Data In............................................................ 205 Serial Data Out ......................................................... 205 Slave Select.............................................................. 205 SS ..................................................................................... 205 SSP Overview. TMR2 Output for Clock Shift............................. 136, 137 SSPEN Bit ........................................................................ 207 SSPM<3:0> Bits ............................................................... 208 SSPOV Bit ........................................................................ 207 Stack Full/Underflow Resets............................................... 64 Status Bits, Significance and Initialization for RCON Register........................................................... 53 SUBFWB .......................................................................... 318 SUBLW ............................................................................. 319 SUBWF............................................................................. 319 SUBWFB .......................................................................... 320 SWAPF ............................................................................. 320 Synchronous Serial Port. See SSP. T TABLAT Register................................................................ 88 Table Pointer Operations (table)......................................... 88 TBLPTR Register................................................................ 88 TBLRD .............................................................................. 321 TBLWT ............................................................................. 322 Time-out in Various Situations (table)................................. 50 Timer0 .............................................................................. 127 Associated Registers................................................ 129 Clock Source Edge Select (T0SE Bit) ...................... 129 Clock Source Select (T0CS Bit) ............................... 129 Interrupt .................................................................... 129 Operation.................................................................. 129 Prescaler .................................................................. 129 Switching Assignment ...................................... 129 Prescaler. See Prescaler, Timer0. 16-Bit Mode Timer Reads and Writes ...................... 129 Timer1 .............................................................................. 131 Associated Registers................................................ 135 Interrupt .................................................................... 134 Operation.................................................................. 132 Oscillator........................................................... 131, 133 Layout Considerations...................................... 133 Overflow Interrupt ..................................................... 131 Resetting, Using a Special Event Trigger Output (CCP).................................................... 134 Special Event Trigger (CCP) .................................... 147 TMR1H Register....................................................... 131 TMR1L Register ....................................................... 131 Use as a Real-Time Clock (RTC) ............................. 134 16-Bit Read/Write Mode ........................................... 134 DS39616D-page 385 PIC18F2331/2431/4331/4431 Timer2 ............................................................................... 136 Associated Registers ................................................ 137 Interrupt..................................................................... 137 Operation .................................................................. 136 Postscaler. See Postscaler, Timer2. Prescaler. See Prescaler, Timer2. PR2 Register............................................................. 136 SSP Clock Shift................................................. 136, 137 TMR2 Register .......................................................... 136 TMR2 to PR2 Match Interrupt ........................... 136, 149 Timer5 ............................................................................... 139 Associated Registers ................................................ 143 Interrupt..................................................................... 142 Noise Filter ................................................................ 142 Operation .................................................................. 140 Continuous Count and Single-Shot................... 141 Sleep Mode....................................................... 142 Prescaler ................................................................... 141 Special Event Trigger Output ............................................................... 142 Reset Input........................................................ 142 16-Bit Read/Write and Write Modes ......................... 141 16-Bit Read-Modify-Write.......................................... 141 Timing Diagrams Automatic Baud Rate Calculation ............................. 225 Auto-Wake-up Bit (WUE) During Normal Operation.............................................. 231 Auto-Wake-up Bit (WUE) During Sleep .................... 231 Brown-out Reset (BOR) ............................................ 349 Capture/Compare/PWM (All CCP Modules) ............. 352 CAPx Interrupts and IC1 Special Event Trigger........ 159 CLKO and I/O ........................................................... 348 Clock, Instruction Cycle .............................................. 65 Dead-Time Insertion for Complementary PWM ........ 191 Duty Cycle Update Times in Continuous Up/Down Count Mode....................................... 188 Duty Cycle Update Times in Continuous Up/Down Count Mode with Double Updates ................................................ 189 Edge Capture Mode .................................................. 156 Edge-Aligned PWM................................................... 188 EUSART Asynchronous Reception .......................... 230 EUSART Asynchronous Transmission ..................... 227 EUSART Asynchronous Transmission (Back to Back)................................................... 227 EUSART Synchronous Receive (Master/Slave) ....... 360 EUSART Synchronous Reception (Master Mode, SREN)....................................... 235 EUSART Synchronous Transmission ....................... 233 EUSART Synchronous Transmission (Through TXEN)................................................ 234 EUSART SynchronousTransmission (Master/Slave)................................................... 360 Example SPI Master Mode (CKE = 0) ...................... 353 Example SPI Master Mode (CKE = 1) ...................... 354 Example SPI Slave Mode (CKE = 0) ........................ 355 Example SPI Slave Mode (CKE = 1) ........................ 356 External Clock (All Modes Except PLL) .................... 346 Fail-Safe Clock Monitor............................................. 278 Input Capture on State Change, Hall Effect Sensor Mode.................................................... 158 I2C Bus Data ............................................................. 357 I2C Bus Start/Stop Bits.............................................. 357 I2C Reception (7-Bit Address)................................... 214 I2C Transmission (7-Bit Address) ............................. 215 DS39616D-page 386 Low-Voltage Detect .................................................. 260 Low-Voltage Detect Characteristics.......................... 342 Noise Filter................................................................ 170 Pulse-Width Measurement Mode ............................. 157 PWM Output ............................................................. 149 PWM Output Override (Example 1) .......................... 197 PWM Output Override (Example 2) .......................... 197 PWM Override Bits in Complementary Mode ........... 195 PWM Period Buffer Updates in Continuous Up/Down Count Mode ................... 186 PWM Period Buffer Updates in Free-Running Mode.......................................... 186 PWM Time Base Interrupt, Continuous Up/Down Count Mode ...................................... 183 PWM Time Base Interrupt, Continuous Up/Down Count Mode with Double Updates................................................ 184 PWM Time Base Interrupt, Free-Running Mode ...... 181 PWM Time Base Interrupt, Single-Shot Mode.......... 182 QEI Inputs When Sampled by Filter ......................... 165 QEI Reset on Period Match ...................................... 165 QEI Reset with the Index Input ................................. 166 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) .................................................. 349 Send Break Character Sequence ............................. 232 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................. 52 SPI Mode (Master Mode).......................................... 210 SPI Mode (Slave Mode with CKE = 0)...................... 210 SPI Mode (Slave Mode with CKE = 1)...................... 211 Start of Center-Aligned PWM ................................... 189 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ........................................... 53 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 1 ....................... 51 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 2 ....................... 52 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) ............... 51 Timer0 and Timer1 External Clock ........................... 351 Transition for Entry to Idle Mode................................. 44 Transition for Entry to SEC_RUN Mode ..................... 41 Transition for Entry to Sleep Mode ............................. 43 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 276 Transition for Wake From Idle to Run Mode............... 44 Transition for Wake From Sleep (HSPLL) .................. 43 Transition From RC_RUN Mode to PRI_RUN Mode.................................................. 42 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) ................................... 41 Transition to RC_RUN Mode ...................................... 42 Velocity Measurement .............................................. 168 Timing Diagrams and Specifications ................................ 346 Capture/Compare/PWM Requirements (All CCP Modules) ............................................ 352 CLKO and I/O Requirements.................................... 348 EUSART Synchronous Receive Requirements........ 360 EUSART Synchronous Transmission Requirements ................................................... 360 Example SPI Mode Requirements (Master Mode, CKE = 0)................................... 353 Example SPI Mode Requirements (Master Mode, CKE = 1)................................... 354 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Example SPI Mode Requirements (Slave Mode, CKE = 0) ..................................... 355 Example SPI Slave Mode Requirements (CKE = 1) .......................................................... 356 External Clock Requirements ................................... 346 Internal RC Accuracy ................................................ 347 I2C Bus Data Requirements (Slave Mode) ............... 358 I2C Bus Start/Stop Bits Requirements (Slave Mode) .................................................... 357 PLL Clock.................................................................. 347 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ......................................... 350 SSP I2C Bus Data Requirements ............................. 359 Timer0 and Timer1 External Clock Requirements ................................................... 351 Top-of-Stack Access ........................................................... 62 TSTFSZ ............................................................................ 323 Two-Speed Start-up .................................................. 263, 276 Two-Word Instructions Example Cases........................................................... 66 TXSTA Register BRGH Bit .................................................................. 221 T0CON Register PSA Bit...................................................................... 129 T0CS Bit.................................................................... 129 T0PS2:T0PS0 Bits .................................................... 129 T0SE Bit.................................................................... 129 2010 Microchip Technology Inc. U UA Bit ............................................................................... 206 W Watchdog Timer (WDT)............................................ 263, 274 Associated Registers................................................ 275 Control Register........................................................ 274 During Oscillator Failure ........................................... 277 Programming Considerations ................................... 274 WWW Address ................................................................. 387 WWW, On-Line Support ....................................................... 9 X XORLW ............................................................................ 323 XORWF ............................................................................ 324 DS39616D-page 387 PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 388 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2010 Microchip Technology Inc. DS39616D-page 389 PIC18F2331/2431/4331/4431 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2331/2431/4331/4431 Literature Number: DS39616D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39616D-page 390 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2331/2431/4331/4431(1), PIC18F2331/2431/4331/4431T(1,2); VDD range 4.2V to 5.5V c) PIC18LF4431-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2331-I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4331-I/P = Industrial temp., PDIP package, normal VDD limits. PIC18LF2331/2431/4331/4431(1), PIC18LF2331/2431/4331/44310T(1,2); VDD range 2.0V to 5.5V Temperature Range I E = = -40C to +85C (Industrial) -40C to +125C (Extended) Package PT SO SP P ML = = = = = TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) 2010 Microchip Technology Inc. Note 1: 2: F = Standard Voltage Range LF = Wide Voltage Range T = in Tape and Reel - SOIC and TQFP Packages only. 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