AVR 8-Bit RISC - Data Sheets - Atmel Corporation

Introduction

This document contains the latest information about the AVR data book and the AVR

data sheet s.

All references to the data book refers to the August 1999 version of the “AVR® RISC

MICROCONTROLLER DATA BOOK”.

All references to the AVR data she ets refer to the latest ve rsion of the A VR data

sheets on Atmel’s web page www.atmel.com.

The d ata she ets on Atmel’ s web page are up dated m ore freq uently than th e prin ted

data book . All kno wn errors in each data shee t are corrected when a new v ersion is

released.

This document contains known errors that have not been corrected yet. All designers

using AVR microcontrollers should use t his document together with the data sheets. It

is updated frequently, and should contain a complete list of all known documentation

errors at any given t ime.

Please note that this document only covers errors in the AVR documentation. For

errors in the AVR microcontrollers, see the errata sheet for each device.

If you find errors in the documentation that are not listed in this document, please

send an email to the AVR support line avr@atmel.com.

Overview of data shee ts

Part Number Data Sheet Revision

in the August 1999

AVR Data Book

Data Sheet Revision

on Atmel’s web site

www.atmel.com

AT90S1200 0838E-04/99 0838E-04/99

AT90S2313 0839E-04/99 0839E-04/99

AT90S/LS2323 and AT90S/LS2343 1004B-04/99 1004B-04/99

AT90S/LS2333 and AT90S/LS4443 1042D-04/99 1042D-04/99

AT90S4414/8515 0841E-04/99 0841E-04/99

AT90S/LS4434 and AT90S/LS8535 1041E-04/99 1041E-04/99

AT90C8534 1229A-04/99 1229A-04/99

ATtiny10/11/12 1006A-04/99 1006B-10/99

ATtiny15 1187A-06/99 1187B-11/99

ATtiny22/22L 1273A-04/99 1273A-04/99

ATmega161/161L 1228A-05/99 1228A-08/99

ATmega603/603L and ATmega103/103L 0945D-06/99 0945E-12/99

AVR Instruction Set 0856B-06/99 0856B-06/99

ATtiny28 N/A 1062B-10/99

Rev. 12/99A

8-Bit

Microcontroller

Data

Book Updates

and Changes

Data Book Updates and Changes

AT90S1200

The latest data sheet on the web is rev. 0838E-04/99.

The data sheet in the printed data book is rev. 0838E-04/99.

Changes in the AT90S1200 Data Sheet:

Page: Change or Add:

2-3 In feat ure list under I/O and packages, replace “20-pin PDIP and SOIC” by “20-pin PDIP, SOIC and SSOP”.

2-20 Table 4: remo ve this no te: “Note: When ch angi ng the ISC01/ISC00 bi ts, I NT0 must be dis abled by cl earing its Int er -

rupt Enable bi t in the GIMSK registe r. Otherwise an int errupt can occur when the bits are changed.”

2-25 In the note for Table 6, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

In the EEPROM Read/Write Access description, change “When the EEPROM is read or written, the CPU is

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is

halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted

for f our clock cyc les before the next instruction i s e xecuted.”

2-26 In t he Bit 0 - EERE: EEPROM Read Enable descri pti on, change “W hen EERE has b een set, the CPU is hal ted f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

2-27 In the Analog Comparator Control and Status Register description, change the initial value of ACO from “0” to

“N/A”.

2-29 in the Port B Input Pins Address - PINB description, change the Initial Values from “Hi-Z” to “N/A”.

2-33 in the Port D Input Pins Address - PIND description, change the Initial Values of bits 0 to 6 from “Hi-Z” to “N/A”.

2-44 Replace figure 34 by the one below:

Figure 34 Serial Progr amming and Verify

AT90S1200

VCC

2.7 - 6.0

PB7

PB6

PB5

RESET

GND

XTAL1

SCK

MISO

MOSI

GND

CLOCK INPUT

Data Book Updates and Changes

2-49: Replace the row below in DC character isti cs:

by:

2-50 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not tested during manufacturing.”.

2-62 In Register Summary, replace “2-2-xx” by “2-xx”.

VACIO Analog Comparator

Input Offset Voltage VCC = 5V 40 mV

VACIO Analog Compar ator

Input Offset Voltage VCC = 5V

Vin = VCC /2 40 mV

Data Book Updates and Changes

AT90S2313

The latest data sheet on the web is rev. 0839E-04/99.

The data sheet in the printed data book is rev. 0839E-04/99.

Changes in the AT90S2313 Data Sheet:

Page: Change or Add:

3-28 Table 5: remove th is note: “Note: W hen changing th e ISC11/ISC10 bits , INT1 must be disable d by cleari ng its Int er -

rupt Enable bi t in the GIMSK registe r. Otherwise an int errupt can occur when the bits are changed.”

3-29 Table 6: remo ve this no te: “Not e: When ch angi ng the ISC01/ ISC00 bit s, IN T0 must be dis abled by cl earing its Int er-

rupt Enable bi t in the GIMSK registe r. Otherwise an int errupt can occur when the bits are changed.”

3-38 On the top of the page, add paragraph “Note: If the compare register contains the TOP value and the prescaler is

not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and

down-counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the

PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not

interpreted to be reached before the next time the counter reaches the TOP-value, making a one period PWM

pulse.”

3-39 In the note for Table 14, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

In the EEPROM Read/Write Access description, change “When the EEPROM is read or written, the CPU is

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is

halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted

for f our clock cyc les before the next instruction i s e xecuted.”

3-40 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a lo gical on e to the EEMWE bit in EECR (to be a ble to wr ite a logi cal one to the EEMW E bit, the

EEWE bit must be written to zero in the same cycle).”

3-41 In t he Bit 0 - EERE: EEPROM Read Enable descri pti on, change “W hen EERE has b een set, the CPU is hal ted f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

3-47 In the Analog Comparator Control and Status Register description, change the initial value of ACO from “0” to

“N/A”.

3-49 in the Port B Input Pins Address - PINB description, change the Initial Values from “Hi-Z” to “N/A”.

3-54 in the Port D Input Pins Address - PIND description, change the Initial Values of bits 0 to 6 from “Hi-Z” to “N/A”.

3-67 Replace figure 34 by the one below:

Data Book Updates and Changes

Figure 53 Serial Programming and Veri fy

3-72: Replace the row below in DC character isti cs:

by:

3-73 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not tested during manufacturing.”.

3-84 In Register Summary, replace “3-3-xx” and “3-3-3-xx” by “3-xx”.

VACIO Analog Comparator

Input Offset Voltage VCC = 5V 40 mV

VACIO Analog Compar ator

Input Offset Voltage VCC = 5V

Vin = VCC /2 40 mV

AT90S2313

VCC

2.7 - 6.0

PB7

PB6

PB5

RESET

GND

XTAL1

SCK

MISO

MOSI

GND

CLOCK INPUT

Data Book Updates and Changes

AT90S/LS2323 and AT90S/LS2343

The latest data sheet on the web is rev. 1004B-04/99.

The data sheet in the printed data book is rev. 1004B-04/99.

Changes in the AT90S/LS2323 and AT90S/LS2343 Data Sheet:

Page: Change or Add:

4-6 In the Pin Descriptions AT90S/LS2323 replace the description for Port B (PB2..PB0) by

“Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As

input s, Port B pins that are externally pulled low, will source cu rrent if the pull-up r esisto rs are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset

condition becomes act ive.”

4-7 In the Pin Descriptions AT90S/LS2343 replace the description for Port B (PB4..PB0) by

“Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As

input s, Port B pins that are externally pulled low, will source cu rrent if the pull-up r esisto rs are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset

condition becomes act ive.”

4-19 In Figure 20, add a box contai ning “+1” as an input to the summation ope rator.

4-25 In the first paragraph of Watchdog Reset, replace “When the Watchdog times out, it will generate a short reset

pulse of 1 XTAL cycle duration.” by “When the Watchdog times out, it will generate a short reset pulse of 1 CPU

clock cycle duration.”

4-29 Table 9: remo ve this no te: “Not e: When ch angi ng the ISC01/ ISC00 bit s, IN T0 must be dis abled by cl earing its Int er-

rupt Enable bi t in the GIMSK registe r. Otherwise an int errupt can occur when the bits are changed.”

4-34 In the note for Table 11, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

In EEPROM Read/W rite Acces s, repl ace the 6th line “When t he EEPROM is read or writ ten, the CPU is halted for

two clock cycles before the next instruction is executed.” by “When the EEPROM is written, the CPU is halted for

two clock cycles bef ore the next instruction is executed. When it is read, the CPU is halted for 4 clock cycles.”.

4-35 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a logica l one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

In the Bit 0 - EERE: EEPROM Read Enabl e descri ption, change “When EERE has b een set , the CPU i s halt ed f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

4-37 in the Port B Input Pins Address - PINB descrip tion, ch ange the Initial Values of bits 0-4 from “Hi-Z” to “N/A”.

Data Book Updates and Changes

4-38 Replace the section name “MISO - Port B, Bit 1” by “MISO/INT0 - Port B, Bit 1”

4-40 In High-Voltage Serial Programmi ng, replace item 1. by

“Power- up sequen ce: Apply 4.5 - 5.5V betwee n VCC and GND. Set RESET and PB0 to “0” and wait at l east 100 ns.

Then, if the RCEN Fuse is not programmed; Toggle XTAL1/PB3 at least 4 times with minimum 100ns pulse-width.

Set PB3 to “0”. Wait at least 100ns.

or if the RCEN Fuse is programmed; Set PB3 to “0”. Wait at least 4 µs.

In both cases; Then apply 12V to RESET and wait at least 100 ns before changing PB0. Wait 8 µs before giving

any instructions.”

4-40 In Hi gh-Voltage Serial Programmi ng, replace in i tem 5 “Set PB5 to “1”.” by “Set RESET to “0”. ”

4-42 In tabl e 16, replace the entries

by the entries (Note: Bit 7 in the 4’th and 5’th column for PB1 has been inverted compared to the original data

book)

4-43 In figure 35, remove “CLOCK INPUT”, “XTAL1/PB3” and the arrow connecting them.

4-49 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not tested during manufacturing.”.

4-59 In Register Summary, replace all “4-page” by “page”. In addition, for TIMSK; replace ”page 4 -15” by “page 4-28”,

for TIFR; replace “page 4-16” by “page 4-28”, for MCUCR; replace “page 4-16” by “page 4-29”, for MCUSR;

replace “page 4-14” by “page 4-26”.

4-60 In Instruction Set Summary under BRANCH INSTRUCTIONS, replace

Read Fuse and

Lock bits

(AT90S/

LS2323)

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

Sxx_xxFx_xx

Reading

, S, F =’ 0’ means the

Fuse/Lock bit is programmed.

Read Fuse and

Lock bits

(AT90S/

LS2343)

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

Sxx_xxRx_xx

Reading

, S, R =’ 0’ means the

Fuse/Lock bit is programmed.

Read Fuse and

Lock bits

(AT90S/

LS2323)

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

Sxx_xxFx_xx

Reading

, S, F =’ 0’ means the

Fuse/Lock bit is programmed.

Read Fuse and

Lock bits

(AT90S/

LS2343)

PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

Sxx_xxRx_xx

Reading

, S, R =’ 0’ means the

Fuse/Lock bit is programmed.

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2

SBIS P, b Skip if Bit in I/O Register is Set if (R(b)=1) PC ← PC + 2 or 3 None 1 / 2

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

Data Book Updates and Changes

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIS P, b Skip if Bit in I/O Register is Set if (R(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

Data Book Updates and Changes

AT90S/LS2333 and AT90S/LS4433

The latest data sheet on the web is rev. 1042D-04/99.

The data sheet in the printed data book is rev. 1042D-04/99.

Changes in the AT90S/LS2333 and AT90S/LS4433 Data Sheet:

Page: Change or Add:

5-6 In “Pin Descri ptions ”, AVCC, change “This is the suppl y vo ltage f or the A/D Conver ter. It should be ext ernall y con-

nected to Vcc via a low-pass filter.” to “ This is the supply voltage for Port A and the A/ D Converter. I f the ADC is not

used, this pin must be connected to Vcc. If the ADC is used, this pin shoul d be connected to Vcc via a low-pass fil-

ter.”

5-15 In Figure 20, add a box containi ng “+1” as an input t o the summation operator.

5-28 Table 7: remove this note: “Note: When changing the ISC11/ISC10 bits, INT1 must be d isabled by c lear ing it s Inter-

rupt Enable bi t in the GIMSK register. Otherwise an int errupt can occur when the bits are changed.”

Table 8: re move thi s note: “Note: W hen cha nging the I SC01/ ISC00 bit s, INT0 must be dis able d by clear ing it s Inte r-

rupt Enable bi t in the GIMSK register. Otherwise an int errupt can occur when the bits are changed.”

5-34 In “Timer/Counter Control Register 1B - TCCR1B”, bit3 - CTC1, change the count sequence when prescaler is

set to divide by 8 from “...C-1 | C, 0, 0, 0, 0, 0, 0, 0, 0 | ...” to “. ..C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ...”

5-37 Before table 14, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and down-

counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM

output goes active when the counter reaches the TOP value, but the down-counting compare match is not inter-

preted to be reached before the next time the counter reaches the TOP-value, making a one- period PWM pulse.”

5-39 In the note for Table 16, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

befor e changing the Watchdog Timer Prescale Select .”

5-41 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. Writ e a logical one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

5-47. .50 In the UART description, replace “USR” by “UCSRA” and “UCR” by “UCSRB” everywhere.

5-50 In last line, repl ace “UBRRH” by “UBRRHI ”.

5-52 In “Analog Comparator Control and Status Register - ACSR”, the in it ia l va lue o f ACO is “N/ A ”.

5-59 In “ADC Noise Canceling Techniques” item 3, replace “Figure 47” by “Figure 49”.

5-60 In Figure 49, replace the resistor by a 10 µH inductor. Change capacitor value from 10 nF to 100 nF.

5-61 In the Port B Input Pins Address - PINB descript ion, chan ge the Initial Values from “Hi-Z” t o “N/A”.

5-66 In the Port C Input Pins Address - PINC description, change the Initial Values from “Hi-Z” to “N/A”. Ch ange Initial

Values “Q” to “0” (zero).

5-68 In the Port D Input Pins Address - PIND descript ion, chan ge the Initial Values from “Hi-Z” t o “N/A”.

5-80 In “Serial Downloading”, replace Figure 66 by the figure below.

Data Book Updates and Changes

Figur e 66 . Serial Progr ammi ng and Verify

5-86 Replace the row below in DC characteri s tics:

by:

5-86 In “DC Characteristics” , footnote 4, replace “IOL” by “IOH” everywhere.

5-88 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not t ested during manufacturin g.”.

VACIO Analog Comparator

Input Offset Voltage VCC = 5V 40 mV

VACIO Analog Compar ator

Input Offset Voltage VCC = 5V

Vin = VCC /2 40 mV

AT90S2333/4433

VCC

2.7 - 6.0V

PB7

PB6

PB5

RESET

GND

XTAL1

SCK

MISO

MOSI

GND

CLOCK INPUT

Data Book Updates and Changes

AT90S4414/8515

The latest data sheet on the web is rev. 0841E-04/99.

The data sheet in the printed data book is rev. 0841E-04/99.

Changes in the AT90S441 4/8515 Data Sheet:

Page: Change or Add:

6-17 In Figure 19, add a box containing “+ 1” as an input to the summati on operator.

6-29 Table 6: remove this note: “Note: When changing the ISC11/ISC10 bits, INT1 must be d isabled by c lear ing it s Inter-

rupt Enable bi t in the GIMSK register. Otherwise an int errupt can occur when the bits are changed.”

6-30 Table 7: re move thi s note: “Note: W hen cha nging the I SC01/ ISC00 bit s, IN T0 must be d isable d by clear ing it s Int er-

rupt Enable bi t in the GIMSK register. Otherwise an int errupt can occur when the bits are changed.”

6-39 Before table 14, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and down-

counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM

output goes active when the counter reaches the TOP value, but the down-counting compare match is not inter-

preted to be reached before the next time the counter reaches the TOP-value, making a one- period PWM pulse.”

6-41 In the note for Table 15, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

befor e changing the Watchdog Timer Prescale Select .”

In the EEPROM Read/Write Access description, change “When the EEPROM is read or written, the CPU is

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is

halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted

for f our clock cyc les before the next instruction is executed.”

6-42 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rite a logica l one to t he EEMWE bit in EECR (to be ab le to wri te a l ogical o ne to the EEMWE b it, the

EEWE bit must be written to zero in the same cycle).”

6-43 In th e Bit 0 - EERE: EEPROM Read Enable descr ipti on, change “ When EERE has be en set , the CPU i s halt ed for

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

6-54 In the Analog Comparator Control and Status Register description, change the initial value of ACO from “0” to

“N/A”.

6-57 in the Port A Input Pins Addr ess - PINA d escription, cha nge the Initial Values from “Hi- Z” to “N/A” .

6-59 in the Port B Input Pins Addr ess - PINB d escription, cha nge the Initial Values from “Hi- Z” to “N/A” .

6-64 in the Port C Input Pins Addr ess - PINC d escription, cha nge the Initial Values from “Hi- Z” to “N/A” .

6-66 in the Port D Input Pins Addr ess - PIND d escription, cha nge the Initial Values from “Hi- Z” to “N/A” .

6-79 Replace figure 64 by the one below:

Data Book Updates and Changes

Figure 64 Serial Programming and Veri fy

6-84: Replace the row below in DC characteri s tics:

by:

6-88 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not t ested during manufacturin g.”.

6-98 In Register Summary, replace all “6-6-xx” by “6-xx”.

VACIO Analog Comparator

Input Offset Voltage VCC = 5V 40 mV

VACIO Analog Compar ator

Input Offset Voltage VCC = 5V

Vin = VCC /2 40 mV

AT90S4414/8515

VCC

2.7 - 6.0

PB7

PB6

PB5

RESET

GND

XTAL1

SCK

MISO

MOSI

GND

CLOCK INPUT

Data Book Updates and Changes

AT90S/LS4434 and AT90S/LS8535

The latest data sheet on the web is rev. 1041E-04/99.

The data sheet in the printed data book is rev. 1041E-04/99.

Changes in the AT90S/LS4434 and AT90S/LS8535 Data Sheet:

Page: Change or Add:

7-6 In “Pin Descri ptions ”, AVCC, change “This is the suppl y vo ltage f or the A/D Conver ter. It should be ext ernall y con-

nected to Vcc via a low-pass filter.” to “ This is the supply voltage for Port A and the A/ D Converter. I f the ADC is not

used, this pin must be connected to Vcc. If the ADC is used, this pin shoul d be connected to Vcc via a low-pass fil-

ter.”

7-15 In Figure 19, add a box containi ng “+1” as an input t o the summation operator.

7-27 In “Timer /Counter Interrupt Flag Register - TIFR ”, chan ge headi ng “Bit 6 - T OV2: Timer/Counter0 Over flow Flag ”

to “Bit 6 - TOV2: Timer/Counter2 Overf low Flag”.

7-29 Table 9: remove this note: “Note: When changing the ISC11/ISC10 bits, INT1 must be d isabled by c lear ing it s Inter-

rupt Enable bi t in the GIMSK register. Otherwise an int errupt can occur when the bits are changed.”

Table 10: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its

Interrupt Enable bit in the GIMSK re gister. Otherwise an interr upt can occur when the bit s are changed.”

7-30 In the Power Down Mode section, replace parag raph 2 (“Note that if a level triggered interrupt.. . ...on page 7-98.”)

to “ N ote that wh en a le vel triggered interrupt is use d for wake-up from power down, th e low level must be held for a

time longer than the reset delay t ime-out perio d tTOUT.”

7-30 At the end of the Power Save Mode section, add the paragraph “If the asynchronous timer is NOT clocked asyn-

chronously, Power Down Mode is recommended instead of Power Save Mode because the contents of the regis-

ters in the asynchronous timer should be considered undefined after wake up in Power Save Mode, even if AS2 is

0.”

7-36 In “Timer/Counter Control Register 1B - TCCR1B”, bit3 - CTC1, change the count sequence when prescaler is

set to divide by 8 from “...C-1 | C, 0, 0, 0, 0, 0, 0, 0, 0 | ...” to “. ..C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ...”

7-39 Before table 16, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and down-

counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM

output goes active when the counter reaches the TOP value, but the down-counting compare match is not inter-

preted to be reached before the next time the counter reaches the TOP-value, making a one- period PWM pulse.”

7-45 Replace last paragraph on page:

“When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter2 is always running, except in

power down mode. After a power up reset or wake-up from power down, the user should be aware of the fact that

this oscillator might take as long as one second to stabilize. Therefore, the content of all Timer/Counter2 registers

must be consi dered lost after a wake-up from power down, due to the unstable clock signal. The user is advised to

wait for at least one second bef ore using Ti mer/Counte r2 after power- up or wake-up from power down.”

“When the asynchronous operation is selected, the 32kHZ oscillator for Ti mer/Counter2 is always running, except

in power down mode. After a power up reset or wake-up from power down, the user should be aware of the fact

that this oscillator might take as long a s one second to stabili ze. The user is advised to wait for at least one second

befor e using Timer/Counter2 after power- up or wake-up from power down. The contents of all Timer/Counter2 reg-

Data Book Updates and Changes

ist ers mus t be consi dered lost af ter a wake-up fr om power do wn due to un stab le cloc k si gnal upon st art-u p, r egard-

less of whether the oscillator is in use or a clock signal is applied to the TOSC pin.”

7-47 In the note for Table 22, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

7-49 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a logica l one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

In the Bit 0 - EERE: EEPROM Read Enabl e descri ption, change “When EERE has b een set , the CPU i s halt ed f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

7-52 Change Figure 40 to the figure below.

Figur e 40. SPI Transfer For mat with CPHA = 1 and DORD = 0

7-60 In “Analog Comparator Control and Status Register - ACSR”, the initial value of ACO is “N/A”.

7-67 In Figure 50, replace the resistor by a 10 µH inductor. Change capacitor value from 10 nF to 100 nF.

7-69 In the Port A Input Pins Address - PINA description, change the Initial Values from “Hi-Z” to “N/A” .

7-71 In the Port B Input Pins Address - PINB description, change the Initial Values from “Hi-Z” to “N/A” .

7-76 In the Port C Input Pins Address - PINC description, change the Initial Values from “Hi-Z” to “N/A” .

7-79 In the Port D Input Pins Address - PIND description, change the Initial Values from “Hi-Z” to “N/A” .

7-91 In “Serial Downloading”, replace Figure 71 by the figure below.

Figur e 71 . Serial Progr ammi ng and Verify

AT90S4434/8535

VCC

2.7 - 6.0V

PB7

PB6

PB5

RESET

GND

XTAL1

SCK

MISO

MOSI

GND

CLOCK INPUT

Data Book Updates and Changes

7-96 Replace the row below in DC character isti cs:

by:

7-98 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not tested during manufacturing.”.

7-109 In Register Summary, replace all “7-page” by “page”. In addition, replace “page 7-337-” by “page 7-33”, “page 7-

377-” by “page 7-37”, “page 7-387-” by “page 7-38”, “page 7-467-” by “page 7-46”, “page 7-487-” by “pag e 7-48”.

VACIO Analog Comparator

Input Offset Voltage VCC = 5V 40 mV

VACIO Analog Compar ator

Input Offset Voltage VCC = 5V

Vin = VCC /2 40 mV

Data Book Updates and Changes

AT90C8534

The latest data sheet on the web is rev. 1229A-04/99.

The data sheet in the printed data book is rev. 1229A-04/99.

Changes in the AT90C8534 Data Sheet:

Page: Change or Add:

8-5 In “Pin Descriptions”, AVCC, change “This is the supply voltage for the A/D Converter. It should be externally

connected to Vcc via a low-pass filter.” to “This is the supply voltage for the A/D Converter. If the ADC is not used,

thi s pin must be connected to Vcc. If the ADC is used, thi s pin should be connected to Vcc via a low-pass filter.”

8-16 In Figure 19, add a box contai ning “+1” as an input to the summation ope rator.

8-26 At the end of the Interrupt Sense Control 1 description add this text: “When changing the ISC1 bit, an interrupt

can occur. Therefore, it is recommended to first disable INT1 by clearing its Interrupt Enable bit in the GIMSK reg-

ister. Then, the ISC1 bit can be changed. Finally, the INT1 interrupt flag should be cleared by writing a logical one

to its Interrupt Flag bit in the GIFR register before the int e rrupt is re-enabled. ”

At the end of the Interrupt Sense Control 0 description add this text: “When changing the ISC0 bit, an interrupt

can occur. Therefore, it is recommended to first disable INT0 by clearing its Interrupt Enable bit in the GIMSK reg-

ister. Then, the ISC0 bit can be changed. Finally, the INT0 interrupt flag should be cleared by writing a logical one

to its Interrupt Flag bit in the GIFR register before the int e rrupt is re-enabled. ”

8-31 In the EEPROM Read/Write Access description, change “When the EEPROM is read or written, the CPU is

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is

halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted

for f our clock cyc les before the next instruction i s e xecuted.”

8-32 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a logica l one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

In the Bit 0 - EERE: EEPROM Read Enabl e descri ption, change “When EERE has b een set , the CPU i s halt ed f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

Data Book Updates and Changes

ATtiny10/11/12

The latest data sheet on the web is rev. 1006B-10/99.

The data sheet in the printed data book is rev. 1006A-04/99.

Changes in the ATtiny10/11/12 Data Sheet on the web:

Page: Change or Add:

27 Table 13: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its

Interrupt Enable bit in the GIMSK re gister. Otherwise an interr upt can occur when the bit s are changed.”

In the first paragraph of Sleep modes for the ATtiny10/11 sectio n, replac e the sentence

“On wake-up from Power Down Mode on pin change, the two instructions following SLEEP are executed before

the pin cha nge interrupt routine.

“On wake-u p fr om Power Down Mode on pin chang e, 2 i nstruc tion cyc le s are execut ed bef ore the pi n change int er-

rupt flag is updated. During these cycles, the processor executes instructions, but the interrupt condition is not

readable, and the interrupt routine has not started yet.

32 In the note for Table 16, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

33 In the last sent ence of the fir st paragra ph, chan ge “When the EEPROM is read or written, the CPU is halted for two

clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two

clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock

cycles before the next instruction is executed.”

In th e EEPROM Control Register descr iption, change the init ial value of EEWE from “0” to “X”.

34 In th e Bit 0 - EERE: EEPROM Read Enable descr i ption, change “When EERE has be en set , the CPU i s halt ed for

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

Changes in the ATtiny10/11/12 section in the data book

Page: Change or Add:

9-3 In both Pin Configuration figures, repl ace RESET with RESET.

9-14 In Figur e 12, add a box containing “+1” as an input to the summation operat or.

9-24 In the first line of the W atchdog Reset section, change “ 1 XTAL cycle” to “1 CK cycle”.

In Figur e 22, change “1 XTAL Cycle” to “1 CK Cycle”.

9-29 Table 13: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its

Interrupt Enable bit in the GIMSK re gister. Otherwise an interr upt can occur when the bit s are changed.”

In the first paragraph of Sleep modes for the ATtiny10/11 sectio n, replac e the sentence

Data Book Updates and Changes

“On wake-up from Power Down Mode on pin change, the two instructions following SLEEP are executed before

the pin change int errupt rout ine.

“On wake- up from Powe r Down Mode on pin chan ge, 2 inst ruc tion cy cles are ex ecut ed before the pin chan ge inter -

rupt flag is updated. During these cycles, the processor executes instructions, but the interrupt condition is not

readable, and the interrupt routine has not started yet.

9-34 In the note for Table 15, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

In the first paragraph of ATtiny12 Calibrated Internal RC Oscillator section, add “For details on how to use the

pre-programmed calibration value, see the section ‘Calibration Byte in ATtiny12’ on page 9-42.

In the second paragraph, add “The calibrated oscillator is used to time EEPROM access. If EEPROM is written, do

not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM write may fail. Table 1

shows the range for OSCCAL. Note that the Oscillator is intended for calibration to 1.0MHz, thus tuning to other

values is not guaranteed.

9-35 In the second line, change “The write access time is in the range of 2.5 - 4ms, depending on the VCC.” to “The write access

time is in the range of 1.9 - 3.4ms, depending on the frequency of the calibrated RC oscillator.”

In the last sen tence of the fir st paragra ph, chan ge “When the EEPROM is read or written, the CPU is halted for two

clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two

clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock

cycles before the next instruction is executed.”

In the EEPROM Control Register descr ipt ion, cha nge the i nitial value of EEW E from “0” to “X”.

9-36 In the 14th line, remove “(typically 2.5ms at VCC = 5V or 4 ms at VCC = 2.7V)”

In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a logica l one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

In the Bit 0 - EERE: EEPROM Read Enabl e descri ption, change “When EERE has b een set , the CPU i s halt ed f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

9-37 In the Analog Comparator Control and Status Register description, change the initial value of ACO from “0” to

“N/ A”.

9-39 In the Port B Input Pins Address - PINB description, change the Initial Value of bits 0-5 from “Hi-Z” to “N/A”.

9-40 In the first line of section Alternate Functions of Port B, change “The alternate pin funct ions of Port B are:” to “All

Port B pins ar e con nected to a p in ch ange detect or that can t rigger the pi n ch ange inter r upt. See ‘ Pin Change Int er-

rupt ’ on page 9-28 for details. In addi tion, Port B has the followi ng alternate functions:”.

Table 1. Internal RC Oscillator Frequency Range.

OSCCAL value Min. Frequency Max Frequency

$00 0.5MHz 1.0MHz

$7F 0.7MHz 1.5MHz

$FF 1.0MHz 2.0MHz

Data Book Updates and Changes

9-42 In the section Calibration Byte in ATtiny12, add “At start-up, the user software must read this flash location and

write the value to the OSCCAL register.”

In the section ATtiny10/11, change “The +12V is used for programming enable only, and no current of significance is

drawn by this pin.” to “Only minor currents (<1mA) are drawn from the +12V pin during programming.”.

9-44 In Table 21, remove the entire first row. In the first cell of the second row, remove “(ATtiny12)”.

9-45 In the note on the bott om of the page, change “9, 6 = RSTISBL Fuse” to “9, 6 = RSTDISBL Fuse”.

9-46 In Table 22, remove the “tWLWH_CE “row.

In Figure 30, remove “CLOCK INPUT”, “PB3 (XTAL1)” and the arrow connecting them.

9-47 In the sixth line, change “Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2” to “The device can be clocked by any clock option during Low-Voltage Serial Pro-

gramming.”.

In the two last lines of the first paragraph, change “2 XTAL clock cycles” to “2 CK clock cycles”.

In the first entry of the Low-Voltage Serial Programming Algorithm, change “If a crystal is not connected across

pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin.” to “In accordance with the setting of CKSEL fuses,

apply a crystal/ resonat or, external clock or RC network, or let the device run on the internal RC oscillator.”.

In t he fifth entry, change the first “tWD_PROG” to “t WD_FLASH or tWD_EEPROM”. Change t he second “ tWD_PROG” to “tWD_FLASH

and tWD_EEPROM”.

9-48 In the Data Polling section, change the first “tWD_PROG” to “tWD _F LA SH or tWD_EEPROM”. Change the second and third

“tWD_PROG” to “tWD_EEPROM”.

9-50 Replace Table 25 and Table 26 with these tables:

9-52 In the DC Characteristics table, replace

Symbol Minimum Wait Delay

tWD_ERASE 3.4 ms

Symbol Minimum Wait Delay

tWD_FLASH 1.7 ms

tWD_EEPROM 3.4 ms

Symbol Parameter Condition Min Typ Max Units

ICC Power Supply Current

Active 4MHz, VCC = 3V 3.0 mA

Idle 4MHz, VCC = 3V 1.0 1.2 mA

Power Down(5), VCC =

3V, WDT enabled 9.0 15 µA

Power Down(5), VCC =

3V. WDT disabled <1 2 µA

Data Book Updates and Changes

with

Vacio Analog Comp

Input Offset V VCC = 5V 40 mV

Iaclk Analog Comp

Input leakage A VCC = 5V

VIN = VCC/2 -50 50 nA

Tacpd Analog Comp

Propagation Del. VCC = 2.7V

VCC = 4.0V 750

500 ns

Symbol Parameter Condition Min Typ Max Units

ICC Power Supply Current

Active 1MHz, VCC = 3V

(ATtiny12V) TBD mA

Active 2MHz, VCC = 3V

(ATtiny10/11L) TBD mA

Active 4MHz, VCC = 3V

(ATtiny12L) 3.0 mA

Active 6MHz, VCC = 5V

(ATtiny10/11) TBD mA

Active 8MHz, VCC = 5V

(ATtiny12) TBD mA

Idle 1MHz, VCC = 3V

(ATtiny12V) TBD mA

Idle 2MHz, VCC = 3V

(ATtiny10/11L) TBD mA

Idle 4MHz, VCC = 3V

(ATtiny12L) 1.0 1.2 mA

Idle 6MHz, VCC = 5V

(ATtiny10/11) TBD mA

Idle 8MHz, VCC = 5V

(ATtiny12) TBD mA

Power Down(5), VCC =

3V, WDT enabled 9.0 15 µA

Power Down(5), VCC =

3V. WDT disabled <1 2 µA

VACIO Analog Comparator

Input Offset Voltage VCC = 5V

VIN = VCC/2 40 mV

IACLK Analog Comparator

Input Leakage Current VCC = 5 V

VIN = VCC/2 -50 50 nA

TACPD Analog Comparator

Propagation Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

Symbol Parameter Condition Min Typ Max Units

Data Book Updates and Changes

9-53 In the first table, change the title from “External Clock Drive” to “External Clock Drive ATtiny12” and add this table:

9-54 In the first line, change “These data are characterized, but not tested.” to “These figures are not tested during manufactur-

ing.”.

9-72 In row 12 (MCUSR) of the tabl e, change “WDTR” to “WDRF” and “BODR” to “BORF” .

External Clock Drive ATtiny10/11

Symbol Parameter

VCC = 2.7V to 4.0V VCC = 4.0V to 5.5V

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0206MHz

CLCL Clock Period 500 167 ns

tCHCX High Time 200 67 ns

tCLCX Low Time 200 67 ns

tCLCH Rise Time 1.6 0.5 µs

tCHCL Fa ll Time 1.6 0 . 5 µs

Data Book Updates and Changes

ATtiny15L

The latest data sheet on the web is rev. 1187B-11/99.

The data sheet in the printed data book is rev. 1187A-06/99.

Changes in the ATtiny15L Data Sheet on the web:

None.

Changes in the ATtiny15L section in the data book:

The data sheet for ATtiny15 has gone thro ugh seri ous improvemen ts and corrections since the printing of the “AVR

RISC MICROCONTROLLER DATA BOOK AUGUST 1999”. The user is advised to download the complete new

ATtiny15 data sheet from the Web, since correcting the present data book would not give a user friendly result .

Data Book Updates and Changes

ATtiny22/22L

The latest data sheet on the web is rev. 1273A-04/99.

The data sheet in the printed data book is rev. 1273A-04/99.

Changes in the ATtiny22/22L Data Sheet:

Generally: The external clock option does not exist in ATtiny22/L. Therefore, all references to the RCEN fuse and external

clock are wrong, and the part comes as ATtiny22L only, not ATtiny22.

Page: Change or Add:

All For all “ATtiny22/L” read “ATtiny22L”.

11-3 In the feature list, replace the following lines

•Special Microcontroller Features

–...

– Selectable On-chip RC Oscillator

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.4 mA

– Idle Mode: 0.5 mA

– Power Down Mode: <1 µA

•Operating Voltages

– 2.7 - 6.0V (ATtiny22L)

– 4.0 - 6.0V (ATtiny22)

•Speed Gr ades

– 0 - 4 MHz (ATtiny22L)

– 0 - 8 MHz (ATtiny22)

by the following description;

•Special Microcontroller Features

–...

– On-chip RC Oscillator

•Power Consumption at 3V, 25°C

– Active: 1.5 mA

– Idle Mode: 100µA

– Power Down Mode: <1 µA

•Operating Voltages

– 2.7 - 6.0V

•Speed Gr ade

– Internal Oscillator ~1MHz@5.0V

11-3 Replace Pin Configuration by the figure shown below.

RESET

PB3

PB4

GND

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

Data Book Updates and Changes

11-5 In the Pin Descriptions ATtiny22/L repl ace the description for Port B (PB4..PB0) by

“Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As

input s, Port B pins that are externally pulled low, will source cu rrent if the pull-up r esisto rs are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset

condition becomes act ive.”

11-5 Remove the description “CLOCK” under Pin Descriptions ATtiny22/L.

11-5 The whole secti on “ Clock options“ incl uding Figure 2 should be replaced by

“Clock Source

The ATtiny22L is clocked by an on-chip RC oscillator. This RC oscillator runs at a nominal frequency

of 1 MHz (VCC = 5V).“

11-16 In Figur e 18 , add a box containing “+1” as an input t o the summation operator.

11-16 Replace second paragraph under Memory Access and Instruction Execution Timing, “The A V R C P U is d riv e n

by the System Clock Ø, directly generated from the external clock signal applied to the CLOCK pin.” by “The AVR

CPU is driven by the Syst em Clock Ø, di rectly gener ated from the internal RC oscillator.“

11-21 In Power-On Reset, replace the first paragraph; ”The ATtiny22/L is designed for use in systems where it can oper-

ate from the internal RC oscillator or in applications where a clock signal is provided by an external clock source.

After VCC has reached VPOT, the device will start after the time tTOUT (see Figure 23). If the clock signal is provided

by an external clock source, the clock must not be applied until VCC has reached the minimum voltage defined for

the applied frequency. “ by “ The ATtiny22L is de sig ned for use in systems where i t can o perat e from the i nte rnal RC

oscillator. After VCC has reached VPOT, the device will start after the time tTOUT (see Figure 23).”

11-23 In the first paragraph of Watchdog Reset, replace “When the Watchdog times out, it will generate a short reset

pulse of 1 CPU cycle duration.” by “When the Watchdog times out, it will generate a short reset pulse of 1 clock

cycle duration.”

11-27 Table 7: r emove this no te: “Not e: When ch anging the ISC01/ ISC00 bit s, I NT0 must be dis abl ed by clear ing its Int er-

rupt Enable bi t in the GIMSK registe r. Otherwise an int errupt can occur when the bits are changed.”

11-31 In the note for Table 9, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.”

11-32 In line number 6, replace “When the EEPROM is read or written, the CPU is halted for two clock cycles before the

next instruction is executed.” by “When the EEPROM is written, the CPU is halted for two clock cycles before the

next instruction is executed. When it is read, the CPU is hal ted for 4 clock cycles.”.

11-33 In the Bit1 - EEWE: EEPROM Write Enable description, change “4. Write a logical one to the EEMWE bit in

EECR” to “4. W rit e a logica l one to the EEMWE bit in EECR (to be abl e to writ e a logical one to the EEMWE bit, the

EEWE bit must be written to zero in the same cycle).”

In the Bit 0 - EERE: EEPROM Read Enabl e descri ption, change “When EERE has b een set , the CPU i s halt ed f or

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four

clock cycles before the next instruction is executed.”

11-34 In Table 10, remove the entry for PB3.

11-34 In the Port B Input Pins Address - PINB description, change the In itial Values of bits 0-4 from “ Hi-Z” to “ N/A ”.

11-35 Remove section, CLOCK - Port B, Bit 3.

Data Book Updates and Changes

11-35 Replace the section name “MISO - Port B, Bit 1” by “MISO/INT0 - Port B, Bit 1”

11-36 In section Fuse Bits, replace the first sentence; “The ATtiny22/L has two Fuse bits, SPIEN and RCEN.” by “The

ATtin y22L has one Fuse bit, SPIEN.”, and remove the secon d bu ll et item which is a description of the RCEN fuse.

11-37 In Table 13, delete one of the rows saying

11-37 In High-Voltage Serial Programming Algorithm, replace item 1 by “Power-up sequence: Apply 4.5 - 5.5V

between VCC and GND. Set RESET and PB0 to “0” and wait at least 100 ns. Set PB3 to “0”. Wait at least 4µs.

Apply 12V to RESET and wait at least 100 ns befor e changing PB0. Wai t 8 µs before giving any instructions.”

11-37 In High-Voltage Serial Programming Algorit hm, replace in it em 5 “Set PB5 to “1”.” by “Set RESET to “0”.”

11-38 In Figure 31, replace “XTAL1/PB3” by “PB3”.

11-38 In tabl e 14, replace the entries

by the entries (Note: For Read Fuse and Lock bits; Bit 7 in the 4’th and 5’th column for PB1 have been inverted

compa red to the original data book.

and delete the note “R = RCEN Fuse“ to this table.

11-40 In figure 33, remove “CLOCK INPUT”, “XTAL1/PB3” and the arrow connecting them.

11-40 In last paragraph, replace “Either an external clock is applied to the XTAL1/PB3 pin or the device must be clocked

from the internal RC-oscillator.” by “The device is clocked from the internal RC-oscillator.”

11-41 In item “1. Power-up sequence”, replace “RESET” by “RESET” (two occurrences) and delete “If the device is pro-

grammed for external clocking, apply a 0 to 8 MHz clock to the PB3 pin. If the internal RC oscillator is selected as

the clo ck source, no exter nal cl ock source need s to be applied.”

11-43 In tabl e 17, replace the entries

ATtiny22/L 2.7 - 6.0V 4.5 - 5.5V

Write Fuse bits PB0

PB1

PB2

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_11S1_111R_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait tWLWH_PFB after Instr.3 for the

W rite Fuse bits cycle to finish. Set S,R

= “0” to program, “1” to unprogram.

Read Fuse and

Lock bits PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

1_2Sxx_xxRx_xx

Reading 1, 2, S, R = “0” means the

Fuse/Lock bit is programmed.

Write Fuse bit PB0

PB1

PB2

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_11S1_1110_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait tWLWH_PFB after Instr.3 for the

Write Fuse bit cycle to finish. Set S =

“0” to program, “1” to unprogram.

Read Fuse and

Lock bits PB0

PB1

PB2

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

1_2Sxx_xx0x_xx

Reading 1, 2, S= “0” means the

Fuse/Lock bit is programmed.

Read Lock and

Fuse Bits 0101 1000 xxxx xxxx xxxx xxxx

Sx xxxRRead Lock and Fuse bits. ‘0’ =

programmed, ‘1’ = unprogrammed.

Write RCEN Bit 1010 1100 1011 111Rxxxx xxxx xxxx xxxx Write RCEN Fuse. Set bit R = ‘0’ to

program, ‘1’ to unprogram.(1)

Data Book Updates and Changes

by the entry (Remove the entry “Write RCEN Bit”):

and remove the notes “R = RCEN Fuse” and “When the state of the RCEN bit is changed, the device must be

powe r cycled fo r the changes to have any effect.”

11-44 Above Table 18, add “ The per iod of th e inter nal RC osc ill ator - tCLCL is vol tage depend ent as sho wn in “Typical char -

acteristics”, and delete the entries for 1/tCLCL(VCC = 2.7 - 4.0V), tCLCL(VCC = 2.7 - 4.0V), 1/tCLCL(VCC = 4.0 - 6.0V),

tCLCL(VCC = 4.0 - 6.0V),.

11-45 In DC Chara cteristics, replace the entries:

by the entries

11-46 Remove the sections External Clock Drive Waveforms and External Clock Drive.

11-46 In first line of Typical Characteristics, change “These data are characterized, but not tested.” to “These figures

are not t ested during manufacturin g.”.

11-46 For last sentence in second paragraph of the section Typical Characteristics, replace “The dominating factors are

the operating voltage and frequency“ by “The dominating factor is the operating voltage, as the frequency of

ATti ny22L is also a function of the operating vol tage.”

11-47 Remove Figure 37 and Figure 38

11-48 Remove Figure 40

11-49 Remove Figure 41

11-56 In Register Summary, replace all “11-page” by “page”. In addition, for TIMSK; replace ”page 11-15” by “page 11-

25”, for TIFR; replace “page 11-16” by “page 11-26”, for MCUCR; replace “page 11-16” by “page 11-26”, for

MCUSR; replac e “page 11-14” by “page 11-24”

Read Lock and

Fuse Bit 0101 1000 xxxx xxxx xxxx xxxx

Sx xxx0 R ead Lock and Fuse bit. ‘0’ =

programmed, ‘1’ = unprogrammed.

ICC Power Supply Current Active 4 MHz, VCC = 3V 3.0 mA

Idle 4 MHz, VCC = 3V 1.1 mA

Power Down 4 MHz(2),

VCC = 3V WDT Enabled 25.0 µA

Power Down 4 MHz(2),

VCC = 3V WDT Disabled 20.0 µA

ICC Power Supply Current Active, VCC = 3V 1.5 mA

Idle, VCC = 3V 100 µA

Power Down,

VCC = 3V WDT Enabled 25.0 µA

Power Down,

VCC = 3V WDT Disabled 20.0 µA