56F8300
16-bit Digital Signal Controllers
freescale.com
56F8345/56F8145
Data Sheet
Preliminary Technical Data
MC56F8345
Rev. 17
01/2007
56F8345 Technical Data, Rev. 17
2 Freescale Semiconductor
Preliminary
Document Revision History
Version History Description of Change
Rev 1.0 Pre-Release version, Alpha customers only
Rev 2.0 Initial Public Release
Rev 3.0 Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additio nal
grammar issues.
Rev 4.0 Added “Typical Min” values to Table 10-16. Edited grammar, spelling, consistency of
language throughout family. Updated va lues in Current Consumption per Power Supply Pin,
Table 10-7, Regulator Parameters, Table 10-9, External Clo ck Operation Timing
Requirements Table 10-13, SPI Timing, Table 10-17, ADC Parameters, Table 10-23, and IO
Loading Coefficients at 10MHz, Table 10-24.
Rev 5.0 Added Part 4.8. Added the word “access” to FM Error Interrupt in Table 4-5. Removed min
and max numbers. Clarified CSBAR 0 and CSBAR 1 reset values in Table 4-10. Removed
min and max numbers, only documenting Typ. numbers for LVI in Table 10-6.
Rev 6.0 Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in
Table 10-3 in Pd characteristics.
Rev 7.0 Replaced any reference to Flash Interfa ce Unit with Flash Memory Module. Added note to
VCAP pin in Table ?-??????. Removed unneccessary notes in Table 10-12. Corrected
temperature range in Table 10-14. Added ADC calibration information to Table 10-23 and
new graphs in Figure 10-21.
Rev 8.0 Clarified Table 10-22. Corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5. Removed text and Table 10-2. Replaced with note to Table 10-1.
Rev 9.0 Added 56F8145 information; edited to indicate differences in 56F8345 and 56F8145.
Reformatted for Freescale look and feel. Updated Temper ature Sensor and ADC tables;
updated balance of electrical tables for consistency throughout fa mily. Clarified I/O power
description in Table ?-??????, added note to Table 10-7 and clarified Section 12.3.
Rev 10.0 Corrected beginning address for On-Chip Data RAM, Table 4-6.
Rev 11.0 Corrected addresses in Table 4-6.
Rev 12.0 Corrected Figure 10-21. Added output voltage maximum value and note to clarify in
Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on
customer usage and must be determined by reliability engineering. Clarifie d value and unit
measure for Maximum allowed PD in Table 10-3. Corrected note about average value for
Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in
Table 13-1.
Rev 13.0 Updated Table 10-23 to reflect new value for maximum Uncalibrated Gain Erro r
Rev 14.0 Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted fo rmula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4. Added RoHS-compliance and “pb-free” language to back cover.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 3
Preliminary
Rev 15.0 Updated JTAG ID in Section 6.5.4. Added information/corrected state during reset in
Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing
maximum value to 8.4MHz.
Rev 16.0 Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2.
Rev. 17 • Added the following note to the description of the TMS signal in Table 2-2:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Added the following note to the description of the TRST signal in Table 2-2:
Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a
debugging environment, TRST may be tied to VSS through a 1K resistor.
Document Revision History (Continued)
Version History Description of Change
Please see http://www.freescale.com for the most current data sheet revision.
56F8345 Technical Data, Rev. 17
4 Freescale Semiconductor
Preliminary
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 5
Preliminary
56F8345/56F8145 Block Diagram - 128 LQFP
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
COP/
Watchdog
SCI1 or
GPIOD
42IRQA IRQB
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SCI0 or
GPIOE
SPI0 or
GPIOE
IPBus Bridge (IPBB)
Decoding
Peripherals
Peripheral
Device Selects RW
Control IPAB IPWDB IPRDB
2
System Bus
R/W Control
PAB
PAB
CDBW
CDBR
CDBW
JTAG/
EOnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
VCAP VDD VSS VDDA VSSA
547 52
VPP
2
RESET
RSTO
4
6
3
4
6
3
Quad Ti me r
D or GPIOE
Quad Timer
C or GPIOE
ADCA
4
5
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
FlexCAN
2
4
2
ADCB
4
4
VREF
TEMP_SENSE
4
* External
Address Bus
Switch
External Bus
Interface Unit
* External
Data
Bus Switch
A8-13 or GPIOA0-5
D7-10 or GPIOF0-3
GPIOB0-4 or A16-20
GPIOD0-5 or CS2-7
* Bus
Control
6
5
4
6
* EMI not functional in
this package; use as
GPIO pi ns
PLL
Clock
Generator XTAL
EXTAL
CLKMODE
Integration
Module
System
P
O
RO
S
C
Clock
resets
CLKO
PWM Outputs
Fault Inputs
PWMA
Current Sense Inputs
or GPIOC
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
or GPIOD
OCR_DIS
4AD1
AD0
4
AD1
AD0
Data Memory
4K x 16 Flash
4K x 16 RAM
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash Control
56F8345/56F8145 General Description
Note: Features in italics are NOT available in the 56F8145 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
•Up to two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Ti mers
• Computer Operating Properly (COP)/Watc hdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
56F8345 Technical Data, Rev. 17
6 Freescale Semiconductor
Preliminary
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 56F8345/56F8145 Features . . . . . . . . . . . .7
1.2 Device Description. . . . . . . . . . . . . . . . . . . .9
1.3 Award-Winning Development Enviro nment11
1.4 Architecture Block Diagram. . . . . . . . . . . .12
1.5 Product Documentation. . . . . . . . . . . . . . .16
1.6 Data Sheet Conventions . . . . . . . . . . . . . .16
Part 2 Signal/Connection Descriptions . . . .17
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .20
Part 3 On-Chip Clock Synthesis (OCCS). . .36
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .36
3.2 External Clock Operation. . . . . . . . . . . . . .36
3.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .38
Part 4 Memory Map . . . . . . . . . . . . . . . . . . . .38
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .38
4.2 Program Map. . . . . . . . . . . . . . . . . . . . . . .39
4.3 Interrupt Vector Table . . . . . . . . . . . . . . . .41
4.4 Data Map. . . . . . . . . . . . . . . . . . . . . . . . . .45
4.5 Flash Memory Map . . . . . . . . . . . . . . . . . .4 5
4.6 EOnCE Memory Map. . . . . . . . . . . . . . . . .46
4.7 Peripheral Memory Mapped Registers . . .47
4.8 Factory Programmed Memory. . . . . . . . . .73
Part 5 Interrupt Controller (ITCN). . . . . . . . .74
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .74
5.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3 Functional Description. . . . . . . . . . . . . . . .74
5.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . .76
5.5 Operating Modes. . . . . . . . . . . . . . . . . . . .76
5.6 Register Descriptions . . . . . . . . . . . . . . . . .77
5.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Part 6 System Integration Module (SIM) . .104
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . .104
6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . .104
6.3 Operating Modes. . . . . . . . . . . . . . . . . . .105
6.4 Operating Mode Register. . . . . . . . . . . . .105
6.5 Register Descriptions. . . . . . . . . . . . . . . .106
6.6 Clock Generation Overview. . . . . . . . . . .119
6.7 Power-Down Modes Overview . . . . . . . .119
6.8 Stop and Wait Mode Disable Func tion . .120
6.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Part 7 Security Features . . . . . . . . . . . . . . .121
7.1 Operation with Security Enabled . . . . . . .121
7.2 Flash Access Blocking Mechanisms . . . .122
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 1 25
8.2 Memory Maps . . . . . . . . . . . . . . . . . . . . . 125
8.3 Configuration. . . . . . . . . . . . . . . . . . . . . . 125
Part 9 Joint Test Action Group (JTAG) . . 131
9.1 JTAG Information . . . . . . . . . . . . . . . . . .131
Part 10 Specifications . . . . . . . . . . . . . . . . 131
10.1 General Characteristics. . . . . . . . . . . . . .131
10.2 DC Electrical Characteristics . . . . . . . . . . 136
10.3 AC Electrical Characteristics. . . . . . . . . .140
10.4 Flash Memory Characteristics. . . . . . . . . 140
10.5 External Clock Operation Timing . . . . . . 141
10.6 Phase Locked Loop Timing. . . . . . . . . . . 141
10.7 Crystal Oscillator Timing . . . . . . . . . . . . .142
10.8 Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . .142
10.9 Serial Peripheral Interface (SPI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 144
10.10 Quad Timer Timing . . . . . . . . . . . . . . . . .148
10.11 Quadrature Decoder Timing . . . . . . . . . .148
10.12 Serial Communication Interface (SCI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 149
10.13 Controller Area Network (CAN) Timing. . 150
10.14 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 1 50
10.15 Analog-to-Digital Converter (ADC)
Parameters. . . . . . . . . . . . . . . . . . . 152
10.16 Equivalent Circuit for ADC Inputs . . . . . . 155
10.17 Power Consumption . . . . . . . . . . . . . . . . 156
Part 11 Packaging . . . . . . . . . . . . . . . . . . . 158
11.1 56F8345 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 158
11.2 56F8145 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 161
Part 12 Design Considerations. . . . . . . . . 167
12.1 Thermal Design Considerations . . . . . . . 1 67
12.2 Electrical Design Considerations . . . . . .168
12.3 Power Distribution and I/O Ring
Implementation. . . . . . . . . . . . . . . .169
Part 13 Ordering Information . . . . . . . . . . 170
Table of Contents
56F8345/56F8145 Features
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 7
Preliminary
Part 1 Overview
1.1 56F8345/56F8145 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier -Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8345 and 56F8145 devices.
Table 1-1 Device Differences
Feature 56F8345 56F8145
Guaranteed Speed 60MHz/60 MIPS 40MHz/40MIPS
Program RAM 4KB Not Available
Data Flash 8KB Not Available
PWM 2 x 6 1 x 6
CAN 1 Not Available
Quad Timer 4 2
Quadrature Decode r 2 x 4 1 x 4
Temperature Sensor 1 Not Available
56F8345 Technical Data, Rev. 17
8 Freescale Semiconductor
Preliminary
1.1.3 Memory
Note: Features in italics are NOT available in the 56F8145 device.
• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security protection feature
• On-chip memory, including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
—8KB of Data RAM
— 8KB of Boot Flash
• EEPROM emulation capability
1.1.4 Peripheral Circuits
Note: Features in italics are NOT available in the 56F8145 device.
• Pulse Width Modulato r module:
— In the 56F83 45, two Pulse W idth Modu lator modules, each with six P WM outputs, three Current Sen se
inputs, and four Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned
and edge-aligned modes
— In the 56F8145, one Pul se W idth Modulator module with six PWM outputs, three Current Sense inputs
and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
• Four 12-bit, Analog-to-Digital Co nv erters (ADCs), which support four simultaneous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchr onized through Timer C, channels
2 and 3
• Quadrature Deco der:
— In the 56F8345, two four-input Quadrature Decoders or two additional Quad Timers
— In the 56F8145, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A
•Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip
temperature
•Quad Timer:
— In the 56F8345, four dedicated general-purpose Quad T imers totaling six dedicated pins: Timer C with
two pins and Timer D with four pins
— In the 56F8145, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO
• Optional On-Chip Regulator
• FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
• Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines); SPI 1 can also be used as Quadrature Decoder 1 or Quad Timer B
• Computer Operating Properly (COP)/Watchdog timer
Device Description
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 9
Preliminary
• Two dedicated external interrupt pins
• 49 General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO
• External reset input pin for hardware reset
• External reset output pin for system reset
• Integrated low-voltage interrupt module
• JTAG/ Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8345 and 56F8145 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of their low cost, configuration flexibility, and compact program code, the 56F8345 and 56F8145 are
well-suited for many applications. The devices include many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8345 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8345 and 56F8145 support program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. These devices also provide two external
dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
1.2.1 56F8345 Features
The 56F8345 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable
through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash
is incorporated for easy customer inclusion of field-programmable software routines that can be used to
56F8345 Technical Data, Rev. 17
10 Freescale Semiconductor
Preliminary
program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be
independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash
page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8345 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both
BDC and BLDC (Brush and Brushless DC motors); SRM and VR M (Switched and Variable Reluctance
Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. A patented PWM waveform distortion
correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit
integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to
synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.
The 56F8345 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal
interrupt controller are also a part of the 56F8345.
1.2.2 56F8145 Features
The 56F8145 controller includes 128KB of Program Flash, programmable through the JTAG port, and
8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of
field-programmable software routines that can be used to program the main Program Flash memory area.
The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page
erase size is 1KB. The Boot Flash page erase size is 512 bytes; Boot Flash memory can also be either bulk
or page erased.
A key application-specific feature of the 56F8145 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and can also support six independent PWM functions to enhance motor control functionality.
Complementary operation permits programmable dead time insertion, distortion correction via current
sensing by software, and separate top and bottom output polarity control. The up-counter value is
programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
Award-Winning Development Environment
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 11
Preliminary
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. The PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8145 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI s); two Seria l Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8145.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56F8345 Technical Data, Rev. 17
12 Freescale Semiconductor
Preliminary
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8145 device and are shaded in the following figures.
The 56F8345/56F8145 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the
internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the
on-board regulator and power and ground signals. They also do not show the multiplexing between
peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which
signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C input channel as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User’s Manual for clarification on the operation of all three of these
peripherals.
Architecture Block Diagram
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 13
Preliminary
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56800E
Program
Flash
Program
RAM
Data RAM
EMI*
Data
Flash
IPBus
Bridge
Boot
Flash
Flash
Memory
Module
* EMI not functional in this package; since only part of
the address/data bus is bonded out, use as GPIO pins
NOT available on the 56F8145 device.
JTAG / EOnCE
5
11
pdb_m[15:0]
4
pab[20:0]
cdbw[31:0]
xab2[23:0]
xab1[23:0]
cdbr_m[31:0]
xdb2_m[15:0
6
Address
Data
Control
CHIP
TAP
Controller
TAP
Linking
Module
External
JTAG Port
To Flash
Control
Logic
IPBus
56F8345 Technical Data, Rev. 17
14 Freescale Semiconductor
Preliminary
Figure 1-2 Peripheral Subsystem
Timer A
Timer C
Timer D
SPI1
ADCB
ADCA
FlexCAN
GPIOA
SPI0
SCI0
SCI1
Interrupt
Controller
To/From IPBus Bridge
PWMA
PWMB
Quadrature Decoder 0
Note: ADC A and ADC B use the same
voltage reference circuit with VREFH,
VREFP, VREFMID, VREFN, and VREFLO
pins.
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
Timer B
Quadrature Decoder 1
TEMP_SENSE
NOT available on the 56F8145 device.
Low-Voltage Interrupt
System POR
COP Reset
RESET
POR & LVI
SIM
COP
2
13
13
CLKGEN
(OSC / PLL)
4
4
4
SYNC Output
SYNC Output
2
ch3i ch2i
ch3o ch2o
8
8
1
2
2
4
IPBus
Architecture Block Diagram
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 15
Preliminary
Table 1-2 Bus Signal Names
Name Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operatio ns.
cdbw[15:0] Primary core data bus use d for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0] Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interfac e Bus
cdbr_m[31:0] Primary core data bus for memory reads. Add re ssed via xab1 bus.
cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0] Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
1. Byte accesses can only occur in t he bottom half of the memory address space. The MSB of the address will be forced
to 0.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bu s used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0] Secondary data ad dress bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
56F8345 Technical Data, Rev. 17
16 Freescale Semiconductor
Preliminary
1.5 Product Documentation
The documents listed in Table 1-3 are required for a complete description and proper design with the
56F8345 and 56F8145 devices. Documentation is available from local
Freescale
distributors,
Freescale
Semiconductor sales offices,
Freescale
Literature Distribution Centers, or online at
http://www.freescale.com.
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
Table 1-3 Chip Documentation
Topic Description Order Number
DSP56800E
Reference Manual Detailed description of the 56800E family architecture,
16-bit controller core processor, and the instruction set DSP56800EERM
56F8300 Peripheral User
Manual Detailed description of perip herals of the 56F8300
family of devices MC56F8300UM
56F8300 SCI/CAN
Bootloader User Manual Detailed description of th e SCI/CAN Bootloaders
56F8300 family of devices MC56F83xxBLUM
56F8345/56F8145
Technical Data Sheet Electrical and timing specifications, pin descriptions,
device specific peripheral information and package
descriptions (this document)
MC56F8345
Errata Details any chip issues that might be present MC56F8345E
MC56F8145E
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
Introduction
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 17
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8345 and 56F8145 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Grou p Number of Pins in Package
56F8345 56F8145
Power (VDD or VDDA)99
Power Option Control 11
Ground (VSS or VSSA)66
Supply Capacitors1 & VPP
1. If the on-chip regulator is disabled, the VCAP pins ser ve as 2. 5V VDD_CORE power inputs
66
PLL and Clock 44
Bus Control 66
Interrupt and Program Control 44
Pulse Width Modulator (PWM) Ports 26 13
Serial Peripheral Interface (SPI) Port 0 44
Serial Peripheral Interface (SPI) Port 1 —4
Quadrature Decoder Port 02
2. Alternately, can f unction as Quad Timer pins or GPIO
44
Quadrature Decoder Port 13
3. Pins in this section can function as Quad Timer, SPI 1, orGPIO
4—
Serial Communications Interface (SCI) Ports 44
CAN Ports 2—
Analog-to-Digital Converter (ADC) Ports 21 21
Timer Module Ports 64
JTAG/Enhanced On-Chip Emulati on (EOnCE) 55
Temperature Sense 1—
Dedicated GPIO ( Address Bus = 11; Data Bus = 44)
4. EMI not functional in these packages; use as GPIO pins.
Note: See Table 1-1 for 56F8145 functional differences.
28 28
56F8345 Technical Data, Rev. 17
18 Freescale Semiconductor
Preliminary
Figure 2-1 56F8345 Signals Identified by Functional Group1 (128-Pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
VDD_IO
VDDA_OSC_PLL
VSS
VSSA_ADC
Other
Supply
Ports
PLL
and
Clock
*External
Address
Bus
or GPIO
*External
Data Bus
*External
Bus
Control
SCI0 or
GPIOE
SCI1 or
GPIO
JTAG/
EOnCE
Port
5
1
7
1
1
VCAP1 - VCAP4
VPP1 & VPP24
2
Power
Power
Power
Ground
Ground
1
1
1
A8 - A13 (GPIOA0 - 5)
D7 - D10 (GPIOF0 - 3)
GPIOD0 - 5 (CS2 - 7)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
PHASEB0(TA1, GPIOC5 )
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
ISA0 - 2 (GPIOC8 - 10)
FAULTB0-3
PWMB0 - 5
ANA0 - 7
TD0 - 3 (GPIOE10 - 13)
IRQA
IRQB
RESET
RSTO
SPI0 or
GPIO
Quadrature
Decoder 1 or
Quad Timer B
or SPI1 or
GPIO
Temperature
Sensor
6
5
4
1
1
1
1
1
1
1
1
1
6
3
3
8
5
4
GPIOB0-4 (A16 - 20)
6
EXTAL
XTAL
CLKO
1
7
1
1
1
1
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TCK
TMS
TDI
TDO
TRST
SCLK0 (GPIOE4)
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
PHASEB1 (TB1, MOSI1, GPIOC1)
INDEX1 (TB2, MISO1, GPIOC2)
HOME1 (TB3, SS1, GPIOC3)
PWMA0 - 5
FAULTA0 - 3
ISB0 - 2 (GPIOD10 - 12)
ANB0 - 7
CAN_RX
CAN_TX
TC0 - 1 (GPIOE8 - 9)
PWMA
PWMB
ADCB
ADCA
CAN
Interrupt/
Program
Control
PHASEA1(TB0, SCLK1, GPIOC0)
6
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
6
4
8
1
1
2
1
1
1
1
VREF
CLKMODE 1
TEMP_SENSE
1
* EMI not functional in this package; use as GPIO pins
OCR_DIS
VDDA_ADC
156F8345
PHASEA0 (TA0, GPIOC4)
Quad
Timer C
and D or
GPIO
Introduction
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 19
Preliminary
Figure 2-2 56F8145 Signals Identified by Functional Group1 (128-Pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
VDD_IO
VDDA_OSC_PLL
VSS
VSSA_ADC
Other
Supply
Ports
PLL
and
Clock
*External
Address
Bus
or GPIO
*External
Data Bus
*External
Bus
Control
SCI0 or
GPIOE
SCI1 or
GPIO
JTAG/
EOnCE
Port
5
1
7
1
1
VCAP1 - VCAP4
VPP1 & VPP24
2
Power
Power
Power
Ground
Ground
1
1
1
A8 - A13 (GPIOA0 - 5)
D7 - D10 (GPIOF0 - 3)
GPIOD0 - 5 (CS2 - 7)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
PHASEB0(TA1, GPIOC5 )
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
(GPIOC8 - 10)
FAULTB0-3
PWMB0 - 5
ANA0 - 7
(GPIOE10 - 13)
IRQA
IRQB
RESET
RSTO
SPI0 or
GPIO
SPI1 or
GPIO
6
5
4
1
1
1
1
1
1
1
1
1
3
3
8
5
4
GPIOB0-4 (A16 - 20)
6
EXTAL
XTAL
CLKO
1
7
1
1
1
1
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TCK
TMS
TDI
TDO
TRST
SCLK0 (GPIOE4)
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIO E7)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(SS1,GPIOC3)
ISB0 - 2 (GPIOD10 - 12)
ANB0 - 7
TC0 - 1 (GPIOE8 - 9)
GPIO
PWMB
ADCB
ADCA
Interrupt/
Program
Control
(SCLK1, GPIOC0)
6
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
4
8
2
1
1
1
1
VREF
CLKMODE 1
* EMI not functional in this package; use as GPIO pins
OCR_DIS
VDDA_ADC
156F8145
PHASEA0 (TA0, GPIOC4)
QUAD
Timer C or
GPIO
56F8345 Technical Data, Rev. 17
20 Freescale Semiconductor
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
EMI is not functional in this package; since only part of the address/data bus is bonded out, use as GPIO
pins.
Note: Signals in italics are NOT available in the 56F8145 device.
If the “State During Reset” lists more than one state fo r a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information fo r the 128-Pin LQFP
Signal
Name Pin No. Type State
During
Reset Signal Description
VDD_IO 4 Supply I/O Power — This pin supplies 3.3V power to the chip I/O
interface and also the Processor core throught the on-chip
voltage regulator, if it is enabled.
VDD_IO 14
VDD_IO 25
VDD_IO 36
VDD_IO 62
VDD_IO 76
VDD_IO 112
VDDA_ADC 94 Supply ADC Power — This pin supplies 3. 3V po w er to the ADC
modules. It must be connected to a clean analo g power supply.
VDDA_OSC_
PLL 72 Supply Oscillator and PLL Power — This pin supplies 3.3V power to
the OSC and to the internal regulator that in turn supplies the
Phase Locked Loop. It must be connected to a clean analog
power supply.
VSS 3 Supply Ground — These pins provide groun d for chip logic and I/O
drivers.
VSS 21
VSS 35
VSS 59
VSS 65
Signal Pins
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 21
Preliminary
VSSA_ADC 95 Supply ADC Analog Ground — This pin supplies an analog ground to
the ADC modul e s.
OCR_DIS 71 Input Input On-Chip Regul ator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from powe r-up
to shut down. Do not try to toggle this pin for p ower savings
during operation.
VCAP149 Supply Supply VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2μF or greater bypa ss capacito r in order
to bypass the core logic voltage regulator, required for proper
chip operation. When OCR_DIS is tied to VDD (regulator
disabled), these pins become VDD_CORE and should be
connected to a regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered
with an external supply.
VCAP2122
VCAP375
VCAP413
VPP1119 Input Input VPP1 - 2 — These pins should be left unconnected as an open
circuit for normal functionality.
VPP25
CLKMODE 79 Input Input Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the
input clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
EXTAL 74 Input Input External Crystal Oscillator Input — This input ca n be
connected to an 8MHz external crystal. Tie this pin low if XTAL is
driven by an external clock source.
XTAL 73 Input/
Output Chip-driven Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide th e clock directly to
the core. This input clock can also be selected as the input clock
for the on-chip PLL.
Table 2-2 Signal and Package Information fo r the 128-Pin LQFP
Signal
Name Pin No. Type State
During
Reset Signal Description
56F8345 Technical Data, Rev. 17
22 Freescale Semiconductor
Preliminary
CLKO 6 Output In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock
and postscaler clock. Other signals are al so available for test
purposes.
See Part 6.5.7 for details.
A8
(GPIOA0)
15 Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A8 - A13 specify six of the address lines for
external program or data memory accesses. Depending upon
the state of the DRV bit in the EMI bus control register (BCR), A8
- A13 and EMI control signals are tri-stated when th e external
bus is inactive.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to address bus functionality and
must be programme d as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
A9
(GPIOA1) 16
A10
(GPIOA2) 17
A11
(GPIOA3) 18
A12
(GPIOA4) 19
A13
(GPIOA5) 20
GPIOB0
(A16)
27 Schmitt
Input/
Output
Output
Input,
pull-up
enabled
Port B GPIO — These four GPIO pins can be individually
programmed as an input or output pin.
Address Bus — A16 - A19 specify four of the address lines for
external program or data memory accesses. Depending upon
the state of the DRV bit in the EMI bus control register (BCR),
A16 - A19 and EMI control signals are tri-stated when the
external bus is inactive.
After reset, the default state is GPIO.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.
GPIOB1
(A17)
28
GPIOB2
(A18)
29
GPIOB3
(A19)
30
Table 2-2 Signal and Package Information fo r the 128-Pin LQFP
Signal
Name Pin No. Type State
During
Reset Signal Description
Signal Pins
56F8345 Technical Data, Rev. 17
Freescale Semiconductor 23
Preliminary
GPIOB4
(A20)
(prescaler_
clock)
31 Schmitt
Input/
Output
Output
Output
Input,
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed
as an input or output pin.
Address Bus — A20 specifies one of the address lines for
external program or data memory accesses. Depending upon
the state of the DRV bit in the EMI bus control register (BCR),
A20 and EMI control signals are tri-stated when the external bus
is inactive.
Clock Output — can be used to monitor the prescaler_clock on
GPIOB4.
After reset, the default state is GPIO.
This pin can also be used to view the prescaler_clock. In these
cases, the GPIOB_PER can be used to disable the GPIO. The
CLKOSR register in the SIM can then be used to choose
between address and clock functions; see
Part 6.5.7 for details.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOB_PUR register.
D7
(GPIOF0)
22 Input/
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D7 - D10 specify part of the data for external
program or data memory accesses. Depending upon the state of
the DRV bit in the EMI bus control register (BCR), D7 - D10 are
tri-stated when the external bus is inac tive
Port F GPIO — These four GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to data bus functionality and
should be programmed as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
D8
(GPIOF1) 23
D9
(GPIOF2) 24
D10
(GPIOF3) 26
Table 2-2 Signal and Package Information fo r the 128-Pin LQFP
Signal
Name Pin No. Type State
During
Reset Signal Description
56F8345 Technical Data, Rev. 17
24 Freescale Semiconductor
Preliminary
GPIOD0
(CS2)
42 Input/
Output
Output
Input,
pull-up
enabled
Port D GPIO — These six GPIO pins can be individually
programmed as input or output pins.
Chip Select — CS2 - CS7 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map. Depending upon the state of the DRV bit in the
EMI bus control register (BCR), CS2 - CS7 are tri-stated when
the external bus is inactive.
After reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
GPIOD1
(CS3)43
GPIOD2
(CS4)44
GPIOD3
(CS5)45
GPIOD4
(CS6) 46
GPIOD5
(CS7) 47
TXD0
(GPIOE0)
7 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
(GPIOE1)
8 Input
Input/
Output
Input,
pull-up
enabled
Receive Data — SCI0 receive data input
Port E GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
TXD1
(GPIOD6)
40 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information fo r the 128-Pin LQFP
Signal
Name Pin No. Type State
During
Reset Signal Description