STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Arm(R) Cortex(R)-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/ 512+16+4KB RAM, USB OTG HS/FS, 28 com IF, LCD, DSI Datasheet - production data Features * Core: Arm(R) 32-bit Cortex(R)-M7 CPU with DPFPU, ART AcceleratorTM and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. * Memories - Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write - SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories * Dual mode Quad-SPI * Graphics - Chrom-ART AcceleratorTM (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface - Hardware JPEG codec - LCD-TFT controller supporting up to XGA resolution - MIPI(R) DSI host controller supporting up to 720p 30 Hz resolution * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - Dedicated USB power - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration September 2017 This is information on a product in full production. &"'! LQFP100 (14 x 14 mm) UFBGA176 (10 x 10 mm) WLCSP180 LQFP144 (20 x 20 mm) (0.4 mm pitch) LQFP176 (24 x 24 mm) TFBGA216 (13 x 13 mm) TFBGA100 (8 x 8 mm) LQFP208 (28 x 28 mm) * Low-power - Sleep, Stop and Standby modes - VBAT supply for RTC, 32x32 bit backup registers + 4 Kbytes backup SRAM * 3x12-bit, 2.4 MSPS ADC: up to 24 channels * Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters * 2x12-bit D/A converters * General-purpose DMA: 16-stream DMA controller with FIFOs and burst support * Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer * Debug mode - SWD & JTAG interfaces - Cortex(R)-M7 Trace MacrocellTM * Up to 168 I/O ports with interrupt capability - Up to 164 fast I/Os up to 108 MHz - Up to 166 5 V-tolerant I/Os DocID029041 Rev 6 1/255 www.st.com STM32F765xx STM32F767xx STM32F768Ax STM32F769xx * Up to 28 communication interfaces - Up to 4 I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) - Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio - 2 x SAIs (serial audio interface) - 3 x CANs (2.0B Active) and 2x SDMMCs - SPDIFRX interface - HDMI-CEC - MDIO slave interface * Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII * 8- to 14-bit camera interface up to 54 Mbyte/s * True random number generator * CRC calculation unit * RTC: subsecond accuracy, hardware calendar * 96-bit unique ID Table 1. Device summary Reference Part number STM32F765xx STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG STM32F767xx STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI STM32F768Ax STM32F768AI STM32F769xx STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, STM32F769NG, STM32F769NI 2/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.11 Chrom-ART AcceleratorTM (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 2.13 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.19 2.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35 2.20 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 2.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID029041 Rev 6 3/255 6 Contents STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 42 2.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 43 2.27 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.28 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.30 Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.31 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 45 2.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 45 2.33 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 46 2.35 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 46 2.36 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 48 2.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.42 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 49 2.43 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.44 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.45 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.46 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.47 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 115 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 115 5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 115 5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 145 5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 156 5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DocID029041 Rev 6 5/255 6 Contents 6 7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 213 5.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 214 5.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 216 5.3.35 DFSDM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 219 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1 LQFP100 14x 14 mm, low-profile quad flat package information . . . . . . 221 6.2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.3 LQFP144 20 x 20 mm, low-profile quad flat package information . . . . . 228 6.4 LQFP176 24 x 24 mm, low-profile quad flat package information . . . . . 232 6.5 LQFP208 28 x 28 mm low-profile quad flat package information . . . . . . 236 6.6 WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.7 UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 6.8 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 252 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 6/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 114 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 115 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode), regulator ON . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Typical and maximum current consumption in Run mode, code with data processing DocID029041 Rev 6 7/255 10 List of tables Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. 8/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 126 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 127 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 127 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 128 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 129 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (dual bank configuration nDBANK=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 189 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 190 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 194 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 198 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 DFSDM measured timing 1.71-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 220 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 220 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 222 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 227 DocID029041 Rev 6 9/255 10 List of tables STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 134. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 245 Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 137. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 248 Table 138. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table 139. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 140. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 252 Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 10/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx block diagram . . . . 19 STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 34 STM32F76xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F76xxx TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32F76xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32F76xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F769xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32F769Ax/STM32F768Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32F76xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F769xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32F76xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32F76xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32F769xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 150 MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 150 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 170 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 170 DocID029041 Rev 6 11/255 13 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 12/255 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 186 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 192 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 194 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 197 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 207 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 207 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 221 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 TFBGA100, 8 x 8 x 0.8mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 228 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. List of figures LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 232 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 236 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 DocID029041 Rev 6 13/255 13 Description 1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the high-performance Arm(R) Cortex(R)-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex(R)-M7 core features a floating point unit (FPU) which supports Arm(R) double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces: * Up to four I2Cs * Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. * Four USARTs plus four UARTs * An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI) * Three CANs * Two SAI serial audio interfaces * Two SDMMC host interfaces * Ethernet and camera interfaces * LCD-TFT display controller * Chrom-ART AcceleratorTM * SPDIFRX interface * HDMI-CEC Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices operate in the -40 to +105 C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. 14/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description These features make the STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile applications, Internet of Things * Wearable devices: smartwatches The following table lists the peripherals available on each part number. DocID029041 Rev 6 15/255 53 STM32F 765Vx Peripherals Flash memory in Kbytes SRAM in Kbytes 1024 2048 STM32F767 /769Vx 1024 STM32F 765Zx STM32F767 /769Zx STM32F 769Ax 2048 1024 2048 1024 2048 1024 2048 Instruction 16 Backup 4 STM32F767 /769Bx STM32F 765Nx 1024 2048 STM32F767 /769Nx 1024 2048 Yes Yes No Yes 10 Advancedcontrol 2 Basic 2 Low-power 1 SPI / I2S Yes 4/3 (simplex)(2) 6/3 (simplex)(2) I2C 4 USART/UART 4/4 USB OTG FS Yes USB OTG HS Yes CAN 3 SAI 2 SPDIFRX 4 inputs SDMMC1 Yes SDMMC2 Yes(3) Camera interface Yes Host(4) No No Yes Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DocID029041 Rev 6 Generalpurpose Random number generator LCD-TFT STM32F 765Bx Yes(1) Ethernet MIPI-DSI STM32F767 /769Ix 1024 2048 1024 2048 1024 2048 1024 2048 512(368+16+128) Quad-SPI Communication interfaces 2048 STM32F 765Ix System FMC memory controller Timers STM32F 768Ax Description 16/255 Table 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts Peripherals STM32F 765Vx STM32F767 /769Vx STM32F 765Zx STM32F767 /769Zx STM32F 769Ax STM32F 768Ax Chrom-ART AcceleratorTM (DMA2D) JPEG codec GPIOs No Yes No 82 Yes 114 129 STM32F 765Bx STM32F767 /769Bx STM32F 765Nx STM32F767 /769Nx No Yes No Yes No Yes 140 132 168 159 168 159 Yes (4 filters) 12-bit ADC 3 16 24 Yes 2 12-bit DAC Number of channels 216 MHz(5) Maximum CPU frequency DocID029041 Rev 6 1.7 to 3.6 V(6) Operating voltage Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Package STM32F767 /769Ix Yes DFSDM1 Number of channels STM32F 765Ix Junction temperature: -40 to + 125 C LQFP100 TFBGA100 LQFP144 WLCSP180 UFBGA176(7) LQFP176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. LQFP208 TFBGA216 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts (continued) 3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 4. DSI host interface is only available on STM32F769x sales types. 5. 216 MHz maximum frequency for - 40C to + 85C ambient temperature range (200 MHz maximum frequency for - 40C to + 105C ambient temperature range). 6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). 7. UFBGA176 is not available for STM32F769x sales types. Description 17/255 Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Full compatibility throughout the family The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package 3& 9'' 966$ 95() 9''$ 3$:.83 3$ 3$ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 9'' 3% 9&$3 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3& 3% 3& 3$ 3$ 3$ 3$ 9'' 3$ 3& 966$ 95() 9''$ 3$:.83 3$ 3$ 3$ 966 670)[[[ 3LQVWRDUHQRWFRPSDWLEOH 9'' 966 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9'' 966 06Y9 The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are fully pin to pin compatible with STM32F4xx devices. 18/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description Figure 2. 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The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID029041 Rev 6 19/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2 Functional overview 2.1 Arm(R) Cortex(R)-M7 with FPU The Arm(R) Cortex(R)-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering an outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: - Six-stage dual-issue pipeline - Dynamic branch prediction - Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) - 64-bit AXI4 interface - 64-bit ITCM interface - 2x32-bit DTCM interfaces The processor supports the following memory interfaces: * Tightly Coupled Memory (TCM) interface. * Harvard instruction and data caches and AXI master (AXIM) interface. * Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow an efficient signal processing and a complex algorithm execution. It supports single and double precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 2 shows the general block diagram of the STM32F76xxx family. Note: The Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. 2.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 20/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.3 Functional overview Embedded Flash memory The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. The Flash interface features: 2.4 * Single /or Dual bank operating modes, * Read-While-Write (RWW) in Dual bank mode. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.5 Embedded SRAM All the devices feature: * * System SRAM up to 512 Kbytes: - SRAM1 on AHB bus Matrix: 368 Kbytes - SRAM2 on AHB bus Matrix: 16 Kbytes - DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: - It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. * 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. DocID029041 Rev 6 21/255 53 Functional overview 2.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx AXI-AHB bus matrix The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx system architecture is based on 2 sub-systems: * An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: * - 3x AXI to 32-bit AHB bridges connected to AHB bus matrix - 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix - The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. ,^ D ZZd Z D >d&dD h^,^D DW d,ZEdD ,W y/D .% ,'&DFKH 'W D h^Kd' >d&d D ,^ DDD DW/ ZD 'W D DDD /dD dD Figure 3. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) dDZD < /dDZD < y/Z , Zd /dD , &>^, D ^D ^ZD < ^ZD < , W , &D D W W Y^W/ D^ 06Y9 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. 22/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.7 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and the transfer sizes between the source and the destination are independent. The DMA can be used with the main peripherals: * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * DAC * SDMMC * Camera interface (DCMI) * ADC * SAI * SPDIFRX * Quad-SPI * HDMI-CEC * JPEG codec * DFSDM1 DocID029041 Rev 6 23/255 53 Functional overview 2.8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: * The NOR/PSRAM memory controller * The NAND/memory controller * The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: * Interface with static-memory mapped devices including: - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-,16-,32-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: * Direct mode through registers * External Flash status register polling mode * Memory mapped mode. Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access. Code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. 24/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.10 Functional overview LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 2.11 * 2 display layers with dedicated FIFO (64x32-bit) * Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events Chrom-ART AcceleratorTM (DMA2D) The Chrom-Art AcceleratorTM (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: * Rectangle filling with a fixed color * Rectangle copy * Rectangle copy with pixel format conversion * Rectangle composition with blending and pixel format conversion Various image format codings are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 2.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. DocID029041 Rev 6 25/255 53 Functional overview 2.13 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx JPEG codec (JPEG) The JPEG codec provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features: 2.14 * 8-bit/channel pixel depths * Single clock per pixel encoding and decoding * Support for JPEG header generation and parsing * Up to four programmable quantization tables * Fully programmable Huffman tables (two AC and two DC) * Fully programmable minimum coded unit (MCU) * Encode/decode support (non simultaneous) * Single clock Huffman coding and decoding * Two-channel interface: Pixel/Compress In, Pixel/Compressed Out * Stallable design * Support for single, greyscale component * Functionality to enable/disable header processing * Internal register interface * Fully synchronous design * Configured for high-speed decode mode External interrupt/event controller (EXTI) The external interrupt/event controller consists of 25 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 2.15 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. 26/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.16 Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space mapped on ITCM or AXIM interface * All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface * The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to STM32 microcontroller system memory boot mode application note (AN2606) for details. 2.17 Note: Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. * * VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: - During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - The VDDSDMMC rising and falling time rate specifications must be respected - In operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to DocID029041 Rev 6 27/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx disappear. The following conditions VDDUSB must be respected: - During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - The VDDUSB rising and falling time rate specifications must be respected (see Table 20 and Table 21) - In operating mode phase, VDDUSB could be lower or higher than VDD: - If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 4. VDDUSB connected to VDD power supply 9'' 9''B0$; 9'' 9''$ 9''86% 9''B0,1 3RZHURQ 2SHUDWLQJPRGH 3RZHUGRZQ WLPH 069 28/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 5. VDDUSB connected to external power supply 9''86%B0$; 86% IXQFWLRQDODUHD 9''86% 9''86%B0,1 86%QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 9''B0,1 2SHUDWLQJPRGH 3RZHURQ WLPH 3RZHUGRZQ 069 The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins: * VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global VDD. * The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally to VDD12DSI. * The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin. * The VSSDSI pin is an isolated supply ground used for DSI sub-system. * If the DSI functionality is not used at all, then: - The VDDDSI pin must be connected to global VDD. - The VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed. - The VSSDSI pin must be grounded. 2.18 Power supply supervisor 2.18.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through DocID029041 Rev 6 29/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.18.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 1567 9'' $SSOLFDWLRQUHVHW VLJQDO 3'5B21 966 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD. All the packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. 30/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 2.19 Voltage regulator The regulator has four operating modes: * * 2.19.1 Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: * MR mode used in Run/sleep modes or in Stop modes - In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. - In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). DocID029041 Rev 6 31/255 53 Functional overview * STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: * - LPR operates in normal mode (default mode when LPR is ON) - LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. `-' means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 2.19.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In the regulator OFF mode, the following features are no more supported: 32/255 * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. * The over-drive and under-drive modes are not available. * The Standby mode is not available. DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDORSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: Note: * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DocID029041 Rev 6 33/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization 9'' 3'5 RU9 9 0LQ9 9&$3B9&$3B WLPH 1567 3$ WLPH DLJ 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization 9'' 3'5 9RU9 9&$3B9&$3B 9 0LQ9 1567 WLPH 3$DVVHUWHGH[WHUQDOO\ WLPH DLH 1. This figure is valid whatever the internal reset mode (ON or OFF). 34/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.19.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 LQFP144, LQFP208 LQFP176, UFBGA176, TFBGA100, TFBGA216 WLCSP180 Yes Internal reset ON Internal reset OFF Yes No No Yes Yes Yes Yes BYPASS_REG set BYPASS_REG set PDR_ON set to VDD PDR_ON set to VSS to VDD to VSS Yes(1) 1. Available only on dedicated part number. Refer to Section 7: Ordering information. 2.20 Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. DocID029041 Rev 6 35/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator(LSE) * The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.21 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): - Normal mode (default mode when MR or LPR is enabled) - Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode * Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering 36/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 2.22 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and the VBAT pin should be connected to VDD. 2.23 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. DocID029041 Rev 6 37/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 38/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 2.23.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F76xxx devices (see Table 6 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F76xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 2.23.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. DocID029041 Rev 6 39/255 53 Functional overview 2.23.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 2.23.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 2.23.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 2.23.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 40/255 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.24 Functional overview Inter-integrated circuit interface (I2C) The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * I2C-bus specification and user manual rev. 5 compatibility: - Slave and master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X 1. X: supported. DocID029041 Rev 6 41/255 53 Functional overview 2.25 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USART. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: * Full-duplex asynchronous communications * Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance * Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming * A common programmable transmit and receive baud rate of up to 27 Mbit/s when the USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. * Auto baud rate detection * Programmable data word length (7 or 8 or 9 bits) word length * Programmable data order with MSB-first or LSB-first shifting * Programmable parity (odd, even, no parity) * Configurable stop bits (1 or 1.5 or 2 stop bits) * Synchronous mode and clock output for synchronous communications * Single-wire half-duplex communications * Separate signal polarity control for transmission and reception * Swappable Tx/Rx pin configuration * Hardware flow control for modem and RS-485 transceiver * Multiprocessor communications * LIN master synchronous break send capability and LIN slave break detection capability * IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode * Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard ) * Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length 42/255 UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 54 Mbits/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.27 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC'97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. DocID029041 Rev 6 43/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SAI1 and SAI2 can be served by the DMA controller 2.28 SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main features of the SPDIFRX are the following: * Up to 4 inputs available * Automatic symbol rate detection * Maximum symbol rate: 12.288 MHz * Stereo stream from 32 to 192 kHz supported * Supports Audio IEC-60958 and IEC-61937, consumer applications * Parity bit management * Communication using DMA for audio samples * Communication using DMA for control and user channel information * Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 2.29 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 2.30 Audio and LCD PLL (PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. 44/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.31 Functional overview SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support the MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 2.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: * Supports 10 and 100 Mbit/s rates * Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors * Tagged MAC frame support (VLAN support) * Half-duplex (CSMA/CD) and full-duplex operation * MAC control sublayer (control frames) support * 32-bit CRC generation and removal * Several address filtering modes for physical and multicast address (multicast and group addresses) * 32-bit status code for each transmitted or received frame * Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. * Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input * Triggers interrupt when system time becomes greater than target time DocID029041 Rev 6 45/255 53 Functional overview 2.33 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Controller area network (bxCAN) The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM are dedicated for CAN3. 2.34 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints * 12 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * HNP/SNP/IP inside (no need for any external resistor) For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.35 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 46/255 * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.36 Functional overview * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * for OTG/Host modes, a power switch is needed in case bus-powered devices are connected High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 2.37 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It features: * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports continuous mode or snapshot (a single frame) mode * Capability to automatically crop the image DocID029041 Rev 6 47/255 53 Functional overview 2.38 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Management Data Input/Output (MDIO) slaves The devices embed a MDIO slave interface it includes the following features: * - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers * Configurable slave (port) address * Independently maskable interrupts/events: * 2.39 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: - MDIO Register write - MDIO Register read - MDIO protocol error Able to operate in and wake up from STOP mode Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.40 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. A fast I/O handling allows a maximum I/O toggling up to 108 MHz. 2.41 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 48/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.42 Functional overview Digital filter for Sigma-Delta Modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface formats (to support various modulators). The DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: * * 8 multiplexed input digital serial channels: - Configurable SPI interface to connect various SD modulator(s) - Configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - Clock output for SD modulator(s): 0..20 MHz Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): - * internal sources: device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: - Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024) - integrator: oversampling ratio (1..256) * Up to 24-bit output data resolution, signed output data format * Automatic data offset correction (offset stored in register by user) * Continuous or single conversion * Start-of-conversion triggered by: * * - Software trigger - Internal timers - External events - Start-of-conversion synchronously with first digital filter module (DFSDM0) Analog watchdog feature: - Low value and high value data threshold registers - Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) - Input from final output data or from selected input digital serial channels - Continuous monitoring independently from standard conversion Short circuit detector to detect saturated analog input values (bottom and top range): - Up to 8-bit counter to detect 1..256 consecutive 0's or 1's on serial data stream - Monitoring continuously each input serial channel * Break signal generation on analog watchdog event or on short circuit detector event * Extremes detector: - Storage of minimum and maximum values of final conversion data DocID029041 Rev 6 49/255 53 Functional overview - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refreshed by software * DMA capability to read the final conversion data * Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence * "regular" or "injected" conversions: - "regular" conversions can be requested at any time or even in continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority Table 9. DFSDM implementation DFSDM features Number of filters: x (DFSDM_FLTx) 4 Number of input transceivers/channels: y (DFSDM_CHy) 8 Internal ADC parallel input support - Number of external triggers (JEXTSEL size) ID register support 50/255 DFSDM1 32 - DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.43 Functional overview Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.44 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability for each channel * External triggers for conversion * Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.45 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.46 Embedded Trace MacrocellTM The Arm embedded trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F76xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or DocID029041 Rev 6 51/255 53 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 2.47 DSI Host (DSIHOST) The DSI Host is a dedicated peripheral for interfacing with MIPI(R) DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. These interfaces are as follows: * * * LTDC interface: - Used to transmit information in Video mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI). - Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command mode (DBI). APB slave interface: - Allows the transmission of generic information in Command mode, and follows a proprietary register interface. - Can operate concurrently with either LTDC interface in either Video mode or Adapted Command mode. Video mode pattern generator: - Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli. The DSI Host main features: * Compliant with MIPI(R) Alliance standards * Interface with MIPI(R) D-PHY * Supports all commands defined in the MIPI(R) Alliance specification for DCS: Transmission of all Command mode packets through the APB interface - Transmission of commands in low-power and high-speed during Video mode * Supports up to two D-PHY data lanes * Bidirectional communication and escape mode support through data lane 0 * Supports non-continuous clock in D-PHY clock lane for additional power saving * Supports Ultra Low-power mode with PLL disabled * ECC and Checksum capabilities * Support for End of Transmission Packet (EoTp) * Fault recovery schemes * 3D transmission support * Configurable selection of system interfaces: * 52/255 - - AMBA APB for control and optional support for Generic and DCS commands - Video Mode interface through LTDC - Adapted Command mode interface through LTDC Independently programmable Virtual Channel ID in DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx - Video mode - Adapted Command mode - APB Slave Functional overview Video Mode interfaces features: * LTDC interface color coding mappings into 24-bit interface: - 16-bit RGB, configurations 1, 2, and 3 - 18-bit RGB, configurations 1 and 2 - 24-bit RGB * Programmable polarity of all LTDC interface signals * Maximum resolution is limited by available DSI physical link bandwidth: - Number of lanes: 2 - Maximum speed per lane: 500 Mbps1Gbps Adapted interface features Support for sending large amounts of data through the memory_write_start(WMS) and memory_write_continue(WMC) DCS commands * LTDC interface color coding mappings into 24-bit interface: - 16-bit RGB, configurations 1, 2, and 3 - 18-bit RGB, configurations 1 and 2 - 24-bit RGB Video mode pattern generator: * Vertical and horizontal color bar generation without LTDC stimuli * BER pattern without LTDC stimuli DocID029041 Rev 6 53/255 53 Pinouts and pin description 3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description s s^^ W W W W KKd W W W W W W W W W W W W W W W W W W Figure 11. STM32F76xxx LQFP100 pinout /4)3 s s^^ sW W W W W W W W W W W W W W W W W W W W W W W s^^ s W W W W W W W W W W W W W W W W W W W W sW s^^ s W W W W W sd WEd/dDW WK^/E WK^Khd s^^ s W,K^/E W,K^Khd EZ^d W W W W s^^ sZ& s WtY&W W/ W/ W/ W, W, W, s s^^ sW W W W W W W W W W W sh^ s^^ W' W' W' W' W' W' W' W< W< W< s^^ s W: W: W: W: W: W: W W s s^^ W W W W W W W W W W W W W W W s s^^ W W W W/ W: W: W: W: W: W& W& s^^ s W& W& W& W' W' W W W s^^ s W W W W W W W W sW s^^ s W: W, W, W, W, W, W, W, s W W W W W W sd W/ W W W W/ W/ W/ s^^ s W& W& W& W/ W/ W/ W& W& W& s^^ s W& W& W& W& W& W, W, EZ^d W W W W s s^^ sZ& s W W W W, W, W, W, W s^^ s W/ W/ W/ W/ s WZKE s^^ W W W W KKd W W W W W W' W< W< W< W< W< s s^^ W' W' W' W' W' W' W: W: W: W: W W s^DD s^^ W W W W W W W W W W W s W/ Figure 17. STM32F76xxx LQFP208 pinout 1. The above figure shows the package top view. 60/255 DocID029041 Rev 6 06Y9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description /4)3ZLWK'6, W/ W/ W/ W, W, W, s s^^ sW W W W W W W W W W W sh^ s^^ W' W' W' W' W' W' W' s^^^/ ^/E ^/W s^/ ^/@3'>@ ,1 i) 9'' 9''86% ,2 /RJLF .HUQHOORJLF &38 GLJLWDO 5$0 9&$3B 9&$3B 9'' iQ) i) /HYHOVKLIWHU 9''6'00& 9ROWDJH UHJXODWRU 966 )ODVKPHPRU\ %<3$66B5(* 9''86% Q) ) 27*)6 3+< 9'''6, 9&$3'6, 9'''6, ) 966'6, 3'5B21 9'' '6, 3+< 5HVHW FRQWUROOHU 9''$ 95() Q) ) '6, YROWDJH UHJXODWRU Q) ) 95() 95() $'& $QDORJ 5&V3// 966$ 06Y9 108/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 26. STM32F767xx/STM32F777xx power supply scheme 9 %$7 9 ''6'00& 287 3*>@3'>@ ,1 287 3$>@3%>@ 9 ''86% ,1 9''86% /HYHOVKLIWHU ,1 9 ''6'00& /HYHOVKLIWHU *3 ,2 V /HYHOVKLIWHU 287 Q) ) EDFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 3RZHUVZLWFK 9%$7 WR9 ,2 /RJLF ,2 /RJLF ,2 /RJLF Q) ) 27*)6 3+< i) 9 '' 9 '' iQ) i) .HUQHOORJLF &38 GLJLWDO 5$0 9 &$3B 9 &$3B 9ROWDJH UHJXODWRU 9 66 )ODVKPHPRU\ %<3$66B5(* 3'5B21 9 '' 9 ''$ 9 5() Q) ) 5HVHW FRQWUROOHU Q) ) 9 5() 9 5() $'& $QDORJ 5&V3// 9 66$ 06Y9 1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.18: Power supply supervisor and Section 2.19: Voltage regulator. 2. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. DocID029041 Rev 6 109/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 5.1.7 Current consumption measurement Figure 27. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics, Table 16: Current characteristics, and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 15. Voltage characteristics Symbol VDD-VSS VIN Ratings Min Max - 0.3 4.0 Input voltage on FT pins(3) VSS - 0.3 VDD+4.0 Input voltage on TTa pins VSS - 0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins(4) - 50 External main supply voltage (including VDDA, VDD, VBAT, VDDUSB, VDDDSI (1) and VDDSDMMC)(2) Input voltage on BOOT pin |VDDx| |VSSX -VSS| VESD(HBM) 110/255 Electrostatic discharge voltage (human body model) DocID029041 Rev 6 see Section 5.3.18: Absolute maximum ratings (electrical sensitivity) Unit V mV - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Applicable only for STM32F7x9 sales types. 2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 3. VIN maximum value must always be respected. Refer to Table 16 for the values of the maximum allowed injected current. 4. Include VREF- pin. Table 16. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) IVSS (1) IVDDUSB 420 Total current out of sum of all VSS_x ground lines (sink) -420 Total current into VDDUSB power line (source) 25 IVDDSDMMC Total current into VDDSDMMC power line (source) IVDD IVDDSDMMC IVSS IIO IIO IINJ(PIN) IINJ(PIN)(4) 60 Maximum current into each VDD_x power line (source)(1) 100 Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100 Maximum current out of each VSS_x ground line (sink) (1) -100 Output current sunk by any I/O and control pin 25 Output current sourced by any I/Os and control pin -25 Total output current sunk by sum of all I/O and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 Total output current sunk by sum of all SDMMC I/Os 120 Total output current sourced by sum of all I/Os and control pins except USB I/Os(2) -120 Injected current on FT, FTf, RST and B pins Unit (3) mA -5/+0 Injected current on TTa pins(4) 5 Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of - 5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 65. DocID029041 Rev 6 157/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 65. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0, DSI_D0P, DSI_D0N, DSI_D1P, DSI_D1N, DSI_CKP, DSI_CKN pin -0 0 Injected current on NRST pin -0 NA(1) Injected current on PC0, PC2, PH1_OSCOUT pins -0 NA(1) Injected current on any other FT pin -5 NA(1) Injected current on any other pins -5 +5 Unit mA 1. Injection is not possible. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.20 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 66: I/O static characteristics are derived from tests performed under the conditions summarized in Table 18. All I/Os are CMOS and TTL compliant. Table 66. I/O static characteristics Symbol Parameter FT, TTa and NRST I/O input low level voltage VIL BOOT I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) VIH BOOT I/O input high level voltage FT, TTa and NRST I/O input hysteresis VHYS BOOT I/O input hysteresis 158/255 Conditions Min Typ 1.7 VVDD3.6 V - - 1.75 VVDD 3.6 V, - 40 CTA 105 C - - 1.7 VVDD 3.6 V, 0 CTA 105 C - 1.7 VVDD3.6 V 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C 1.7 VVDD3.6 V Max Unit 0.35VDD - 0.04(1) 0.3VDD(2) V 0.1VDD+0.1(1) 0.45VDD+0.3(1) 0.7VDD(2) - V 0.17VDD+0.7(1) - - 10%VDD(3) - - 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C DocID029041 Rev 6 V 0.1 - - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 66. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max VSS VIN VDD - - 1 VIN = 5 V - - 3 30 40 50 PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) 7 10 14 All pins except for PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) 30 40 50 7 10 14 - 5 - I/O input leakage current Ilkg (4) I/O FT input leakage current (5) RPU RPD CIO(8) Weak pull-up equivalent resistor(6) Weak pulldown equivalent resistor(7) All pins except for PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) A VIN = VSS k VIN = VDD PA10/PB12 (OTG_FS_I D,OTG_HS_ ID) I/O pin capacitance Unit - pF 1. Guaranteed by design. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 65: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 65: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 39. DocID029041 Rev 6 159/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 39. FT I/O input characteristics 9,/9,+9 '' 9 LQ P + 9, W HQ HP LU TX 26 0 & LQ U S LQ G H VW OD PX VL LJQ V 'H Q GR $UHDQRWGHWHUPLQHG % XOD QVLP VLJ Q'H HGR %DV 9'' D[ ,/P 9 WLRQV P 9,+ QV WLR 7H H DV Q LR FW X RG 77/UHTXLUHPHQW 9,+PLQ 9 '' 9 UH 77/UHTXLUHPHQW 9,/PD[ 9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' 9''9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 16). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 16). Output voltage levels Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. All I/Os are CMOS and TTL compliant. 160/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 67. Output voltage characteristics Symbol Parameter Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD - 0.4 - VDD - 0.4 - Output low level voltage for an I/O pin TTL port(2) IIO =+8mA 2.7 V VDD 3.6 V - 0.4 VOH (3) Output high level voltage for an I/O pin except PC14 TTL port(2) IIO =-8mA 2.7 V VDD 3.6 V 2.4 - VOL(1) Output low level voltage for an I/O pin IIO = +20 mA 2.7 V VDD 3.6 V - 1.3(4) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -20 mA VDD -1.3(4) 2.7 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +6 mA 1.8 V VDD 3.6 V VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -6 mA 1.8 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +4 mA 1.7 V VDD 3.6V - 0.4(5) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -4 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOH(3) Output high level voltage for PC14 IIO = -1 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin except PC14 Unit CMOS port(2) IIO = -8 mA 2.7 V VDD 3.6 V V CMOS port(2) VOH(3) VOL (1) Output high level voltage for PC14 IIO = -2 mA 2.7 V VDD 3.6 V V - V 0.4(4) V VDD -0.4(4) - V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 16. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 16 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data. 5. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 40 and Table 68, respectively. DocID029041 Rev 6 161/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Unless otherwise specified, the parameters given in Table 68 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 68. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Maximum frequency (3) 00 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 01 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 10 tf(IO)out/ tr(IO)out 162/255 Output high to low level fall time and output low to high level rise time Conditions Min Typ Max CL = 50 pF, VDD 2.7 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.7 V - - 8 CL = 10 pF, VDD 1.8 V - - 4 CL = 10 pF, VDD 1.7 V - - 3 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 CL = 50 pF, VDD 2.7 V - - 25 CL = 50 pF, VDD 1.8 V - - 12.5 CL = 50 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 50 CL = 10 pF, VDD 1.8 V - - 20 CL = 10 pF, VDD 1.7 V - - 12.5 CL = 50 pF, VDD 2.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 6 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.7 V - - 50(4) CL = 10 pF, VDD 2.7 V - - 100(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 1.8 V - - 50 CL = 10 pF, VDD 1.7 V - - 42.5 CL = 40 pF, VDD 2.7 V - - 6 CL = 10 pF, VDD 2.7 V - - 4 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 1.7 V - - 6 DocID029041 Rev 6 Unit MHz ns MHz ns MHz ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 68. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD 2.7 V - - 100(4) CL = 30 pF, VDD 1.8 V - - 50 CL = 30 pF, VDD 1.7 V - - 42.5 CL = 10 pF, VDD 2.7 V - - 180(4) CL = 10 pF, VDD 1.8 V - - 100 CL = 10 pF, VDD 1.7 V - - 72.5 CL = 30 pF, VDD 2.7 V - - 4 CL = 30 pF, VDD 1.8 V - - 6 CL = 30 pF, VDD 1.7 V - - 7 CL = 10 pF, VDD 2.7 V - - 2.5 CL = 10 pF, VDD 1.8 V - - 3.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller - Unit MHz ns ns 1. Guaranteed by design. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F76xxx and STM32F77xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 40. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 40. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU,2 RXW WI,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH,2$&FKDUDFWHULVWLFV DocID029041 Rev 6 DLG 163/255 220 Electrical characteristics 5.3.21 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 66: I/O static characteristics). Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 69. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VF(NRST) (2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 41. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 69. Otherwise the reset is not taken into account by the device. 164/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.22 Electrical characteristics TIM timer characteristics The parameters given in Table 70 are guaranteed by design. Refer to Section 5.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 70. TIMx characteristics(1)(2) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 216 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 100 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 216 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. 5.3.23 RTC characteristics Table 71. RTC characteristics 5.3.24 Symbol Parameter Conditions - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register Min Max 4 - 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 72 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 18. Table 72. ADC characteristics Symbol VDDA VREF+ fADC Parameter Power supply Positive reference voltage ADC clock frequency Conditions VDDA -VREF+ < 1.2 V VDDA = 1.7(1) to 2.4 V VDDA = 2.4 to 3.6 V DocID029041 Rev 6 Min Typ Max Unit 1.7(1) - 3.6 V 1.7(1) - VDDA V 0.6 15 18 MHz 0.6 30 36 MHz 165/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 72. ADC characteristics (continued) Symbol fTRIG(2) VAIN RAIN(2) Parameter External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 k - 1.5 - 6 k - - 4 7 pF - - 0.100 s 1/fADC tlat(2) Injection trigger conversion latency fADC = 30 MHz - - - 3(5) tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 s - - - 2(5) 1/fADC tS(2) Sampling time fADC = 30 MHz 0.100 - 16 s - 3 - 480 1/fADC tSTAB(2) Power-up time - - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s tCONV(2) Total conversion time (including sampling time) 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(2) 166/255 (fADC = 36 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2.4 Msps 12-bit resolution Interleave Dual ADC mode - - 4.5 Msps 12-bit resolution Interleave Triple ADC mode - - 7.2 Msps DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 72. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 72. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 73. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(1) 3 4 2 3 1 3 1 2 2 3 Unit LSB 1. Guaranteed by characterization results. Table 74. ADC static accuracy at fADC = 30 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA -VREF < 1.2 V Typ Max(1) 2 5 1.5 2.5 1.5 4 1 2 1.5 3 Unit LSB 1. Guaranteed by characterization results. DocID029041 Rev 6 167/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 75. ADC static accuracy at fADC = 36 MHz Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(1) 4 7 2 3 3 6 2 3 3 6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - 67 - 72 - dB 1. Guaranteed by characterization results. Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - 70 - 72 - dB 1. Guaranteed by characterization results. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.20 does not affect the ADC accuracy. 168/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 42. ADC accuracy characteristics 6 $$! 6 2%& ;,3" )$%!, ORDEPENDINGONPACKAGE= %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AIC 1. See also Table 74. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 43. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 72 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DocID029041 Rev 6 169/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() )Q) 9''$ )Q) 966$95() DLE 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF- s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$ )Q) 95()966$ DLF 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF- s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. 170/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.25 Electrical characteristics Temperature sensor characteristics Table 78. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 - mV/C Voltage at 25 C - 0.76 - V tSTART(2) Startup time - 6 10 s TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 10 - - s TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 79. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FF0 F44C - 0x1FF0 F44D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FF0 F44E - 0x1FF0 F44F 5.3.26 VBAT monitoring characteristics Table 80. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - K Q Ratio on VBAT measurement - 4 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s Er(1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 5.3.27 Reference voltage The parameters given in Table 81 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 81. internal reference voltage Symbol VREFINT TS_vrefint(1) VREFINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V - 10 - - s VDD = 3V 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range DocID029041 Rev 6 171/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 81. internal reference voltage (continued) Symbol Parameter TCoeff(2) tSTART (2) Conditions Min Typ Max Unit Temperature coefficient - - 30 50 ppm/C Startup time - - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 82. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 5.3.28 Memory address Raw data acquired at temperature of 30 C VDDA = 3.3 V 0x1FF0 F44A - 0x1FF0 F44B DAC electrical characteristics Table 83. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.7(1) - 3.6 V VREF+ Reference supply voltage 1.7(1) - 3.6 V VSSA Ground 0 - 0 V - 5 - k - 25 - - Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum k resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Capacitive load - - 50 pF DAC_OUT Lower DAC_OUT voltage with buffer ON min(2) 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA - 0.2 V DAC_OUT Lower DAC_OUT voltage with buffer OFF min(2) - 0.5 - mV - VREF+ - 1LSB V RLOAD (2) RO(2) CLOAD(2) Connected to Resistive load VSSA with buffer ON Connected to VDDA DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) 172/255 - DocID029041 Rev 6 VREF+ VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 83. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit A Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 A With no load, middle code (0x800) on the inputs - 475 625 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - 0.5 LSB Given for the DAC in 10-bit configuration. - - 2 LSB Given for the DAC in 12-bit configuration. - - 1 LSB Given for the DAC in 10-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - 4 LSB Given for the DAC in 12-bit configuration. - - 10 mV Given for the DAC in 12-bit configuration Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration - 3 6 s CLOAD 50 pF, RLOAD 5 k IDDA(4) DNL(4) Gain error(4) DAC DC VDDA current consumption in quiescent mode(3) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the (4) tSETTLING highest input codes when DAC_OUT reaches final value 4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD 50 pF, RLOAD 5 k Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD 50 pF, RLOAD 5 k DocID029041 Rev 6 173/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 83. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - -67 -40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 46. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.29 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s. * Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0410 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below: 174/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 84. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 16 Analog filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: * The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. * The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: Tr(SDA/SCL)=0.8473xRpxCload Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 5.3.20: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 85 for the analog filter characteristics: Table 85. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 70(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. DocID029041 Rev 6 175/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 86 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 86. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode SPI1,4,5,6 2.7VDD3.6 54(2) Master mode SPI1,4,5,6 1.71VDD3.6 27 Master transmitter mode SPI1,4,5,6 1.71VDD3.6 54 Slave receiver mode SPI1,4,5,6 1.71VDD3.6 54 - - MHz Slave mode transmitter/full duplex SPI1,4,5,6 2.7VDD3.6 50(3) Slave mode transmitter/full duplex SPI1,4,5,6 1.71VDD3.6 37(3) Master & Slave mode SPI2,3 1.71VDD3.6 27 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*TPLCK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*TPLCK - - tw(SCKH) tw(SCKL) SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2 176/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 86. SPI dynamic characteristics(1) (continued) Symbol Conditions Min Typ Max Master mode 4 9(4) - - tsu(SI) Slave mode 4.5 - - th(MI) Master mode 3 0(4) - - Slave mode 2 - - tsu(MI) Parameter Data input setup time Data input hold time th(SI) ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 Slave mode 2.7VDD3.6V - 6.5 10 Slave mode 1.71VDD3.6V - 6.5 13.5 tv(MO) Master mode - 2 6 th(SO) Slave mode 1.71VDD3.6V 4.5 - - Master mode 0 - - tv(SO) Data output valid time Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz. 3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. 4. Only for SPI6. Figure 47. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. 6&.LQSXW WVX166 WK166 WZ6&.+ WU6&. &3+$ &32/ &3+$ &32/ WD62 WZ6&./ WY62 )LUVWELW287 0,62RXWSXW WK62 1H[WELWV287 WI6&. WGLV62 /DVWELW287 WK6, WVX6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 DocID029041 Rev 6 177/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 6&.LQSXW &3+$ &32/ &3+$ &32/ WY62 WK62 )LUVWELW287 0,62RXWSXW WVX6, WU6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 49. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 178/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 87 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 87. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256xFs(2) MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs 30 70 DCK I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 5 - th(WS) WS hold time Slave mode 2 - Master receiver 2.5 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) - 12 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. The maximum value of 256xFs is 49.152 MHz (APB1 maximum frequency). Note: Refer to RM0410 reference manual I2S section for more details about the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID029041 Rev 6 179/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 50. I2S slave timing diagram (Philips protocol)(1) &.,QSXW WF&. &32/ &32/ WZ&.+ WK:6 WZ&./ :6LQSXW WY6'B67 WVX:6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW %LWQWUDQVPLW WVX6'B65 /6%UHFHLYH 6'UHFHLYH WK6'B67 /6%WUDQVPLW WK6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 069 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 51. I2S master timing diagram (Philips protocol)(1) WI&. WU&. &.RXWSXW WF&. &32/ WZ&.+ &32/ WY:6 WK:6 WZ&./ :6RXWSXW WY6'B07 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW 6'UHFHLYH /6%WUDQVPLW WK6'B05 WVX6'B05 /6%UHFHLYH %LWQWUDQVPLW WK6'B07 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 069 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 180/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics JATG/SWD characteristics Unless otherwise specified, the parameters given in Table 88 for JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C=30 pF * Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 88. Dynamics characteristics: JTAG characteristics Symbol Parameter Fpp 1/tc(TCK) Conditions Min Typ Max 2.7V @ WVX5;' WVX&56 WLK5;' WLK&56 50,,B5;'>@ 50,,B&56B'9 DLE DocID029041 Rev 6 189/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 98. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 2 - - tsu(CRS) Carrier sense setup time 2 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 7.5 8 12 td(TXD) Transmit data valid delay time 7 7.5 12.5 Unit ns 1. Guaranteed by characterization results. Table 99 gives the list of Ethernet MAC signals for MII and Figure 59 shows the corresponding timing diagram. Figure 60. Ethernet MII timing diagram 0,,B5;B&/. WVX5;' WVX(5 WVX'9 WLK5;' WLK(5 WLK'9 0,,B5;'>@ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG7;(1 WG7;' 0,,B7;B(1 0,,B7;'>@ AIB Table 99. Dynamics characteristics: Ethernet MAC signals for MII(1) 190/255 Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 2.5 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 0.5 - - tsu(ER) Error setup time 2.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 10 8 13 td(TXD) Transmit data valid delay time 9 7.5 13 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by characterization results. Table 100. MDIO Slave timing parameters Symbol Min Typ Max Unit Management Data clock - - 40 MHz td(MDIO) Management Data input/output output valid time 7 8 20 tsu(MDIO) Management Data input/output setup time 4 - - th(MDIO) Management Data input/output hold time 1 - - FsDC Parameter ns The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: FPCLK2 1.5 * FMDC Figure 61. MDIO Slave timing diagram W0'& WG0',2 WVX0',2 WK0',2 06Y9 CAN (controller area network) interface Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 5.3.30 FMC characteristics Unless otherwise specified, the parameters given in Table 101 to Table 114 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD DocID029041 Rev 6 191/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 62 through Figure 65 represent asynchronous waveforms and Table 101 through Table 108 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * Capcitive load CL = 30 pF In all timing tables, the THCLK is the HCLK clock period Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 192/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK - 1 2 THCLK +1 0 0.5 2THCLK - 1 2THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time THCLK - 1 - tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK - 1 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - THCLK + 1 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 102. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1) Symbol Min Max FMC_NE low time 7THCLK +1 7THCLK +1 FMC_NWE low time 5THCLK -1 5THCLK +1 FMC_NWAIT low time THCLK -0.5 - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - tw(NE) tw(NOE) tw(NWAIT) Parameter Unit ns 1. Guaranteed by characterization results. DocID029041 Rev 6 193/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6 TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK - 1 3THCLK + 1 FMC_NEx low to FMC_NWE low THCLK - 1 THCLK + 0.5 THCLK - 1.5 THCLK + 0.5 THCLK - - 0 THCLK - 0.5 - - 0.5 THCLK - 0.5 - FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - THCLK + 1 tw(NADV) 1. Guaranteed by characterization results. 194/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) Min Max Unit 8THCLK - 1 8THCLK + 1 6THCLK - 1.5 6THCLK + 0.5 FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK - 1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK + 2 - ns 1. Guaranteed by characterization results. Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &-#? !$;= TSU$ATA?./% TH$ATA?./% $ATA !DDRESS TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 DocID029041 Rev 6 195/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 105. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3THCLK - 1 3THCLK + 1 2THCLK 2THCLK + 0.5 THCLK - 1 THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time THCLK - 0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) THCLK + 0.5 - th(A_NOE) Address hold time after FMC_NOE high THCLK - 0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NE) Data to FMC_NEx high setup time THCLK - 1 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK - 1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 106. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol tw(NE) tw(NOE) Parameter FMC_NE low time FMC_NWE low time Max 8THCLK - 1 8THCLK + 1 5THCLK - 1.5 5THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK + 1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid - 1. Guaranteed by characterization results. 196/255 Min DocID029041 Rev 6 4THCLK+ 1 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms TW.% &-#? .%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?.7% &-#? .",;= .", T V!?.% &-#? !$;= T V$ATA?.!$6 !DDRESS TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 107. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) Parameter Min Max Unit FMC_NE low time 4THCLK - 1 4THCLK + 1 FMC_NEx low to FMC_NWE low THCLK - 1 THCLK + 0.5 FMC_NWE low time 2THCLK - 0.5 2THCLK+ 0.5 FMC_NWE high to FMC_NE high hold time THCLK - 0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 THCLK THCLK+ 1 FMC_AD(adress) valid hold time after FMC_NADV high) THCLK - 0.5 - th(A_NWE) Address hold time after FMC_NWE high THCLK + 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK - 0.5 - tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FMC_NADV low time tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK + 0.5 - DocID029041 Rev 6 ns 197/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time Min Max 9THCLK - 1 9THCLK + 1 Unit 7THCLK - 0.5 7THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK - 1 - 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 66 through Figure 69 represent synchronous waveforms and Table 109 through Table 112 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable; * MemoryType = FMC_MemoryType_CRAM; * WriteBurst = FMC_WriteBurst_Enable; * CLKDivision = 1; * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM * CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all the timing tables, the THCLK is the HCLK clock period. - For 2.7 VVDD3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at CL=30 pF (on FMC_CLK). - 198/255 For 1.71 VVDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK). DocID029041 Rev 6 ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 66. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, &-#?.%X T D#,+, .!$6, TD#,+( .%X( TD#,+, .!$6( &-#?.!$6 TD#,+, !6 TD#,+( !)6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% T D#,+, !$6 &-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 TH#,+( .7!)46 TH#,+( .7!)46 -36 DocID029041 Rev 6 199/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 109. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1. td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK - 0.5 - tw(CLK) td(CLKL-NExL) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 200/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 67. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+( .%X( &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+( .7%( TD#,+, .7%, &-#?.7% TD#,+, !$)6 TD#,+, !$6 &-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( &-#?.", -36 DocID029041 Rev 6 201/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 110. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 .5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 0.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 202/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &-#?$;= TH#,+( $6 $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B $ TH#,+( .7!)46 TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 TH#,+( .7!)46 -36 Table 111. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) t(CLKL-NExL) td(CLKH-NExH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high DocID029041 Rev 6 Unit ns 203/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Figure 69. Synchronous non-multiplexed PSRAM write timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, .7%, TD#,+( .7%( &-#?.7% TD#,+, $ATA TD#,+, $ATA $ &-#?$;= $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TD#,+( .",( TH#,+( .7!)46 &-#?.", -36 204/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 112. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 1 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 1 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. NAND controller waveforms and timings Figure 70 through Figure 73 represent synchronous waveforms, and Table 113 and Table 114 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x01; * COM.FMC_WaitSetupTime = 0x03; * COM.FMC_HoldSetupTime = 0x02; * COM.FMC_HiZSetupTime = 0x01; * ATT.FMC_SetupTime = 0x01; * ATT.FMC_WaitSetupTime = 0x03; * ATT.FMC_HoldSetupTime = 0x02; * ATT.FMC_HiZSetupTime = 0x01; * Bank = FMC_Bank_NAND; * MemoryDataWidth = FMC_MemoryDataWidth_16b; * ECC = FMC_ECC_Enable; * ECCPageSize = FMC_ECCPageSize_512Bytes; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID029041 Rev 6 205/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 70. NAND controller waveforms for read access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% TD!,% ./% TH./% !,% &-#?./%.2% TSU$ ./% TH./% $ &-#?$;= -36 Figure 71. NAND controller waveforms for write access &-#?.#%X !,%&-#?! #,%&-#?! TH.7% !,% TD!,% .7% &-#?.7% &-#?./%.2% TV.7% $ TH.7% $ &-#?$;= -36 206/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 72. NAND controller waveforms for common memory read access &-#?.#%X !,%&-#?! #,%&-#?! TH./% !,% TD!,% ./% &-#?.7% TW./% &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 Figure 73. NAND controller waveforms for common memory write access &-#?.#%X !,%&-#?! #,%&-#?! TD!,% ./% TW.7% TH./% !,% &-#?.7% &-#?. /% TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 Table 113. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max Unit 4THCLK - 0.5 4THCLK + 0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK + 1 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4THCLK - 2 - ns 1. Guaranteed by characterization results. DocID029041 Rev 6 207/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 114. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter Min Max Unit 4THCLK - 0.5 4THCLK + 0.5 FMC_NWE low width tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2THCLK - 1 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK - 1 - - 3THCLK + 1 2THCLK - 2 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid ns 1. Guaranteed by characterization results. SDRAM waveforms and timings * CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. - For 3.0 VVDD3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on FMC_SDCLK). - For 2.7 VVDD3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). - For 1.71 VVDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK). Figure 74. SDRAM read access waveforms (CL = 1) &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TD3$#,+,?.2!3 TH3$#,+,?.2!3 &-#?3$.2!3 TH3$#,+,?.#!3 TD3$#,+,?.#!3 &-#?3$.#!3 &-#?3$.7% TSU3$#,+(?$ATA &-#?$;= TH3$#,+(?$ATA $ATA $ATA $ATAI $ATAN -36 208/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 115. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 tsu(SDCLKH _Data) Data input setup time 1.5 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Table 116. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 tsu(SDCLKH_Data) Data input setup time 0 - th(SDCLKH_Data) Data input hold time 4.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. DocID029041 Rev 6 209/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 75. SDRAM write access waveforms &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TH3$#,+,?.2!3 TD3$#,+,?.2!3 &-#?3$.2!3 TD3$#,+,?.#!3 TH3$#,+,?.#!3 TD3$#,+,?.7% TH3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD3$#,+,?$ATA $ATA &-#?$;= $ATA $ATAI $ATAN TH3$#,+,?$ATA TD3$#,+,?.", &-#?.",;= -36 Table 117. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - 1. Guaranteed by characterization results. 210/255 DocID029041 Rev 6 Unit ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 118. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. 5.3.31 Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 119 and Table 120 for Quad-SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 18: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 20 pF * Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics. Table 119. Quad-SPI characteristics in SDR mode(1) Symbol Fck1/t(CK) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 VVDD<3.6 V CL=20 pF - - 108 1.71 V@ 069 5.3.33 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 122 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 18, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity: low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits Table 122. LTDC characteristics (1) Symbol Parameter Min Max Unit fCLK LTDC clock output frequency - 83 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH), tw(CLKL) Clock High time, low time tv(DATA) Data output valid time - 6 th(DATA) Data output hold time 0 ns tv(HSYNC), tv(VSYNC), tv(DE) HSYNC/VSYNC/DE output valid time - 3.5 th(HSYNC), th(VSYNC), th(DE) HSYNC/VSYNC/DE output hold time 0.5 - 1. Guaranteed by characterization results. 214/255 tw(CLK)/2-0.5 tw(CLK)/2+0.5 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 79. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY+6<1& WY+6<1& /&'B+6<1& WK'( WY'( /&'B'( WY'$7$ /&'B5>@ /&'B*>@ /&'B%>@ 1JYFM 1JYFM 1JYFM / WK'$7$ +6<1& +RUL]RQWDO ZLGWK EDFNSRUFK $FWLYHZLGWK +RUL]RQWDO EDFNSRUFK 2QHOLQH 069 Figure 80. LCD-TFT vertical timing diagram W&/. /&'B&/. WY96<1& WY96<1& /&'B96<1& /&'B5>@ /&'B*>@ /&'B%>@ -LINESDATA 96<1& 9HUWLFDO ZLGWK EDFNSRUFK $FWLYHZLGWK 9HUWLFDO EDFNSRUFK 2QHIUDPH 069 DocID029041 Rev 6 215/255 220 Electrical characteristics 5.3.34 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 123 for DFSDM are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30pF * Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for DFSDM1). Table 123. DFSDM measured timing 1.71-3.6V Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) fCKIN (1/TCKIN) Input clock frequency fCKOUT Output clock frequency 1.71 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.71 < VDD < 3.6 V 45 50 55 216/255 DocID029041 Rev 6 Unit MHz % STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 123. DFSDM measured timing 1.71-3.6V (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V 2 - - Unit ns th Data input hold time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V 3 - - TManchester Manchester data period (recovered clock period) Manchester mode (SITP[1:0]=2,3), Internal clock mode (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V (CKOUTDIV+1) * TDFSDMCLK - (2*CKOUTDIV) * TDFSDMCLK DocID029041 Rev 6 217/255 220 Electrical characteristics 5.3.35 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DFSDM timing diagrams ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63,WLPLQJ63,&.6(/ 63,WLPLQJ63,&.6(/ Figure 81. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD 069 218/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.36 Electrical characteristics SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 124 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Figure 82. SDIO high-speed mode Figure 83. SD default mode DocID029041 Rev 6 219/255 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 124. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50 MHz 3.5 - - tIH Input hold time HS fpp =50 MHz 2.5 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =50 MHz - 11 12 tOH Output hold time HS fpp =50 MHz 9 - - ns CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25 MHz 3.5 - - tIHD Input hold time SD fpp =25 MHz 2.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 0.5 1.5 tOHD Output hold default time SD fpp =25 MHz 0 - - ns 1. Guaranteed by characterization results. Table 125. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fpp =50 MHz 3 - - tIH Input hold time HS fpp =50 MHz 4 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS fpp =50 MHz - 11 15.5 tOH Output hold time HS fpp =50 MHz 9.5 - - 1. Guaranteed by characterization results. 2. Cload = 20 pF. 220/255 DocID029041 Rev 6 ns STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. LQFP100 14x 14 mm, low-profile quad flat package information Figure 84. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline MM C ! ! 3%!4).'0,!.% # ! '!5'%0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B 6.1 E ,?-%?6 1. Drawing is not to scale. DocID029041 Rev 6 221/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 126. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 222/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 85. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint AIC 1. Dimensions are expressed in millimeters. DocID029041 Rev 6 223/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP100 device making The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 86. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 7*5 5HYLVLRQFRGH 3 'DWHFRGH : 88 3LQLGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 224/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 87. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $EDOO LQGH[ $EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) * ( $ % & ' ( ) * + . ( 6.2 Package information H $ %277209,(: E %$//6 HHH & $ % III & 7239,(: $4B0(B9 1. Drawing is not to scale. Table 127. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 DocID029041 Rev 6 225/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 127. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 88. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint 'SDG 'VP 1. Dimensions are expressed in millimeters. 226/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm TFBGA100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 89. TFBGA100, 8 x 8 x 0.8mm thin fine-pitch ball grid array package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 7*) 5HYLVLRQFRGH 3 'DWHFRGH %DOO$ LGHQWLILHU : 88 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 227/255 254 Package information 6.3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP144 20 x 20 mm, low-profile quad flat package information Figure 90. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'%0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 228/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 229/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 91. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. 230/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP144 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 92. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 3 45.';*5 : 88 3LQ LGHQWLILHU 'DWHFRGH -36 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 231/255 254 Package information 6.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP176 24 x 24 mm, low-profile quad flat package information Figure 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline C ! ! ! # 3EATINGPLANE MM GAUGEPLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. 232/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 C 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0200 - 1.0276 HE 25.900 - 26.100 1.0200 - 1.0276 L 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - ZD - 1.250 - - 0.0492 - ZE - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k 0 - 7 0 - 7 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 233/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 94. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. 234/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP176 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example 3URGXFWLGHQWLILFDWLRQ 45.'**5 5HYLVLRQFRGH : 88 'DWHFRGH 3 3LQ LGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 235/255 254 Package information 6.5 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP208 28 x 28 mm low-profile quad flat package information Figure 96. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*(3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. 236/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 -- - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.1024 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1732 1.1811 1.1890 E1 27.800 28.000 28.200 1.0945 1.1024 1.1102 E3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID029041 Rev 6 237/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 97. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint -36 1. Dimensions are expressed in millimeters. 238/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP208 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 98. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 45.'#*5 3LQ LGHQWLILHU 'DWHFRGH \HDUZHHN <:: 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 239/255 254 Package information 6.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information Figure 99. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline H ' ) $%$// /2&$7,21 * '(7$,/$ H ( $ 25,(17$7,21 5()(5(1&( H $ H 7239,(: $ $ %277209,(: 6,'(9,(: %803 6($7,1*3/$1( '(7$,/$ 527$7('R $*B:/&63B0(B9 1. Drawing is not to scale. 240/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 - 0.025 - - 0.0010 - (2) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 5.502 5.537 5.572 0.2166 0.2180 0.2194 E 6.060 6.095 6.130 0.2386 0.2400 0.2413 e - 0.400 - - 0.0157 - e1 - 4.800 - - 0.1890 - e2 - 5.200 - - 0.2047 - F - 0.368 - - 0.0145 - G - 0.477 - - 0.0188 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - b 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. DocID029041 Rev 6 241/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 100. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP $*B:/&63B)3B9 1. Dimensions are expressed in millimeters. Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) 242/255 Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.1 mm DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information WLCSP180 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 101. WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example 3URGXFWLGHQWLILFDWLRQ 45.'"*: 5HYLVLRQFRGH 'DWHFRGH : 88 3 %DOO$ LGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 243/255 254 Package information 6.7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information Figure 102. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ $EDOO LGHQWLILHU $EDOO LQGH[ DUHD $ & & Z KddKDs/t EEDOOV dKWs/t HHH 0 & $ III 0 & Ds 1. Drawing is not to scale. Table 134. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3917 0.3937 0.3957 E 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 244/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 103. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP &Ws Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID029041 Rev 6 245/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA 176+25 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 104. UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) ,,. 'DWHFRGH %DOO$ LQGHQWLILHU < :: 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 246/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6.8 Package information TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information Figure 105. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ ' H ; $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ' $ * ( ( H < 5 EEDOOV HHH 0 = < ; III 0 = %277209,(: 7239,(: $/B0(B9 1. Drawing is not to scale. Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 12.850 13.000 13.150 0.5118 0.5118 0.5177 D1 - 11.200 - - 0.4409 - E 12.850 13.000 13.150 0.5118 0.5118 0.5177 E1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - F - 0.900 - - 0.0354 - DocID029041 Rev 6 247/255 254 Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 136. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max G - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 106. TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array package recommended footprint 'SDG 'VP $/B)3B9 Table 137. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA) Dimension 248/255 Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information TFBGA216 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 107. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package top view example 3URGXFWLGHQWLILFDWLRQ 45.' 5HYLVLRQFRGH /*) 3 %DOO$ LGHQWLILHU 'DWHFRGH : 88 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID029041 Rev 6 249/255 254 Package information 6.9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 138. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm / 0.8 mm pitch 36.2 Thermal resistance junction-ambient WLCSP180 - 0.4 mm pitch 30 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm / 0.5 mm pitch 19 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.5 mm pitch 39 Thermal resistance junction-ambient TFBGA216 - 13 x 13 mm / 0.8 mm pitch 29 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 250/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 7 Ordering information Ordering information Table 139. Ordering information scheme Example: STM32 F 76x V G T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 765= STM32F765xx, USB OTG FS/HS, camera interface, Ethernet 767= STM32F767xx, USB OTG FS/HS, camera interface, Ethernet, LCD-TFT 768 = STM32F768Ax, USB OTG FS/HS, camera interface, DSI host, WLCSP with internal regulator OFF 769= STM32F769xx, USB OTG FS/HS, camera interface, Ethernet, DSI host Pin count V = 100 pins Z = 144 pins I = 176 pins A = 180 pins B = 208 pins N = 216 pins Flash memory size G = 1024 Kbytes of Flash memory I = 2048 Kbytes of Flash memory Package T = LQFP K = UFBGA H = TFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DocID029041 Rev 6 251/255 254 Recommendations when using internal reset OFF Appendix A STM32F765xx STM32F767xx STM32F768Ax Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD * The over-drive mode is not supported Operating conditions Table 140. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz Maximum Flash memory access frequency with wait states (1)(2) 168 MHz with 8 wait states and over-drive OFF I/O operation Possible Flash memory operations 8-bit erase and - No I/O program compensation operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from the Flash memory since the ART accelerator or L1cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 2.18.1: Internal reset ON). 252/255 DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Revision history Revision history Table 141. Document revision history Date Revision 21-Mar-2016 1 Initial release. 2 DFSDM replaced by DFSDM1 in: - Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. - Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping. - Table 14: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses. - Section 5.3.34: Digital filter for Sigma-Delta Modulators (DFSDM) characteristics. Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts adding DFSDM1 features. Updated Table 40: Peripheral current consumption adding DFSDM1 current consumption. Updated cover in 2 pages. Update cover replacing for SPI `up to 50 Mbit/s' by `up to 54 Mbit/s'. 3 Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts GPIO number. Updated Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping adding CAN3_RX alternate function on PA8/AF11. 4 Updated Table 98: Dynamics characteristics: Ethernet MAC signals for RMII. Updated Table 72: ADC characteristics sampling rate. Updated all the notes removing `not tested in production'. Updated Figure 47: SPI timing diagram - slave mode and CPHA = 0 and Figure 48: SPI timing diagram - slave mode and CPHA = 1(1) with modified NSS timing waveforms (among other changes). Updated Table 122: LTDC characteristics clock output frequency at 65 MHz. Updated Section 5.2: Absolute maximum ratings. Updated Section 6: Package information adding information about other optional marking or inset/upset marks. 26-Apr-2016 06-May-2016 22-Dec-2016 Changes DocID029041 Rev 6 253/255 254 Revision history STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 141. Document revision history (continued) Date 09-Aug-2017 11-Sep-2017 254/255 Revision Changes 5 Updated note 1 below all the package device marking figures. Updated cover title. Updated Section 1: Description. Updated Section 2.47: DSI Host (DSIHOST) video mode interface features. Added Table 9: DFSDM implementation. Updated Figure 11: STM32F76xxx LQFP100 pinout pin 43 and pin 44. Updated Table 65: I/O current injection susceptibility note by `injection is not possible'. Updated Table 122: LTDC characteristics LTDC clock frequency at 83 MHz. Updated Table 72: ADC characteristics RADC min at 1.5 Kohm. Updated Figure 41: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Table 83: DAC characteristics RLOAD feature. 6 Added TFBGA100 package: - Updated cover page. - Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts. - Updated Table 4: Regulator ON/OFF and internal reset ON/OFF availability. - Added Figure 12: STM32F76xxx TFBGA100 pinout. - Updated Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. - Updated Table 18: General operating conditions. - Updated Table 63: ESD absolute maximum ratings. - Updated note below Figure 44: Power supply and reference decoupling (VREF+ not connected to VDDA). - Updated note below Figure 45: Power supply and reference decoupling (VREF+ connected to VDDA). - Added Section 6.2: TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information. - Updated Table 138: Package thermal characteristics. DocID029041 Rev 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID029041 Rev 6 255/255 255