Features
•Ballast control and half-bridge driver in one IC
•Transformer-less lamp power sensing
•Closed-loop lamp power control
•Closed-loop preheat current control
•Programmable preheat time
•Programmable preheat current
•Lamp ignition detection
•Programmable ignition-to-dim time
•0.5 to 5VDC dimming control input
•Min and max lamp power adjustments
•Programmable minimum frequency
•Internal current sense blanking
Data Sheet No. PD60194_A
DIMMING BALLAST CONTROL IC
Typical Connection
Description
Description: The IR21592/IR21593 are complete dimming ballast controllers and 600V
half-bridge drivers all in one IC. The architecture includes phase control for trans-
former-less lamp power sensing and regulation which minimizes changes needed to
adapt non-dimming ballasts for dimming. Externally programmable features such as
preheat time and current, ignition-to-dim time, and a complete dimming interface with
minimum and maximum settings provide a high degree of flexibility for the ballast
design engineer. Protection from failure of a lamp to strike, filament failures, thermal
overload, or lamp failure during normal operation, as well as an automatic restart
function, have been included in the design. The heart of this control IC is a voltage-
controlled oscillator with externally programmable minimum frequency. The IR21592/
IR21593 are available in both 16 pin DIP and 16 pin narrow body SOIC packages.
16
15
14
134
3
2
1
5
6
7
11
10
8 9
12
VDC
VCO
IPH
FMIN
MIN
MAX
DIM
CPH
CS
LO
COM
VCC
VB
VS
HO
SD
+ DC Bus
+ Rectified AC Line
- DC Bus
RMIN
CPH
CVCO
RCS
RMAX
RFMIN
RIPH
0.5 to 5VDC RDIM
CVDC
RVDC
RVAC RPULL-UP
Single Lamp Dimmable
Packages
16 Lead PDIP
16 Lead SOIC
(narrow body)
Parameter IR21592 IR21593
Deadtime 1.8us 1.0us
Frequen cy
Range See
Graph 11 See
Graph 12
www.irf.com 1
IR21592(S)
IR21593(S)
•Full lamp fault protection
•Brown-out protection
•Automatic restart
•Micro-power startup
•Zener clamped Vcc
•Over-temperature protection
•16-pin DIP and SOIC package types
IR21592/IR21593(S)
2www.irf.com
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage -0.3 625
VSHigh side floating supply offset voltage VB - 25 VB + 25
VHO High side floating output voltage VS - 0.3 VB + 0.3
VLO Low side output voltage -0.3 VCC + 0.3
IOMAX Maximum allowable output current (either output) -500 500
due to external power transistor miller effect
VVCO Voltage controlled oscillator input voltage -0.3 6.0 V
ICPH CPH current - 5 5 mA
VIPH IPH voltage -0.3 5.5
VDIM Dimming control pin input voltage -0.3 5.5
VMAX Maximum lamp power setting pin input voltage -0.3 5.5
VMIN Minimum lamp power setting pin input voltage -0.3 5.5
VCS Current sense input voltage -0.3 5.5
ISD Shutdown pin current -5 5
ICC Supply current (note 1) — 25
dV/dt Allowable offset voltage slew rate - 50 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (16 pin DIP) — 1.60
PD = (TJMAX-TA)/RthJA (16 pin SOIC) — 1.25
RthJA Thermal resistance, junction to ambient (16 pin DIP) — 7 5
(16 pin SOIC) — 1 15
TJJunction temperature -55 15 0
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 300
V
mA
V
mA
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown
voltage of 15.6V (VCLAMP). Please note that this supply pin should not be driven by a DC, low impedance
power source greater than the diode clamp voltage (VCLAMP) as specified in the Electrical Characteristics
section.
W
oC
oC/W
IR21592/IR21593(S)
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Note 2: Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead
regulating its voltage, VCLAMP.
Note 3: The MAX lead is a voltage-controlled current source. For optimum dim interface current mirror performance,
this current should be kept between 0 and 750µA.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol Definition Min. Max. Units
VBS High side floating supply voltage VCC - 0.7 V CLAMP
VSSteady state high side floating supply offset voltage -1 6 00
VCC Supply voltage VCCUV+ VCLAMP (15.6)
ICC Supply current note 2 1 0 mA
VVCO VCO pin voltage 05
VDIM DIM pin voltage 0.5 5.0
VMAX MAX pin current (note 3) -750 0 µA
VMIN MIN pin voltage 1 3
VBSMIN Minimum required VBS voltage for proper HO functionality —
5
RFMIN Minimum frequency setting resistance 10 100 kΩ
ISD Shutdown pin current -1 1
ICS Current sensing pin current -1 1
TJJunction temperature -40 125 oC
V
V
mA
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k,
RMIN = 56k, VCPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified.
Supply Characteristics
VCCUV+ VCC supply undervoltage positive going 12.0 12.5 13.0
threshold
VCCHYS VCC supply undervoltage lockout hysteresis 1.5 1.6 1.7
IQCCUV UVLO mode quiescent current 70 200 330 VCC = 10V
IQCCFLT Fault-mode quiescent current — 240 — SD=5V, CS=2V, or
Tj > TSD
ICCFMIN VCC supply current @ FMIN (IR21592) — 5.6 — VVCO = 0V
ICCFMAX VCC supply current @ FMAX (IR21592) — 6.0 — VVCO = 5V
ICCFMIN VCC supply current @ FMIN (IR21593) — 5.4 — VVCO = 0V
ICCFMAX VCC supply current @ FMAX (IR21593) — 6.8 — VVCO = 5V
VCLAMP VCC zener shunt clamp voltage 14.5 15.6 16.5 V ICC = 10mA
Symbol Definition Min. Typ. Max. Units Test Conditions
µA
V
mA
V
IR21592/IR21593(S)
4www.irf.com
Electrical Characteristics (cont.)
VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k,
RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
Floating Supply Characteristics
IBSFMIN VBS supply current (low freq.) — 0 — VVCO = 0V
IBSFMAX VBS supply current (high freq.) — 30 — V VCO = 5V
ILK Offset supply leakage current — — 50 VB = VS = 600V
µA
Oscillator I/O Characteristics
fvco VCO frequency range (IR21592) 15 18 22 VVCO=0V, RFMIN=40KΩ
(See graph 11) 73 95 108 VVCO=5V, RFMIN=40KΩ
fvco VCO frequency range (IR21593) — 30 — VVCO=0V, RFMIN=40KΩ
(See graph 12) — 230 — VVCO=5V, RFMIN=40KΩ
d Gate drive outputs duty cycle — 50 —% V
VCO = 2.5V
VVCOFLT Fault-mode VCO pin voltage (UVLO, — 5—
V
shutdown, over-current/temp.)
IVCOPH Preheat mode VCO pin discharge current — 1.0 — VCPH=2.5V, VIPH=0.5V
IVCODIM Dim mode VCO pin discharge current — 16.0 — VVCO=2.5V, VCPH=5.5V,
VIPH=0.5V, 1V Pulse at
CS
µA
kHz
t r Turn-on rise time 48.5 120 180
tf Turn-off fall time 24.25 65 145
Gate Driver Output Characteristics
ns
IVCOPK Amplitude control VCO pin charging current — 60 — µA VCPH=0V, VCS =1V,
VIPH=0.5V, VVCO=2.5V
tDTLO LO output deadtime (IR21592) — 1.8 —
tDTHO HO output deadtime (IR21592) — 1.8 —
tDTLO LO output deadtime (IR21593) — 1.0 —
tDTHO HO output deadtime (IR21593) — 1.0 —
µsVVCO=0V, VMIN=1.5V,
VIPH=0.5V
IR21592/IR21593(S)
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Electrical Characteristics (cont.)
VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k,
RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
VFMIN FMIN pin voltage during normal operation 4.6 5. 1 6.25 V VMIN=1.5V,VIPH=0.5V
VFMINFLT FMIN pin voltage during fault mode — 0.0 — V SD = 5V, or CS = 2V,
or Tj > TSD
Minimum Frequency Setting
VSDTH+ Rising shutdown pin threshold voltage 1.6 2.0 2.6 VCPH =VIPH=0V
VCSTH Peak over current threshold 1.2 1.6 1 .9 VCPH < 5V
VVDCTH+ Rising VDC pin threshold voltage — 5.1 — VCPH=VCS=VSD=0V
VSDHYS SD threshold hysteresis — 150 — mV VCPH =VIPH=0V
VVDCHYS VDC threshold hysteresis — 2.1 — VCPH =VCS=VSD = 0V
VSDCLMP SD pin clamp voltage — 7.6 — ISD = 100mA
TSD Thermal shutdown junction temperature — 165 — oC
Protection Characteristics
V
V
VCSTHZX Zero-crossing threshold voltage — 0.0 — V VCPH =5.5V,VIPH=0.5V
tBlank Zero-crossing internal blank time 291 400 1030 ns VCPH =5.5V,VIPH=0.5V
Phase Control
VDIMOFF DIM pin offset voltage — 0.5 —
VMINMIN DIM minimum reference voltage (MIN pin) — 1.0 — VCPH=5.5V,VIPH=0.5V
VMINMAX DIM maximum reference voltage (MIN pin) —3.0 — VCPH =0.5V,VIPH=0.5V
Dimming Interface
V
Preheat Characteristics
ICPH CPH pin charging current 0.8 1.3 2.1 µA VCPH=VDIM=4.7V,
VCS=1.0V
VCPHIGN CPH pin ignition mode threshold voltage 4. 3 5.0 5.7 VCS=2.0V
VCPHCLMP CPH pin clamp voltage — 10 — VCS=VDIM=VIPH=0V
IIPH IPH pin DC source current —25—
µAVCPH=VDIM=4.7V,
IIPH=1/RFMIN
VCSTHPH Peak preheat current regulation threshold — 0.7 — V RIPH=27K, VMIN=0V,
VCPH=0V, VCSTH =
(IIPH) x (RIPH)
VCPHFLT CPH pin voltage during UVLO or fault — 0 .0 — V SD = 5V, or CS = 2V,
or Tj > TSD
V
Ignition Detection
IIPHIGN+ IPH source current (Vcs rising) — 30 —VCS=0V, RIPH=18K,
VCPH>5.1V
IIPHIGN- IPH source current (Vcs falling) — 27.5 — VCS =1.0V,
VCPH>5.1V
µA
IR21592/IR21593(S)
6www.irf.com
Lead Assignments & Definitions
Block Diagram
Pin # Symbol Description
1
11
10
9
3
8
7
6
5
4
2
16
15
14
13
12
VDC
HO
VB
VS
VCC
COM
LO
CS
SD
FMIN
MIN
MAX
DIM
CPH
VCO Line input voltage detection
Voltage controlled oscillator Input
Preheat timing input
0.5 to 5VDC dimming control input
Maximum lamp power setting
Minimum lamp power setting
Minimum frequency setting
Shutdown input
Current sensing input
Low-side gate driver output
IC power & signal ground
Logic & low-side gate driver supply
High-side gate driver floating supply
High voltage floating return
High-side gate driver output
Pin Assignments
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDC
VCO
CPH
DIM
MAX
MIN
FMIN
IPH
LO
COM
VCC
VB
VS
HO
SD
CS
IPH Peak preheat current reference
LEVEL
SHIFT
PULSE
FILTER &
LATCH
3
5.1V
4
6
10V
2
1.0uA
5
7
8
5.1V
1.0V
CPH
DIM
MAX
MIN
FMIN
IPH
VCO
QS
R2 Q
R1 QT
RQ
16
14
15 VS
HO
VB
13
11
12 COM
LO
VCC
15.6V
10
1.6V
CS
UNDER-
VOLTAGE
DETECT
1
VDC
ICT
ICT
15uA
1uA
60uA
CT
IFMIN
QS
RQ
QS
RQ
IDIM
5.1V 1
0
VCC
400ns
DELAY
5.1V
3V
RFB
V
ERR
REF
FB
CT
OVER-
TEMP
DETECT
IGN
DET QS
RQ
9SD
2.0V 7.6V
Q
S
RQ
IDT
ICT
+
IDIM/5
4/RFMIN
1/RFMIN
0.1/RFMIN
0.1/RFMIN
IR21592/IR21593(S)
www.irf.com 7
State Diagram
PREHEAT Mode
1/2-BridgeOscillator On
VCSPK+VIPH (Peak Current Control)
CPH Charging@IPH+1µA
DIM+Open Circuit
Over-Current Disabled
UVLO Mode
1/2-Bridge Off
IQCC=200mA
CPH=0V
Oscillator Off
FAULT Mode
Fault Latch Set
1/2-Bridge Off
IQCC=240µA
CPH=0V
VCC=15.6V
Oscillator Off
DIM Mode
PhaseCS=PhaseREF
DIM=CPH
Over-Current Enabled
CPH > 5.1V
(End of PREHEAT Mode)
VCC < 10.9V
(VCC Fault or Power Down)
or
VDC < 3.0V
(dc Bus/ac Line Fault or Power Down)
or
SD > 2.0V
(Lamp Fault or Lamp Removal)
SD > 2.0V
(Lamp Removal)
or
VCC < 10.9V
(Power Turned Off)
CS > V CSTH (1.6V)
(Failure to Strike Lamp
or Hard Switching)
or
TJ> 165C
(Over-Temperature)
TJ > 165C
(Over-Temperature)
CS > VCSTH (1.6V)
(Over-Current or Hard Switching)
or
TJ > 165C
(Over-Temperature) VCS>VIPH(enable ignition detection)
then
VCS<VIPH(ignition detected)
VCC > 12.5V (UV+)
and
VDC > 5.1V (Bus OK)
and
SD < 1.7V (Lamp OK)
and
TJ < 165C (T jmax)
Power Turned On
IGNITION Mode
fPH ramps to fMIN
CPH Charging@IPH+1µA
DIM=Open Circuit
Over-Current Enabled
IR21592/IR21593(S)
8www.irf.com
VDC
CPH
VCO
SD
HO
LO
PH FLT
IGN
SD PH
IGN
DIM UVLOUVLO
VDCTH-
VDCTH+
5.1V
VDIM
5V
5V
CS
1.6V
VIPH
VCC
UVLO-
UVLO+
15.6V
f
Timing Diagram
Non-strike fault condition with lamp exchange
IR21592/IR21593(S)
www.irf.com 9
External Components Selection Procedure
(Note:
Please refer to
"Typical Connection"
diagram, page 1)
Calculate RCS
PK
IGN
CS I
R6.1
=
RCS sets the maximum ignition current
which corresponds to the maximum
ignition voltage across the lamp. RCS IIGN VIGN
Select RFMIN
Use Graph 5 or Graph 6
The minimum operating frequency must
be lower than f100% of fIGN (whichever is
lower). RFMIN also programs IMIN and
IIPH, so RFMIN must be set first.
RFMIN fMIN
BEGIN
Calculate RPULL-UP
QCCUV
ONTURN
UPPULL I
VAC
R−
−=
Set RVAC and RVDC such that the voltage
on pin VDC will exceed 5.1 volts at the
desired line turn-on voltage. RVDC VACTURN-ON
Calculate RVDC
ONTURN
VAC
ONTURN
VDC
VAC
R
VAC
R
−
−
−
=1.5
1
1.5
The voltage at pin IPH is the reference
for amplitude current control during
preheat mode. RIPH must be set after
RFMIN.RIPH IPH VPH
Select & Calculate RIPH
Use Graph 8 to find IIPH,
then calculate RIPH:
IPH
CSPH
IPH I
RI
RPK ⋅
=
Calculate CCPH
()
PHCPH teC 76.2 −=
During preheat, an internal 1.3 µA
current source at pin CPH charges
external capacitor CCPH. Preheat mode
ends when VCPH exceeds 5.1 volts.
CCPH tPH
Calculate ϕMIN (Equations 8 & 9)
RMIN sets the lower phase boundary
corresponding to minimum lamp
power when VDIM = 0 volts. RMIN must
be set after RFMIN.RMIN ϕMIN PLAMP
Calculate RMAX
Use Equation 15 RMAX ϕMAX PLAMP
RMAX sets the upper phase boundary
corresponding to maximum lamp power
when VDIM = 5 volts. RMAX must be set
after RFMIN and RMIN.
Find VMIN (Graph 9)
Find IMIN (Graph 7)
MIN
MIN
MIN I
V
R=
Calculate RMIN
IR21592/IR21593(S)
10 www.irf.com
Graph 3. IMIN vs RFMIN (IR21592/IR21593) Graph 4. IIPH vs RFMIN (IR21592/IR21593)
Characteristic Curves
Graph 2. Frequency vs RFMIN (IR21593)
Graph 1. Frequency vs RFMIN (IR21592)
0
20
40
60
80
100
120
10 20 30 40 50 60 70
RFMIN (KΩ)
Frequency (kHz)
VVCO=5V
VVCO=2V
VVCO=0V
0
40
80
120
160
200
10 20 30 40 50 60 70
RFMIN (KΩ)
Frequency (kHz)
VVCO=5V
VVCO=2V
VVCO=0V
50
100
150
200
250
300
350
400
450
10 20 30 40 50 60 70
RFMIN (KΩ)
IMIN ( A)
10
20
30
40
50
60
70
80
90
100
110
10 20 30 40 50 60 70
RFMIN (KΩ)
IIPH ( A)
IR21592/IR21593(S)
www.irf.com 11
Graph 5. ϕ IIVS/VVSI vs VMIN (IR21592/IR21593)
-90
-75
-60
-45
-30
-15
0
1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
VMIN (V )
IIVSI/VVSI
Graph 6. RMIN vs VMIN
0
0.5
1
1.5
2
2.5
3
-25 0 25 50 75 100 125
Temperature °C
ICPH µA
Graph 7. ICPH vs Temperature (IR21592/IR21593) Graph 8. IMIN vs Temperature (IR21592/IR21593)
5
10
15
20
25
30
2 2.2 2.4 2.6 2.8 3
VMIN (V )
RFMIN=39K
RFMIN=10K
RFMIN=16K
RFMIN=20K
RFMIN=33K
RFMIN=27K
RMIN (KΩ)
90
100
110
120
130
140
150
-25 0 25 50 75 100 125
Te mper atu re ° C
IMIN µA
IR21592/IR21593(S)
12 www.irf.com
Graph 10. VFMIN vs Temperature
(IR21592/IR21593)
Graph 9. IPH vs Temperature
(IR21592/IR21593)
Graph 12. Frequency vs Temperature (IR21593)
RFMIN=39K
Graph 11. Frequency vs Temperature (IR21592)
RFMIN=39K
0
20
40
60
80
100
-25 0 25 50 75 100 125
T emperature °C
Frequency (KHz)
VVCO=3V
VVCO=5V
VVCO=0V
0
40
80
120
160
-25 0 25 50 75 100 125
Temperature °C
Frequency (KHz)
VVCO=3V
VVCO=5V
VVCO=0V
20
24
28
32
36
40
-25 0 25 50 75 100 125
Temperature °C
IIPH A
4
4.4
4.8
5.2
5.6
6
-25 0 25 50 75 100 125
Temperature °C
VFMIN (V)
IR21592/IR21593(S)
www.irf.com 13
20
24
28
32
36
40
-25 0 25 50 75 100 125
Tem per atur e ° C
4
4.4
4.8
5.2
5.6
6
-25 0 25 50 75 100 125
Tem perature °C
VFMIN (V)
Graph 13. IIPH vs Temperature (IR21592/
IR21593) Graph 14. VFMIN vs Temperature (IR21592/
IR21593)
IIPH (µA)
1
1.4
1.8
2.2
2.6
3
-25 0 25 50 75 100 125
Temperature °C
TDEAD (uS)
0
0.4
0.8
1.2
1.6
2
-25 0 25 50 75 100 125
Temperature °C
TDEAD (uS)
Graph 15. TDEAD vs Temperature (IR21592) Graph 16. TDEAD vs Temperature (IR21593)
IR21592/IR21593(S)
14 www.irf.com
Functional Description
Phase Control
To understand phase control, a simplified model
for the ballast output stage is used (Figure 1). The
lamp and filaments are replaced with resistors,
with the lamp inserted between the filament
resistors (R1, R2, R3 and R4).
L
C
Rlamp
Vin
R1 R2
R3 R4
Figure 1, Dimming ballast output stage.
During preheat and ignition (Figure 2), the circuit
is a high-Q series LC with a strong input current to
input voltage phase inversion from +90 to -90
degrees at the resonance frequency. For operating
frequencies slightly above resonance and higher,
the phase is fixed at -90 degrees for the duration
of preheat and ignition. During dimming, the circuit
is an L in series with a parallel R and C, with a
weak phase inversion at high lamp power and a
strong phase inversion at low lamp power.
-30
-20
-10
0
10
20
5 101520253035404550
Frequency [kHz]
Magnitude [dB]
-100
-50
0
50
100
150
200
250
300
350
400
Phase [deg]
10%
50%
100%
100%
50%
10%
PH/IGN
PH/IGN
Figure 2, Typical output stage transfer function for
different lamp power levels.
In the time domain (Figure 3), the input current is
shifted -90 degrees from the input half-bridge
voltage during preheat and ignition, and
somewhere between 0 and -90 degrees after
ignition during running. Zero phase-shift
corresponds to maximum power.
nrun
Vin Iin
t
ph/ign
0
Iinrun
nph/ign
Figure 3, Typical ballast output stage waveforms.
When the phase is calculated and plotted versus
lamp power (Figure 4), the result is a linear dimming
curve, even down to ultra-low light levels where
the resistance of the lamp can change by orders
of magnitude.
IR21592/IR21593(S)
www.irf.com 15
-90.0
-85.0
-80.0
-75.0
-70.0
-65.0
-60.0
0 5 10 15 20 25 30
La mp P o wer [Watts]
Phase [degrees]
Figure 4, Lamp power vs. phase of output stage.
Under-voltage Lock-Out (UVLO)
The IR21592/IR21593 undervoltage lock-out is
designed to maintain an ultra low quiescent
current of less than 200uA, while guaranteeing
the IC is fully functional before the high and low
side output drivers are activated. Figure 5 shows
an efficient supply voltage using the start-up
current of the IR21592/IR21593 together with a
charge pump from the ballast output stage (R1,
C1, C2, D1 and D2).
16
15
14
13
12
11 LO
COM
VCC
VB
VS
HO
Rectified
AC Line
Half-Bridge
Output
C1
R1
D1
D2
Q2
Q1
RVDC
C2
VBUS(+)
D3
C3
RCS
VBUS(-)
1
VDC
R3
CVDC
DISCHARGE
TIME
INTERNAL
CLAMP VOLTAGE
VHYST
V
UVLO+
V
UVLO-
CHARGE PUMP
OUTPUT
t
V
C1
R1 & C1 TIME
CONSTANT
C1
DISCHARGE
Figure 6, Start-up capacitor (C1) voltage.
During the discharge cycle, the rectified current
from the charge pump charges the capacitor above
the minimum operating voltage of the device and
the charge pump and internal 15.6V zener clamp
of the IC take over as the supply voltage. The
start-up capacitor and snubber capacitor must be
selected such that worst case IC conditions are
satisfied. A bootstrap diode (D3) and supply
capacitor (C3) comprise the supply voltage for
the high side driver circuitry. To guarantee that
the high-side supply is charged up before the first
pulse on pin HO, the first pulse from the output
drivers comes from the LO pin. During UVLO,
the high and low side driver outputs are low, pin
VCO is pulled-up internally to 5V resetting the
starting frequency to the maximum, and pin CPH
is short-circuited internally to COM resetting the
preheat time.
Figure 5, Typical application of start-up circuitry.
The start-up capacitor (C1) is charged by current
through resistor (R1) minus the start-up current
drawn by the IC. This resistor is typically chosen
to provide 2X the maximum start-up current at
low line to guarantee start-up under the worst case
condition. Once the capacitor voltage reaches the
start-up threshold, and, the voltage on pin VDC is
above 5.1V (see Brown-out Protection), the IC
turns on and HO and LO begin to oscillate. The
capacitor begins to discharge due to the increase
in IC operating current (Figure 6).
IR21592/IR21593(S)
16 www.irf.com
Brown-out Protection
In addition to the voltage on VCC being above
the start-up threshold, pin VDC must also be
above 5.1V for HO and LO to begin oscillating. A
voltage divider (R3,RVDC) from the rectified AC
line connected to pin VDC measures the rectified
AC line input voltage to the ballast and programs
the turn-on and turn-off line voltages. A filter
capacitor (CVDC) is also connected to pin VDC
that must be chosen such that the ripple is low
enough and the lower turn-off threshold of 3V is
not crossed during normal line conditions. This
detection is necessary due to the possibility of
the lamp extinguishing during low-line conditions
before the IC is properly reset. Should a brown-
out occur, the DC bus can drop to a level below
the minimum required for the tank circuit to
maintain the necessary lamp voltage. This
detection will insure a clean turn-off before the
DC bus drops too low and properly resets the
IC to the preheat mode when the line returns.
Preheat (PH)
The IR21592/IR21593 enters preheat mode
when VCC exceeds the UVLO+ threshold and
VDC exceeds 5.1V. HO and LO begin to
oscillate at the maximum operating frequency
with 50% duty cycle and at the internally set
dead-time of 2us (IR21592) or 1µs (IR21593). Pin
CPH is disconnected from COM and an internal
1uA current source (Figure 7) charges the external
timing capacitor on CPH linearly.
3
7.6V
2
1uA
7
8
CPH
FMIN
IPH
VCO
11
12 COM
LO
10 CS
1uA
60uA
IFMIN
1/RFMIN
5.1V
Q2
RCS
VCO
PH
LOGIC
16 HO Q2
15 VS
RFMIN
RIPH
CCPH
CVCO Half
Bridge
Output
ILOAD
VBUS(+)
VBUS(-)
Load
Return
Half
Bridge
Driver
IR21592/IR21593
Figure 7, IR21592/IR21593 preheat circuitry.
An internal 1uA current source slowly discharges
the external capacitor on pin VCO and the voltage
on pin VCO begins to decrease. This decreases
the frequency, which, for operating frequencies
above resonance, increases the load current.
When the peak voltage measured on pin CS,
produced by a portion of the load current flowing
through an external sense resistor (RCS), exceeds
the voltage level on pin IPH, a 60uA internal
current source is connected to pin VCO and the
capacitor charges (Figure 8). This forces the
frequency to increase and the load current to
decrease. When the voltage on pin CS decreases
below the voltge on pin IPH, the 60uA current
source is disconnected and the frequency
decreases again.
IR21592/IR21593(S)
www.irf.com 17
60uA
-1uA
t
t
t
t
V
CVCO
I
CVCO
V
RCS
VS
LO
HO
VIPH
Figure 8, Peak load current regulation timing diagram.
This feedback keeps the peak preheat current
regulated to the user-programmable setting on pin
IPH for the duration of the preheat time. An
internal current source connected to an external
resistor on pin IPH sets a voltage reference for
the peak pre-heat current. The pre-heat time
continues until the voltage on pin CPH exceeds
5V.
Ignition (IGN)
The IR21592/IR21593 enters ignition mode when
the voltage on pin CPH exceeds 5V. The peak
current regulation reference voltage is
disconnected from the user-programmable
setting on pin IPH and is connected to a higher
internal threshold of 1.6V (Figure 9).
3
7.6V
2
1uA
4
CPH
DIM
VCO
11
12 COM
LO
10 CS
1uA
1.6V
Q2
RCS
VCO
PH
LOGIC
16HO Q2
15 VS
RDIM
CCPH
CVCO Half
Bridge
Output
ILOAD
VBUS(+)
VBUS(-)
Load
Return
Half
Bridge
Driver
IR21592/IR21593
DIM
INTERFACE
0.5 to 5V
PHASE
CONTROL
FAULT
LOGIC
Figure 9, IR21592/IR21593 ignition circuitry.
The ignition ramp is then initiated as the
capacitor on pin VCO discharges linearly
through an internal 1uA current source. The
frequency decreases linearly towards the
resonance frequency of the high-Q ballast output
stage, causing the lamp voltage and load current
to increase (Figure 10). The frequency
continues to decrease until the lamp ignites or
the current limit of the IR21592/IR21593 is
reached. If the current limit is reached, the
IR21592/IR21593 enters FAULT mode. The 1.6V
threshold together with the external current
sensing resistor on pin CS determine the
maximum allowable peak ignition current (and
therefore peak ignition voltage) of the ballast
output stage. The peak ignition current must not
exceed the maximum allowable current ratings
of the output stage MOSFETs or IGBTs, and,
the resonant inductor must not saturate at
any time.
To prevent a "flash" across the lamp during
ignition at low dim settings, an ignition detection
IR21592/IR21593(S)
18 www.irf.com
circuit measures the voltage at the CS pin and
compares it against the voltage at the IPH pin.
During the rising ignition ramp, the voltage at
the IPH pin is increased to 20% above its value
5.1V
VCPH
VVCO
t
t
PH IGN DIM
VDIM
RDIM & CTPH
TIME CONSTANT
IGN-TO-DIM
TIME
Figure 10, IR21592/IR21593 ignition detection.
during preheat mode. When the voltage on the
CS pin exceeds this voltage, the voltage on the
IPH pin is decreased to VIPH Pre-Heat +10% and
the ignition detection circuit is then active (See
Figure 10). When the lamp ignites, the voltage on
the CS pin will then fall below the voltage on the
IPH pin and the IC enters DIM Mode and the phase
control loop is closed. In order for the ignition
detection circuit to function properly and for the IC
to enter DIM mode, the voltage on the CS pin must
first rise above VIPH Pre-Heat + 20% during the
ignition ramp to activate the circuit, and then
decrease below VIPH Pre-Heat +10% when the lamp
ignites.
Ignition-to-Dim (IGN-to-DIM)
When the IR21592/IR21593 enters dim mode, the
phase control loop is closed and the phase of the
load current is regulated against the user control
input on pin DIM. To control the rate at which the
dim setting changes from maximum brightness
to the user setting (IGN-TO-DIM time, Figure 11),
pin DIM is connected internally to pin CPH when
the IR21592/IR21593 enters DIM mode. The
resistor on pin DIM (RDIM) discharges the
capacitor on pin CPH down to the user dim
setting. The resistor can be selected for a fast
time constant to minimize the amount of flash
visible over the lamp just after ignition, or, a
long time constant such that the brightness
ramps down smoothly to the user setting. Should
the ignition-to-dim time be too fast, however, the
loop can respond faster than the ionization
constant of the lamp (milliseconds) causing the
VCO to over-shoot. This can result in a
frequency that is higher than the minimum
brightness frequency and can extinguish the
lamp. The capacitor on pin CPH serves multiple
functions by setting the preheat time, the travel
rate just after ignition (together with resistor
RDIM), and, serving as a filter capacitor on pin
Figure 11, IR21592/IR21593 ignition timing diagram.
VIPH
VIPH + 20%
VIPH + 10%
CS
PH IGN DIM
IR21592/IR21593(S)
www.irf.com 19
Once lock is achieved, the phase detector (PDET)
outputs short pulses to an open-drain PMOS that
charges the VCO capacitor through an internal
resistor (RFB) each time an error pulse occurs
(Figure 13). This action "nudges" the integrator at
the input of the VCO to keep the phase of the
output stage current exactly locked in phase with
the reference.
νREF
νFB
VCS
t
VVCO
t
LO
νERR
Figure 13, Phase control timing diagram.
The IR21592/IR21593 includes a dimming
interface for analog lamp power control. The
DIM pin input requires a voltage in the range of
0.5 to 5VDC, with 5V corresponding to minimum
phase shift (maximum lamp power). The output
of the dim interface is the voltage on pin MIN,
which is compared with the internal timing
capacitor (CT) voltage to produce a frequency-
independent digital reference phase (Figure 14).
DIM during dimming to increase high-frequency
noise immunity and minimize component count.
Dimming (DIM)
To regulate lamp power, the error between the
reference phase and the phase of the output stage
current forces the VCO to steer the frequency in
the proper direction, as determined by the transfer
function of the output stage, such that the error is
forced to zero. An internal 15uA current source is
connected to pin VCO during dimming mode
(Figure 12) to discharge the VCO capacitor and
decrease the frequency towards lock.
3
7.6V
2
4
CPH
DIM
VCO
11
12 COM
LO
10 CS
16uA
1.6V
Q2
RCS
VCO 16 HO Q2
15 VS
RDIM
CCPH
CVCO
Half
Bridge
Output
ILOAD
VBUS(+)
VBUS(-)
Load
Return
Half
Bridge
Driver
IR2159
DIM
INTERFACE
0.5 to 5V
PHASE
CONTROL
RFB
VCC
FAULT
LOGIC
RMAX
RMIN
5
6
MAX
MIN
Figure 12, IR21592/IR21593 dimming circuitry.
IR21592/IR21593(S)
20 www.irf.com
1V
3V
5V
00.5V 5V
VMIN
VDIM
R
MIN
R
MAX
V
CT
LO
USER
SETTING
DIM
RANGE
ν
0 -90 -180
ΕΕΕ
ν
REF
Figure 14, Dimming interface
The charging time of CT from 1V to 5.1V
determines the on-time of output gate drivers HO
and LO and corresponds to -180 degrees of
possible phase shift in load current (minus
deadtime). For the 0 to -90 degree dim range, the
voltage on pin MIN is bounded between 1V and
3V using pins MIN and MAX. An external resistor
on pin MAX programs the minimum phase shift
reference (maximum lamp power) corresponding
to 5V on pin DIM, and an external resistor on pin
MIN sets the maximum phase shift (minimum
lamp power) corresponding to 0.5V on pin DIM.
Current Sensing
During dimming, the current sensing circuitry
(Figure 15) detects over-current which can occur
during hard-switching (see Fault section), and
zero-crossing to measure the phase of the total
load current. To reject any switching noise which
can occur at the turn-on of the low-side MOSFET
or IGBT, a digital current sense blanking circuit
blanks out the signal from the zero-crossing
detection comparator for 400ns after LO goes 'high'
(Figure 16).
11
12 COM
LO
10 CS
1.6V
Q2
RCS
16 HO Q2
15 VS
Half
Bridge
Output
ILOAD
VBUS(+)
VBUS(-)
Load
Return
Half
Bridge
Driver
IR2159
PHASE
CONTROL
FAULT
LOGIC
400ns
BLANK
R1
Figure 15, Current sensing circuitry.
The internal blank time reduces the dimming range
slightly (Figure 16) when operating at minimum
phase shift (maximum lamp power). The external
programming resistor on pin MAX must be
selected such that the minimum phase shift is
set a safe margin away from the blank time. A
series resistor (R1) is required to limit the amount
of current flowing out of pin CS when the voltage
across RCS goes below -0.7V. A filter capacitor
at pin CS may be required due to other possible
asynchronous noise sources present in the ballast
system.
IR21592/IR21593(S)
www.irf.com 21
ϑ
BLANK
V
CS
t
LO
Switching
Noise
Dimming
Range
Fault Mode (FAULT)
During dimming, the peak current regulation circuit
active during preheat and ignition is disabled.
Should non-zero voltage switching at the output
of the half-bridge occur (Figure 17), high current
spikes will result. A lamp filament failure, lamp
end-of-life, lamp removal, or a deadtime shorter
than what is required for commutation, can all
cause hard-switching.
t
t
VS
HO
LO
VCS
1.6V
NORMAL
OPERATION HARD
SWITCHING FAULT
LOAD
REMOVAL
Figure 17, hard-switching with latch off
Figure 16, Current sense timing diagram.
Should the peak voltage on pin CS exceed 1.6V
at any time during dimming, the IR21592/IR21593
enters FAULT mode and the high and low-side
driver outputs, HO and LO, are both turned off.
Cycling the supply voltage on VCC below UVLO-
or the voltage on pin SD above and below SD+
and SD- will reset the IR21592/IR21593 to preheat
(PH) mode (see STATE DIAGRAM).
Ballast Design
Lamp Requirements
Before selecting component values for the ballast
output stage and the programmable inputs of
the IR21592/IR21593, the following lamp
requirements must first be defined:
Variable Description Units
ph
I Filamen t pre-heat current Arms
ph
t Filament pre-heat time s
max
ph
V Maxi mum l amp pr e- heat voltag e Vpp
ign
V Lamp ignition voltage Vpp
%100
P Lamp power at 100% brightness W
%100
V Lamp voltage at 100% brightness Vpp
%1
P Lamp power at 1% brightness W
%1
V Lamp voltage at 1% brightness Vpp
min
Cath
I Minimum cathode heating current Arms
Table I, Typical lamp requirements
IR21592/IR21593(S)
22 www.irf.com
The operating frequency [Hz] at maximum lamp
power is given as:
The cathode heating current at minimum lamp
power is given as:
2
%1%1
%1
CfV
ICath
π
= (7)
Design Constraints
The inductor and capacitor values should be
iterated until the following design constraints have
been fulfilled (Table II).
Desig n Const raint Reas on
VV
ph ph
<max Ignition during pre-
heat
ff kHz
ph ign
−>5 Production tolerances
II
ign ign
<max I nductor saturation
min%1 CathCath II ≥ Lamp extinguishing
during dim ming
Table II, Ballast design constraints
IR21592/IR21593 Programmable Inputs
In order to program the MIN and MAX settings of
the dimming interface, the phase of the output
stage current at minimum and maximum lamp
power must be calculated. This is obtained using
the following equations:
22
2
%100
2
4%100
2
2%100
4%100
2
2%100
%100
4
1
32
1
32
1
2
1
CL
V
V
VC
P
LCVC
P
LC
f
DC
−
−
−+−=
π
π
(6)
Ballast Output Stage
The components comprising the output stage are
selected using a set of equations. Different ballast
operating frequencies and their respective
voltages and currents are calculated.
The inductor and capacitor values are obtained
using equations (2) through (7). The results of
these equations reveal the location of each
operating frequency and the corresponding
voltages and currents. For a given L, C, DC bus
voltage, and pre-heat current, the resulting voltage
over the lamp during pre-heat is given as:
The resulting operating frequency during pre-heat
is given as:
ph
ph
ph CV
I
f
π
2
= [Hz] (3 )
The resulting operating frequency during ignition
is given as:
LC
V
V
fign
DC
ign
π
π
4
1
2
1+
= [Hz] (4)
The total load current during ignition is given as:
IfCV
ign ign ign
=2
π
[App] (5)
ππ
DC
ph
DC
ph V
I
C
L
V
V2
8
22
1
2
2−
+
=(2)
IR21592/IR21593(S)
www.irf.com 23
]42)
2
2
[(tan
180 3
%
32
%
2
%
%
2
%
%
%
2
%
1
%fLC
P
V
fL
V
P
C
P
V
ππ
π
ϕ
−−= − (9)
With the lamp requirements defined, the L and C
of the ballast output stage selected, and the
minimum and maximum phase calculated, the
component values for setting the programmable
inputs of the IR21592/IR21593 are obtained with
the following equations:
)142()10000( )101()10000()625( −⋅− −⋅−−−
=ef efe
R
MIN
MIN
FMIN
[Ohms] (10)
ign
CS I
R)6.1(2⋅
= [Ohms] (11)
2
phCSFMINIPH IRRR = [Ohms] (12)
−= 45
1
4%1
ϕ
FMIN
MIN R
R[Ohms] (14)
[Ohms] (15)
−⋅−⋅
⋅⋅
=
45
14
86.0
%100
ϕ
FMINMIN
MINFMIN
MAX RR
RR
R
22
2
%
2
4
%
2
2
%
4
%
2
2
%
%
4
1
321321
2
1CL
V
V
VC P
LCVC P
LC
f
DC
−
−
−+−=
π
π
(8)
))(76.2( PHCPH tEC −= [Farads] (13)
IR21592/IR21593(S)
24 www.irf.com
This ballast design procedure has been summarized into the following 3 steps:
Define
Lamp
Requirements
Iterate L and C
to fulfill
constraints
Calculate
IR2159
Programmable
Inputs
Figure 19, Simplified Ballast Design Procedure
Case outline
16 Lead PDIP 01-6015
01-3065 00 (MS-001A)
IR21592/IR21593
IR21592/IR21593(S)
www.irf.com 25
16 -Lead SOIC (narrow body) 01-6018
01-3064 00 (MS-012AC)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice.
This product has been designed and qualfied for the industrial market. 11/13/2003
