Data Sheet No. PD60194_A IR21592(S) IR21593(S) DIMMING BALLAST CONTROL IC Features * Full lamp fault protection * Brown-out protection * Automatic restart * Micro-power startup * Zener clamped Vcc * Over-temperature protection * 16-pin DIP and SOIC package types * Ballast control and half-bridge driver in one IC * Transformer-less lamp power sensing * Closed-loop lamp power control * Closed-loop preheat current control * Programmable preheat time * Programmable preheat current * Lamp ignition detection * Programmable ignition-to-dim time * 0.5 to 5VDC dimming control input * Min and max lamp power adjustments * Programmable minimum frequency * Internal current sense blanking Parameter Deadtime Frequency Range IR21592 1.8us See Graph 11 IR21593 1.0us See Graph 12 Packages Description Description: The IR21592/IR21593 are complete dimming ballast controllers and 600V half-bridge drivers all in one IC. The architecture includes phase control for transformer-less lamp power sensing and regulation which minimizes changes needed to adapt non-dimming ballasts for dimming. Externally programmable features such as preheat time and current, ignition-to-dim time, and a complete dimming interface with minimum and maximum settings provide a high degree of flexibility for the ballast design engineer. Protection from failure of a lamp to strike, filament failures, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of this control IC is a voltagecontrolled oscillator with externally programmable minimum frequency. The IR21592/ IR21593 are available in both 16 pin DIP and 16 pin narrow body SOIC packages. 16 Lead SOIC (narrow body) 16 Lead PDIP Typical Connection + Rectified AC Line Single Lamp Dimmable + DC Bus RVDC CVDC CVCO CPH 0.5 to 5VDC RVAC RPULL-UP 1 2 3 RDIM 4 RMAX 5 RMIN 6 RFMIN 7 RIPH 8 VDC HO VCO VS CPH VB DIM VCC MAX COM MIN LO FMIN CS IPH SD 16 15 14 13 12 11 10 9 RCS - DC Bus www.irf.com 1 IR21592/IR21593(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating supply voltage VS Min. Max. -0.3 625 High side floating supply offset voltage VB - 25 VB + 25 VHO High side floating output voltage VS - 0.3 VB + 0.3 VLO Low side output voltage -0.3 VCC + 0.3 Maximum allowable output current (either output) -500 500 -0.3 6.0 V mA IOMAX due to external power transistor miller effect VVCO Voltage controlled oscillator input voltage I CPH CPH current -5 5 VIPH IPH voltage -0.3 5.5 VDIM Dimming control pin input voltage -0.3 5.5 VMAX Maximum lamp power setting pin input voltage -0.3 5.5 VMIN Minimum lamp power setting pin input voltage -0.3 5.5 VCS Current sense input voltage -0.3 5.5 ISD Shutdown pin current -5 5 ICC Supply current (note 1) -- 25 dV/dt PD Allowable offset voltage slew rate Package power dissipation @ TA +25C PD = (TJMAX-TA)/RthJA RthJA Thermal resistance, junction to ambient -50 50 (16 pin DIP) -- 1.60 (16 pin SOIC) -- 1.25 (16 pin DIP) -- 75 (16 pin SOIC) -- 115 TJ Junction temperature -55 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) -- 300 Note 1: 2 Units V mA V mA V/ns W o C/W o C This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V (VCLAMP). Please note that this supply pin should not be driven by a DC, low impedance power source greater than the diode clamp voltage (VCLAMP) as specified in the Electrical Characteristics section. www.irf.com IR21592/IR21593(S) Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol Definition VBS High side floating supply voltage VS Steady state high side floating supply offset voltage Min. Max. VCC - 0.7 V CLAMP -1 600 V CC Supply voltage V CCUV+ VCLAMP (15.6) I CC Supply current note 2 10 5 VVCO VCO pin voltage 0 VDIM DIM pin voltage 0.5 5.0 VMAX MAX pin current (note 3) -750 0 VMIN MIN pin voltage 1 -- 10 3 Minimum required VBS voltage for proper HO functionality Minimum frequency setting resistance 5 100 ISD Shutdown pin current -1 1 ICS Current sensing pin current -1 1 TJ Junction temperature -40 125 VBSMIN RFMIN Note 2: Note 3: Units V mA V A V k mA o C Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead regulating its voltage, VCLAMP. The MAX lead is a voltage-controlled current source. For optimum dim interface current mirror performance, this current should be kept between 0 and 750A. Electrical Characteristics VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VCPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. VCC supply undervoltage positive going 12.0 threshold VCC supply undervoltage lockout hysteresis 1.5 UVLO mode quiescent current 70 Fault-mode quiescent current -- 12.5 13.0 1.6 200 240 1.7 330 -- -- -- -- -- 5.6 6.0 5.4 6.8 -- -- -- -- 14.5 15.6 16.5 Units Test Conditions Supply Characteristics VCCUV+ VCCHYS IQCCUV IQCCFLT ICCFMIN ICCFMAX ICCFMIN ICCFMAX VCC VCC VCC VCC VCLAMP VCC zener shunt clamp voltage www.irf.com supply supply supply supply current @ FMIN (IR21592) current @ FMAX (IR21592) current @ FMIN (IR21593) current @ FMAX (IR21593) V A mA V VCC = 10V SD=5V, CS=2V, or Tj > TSD VVCO = 0V VVCO = 5V VVCO = 0V VVCO = 5V ICC = 10mA 3 IR21592/IR21593(S) Electrical Characteristics (cont.) VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Floating Supply Characteristics IBSFMIN IBSFMAX ILK VBS supply current (low freq.) VBS supply current (high freq.) Offset supply leakage current -- -- -- 0 30 -- -- -- 50 15 18 22 73 -- -- -- -- 95 30 230 50 5 108 -- -- -- -- -- -- 1.0 16.0 -- -- A VVCO = 0V VVCO = 5V VB = VS = 600V Oscillator I/O Characteristics f vco f vco d VVCOFLT IVCOPH IVCODIM VCO frequency range (IR21592) (See graph 11) VCO frequency range (IR21593) (See graph 12) Gate drive outputs duty cycle Fault-mode VCO pin voltage (UVLO, shutdown, over-current/temp.) Preheat mode VCO pin discharge current Dim mode VCO pin discharge current IVCOPK Amplitude control VCO pin charging current -- 60 -- tDTLO tDTHO tDTLO tDTHO LO output deadtime (IR21592) HO output deadtime (IR21592) LO output deadtime (IR21593) HO output deadtime (IR21593) -- -- -- -- 1.8 1.8 1.0 1.0 -- -- -- -- VVCO=0V, RFMIN=40K kHz % V VVCO=5V, RFMIN=40K VVCO=0V, RFMIN=40K VVCO=5V, RFMIN=40K VVCO = 2.5V VCPH=2.5V, VIPH=0.5V A A s VVCO=2.5V, VCPH=5.5V, VIPH=0.5V, 1V Pulse at CS VCPH=0V, VCS =1V, VIPH=0.5V, VVCO=2.5V VVCO=0V, VMIN=1.5V, VIPH=0.5V Gate Driver Output Characteristics tr Turn-on rise time 48.5 120 180 tf Turn-off fall time 24.25 65 145 4 ns www.irf.com IR21592/IR21593(S) Electrical Characteristics (cont.) VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, CVCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Preheat Characteristics ICPH CPH pin charging current 0.8 1.3 2.1 A VCPHIGN VCPHCLMP IIPH CPH pin ignition mode threshold voltage CPH pin clamp voltage IPH pin DC source current 4.3 -- 5.0 10 5.7 -- V -- 25 -- A VCSTHPH Peak preheat current regulation threshold -- 0.7 -- V VCPHFLT CPH pin voltage during UVLO or fault -- 0.0 -- V SD = 5V, or CS = 2V, or Tj > TSD A VCS=0V, RIPH=18K, VCPH>5.1V VCS =1.0V, VCPH>5.1V VCPH=VDIM=4.7V, VCS=1.0V VCS=2.0V VCS=VDIM=VIPH=0V VCPH=VDIM=4.7V, IIPH=1/RFMIN RIPH=27K, VMIN=0V, VCPH=0V, VCSTH = (IIPH) x (RIPH) Ignition Detection IIPHIGN+ IPH source current (Vcs rising) -- 30 -- IIPHIGN- IPH source current (Vcs falling) -- 27.5 -- 1.6 1.2 -- -- -- -- -- 2.0 1.6 5.1 150 2.1 7.6 165 2.6 1.9 -- -- -- -- -- mV -- 291 0.0 400 -- 1030 V ns VCPH =5.5V,VIPH=0.5V VCPH =5.5V,VIPH=0.5V -- -- -- 0.5 1.0 3.0 -- -- -- V VCPH=5.5V,VIPH=0.5V VCPH =0.5V,VIPH=0.5V 4.6 -- 5.1 0.0 6.25 -- V V VMIN=1.5V,VIPH=0.5V SD = 5V, or CS = 2V, or Tj > TSD Protection Characteristics VSDTH+ VCSTH VVDCTH+ VSDHYS VVDCHYS VSDCLMP TSD Rising shutdown pin threshold voltage Peak over current threshold Rising VDC pin threshold voltage SD threshold hysteresis VDC threshold hysteresis SD pin clamp voltage Thermal shutdown junction temperature V V VCPH =VIPH=0V VCPH < 5V VCPH=VCS=VSD=0V VCPH =VIPH=0V VCPH=VCS=VSD=0V ISD = 100mA oC Phase Control VCSTHZX tBlank Zero-crossing threshold voltage Zero-crossing internal blank time Dimming Interface VDIMOFF VMINMIN VMINMAX DIM pin offset voltage DIM minimum reference voltage (MIN pin) DIM maximum reference voltage (MIN pin) Minimum Frequency Setting VFMIN VFMINFLT FMIN pin voltage during normal operation FMIN pin voltage during fault mode www.irf.com 5 IR21592/IR21593(S) Block Diagram VCC 60uA ICT RFB VCO 2 V 15uA 1uA LEVEL SHIFT VDC 1 S Q R Q PULSE FILTER & LATCH 14 VB 16 HO 15 VS 13 VCC 11 LO 12 COM 10 CS ERR 1.0uA CPH 3 CT REF 10V ICT DIM 4 5.1V S Q R Q S 5.1V Q R1 T Q R Q R2 Q 1.0V 15.6V I DT + I CT 400ns DELAY CT IDIM FB MAX 5 4/RFMIN MIN 6 0.1/R FMIN 0.1/R FMIN IDIM/5 IFMIN FMIN 7 5.1V IPH IGN DET 3V S Q R Q 1.6V 8 S Q R OVERTEMP DETECT UNDERVOLTAGE DETECT 1/RFMIN 1 Q 5.1V 9 2.0V SD 7.6V 0 Lead Assignments & Definitions Pin # Symbol Pin Assignments 6 VDC 1 16 HO VCO 2 15 VS CPH 3 14 VB DIM 4 13 VCC MAX 5 12 COM MIN 6 11 LO FMIN 7 10 CS IPH 8 9 SD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDC VCO CPH DIM MAX MIN FMIN IPH SD CS LO COM VCC VB VS HO Description Line input voltage detection Voltage controlled oscillator Input Preheat timing input 0.5 to 5VDC dimming control input Maximum lamp power setting Minimum lamp power setting Minimum frequency setting Peak preheat current reference Shutdown input Current sensing input Low-side gate driver output IC power & signal ground Logic & low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output www.irf.com IR21592/IR21593(S) State Diagram Power Turned On UVLO Mode 1/2-Bridge Off IQCC=200mA CPH=0V Oscillator Off VCC > 12.5V and VDC > 5.1V and SD < 1.7V and T < 165C J SD > 2.0V (Lamp Removal) or VCC < 10.9V (Power Turned Off) T > 165C J (Over-Temperature) FAULT Mode Fault Latch Set 1/2-Bridge Off IQCC =240A CPH=0V VCC=15.6V Oscillator Off (UV+) (Bus OK) (Lamp OK) (T ) jmax VCC < 10.9V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Power Down) or SD > 2.0V (Lamp Fault or Lamp Removal) PREHEAT Mode 1/2-BridgeOscillator On VCSPK+VIPH (Peak Current Control) CPH Charging@I PH+1A DIM+Open Circuit Over-Current Disabled CPH > 5.1V CS > V CSTH (1.6V) (End of PREHEAT Mode) (Failure to Strike Lamp or Hard Switching) or T J > 165C (Over-Temperature) IGNITION Mode fPH ramps to fMIN CPH Charging@I PH+1A DIM=Open Circuit Over-Current Enabled CS > V CSTH (1.6V) (Over-Current or Hard Switching) or TJ > 165C VCS>VIPH(enable ignition detection) (Over-Temperature) then VCS<VIPH(ignition detected) DIM Mode PhaseCS=PhaseREF DIM=CPH Over-Current Enabled www.irf.com 7 IR21592/IR21593(S) Timing Diagram Non-strike fault condition with lamp exchange VCC 15.6V UVLO+ UVLO- VDC VDCTH+ VDCTH- CPH 5.1V VDIM VCO f 5V SD 5V HO LO CS 1.6V VIPH FLT SD PH IGN 8 PH IGN UVLO DIM UVLO www.irf.com IR21592/IR21593(S) External Components Selection Procedure (Note: Please refer to "Typical Connection" diagram, page 1) BEGIN Calculate R PULL-UP RPULL -UP = VACTURN -ON I QCCUV Calculate R VDC Set RVAC and RVDC such that the voltage on pin VDC will exceed 5.1 volts at the desired line turn-on voltage. The minimum operating frequency must be lower than f100% of f IGN (whichever is lower). RFMIN also programs IMIN and IIPH, so RFMIN must be set first. RCS sets the maximum ignition current which corresponds to the maximum ignition voltage across the lamp. RVDC 5.1 VACTURN -ON = 5.1 1- VACTURN -ON RVAC Select RFMIN Use Graph 5 or Graph 6 RVDC VACTURN-ON RFMIN fMIN RCS IIGN VIGN RIPH IPH VPH CCPH tPH RMIN MIN PLAMP RMAX MAX PLAMP Calculate R CS RCS = 1.6 I IGN PK Select & Calculate R IPH The voltage at pin IPH is the reference for amplitude current control during preheat mode. RIPH must be set after RFMIN. During preheat, an internal 1.3 A current source at pin CPH charges external capacitor CCPH. Preheat mode ends when VCPH exceeds 5.1 volts. Use Graph 8 to find I IPH, then calculate R IPH: RIPH = I PH PK RCS I IPH Calculate C CPH CCPH = (2.6e - 7 ) t PH Calculate R MIN RMIN sets the lower phase boundary corresponding to minimum lamp power when VDIM = 0 volts. RMIN must be set after RFMIN. Find IMIN (Graph 7) Calculate MIN (Equations 8 & 9) Find V MIN (Graph 9) RMIN = RMAX sets the upper phase boundary corresponding to maximum lamp power when VDIM = 5 volts. RMAX must be set after R FMIN and RMIN. www.irf.com VMIN I MIN Calculate R MAX Use Equation 15 9 IR21592/IR21593(S) Characteristic Curves 200 120 100 160 Frequency (kHz) Frequency (kHz) VVCO=5V 80 60 VVCO=2V 40 VVCO=0V 20 VVCO=5V 120 VVCO=2V 80 V VCO=0V 40 0 0 10 20 30 40 50 60 70 10 20 30 RFMIN (K) 40 50 60 70 RFMIN (K) Graph 2. Frequency vs RFMIN (IR21593) Graph 1. Frequency vs RFMIN (IR21592) 450 110 400 100 90 80 300 IIPH ( A) IMIN ( A) 350 250 200 70 60 50 40 150 30 100 20 50 10 10 20 30 40 50 60 RFMIN (K) Graph 3. IMIN vs RFMIN (IR21592/IR21593) 10 70 10 20 30 40 50 60 70 RFMIN (K) Graph 4. IIPH vs RFMIN (IR21592/IR21593) www.irf.com IR21592/IR21593(S) 0 30 -15 RFM 25 RFM RMIN (K) IIVSI/VVSI -30 -45 RFM 15 IN=3 IN=2 RFMIN 3K 7K =20K RFMIN= 10 -75 39K 20 -60 16K RFMIN=10 -90 K 5 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 2 2.2 2.4 2.6 2.8 3 VMIN (V) VMIN (V) Graph 5. IIVS/VVSI vs VMIN (IR21592/IR21593) Graph 6. RMIN vs VMIN 3 150 2.5 140 2 130 IMIN A ICPH A IN= 1.5 120 1 110 0.5 100 90 0 -25 0 25 50 75 100 Temperature C Graph 7. ICPH vs Temperature (IR21592/IR21593) www.irf.com 125 -25 0 25 50 75 100 125 Temperature C Graph 8. IMIN vs Temperature (IR21592/IR21593) 11 IR21592/IR21593(S) 6 36 5.6 32 5.2 IIPH A V FMIN (V) 40 28 24 4.8 4.4 20 -25 0 25 50 75 100 4 -25 125 0 25 50 75 100 125 Temperature C Temperature C Graph 9. IPH vs Temperature (IR21592/IR21593) Graph 10. VFMIN vs Temperature (IR21592/IR21593) 160 100 VVCO=5V VVCO=5V VVCO=3V 120 Frequency (KHz) Frequency (KHz) 80 60 40 VVCO=0V VVCO=3V 80 40 VVCO=0V 20 0 -25 0 25 50 75 100 Temperature C Graph 11. Frequency vs Temperature (IR21592) RFMIN=39K 12 125 0 -25 0 25 50 75 100 125 Temperature C Graph 12. Frequency vs Temperature (IR21593) RFMIN=39K www.irf.com 40 6 36 5.6 32 5.2 VFMIN (V) IIPH (A) IR21592/IR21593(S) 28 24 4.8 4.4 20 4 -25 0 25 50 75 100 125 -25 0 50 75 100 125 Temperature C Temperature C Graph 13. IIPH vs Temperature (IR21592/ IR21593) Graph 14. VFMIN vs Temperature (IR21592/ IR21593) 3 2 2.6 1.6 TDEAD (uS) TDEAD (uS) 25 2.2 1.8 1.4 1.2 0.8 0.4 1 -25 0 25 50 75 100 125 Temperature C Graph 15. TDEAD vs Temperature (IR21592) www.irf.com 0 -25 0 25 50 75 100 125 Temperature C Graph 16. TDEAD vs Temperature (IR21593) 13 IR21592/IR21593(S) Functional Description 400 PH/IGN 20 300 50% 250 10 Magnitude [dB] To understand phase control, a simplified model for the ballast output stage is used (Figure 1). The lamp and filaments are replaced with resistors, with the lamp inserted between the filament resistors (R1, R2, R3 and R4). 350 10% 200 0 100% 150 100 -10 PH/IGN 50 10% 50% -20 0 -50 100% R1 R2 -30 Vin -100 5 L Phase [deg] Phase Control 10 15 20 25 30 35 40 45 50 Frequency [kHz] Rlamp R3 C Figure 2, Typical output stage transfer function for different lamp power levels. R4 Figure 1, Dimming ballast output stage. During preheat and ignition (Figure 2), the circuit is a high-Q series LC with a strong input current to input voltage phase inversion from +90 to -90 degrees at the resonance frequency. For operating frequencies slightly above resonance and higher, the phase is fixed at -90 degrees for the duration of preheat and ignition. During dimming, the circuit is an L in series with a parallel R and C, with a weak phase inversion at high lamp power and a strong phase inversion at low lamp power. In the time domain (Figure 3), the input current is shifted -90 degrees from the input half-bridge voltage during preheat and ignition, and somewhere between 0 and -90 degrees after ignition during running. Zero phase-shift corresponds to maximum power. Vin Iin ph/ign Iin run 0 t nrun nph/ign Figure 3, Typical ballast output stage waveforms. When the phase is calculated and plotted versus lamp power (Figure 4), the result is a linear dimming curve, even down to ultra-low light levels where the resistance of the lamp can change by orders of magnitude. 14 www.irf.com IR21592/IR21593(S) The start-up capacitor (C1) is charged by current through resistor (R1) minus the start-up current drawn by the IC. This resistor is typically chosen to provide 2X the maximum start-up current at low line to guarantee start-up under the worst case condition. Once the capacitor voltage reaches the start-up threshold, and, the voltage on pin VDC is above 5.1V (see Brown-out Protection), the IC turns on and HO and LO begin to oscillate. The capacitor begins to discharge due to the increase in IC operating current (Figure 6). -60.0 -65.0 Phase [degrees] -70.0 -75.0 -80.0 -85.0 VC1 -90.0 0 5 10 15 20 25 30 C1 DISCHARGE Lamp Pow er [Watts] INTERNAL CLAMP VOLTAGE VUVLO+ Figure 4, Lamp power vs. phase of output stage. VHYST VUVLO- Under-voltage Lock-Out (UVLO) The IR21592/IR21593 undervoltage lock-out is designed to maintain an ultra low quiescent current of less than 200uA, while guaranteeing the IC is fully functional before the high and low side output drivers are activated. Figure 5 shows an efficient supply voltage using the start-up current of the IR21592/IR21593 together with a charge pump from the ballast output stage (R1, C1, C2, D1 and D2). VBUS (+) Rectified AC Line R3 R1 VDC 1 16 HO Q1 15 VS 14 VB 13 VCC 12 CVDC RVDC COM 11 LO Half-Bridge Output C3 C2 D3 D1 C1 Q2 D2 RCS V BUS (-) Figure 5, Typical application of start-up circuitry. www.irf.com DISCHARGE TIME CHARGE PUMP OUTPUT R1 & C1 TIME CONSTANT t Figure 6, Start-up capacitor (C1) voltage. During the discharge cycle, the rectified current from the charge pump charges the capacitor above the minimum operating voltage of the device and the charge pump and internal 15.6V zener clamp of the IC take over as the supply voltage. The start-up capacitor and snubber capacitor must be selected such that worst case IC conditions are satisfied. A bootstrap diode (D3) and supply capacitor (C3) comprise the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During UVLO, the high and low side driver outputs are low, pin VCO is pulled-up internally to 5V resetting the starting frequency to the maximum, and pin CPH is short-circuited internally to COM resetting the preheat time. 15 IR21592/IR21593(S) Brown-out Protection VBUS(+) In addition to the voltage on VCC being above the start-up threshold, pin VDC must also be above 5.1V for HO and LO to begin oscillating. A voltage divider (R3,RVDC) from the rectified AC line connected to pin VDC measures the rectified AC line input voltage to the ballast and programs the turn-on and turn-off line voltages. A filter capacitor (CVDC) is also connected to pin VDC that must be chosen such that the ripple is low enough and the lower turn-off threshold of 3V is not crossed during normal line conditions. This detection is necessary due to the possibility of the lamp extinguishing during low-line conditions before the IC is properly reset. Should a brownout occur, the DC bus can drop to a level below the minimum required for the tank circuit to maintain the necessary lamp voltage. This detection will insure a clean turn-off before the DC bus drops too low and properly resets the IC to the preheat mode when the line returns. Preheat (PH) The IR21592/IR21593 enters preheat mode when VCC exceeds the UVLO+ threshold and VDC exceeds 5.1V. HO and LO begin to oscillate at the maximum operating frequency with 50% duty cycle and at the internally set dead-time of 2us (IR21592) or 1s (IR21593). Pin CPH is disconnected from COM and an internal 1uA current source (Figure 7) charges the external timing capacitor on CPH linearly. 16 60uA HO VCO 16 VCO 2 Q2 CVCO Half Bridge Output 1uA Half Bridge Driver VS 15 ILOAD 1uA CPH PH LOGIC 3 CCPH 7.6V FMIN LO 11 Q2 IFMIN 7 RFMIN 5.1V CS 10 RCS COM 1/RFMIN IPH 12 8 RIPH IR21592/IR21593 Load Return VBUS(-) Figure 7, IR21592/IR21593 preheat circuitry. An internal 1uA current source slowly discharges the external capacitor on pin VCO and the voltage on pin VCO begins to decrease. This decreases the frequency, which, for operating frequencies above resonance, increases the load current. When the peak voltage measured on pin CS, produced by a portion of the load current flowing through an external sense resistor (RCS), exceeds the voltage level on pin IPH, a 60uA internal current source is connected to pin VCO and the capacitor charges (Figure 8). This forces the frequency to increase and the load current to decrease. When the voltage on pin CS decreases below the voltge on pin IPH, the 60uA current source is disconnected and the frequency decreases again. www.irf.com IR21592/IR21593(S) HO VBUS(+) LO VS HO VCO 16 VCO 2 Q2 CVCO Half Bridge Output 1uA VRCS t PH LOGIC 1uA CPH VIPH Half Bridge Driver VS 15 ILOAD 3 CCPH t RDIM 11 7.6V DIM 0.5 to 5V LO Q2 DIM INTERFACE 4 FAULT LOGIC CS 1.6V 10 RCS PHASE CONTROL ICVCO COM 12 IR21592/IR21593 60uA Load Return VBUS(-) -1uA t Figure 9, IR21592/IR21593 ignition circuitry. VCVCO t Figure 8, Peak load current regulation timing diagram. This feedback keeps the peak preheat current regulated to the user-programmable setting on pin IPH for the duration of the preheat time. An internal current source connected to an external resistor on pin IPH sets a voltage reference for the peak pre-heat current. The pre-heat time continues until the voltage on pin CPH exceeds 5V. Ignition (IGN) The IR21592/IR21593 enters ignition mode when the voltage on pin CPH exceeds 5V. The peak current regulation reference voltage is disconnected from the user-programmable setting on pin IPH and is connected to a higher internal threshold of 1.6V (Figure 9). www.irf.com The ignition ramp is then initiated as the capacitor on pin VCO discharges linearly through an internal 1uA current source. The frequency decreases linearly towards the resonance frequency of the high-Q ballast output stage, causing the lamp voltage and load current to increase (Figure 10). The frequency continues to decrease until the lamp ignites or the current limit of the IR21592/IR21593 is reached. If the current limit is reached, the IR21592/IR21593 enters FAULT mode. The 1.6V threshold together with the external current sensing resistor on pin CS determine the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs or IGBTs, and, the resonant inductor must not saturate at any time. To prevent a "flash" across the lamp during ignition at low dim settings, an ignition detection 17 IR21592/IR21593(S) circuit measures the voltage at the CS pin and compares it against the voltage at the IPH pin. During the rising ignition ramp, the voltage at the IPH pin is increased to 20% above its value load current is regulated against the user control input on pin DIM. To control the rate at which the dim setting changes from maximum brightness to the user setting (IGN-TO-DIM time, Figure 11), VCPH CS 5.1V VIPH + 20% R DIM & C TPH TIME CONSTANT VIPH + 10% VIPH VDIM t VVCO IGN-TO-DIM TIME t PH IGN DIM PH DIM IGN Figure 10, IR21592/IR21593 ignition detection. Figure 11, IR21592/IR21593 ignition timing diagram. during preheat mode. When the voltage on the CS pin exceeds this voltage, the voltage on the IPH pin is decreased to VIPH Pre-Heat +10% and the ignition detection circuit is then active (See Figure 10). When the lamp ignites, the voltage on the CS pin will then fall below the voltage on the IPH pin and the IC enters DIM Mode and the phase control loop is closed. In order for the ignition detection circuit to function properly and for the IC to enter DIM mode, the voltage on the CS pin must first rise above VIPH Pre-Heat + 20% during the ignition ramp to activate the circuit, and then decrease below VIPH Pre-Heat +10% when the lamp ignites. pin DIM is connected internally to pin CPH when the IR21592/IR21593 enters DIM mode. The resistor on pin DIM (RDIM) discharges the capacitor on pin CPH down to the user dim setting. The resistor can be selected for a fast time constant to minimize the amount of flash visible over the lamp just after ignition, or, a long time constant such that the brightness ramps down smoothly to the user setting. Should the ignition-to-dim time be too fast, however, the loop can respond faster than the ionization constant of the lamp (milliseconds) causing the VCO to over-shoot. This can result in a frequency that is higher than the minimum brightness frequency and can extinguish the lamp. The capacitor on pin CPH serves multiple functions by setting the preheat time, the travel rate just after ignition (together with resistor RDIM), and, serving as a filter capacitor on pin Ignition-to-Dim (IGN-to-DIM) When the IR21592/IR21593 enters dim mode, the phase control loop is closed and the phase of the 18 www.irf.com IR21592/IR21593(S) DIM during dimming to increase high-frequency noise immunity and minimize component count. V CS Dimming (DIM) To regulate lamp power, the error between the reference phase and the phase of the output stage current forces the VCO to steer the frequency in the proper direction, as determined by the transfer function of the output stage, such that the error is forced to zero. An internal 15uA current source is connected to pin VCO during dimming mode (Figure 12) to discharge the VCO capacitor and decrease the frequency towards lock. t LO REF FB ERR V VCO VBUS(+) IR2159 VCC RFB VCO t HO 16 VCO 2 Q2 Half Bridge Output 16uA CVCO Half Bridge Driver VS 15 ILOAD CPH 3 CCPH LO 11 DIM INTERFACE 7.6V Q2 DIM 0.5 to 5V 4 RDIM MAX FAULT LOGIC 5 RMAX MIN RMIN 6 CS 1.6V 10 RCS PHASE CONTROL COM 12 Load Return VBUS(-) Figure 13, Phase control timing diagram. The IR21592/IR21593 includes a dimming interface for analog lamp power control. The DIM pin input requires a voltage in the range of 0.5 to 5VDC, with 5V corresponding to minimum phase shift (maximum lamp power). The output of the dim interface is the voltage on pin MIN, which is compared with the internal timing capacitor (CT) voltage to produce a frequencyindependent digital reference phase (Figure 14). Figure 12, IR21592/IR21593 dimming circuitry. Once lock is achieved, the phase detector (PDET) outputs short pulses to an open-drain PMOS that charges the VCO capacitor through an internal resistor (RFB) each time an error pulse occurs (Figure 13). This action "nudges" the integrator at the input of the VCO to keep the phase of the output stage current exactly locked in phase with the reference. www.irf.com 19 IR21592/IR21593(S) detection comparator for 400ns after LO goes 'high' (Figure 16). VMIN 5V VCT RMIN VBUS(+) R MAX 3V IR2159 HO 1V 16 Q2 DIM RANGE 0 0.5V VDIM USER SETTING Half Bridge Driver 5V LO Half Bridge Output VS 15 ILOAD REF LO 11 0 -90 -180 Q2 FAULT LOGIC 1.6V CS R1 10 Figure 14, Dimming interface RCS PHASE CONTROL The charging time of CT from 1V to 5.1V determines the on-time of output gate drivers HO and LO and corresponds to -180 degrees of possible phase shift in load current (minus deadtime). For the 0 to -90 degree dim range, the voltage on pin MIN is bounded between 1V and 3V using pins MIN and MAX. An external resistor on pin MAX programs the minimum phase shift reference (maximum lamp power) corresponding to 5V on pin DIM, and an external resistor on pin MIN sets the maximum phase shift (minimum lamp power) corresponding to 0.5V on pin DIM. Current Sensing During dimming, the current sensing circuitry (Figure 15) detects over-current which can occur during hard-switching (see Fault section), and zero-crossing to measure the phase of the total load current. To reject any switching noise which can occur at the turn-on of the low-side MOSFET or IGBT, a digital current sense blanking circuit blanks out the signal from the zero-crossing 20 400ns BLANK COM 12 Load Return VBUS(-) Figure 15, Current sensing circuitry. The internal blank time reduces the dimming range slightly (Figure 16) when operating at minimum phase shift (maximum lamp power). The external programming resistor on pin MAX must be selected such that the minimum phase shift is set a safe margin away from the blank time. A series resistor (R1) is required to limit the amount of current flowing out of pin CS when the voltage across RCS goes below -0.7V. A filter capacitor at pin CS may be required due to other possible asynchronous noise sources present in the ballast system. www.irf.com IR21592/IR21593(S) VCS Switching Noise t LO Should the peak voltage on pin CS exceed 1.6V at any time during dimming, the IR21592/IR21593 enters FAULT mode and the high and low-side driver outputs, HO and LO, are both turned off. Cycling the supply voltage on VCC below UVLOor the voltage on pin SD above and below SD+ and SD- will reset the IR21592/IR21593 to preheat (PH) mode (see STATE DIAGRAM). BLANK Ballast Design Dimming Range Lamp Requirements Figure 16, Current sense timing diagram. Fault Mode (FAULT) During dimming, the peak current regulation circuit active during preheat and ignition is disabled. Should non-zero voltage switching at the output of the half-bridge occur (Figure 17), high current spikes will result. A lamp filament failure, lamp end-of-life, lamp removal, or a deadtime shorter than what is required for commutation, can all cause hard-switching. LOAD REMOVAL HO LO VS t VCS 1.6V t NORMAL OPERATION HARD SWITCHING Before selecting component values for the ballast output stage and the programmable inputs of the IR21592/IR21593, the following lamp requirements must first be defined: Variable I ph t ph Description Filament pre-heat current Filament pre-heat time Units Arms s Maximum lamp pre-heat voltage Vpp Vign Lamp ignition voltage Vpp P100% Lamp power at 100% brightness W V100% Lamp voltage at 100% brightness Vpp V phmax P1% Lamp power at 1% brightness W V1% Lamp voltage at 1% brightness Vpp Minimum cathode heating current Arms I Cathmin Table I, Typical lamp requirements FAULT Figure 17, hard-switching with latch off www.irf.com 21 IR21592/IR21593(S) Ballast Output Stage The operating frequency [Hz] at maximum lamp power is given as: The components comprising the output stage are selected using a set of equations. Different ballast operating frequencies and their respective voltages and currents are calculated. The inductor and capacitor values are obtained using equations (2) through (7). The results of these equations reveal the location of each operating frequency and the corresponding voltages and currents. For a given L, C, DC bus voltage, and pre-heat current, the resulting voltage over the lamp during pre-heat is given as: 1 2 2V 2V 8L 2 I ph - DC (2) V ph = DC + C 2 The resulting operating frequency during pre-heat is given as: f ph = 2I ph [Hz] CVph (3) 2 f100% = 2 1 1 32P100 - 2 4% 2 LC C V100% 4V 1 - DC 2 V100% 1 32P100 % + - 2 4 - 2 2 L C LC C V 100% f ign = 1 2 1+ 4 I Cath1% = V1% f1%C 2 (7) Design Constraints The inductor and capacitor values should be iterated until the following design constraints have been fulfilled (Table II). Design Constraint Reason V ph < V phmax Ignition during preheat Production tolerances f ph - f ign > 5kHz I ign < I ignmax Inductor saturation Lamp extinguishing during dimming Table II, Ballast design constraints VDC Vign LC IR21592/IR21593 Programmable Inputs [Hz] (4) The total load current during ignition is given as: Iign = f ign CVign 2 22 (6) The cathode heating current at minimum lamp power is given as: I Cath1% I Cathmin The resulting operating frequency during ignition is given as: 2 [App] (5) In order to program the MIN and MAX settings of the dimming interface, the phase of the output stage current at minimum and maximum lamp power must be calculated. This is obtained using the following equations: www.irf.com IR21592/IR21593(S) 2 4VDC 2 1- V 2 2 1 32P% 1 1 32P% % - + - 2 4 - f% = 2 LC C2V%4 L2C2 LC C V% % = 180 -1 V%2 2P V2 tan [( C - 2% L)2f% - 4 % LC23 f%3] 2P% V% P% (8) (9) With the lamp requirements defined, the L and C of the ballast output stage selected, and the minimum and maximum phase calculated, the component values for setting the programmable inputs of the IR21592/IR21593 are obtained with the following equations: R FMIN = RCS = (25e - 6) - ( f MIN - 10000) (1e - 10) ( f MIN - 10000) (2e - 14) [Ohms] (10) 2 (1.6) I ign [Ohms] (11) RIPH = RFMIN RCS I ph 2 [Ohms] (12) C CPH = (2.6 E - 7)(t PH ) [Farads] (13) [Ohms] (14) RMIN = RMAX = R FMIN 1% 1 - 4 45 0.86 RFMIN RMIN 4 RMIN - RFMIN 1 - 100% 45 [Ohms] www.irf.com (15) 23 IR21592/IR21593(S) This ballast design procedure has been summarized into the following 3 steps: Define Lamp Requirements Iterate L and C to fulfill constraints Calculate IR21592/IR21593 IR2159 Programmable Inputs Figure 19, Simplified Ballast Design Procedure Case outline 16 Lead PDIP 24 01-6015 01-3065 00 (MS-001A) www.irf.com IR21592/IR21593(S) 16 -Lead SOIC (narrow body) 01-6018 01-3064 00 (MS-012AC) IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. This product has been designed and qualfied for the industrial market. 11/13/2003 www.irf.com 25