1
FEATURES
DESCRIPTION/ORDERING INFORMATION
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
ASYNCHRONOUS COMMUNICATIONS ELEMENTWITH AUTOFLOW CONTROL
Programmable Auto- RTS and Auto- CTS Standard Asynchronous Communication Bits(Start, Stop, and Parity) Added to or DeletedIn Auto- CTS Mode, CTS Controls Transmitter
From the Serial Data StreamIn Auto- RTS Mode, RCV FIFO Contents and
5-V, 3.3-V, and 2.5-V OperationThreshold Control RTS
Independent Receiver Clock InputSerial and Modem Control Outputs Drive aRJ11 Cable Directly When Equipment Is on the Transmit, Receive, Line Status, and Data SetSame Power Drop Interrupts Independently ControlledCapable of Running With All Existing Fully Programmable Serial InterfaceTL16C450 Software Characteristics:After Reset, All Registers Are Identical to the 5-, 6-, 7-, or 8-Bit CharactersTL16C450 Register Set
Even-, Odd-, or No-Parity Bit GenerationUp to 24-MHz Clock Rate for up to 1.5-Mbaud and DetectionOperation With V
CC
= 5 V
1-, 1 -, or 2-Stop Bit GenerationUp to 20-MHz Clock Rate for up to 1.25-Mbaud
Baud Generation (dc to 1 Mbit/s)Operation With V
CC
= 3.3 V
False-Start Bit DetectionUp to 48-MHz Clock Rate for up to 3-Mbaud
Complete Status Reporting CapabilitiesOperation with V
CC
= 3.3 V (ZQS Package Only,
3-State Output TTL Drive Capabilities forDivisor = 1)
Bidirectional Data Bus and Control BusUp to 40-MHz Clock Rate for up to 2.5-Mbaud
Line Break Generation and DetectionOperation with V
CC
= 3.3 V (ZQS Package Only,
Internal Diagnostic Capabilities:Divisor 2)
Loopback Controls for CommunicationsUp to 16-MHz Clock Rate for up to 1-Mbaud
Link Fault IsolationOperation With V
CC
= 2.5 V
Break, Parity, Overrun, and Framing ErrorIn the TL16C450 Mode, Hold and Shift
SimulationRegisters Eliminate the Need for PreciseSynchronization Between the CPU and Serial Fully Prioritized Interrupt System ControlsData
Modem Control Functions ( CTS, RTS, DSR,Programmable Baud Rate Generator Allows DTR, RI, and DCD)Division of Any Input Reference Clock by 1 to
Available in 48-Pin PT, 48-Pin PFB, 32-Pin(2
16
1) and Generates an Internal 16 × Clock
RHB, and 24-Pin ZQS Packages
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) ofthe TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of theTL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), theTL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relievesthe CPU of excessive software overhead by buffering received and transmitted characters. The receiver andtransmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiverFIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce softwareoverload and increase system efficiency by automatically controlling serial data flow using RTS output and CTSinput signals.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
NC - No internal connection
NC
NC
RD1
VSS
WR1
XOUT
XIN
NC
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
DSR
DCD
RI
VCC
D0
D1
D2
D3
RHB PACKAGE
(TOP VIEW)
A2
23 22 21 20 19
24 18
CTS
MR
DTR
RTS
INTRPT
A0
17
A1
2 3 4 5 6 7 8
1
D5
D6
D7
SOUT
CS2
D4
NC
SIN
NC - No internal connection
14 15
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
17 18 19 20
PT/PFB PACKAGE
(TOP VIEW)
RI
DCD
DSR
CTS
47 46 45 44 4348 42
NC
D4
D3
D2
D1
D0
DDIS
TXRDY
ADS
XOUT
WR1
WR2
RD1
RD2
NC
40 39 3841
21 22 23 24
37
13
NC
NC
VCC
XIN
VSS
A
ZQS PACKAGE
(TOP VIEW)
1 2 345
B
C
D
E
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
www.ti.com
The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheraldevice or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACEstatus at any time. The ACE includes complete modem control capability and a processor interrupt system thatcan be tailored to minimize software management of the communications link.
Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of dividinga reference clock by divisors from 1 to 65535 and producing a 16 × reference clock for the internal transmitterlogic. Provisions are included to use this 16 × clock for the receiver logic. The ACE accommodates up to a1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is 6.7 µs (startbit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to TXRDYand RXRDY, which provide signaling to a DMA controller.
The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This isaccomplished by eliminating some signals that are not required for some applications. These include the CS0,CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUToutput signals. There is an internal connection between BAUDOUT and RCLK.
All of the functionality of the TL16C550D is maintained in the RHB package.
TERMINAL ASSIGNMENTS(24-Ball ZQS Package) (continued)
(24-Ball ZQS Package)
1 2 3 4 5
AD5 D4 D2 D0 V
CC
BD7 D3 D1 MR
CSIN SOUT D6 CTS RTS
DCS2 WR1 RD1 INTRPT A0
EXIN XOUT V
SS
A2 A1
TERMINAL ASSIGNMENTS
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Product Folder Link(s): TL16C550D TL16C550DI
DETAILED DESCRIPTION
Autoflow Control (see Figure 1 )
Auto- RTS (see Figure 1 )
Auto- CTS (see Figure 1 )
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
The TL16C550D is being made available in a reduced pin count package, the 24-pin ZQS package. This isaccomplished by eliminating some signals that are not required for some applications. These include the CS0,CS1, ADS, RD2, WR2, DSR, RI, DCD, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2,DTR, and BAUDOUT output signals. There is an internal connection between BAUDOUT and RCLK.
Most of the functionality of the TL16C550D is maintained in the ZQS package, except that which involves theeliminated signals.
Autoflow control comprises auto- CTS and auto- RTS. With auto- CTS, the CTS input must be active before thetransmitter FIFO can emit data. With auto- RTS, RTS becomes active when the receiver needs more data andnotifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless thereceiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from aTLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceedsthe receiver FIFO read latency.
Figure 1. Autoflow Control (Auto- RTS and Auto- CTS) Example
Auto- RTS data flow control originates in the receiver timing and control block (see functional block diagram) andis linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of1, 4, or 8 (see Figure 3 ), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send anadditional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because itmay not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS isautomatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4 ), RTS is deasserted after the first data bit of the 16th character ispresent on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the nextbyte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the laststop bit that is currently being sent (see Figure 2 ). The auto- CTS function reduces interrupts to the host system.When flow control is enabled, CTS level changes do not trigger host interrupts because the device automaticallycontrols its own transmitter. Without auto- CTS, the transmitter sends any data present in the transmit FIFO and areceiver overrun error may result.
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Enabling Autoflow Control and Auto- CTS
Auto- CTS and Auto- RTS Functional Timing
Byte 18
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
www.ti.com
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 ( RTS) to a 1.Autoflow incorporates both auto- RTS and auto- CTS. When only auto- CTS is desired, bit 1 in the modem controlregister must be cleared (this assumes that a control signal is driving CTS).
A. When CTS is low, the transmitter keeps sending serial data out.B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the currentbyte but it does not send the next byte.C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 3 and Figure 4 .
A. N = RCV FIFO trigger level (1, 4, or 8 bytes)B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the precedingauto- RTS section.
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full afterfinishing the sixteenth byte.B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing orthere is more than one byte of space available.C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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Product Folder Link(s): TL16C550D TL16C550DI
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
BAUDOUT
SIN
RCLK
SOUT
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRPT
38
33
39
40
41
34
31
30
8
5
7
12
9
A0 28
D(7- 0)
4-2
47-43
Internal
Data Bus
27
26
10
11
24
35
19
20
16
17
22
23
14
15
29
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
RXRDY
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
42
18
VCC
VSS
Power
Supply
RTS
32
Autoflow Control
(AFE)
8
8
8
8
8
8
8
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
FUNCTIONAL BLOCK DIAGRAM (For PT and PFB Packages)
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TL16C550D TL16C550DI
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
SIN
SOUT
CTS
DTR
DSR
DCD
RI
INTRPT
24
22
25
26
27
20
7
6
A0 19
D(7- 0)
5-3
32-29
Internal
Data Bus
18
17
8
23
14
12
10
11
A1
A2
CS2
MR
RD1
WR1
XIN
XOUT
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
28
13
VCC
VSS
Power
Supply
RTS
21
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
www.ti.com
FUNCTIONAL BLOCK DIAGRAM (For RHB Package)
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Product Folder Link(s): TL16C550D TL16C550DI
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
SIN
SOUT
CTS
INTRPT
C4
D4
C2
C1
A0 D5
D(7- 0)
5-3
32-29
Internal
Data Bus
E5
E4
D1
B5
D3
D2
E1
E2
A1
A2
CS2
MR
RD1
WR1
XIN
XOUT
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
A5
E3
VCC
VSS
Power
Supply
RTS
C5
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
FUNCTIONAL BLOCK DIAGRAM (For ZQS Package)
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TL16C550D TL16C550DI
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES)
TERMINAL
I/O DESCRIPTIONNAME NO.
A0 28
Register select. A0 A2 are used during read and write operations to select the ACE registerA1 27 I
to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 26
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive theADS 24 I internal select logic directly; when ADS is high, the register select and chip select signals areheld at the logic levels they were in when the low-to-high transition of ADS occurred.Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clockrate is established by the reference oscillator frequency divided by a divisor specified by theBAUDOUT 12 O
baud generator divisor latches. BAUDOUT may also be used for the receiver section by tyingthis output to RCLK.CS0 9
Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE.CS1 10 I
When any of these inputs are inactive, the ACE remains inactive (see the ADS description).CS2 11
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS 38 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 43D1 44D2 45D3 46 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 47 and status information between the ACE and the CPU.D5 2D6 3D7 4
Data carrier detect. DCD is a modem status signal. Its condition can be checked by readingbit 7 ( DCD) of the modem status register. Bit 3 ( ΔDCD) of the modem status registerDCD 40 I
indicates that DCD has changed states since the last read from the modem status register. Ifthe modem status interrupt is enabled when DCD changes levels, an interrupt is generated.Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDISDDIS 22 O
can disable an external transceiver.Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5( DSR) of the modem status register. Bit 1 ( ΔDSR) of the modem status register indicatesDSR 39 I
DSR has changed levels since the last read from the modem status register. If the modemstatus interrupt is enabled when DSR changes levels, an interrupt is generated.Data terminal ready. When active (low), DTR informs a modem or data set that the ACE isready to establish communication. DTR is placed in the active level by setting the DTR bit ofDTR 33 O
the modem control register. DTR is placed in the inactive level either as a result of a masterreset, during loop mode operation, or clearing the DTR bit.Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to beserviced. Four conditions that cause an interrupt to be issued are: a receiver error, receivedINTRPT 30 O data that is available or timed out (FIFO mode only), an empty transmitter holding register, oran enabled modem status interrupt. INTRPT is reset (deactivated) either when the interruptis serviced or as a result of a master reset.Master reset. When active (high), MR clears most ACE registers and sets the levels ofMR 35
various output signals (see Table 2).1,6,13,NC 21, 25, 36, I No connection37, 48
Outputs 1 and 2. These are user-designated output terminals that are set to the active (low)OUT1 34 level by setting respective modem control register (MCR) bits ( OUT1 and OUT2). OUT1 andOOUT2 31 OUT2 are set to inactive the (high) level as a result of master reset, during loop modeoperations, or by clearing bit 2 ( OUT1) or bit 3 ( OUT2) of the MCR.RCLK 5 I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE.Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE isRD1 19 selected, the CPU is allowed to read status information or data from a selected ACE register.IRD2 20 Only one of these inputs is required for the transfer of data during a read operation; the otherinput must be tied to its inactive level (i.e., RD2 tied low or RD1 tied high).
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TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES) (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6( RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RIRI 41 I has transitioned from a low to a high level since the last read from the modem statusregister. If the modem status interrupt is enabled when this transition occurs, an interrupt isgenerated.
Request to send. When active, RTS informs the modem or data set that the ACE is ready toreceive data. RTS is set to the active level by setting the RTS modem control register bit andRTS 32 O is set to the inactive (high) level either as a result of a master reset or during loop modeoperations or by clearing bit 1 ( RTS) of the MCR. In the auto- RTS mode, RTS is set to theinactive level by the receiver threshold control logic.Receiver ready. Receiver direct memory access (DMA) signaling is available with RXRDY.When operating in the FIFO mode, one of two types of DMA signaling can be selected usingthe FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMAmode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is madebetween CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers aremade continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 orRXRDY 29 O
FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiverholding register, RXRDY is active (low). When RXRDY has been active but there are nocharacters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDYgoes active (low); when it has been active but there are no more characters in the FIFO orholding register, it goes inactive (high).SIN 7 I Serial data input. SIN is serial data input from a connected communications device.Serial data output. SOUT is composite serial data output to a connected communicationSOUT 8 O
device. SOUT is set to the marking (high) level as a result of master reset.Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating inthe FIFO mode, one of two types of DMA signaling can be selected using FCR3. Whenoperating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supportsTXRDY 23 O
single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supportsmultitransfer DMA in which multiple transfers are made continuously until the transmit FIFOhas been filled.V
CC
42 2.25-V to 5.5-V power supply voltageV
SS
18 Supply common
Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while theWR1 16 ACE is selected, the CPU is allowed to write control words or data into a selected ACEIWR2 17 register. Only one of these inputs is required to transfer data during a write operation; theother input must be tied to its inactive level (i.e., WR2 tied low or WR1 tied high).XIN 14 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT 15 crystal).
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TL16C550D TL16C550DI
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS (FOR RHB PACKAGE)
TERMINAL
I/O DESCRIPTIONNAME NO.
A0 19
Register select. A0 A2 are used during read and write operations to select the ACE registerA1 18 I
to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 17
Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE.CS2 8 I
When any of these inputs are inactive, the ACE remains inactive (see the ADS description).Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS 24 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 29D1 30D2 31D3 32 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 1 and status information between the ACE and the CPU.D5 3D6 4D7 5
Data carrier detect. DCD is a modem status signal. Its condition can be checked by readingbit 7 ( DCD) of the modem status register. Bit 3 ( ΔDCD) of the modem status registerDCD 26 I
indicates that DCD has changed states since the last read from the modem status register. Ifthe modem status interrupt is enabled when DCD changes levels, an interrupt is generated.Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5( DSR) of the modem status register. Bit 1 ( ΔDSR) of the modem status register indicatesDSR 39 I
DSR has changed levels since the last read from the modem status register. If the modemstatus interrupt is enabled when DSR changes levels, an interrupt is generated.Data terminal ready. When active (low), DTR informs a modem or data set that the ACE isready to establish communication. DTR is placed in the active level by setting the DTR bit ofDTR 33 O
the modem control register. DTR is placed in the inactive level either as a result of a masterreset, during loop mode operation, or clearing the DTR bit.Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to beserviced. Four conditions that cause an interrupt to be issued are: a receiver error, receivedINTRPT 30 O data that is available or timed out (FIFO mode only), an empty transmitter holding register, oran enabled modem status interrupt. INTRPT is reset (deactivated) either when the interruptis serviced or as a result of a master reset.Master reset. When active (high), MR clears most ACE registers and sets the levels ofMR 35
various output signals (see Table 2).2,9,NC I No connection15, 16,
Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE isRD1 14 I
selected, the CPU is allowed to read status information or data from a selected ACE register.Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6( RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RIRI 27 I has transitioned from a low to a high level since the last read from the modem statusregister. If the modem status interrupt is enabled when this transition occurs, an interrupt isgenerated.
Request to send. When active, RTS informs the modem or data set that the ACE is ready toreceive data. RTS is set to the active level by setting the RTS modem control register bit andRTS 21 O is set to the inactive (high) level either as a result of a master reset or during loop modeoperations or by clearing bit 1 ( RTS) of the MCR. In the auto- RTS mode, RTS is set to theinactive level by the receiver threshold control logic.SIN 6 I Serial data input. SIN is serial data input from a connected communications device.Serial data output. SOUT is composite serial data output to a connected communicationSOUT 7 O
device. SOUT is set to the marking (high) level as a result of master reset.V
CC
28 2.25-V to 5.5-V power supply voltageV
SS
13 Supply common
Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while theWR1 12 I ACE is selected, the CPU is allowed to write control words or data into a selected ACEregister.
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.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
TERMINAL FUNCTIONS (FOR RHB PACKAGE) (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
XIN 10 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT 11 crystal).
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TERMINAL FUNCTIONS (FOR ZQS PACKAGE)
TERMINAL
I/O DESCRIPTIONNAME NO.
A0 D5
Register select. A0 A2 are used during read and write operations to select the ACE registerA1 E5 I
to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 E4
Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remainsCS2 D1 I
inactive.
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS C4 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 A4D1 B4D2 A3D3 B3 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 A2 and status information between the ACE and the CPU.D5 A1D6 C3D7 B1
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to beserviced. Four conditions that cause an interrupt to be issued are: a receiver error, receivedINTRPT D4 O data that is available or timed out (FIFO mode only), an empty transmitter holding register, oran enabled modem status interrupt. INTRPT is reset (deactivated) either when the interruptis serviced or as a result of a master reset.Master reset. When active (high), MR clears most ACE registers and sets the levels ofMR B5
various output signals (see Table 2).Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to readRD1 D3 I
status information or data from a selected ACE register.Request to send. When active, RTS informs the modem or data set that the ACE is ready toreceive data. RTS is set to the active level by setting the RTS modem control register bit andRTS C5 O is set to the inactive (high) level either as a result of a master reset or during loop modeoperations or by clearing bit 1 ( RTS) of the MCR. In the auto- RTS mode, RTS is set to theinactive level by the receiver threshold control logic.SIN C1 I Serial data input. SIN is serial data input from a connected communications device.Serial data output. SOUT is composite serial data output to a connected communicationSOUT C2 O
device. SOUT is set to the marking (high) level as a result of master reset.V
CC
A5 2.25-V to 5.5-V power supply voltageV
SS
E3 Supply common, groundWrite input. When WR1 is active (low) and while the ACE is selected, the CPU is allowed toWR1 D2 I
write control words or data into a selected ACE register.XIN E1 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT E2 crystal).
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
3.3 V ± 10%
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.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range
(2)
0.5 7 VV
I
Input voltage range at any input 0.5 7 VV
O
Output voltage range 0.5 7 VTL16C550D 0 70T
A
Operating free-air temperature range ° CTL16C550DI 40 85T
stg
Storage temperature range 65 150 ° CLead temperature 1.6 mm (1/16 inch) from case for 10 seconds PT/PFB packages 260 ° C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values with respect to V
SS
.
2.5 V ± 10%
MIN NOM MAX UNIT
V
CC
Supply voltage 2.25 2.5 2.75 VV
I
Input voltage 0 V
CC
VV
IH
High-level input voltage 1.8 2.75 VV
IL
Low-level input voltage 0.3 0.6 VV
O
Output voltage 0 V
CC
VI
OH
High-level output current (all outputs) 1 mAI
OL
Low-level output current (all outputs) 2 mAOscillator/clock speed 16 MHz
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
I
Input voltage 0 V
CC
VV
IH
High-level input voltage 0.7 × V
CC
VV
IL
Low-level input voltage 0.3 × V
CC
VV
O
Output voltage 0 V
CC
VI
OH
High-level output current (all outputs) 1.8 mAI
OL
Low-level output current (all outputs) 3.2 mAOscillator/clock speed 20 MHzOscillator/clock speed (ZQS package only) 48 MHz
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5 V ± 10%
ELECTRICAL CHARACTERISTICS
TL16C550D , , TL16C550DI
SLLS597E APRIL 2004 REVISED DECEMBER 2008 ..................................................................................................................................................
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MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 VV
I
Input voltage 0 V
CC
VExcept XIN 2V
IH
High-level input voltage VXIN 0.7 × V
CC
Except XIN 0.8V
IL
Low-level input voltage V0.3 ×XIN
V
CC
V
O
Output voltage 0 V
CC
VI
OH
High-level output current (all outputs) 4 mAI
OL
Low-level output current (all outputs) 4 mAOscillator/clock speed 24 MHz
2.5 V Nominal
over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OH
High-level output voltage
(2)
I
OH
= 1 mA 1.8 VV
OL
Low-level output voltage
(2)
I
OL
= 2 mA 0.5 VV
CC
= 3.6 V, V
SS
= 0,I
I
Input current V
I
= 0 to 3.6 V, All other terminals 10 µAfloatingV
CC
= 3.6 V, V
SS
= 0,High-impedance-state output
V
I
= 0 to 3.6 V,I
OZ
± 20 µAcurrent
Chip selected in write mode or chip deselectV
CC
= 3.6 V, T
A
= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I
CC
Supply current 8 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC
i(CLK)
Clock input capacitance 15 20 pFV
CC
= 0,C
o(CLK)
Clock output capacitance 20 30 pFf = 1 MHz, V
SS
= 0,All other terminals T
A
= 25 ° CC
i
Input capacitance 6 10 pFgroundedC
o
Output capacitance 10 10 pF
(1) All typical values are at V
CC
= 2.5 V and T
A
= 25 ° C.(2) These parameters apply for all outputs except XOUT.
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3.3 V Nominal
5 V Nominal
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.................................................................................................................................................. SLLS597E APRIL 2004 REVISED DECEMBER 2008
over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OH
High-level output voltage
(2)
I
OH
= 1 mA 2.4 VV
OL
Low-level output voltage
(2)
I
OL
= 2 mA 0.5 VV
CC
= 3.6 V, V
SS
= 0,I
I
Input current V
I
= 0 to 3.6 V, All other terminals 10 µAfloatingV
CC
= 3.6 V, V
SS
= 0,High-impedance-state output
V
I
= 0 to 3.6 V,I
OZ
± 20 µAcurrent
Chip selected in write mode or chip deselectV
CC
= 3.6 V, T
A
= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I
CC
Supply current 8 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC
i(CLK)
Clock input capacitance 15 20 pFV
CC
= 0,C
o(CLK)
Clock output capacitance 20 30 pFf = 1 MHz, V
SS
= 0,All other terminals T
A
= 25 ° CC
i
Input capacitance 6 10 pFgroundedC
o
Output capacitance 10 20 pF
(1) All typical values are at V
CC
= 3.3 V and T
A
= 25 ° C.(2) These parameters apply for all outputs except XOUT.
over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OH
High-level output voltage
(2)
I
OH
= 1 mA 4.0 VV
OL
Low-level output voltage
(2)
I
OL
= 2 mA 0.4 VV
CC
= 3.6 V, V
SS
= 0,I
I
Input current V
I
= 0 to 3.6 V, All other terminals 10 µAfloatingV
CC
= 3.6 V, V
SS
= 0,High-impedance-state output
V
I
= 0 to 3.6 V,I
OZ
± 20 µAcurrent
Chip selected in write mode or chip deselectV
CC
= 3.6 V, T
A
= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I
CC
Supply current 10 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC
i(CLK)
Clock input capacitance 15 20 pFV
CC
= 0,C
o(CLK)
Clock output capacitance 20 30 pFf = 1 MHz, V
SS
= 0,All other terminals T
A
= 25 ° CC
i
Input capacitance 6 10 pFgroundedC
o
Output capacitance 10 20 pF
(1) All typical values are at V
CC
= 5 V and T
A
= 25 ° C.(2) These parameters apply for all outputs except XOUT.
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SYSTEM TIMING REQUIREMENTS
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over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT
t
cR
Cycle time, read (t
w7
+ t
d8
+ t
d9
) RC 87 nst
cW
Cycle time, write (t
w6
+ t
d5
+ t
d6
) WC 87 nsf = 16 MHz Max, V
CC
= 2.5 V,
25See Figure 5f = 20 MHz Max, V
CC
= 3.3 V,
20See Figure 5t
w1
Pulse duration, clock high t
XH
nsf = 24 MHz Max, V
CC
= 5 V,
18See Figure 5f = 48 MHz Max, V
CC
= 3.3 V,See Figure 5 8(ZQS package only)f = 16 MHz Max, V
CC
= 2.5 V,
25See Figure 5f = 20 MHz Max, V
CC
= 3.3 V,
20See Figure 5t
w2
Pulse duration, clock low t
XL
nsf = 24 MHz Max, V
CC
= 5 V,
18See Figure 5f = 48 MHz Max, V
CC
= 3.3 V,See Figure 5 8(ZQS package only)t
w5
Pulse duration, ADS low tADS See Figure 6 and Figure 7 9 nst
w6
Pulse duration, WR t
WR
See Figure 6 40 nst
w7
Pulse duration, RD t
RD
See Figure 7 40 nst
w8
Pulse duration, MR t
MR
1µst
su1
Setup time, address valid before ADSt
AS
See Figure 6 and Figure 7 8 nst
su2
Setup time, CS valid before ADSt
CS
t
su3
Setup time, data valid before WR1or WR2 tDS See Figure 6 15 nst
su4
Setup time, CTSbefore midpoint of stop bit See Figure 17 10 nst
h1
Hold time, address low after ADSt
AH
See Figure 6 and Figure 7 0 nst
h2
Hold time, CS valid after ADSt
CH
t
h3
Hold time, CS valid after WR1 or WR2 t
WCS
See Figure 6 10 nst
h4
Hold time, address valid after WR1or WR2 t
WA
t
h5
Hold time, data valid after WR1or WR2 t
DH
See Figure 6 5 nst
h6
Hold time, CS valid after RD1or RD2 t
RCS
See Figure 7 10 nst
h7
Hold time, address valid after RD1or RD2 t
RA
See Figure 6 20 nst
d4
Delay time, CS valid before WR1or WR2
(1)
t
CSW
See Figure 6 7 nst
d5
Delay time, address valid before WR1or WR2
(1)
t
AW
t
d6
Delay time, write cycle, WR1or WR2 to ADSt
WC
See Figure 6 40 nst
d7
Delay time, CS valid to RD1or RD2
(1)
tCSR
See Figure 7 7 nst
d8
Delay time, address valid to RD1or RD2
(1)
t
AR
t
d9
Delay time, read cycle, RD1or RD2 to ADSt
RC
See Figure 7 40 nst
d10
Delay time, RD1or RD2 to data valid t
RVD
C
L
= 75 pF, Figure 7 45 nst
d11
Delay time, RD1or RD2 to floating data t
HZ
C
L
= 75 pF, See Figure 7 20 ns
(1) Only applies when ADS is low.
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