ANALOG Deva FEATURES Internal Isolating Transformers Military Temperature Range Three Accuracy Options 14-Bit or 12-Bit Resolution High, Continuous Tracking Rate 32-Pin Welded Metal Package Hermetically Sealed Ratiometric Conversion Laser Trimmed No External Adjustment Three-State Latched Outputs APPLICATIONS Flight Instrumentation Systems Military Servo Control Systems Artillery Fire Control Systems Avionic Systems Antenna Monitoring Robotics Engine Controllers Coordinate Conversion Axis Transformation CNC Machine Tooling Process Control GENERAL DESCRIPTION The SDC/RDC1740/1741/1742 are hybrid 14- or 12-bit continu- ous tracking synchro or resolver to digital converters contained in 32-pin welded metal packages. In the core of this hybrid the conversion process is performed by a monolithic IC manufac- tured in Analog Devices proprietary BiMOS II process that combines the advantages of CMOS logic and bipolar high accu- racy linear circuits on the same chip. Internal isolating micro- transformers are used to provide true isolation of the signal and reference inputs. The 14- or 12-bit digital word is in a three- state digital form available in two bytes. Using separate ENABLE inputs for the most significant 8 bits and the least significant 6 or 4 bits not only simplifies multiplexing of more than one device onto a single data bus, but also enables the INHIBIT input to be used without interrupting the operation of the tracking loop. The converters are hermetically sealed in a 32-pin welded metal package. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 12- and 14-Bit Hybrid Synchro/ - Resolver-to-Digital Converters SDC/RDC 1740/1741/1742 VP REF HI UP REF LO SCALING R-TO-D +Vs RESISTORS PP $1 AND SMATCH $2 + RESOLVER- CONTROL | Ve TO- 83 eisitat CONVERTER S4 ov GND IRESOLVER OPTION) INHIBIT ENABLE M ENABLE L BUSY 3-STATE BUFFER 3-STATE BUFFER HIGH-BYTE LOW-BYTE | $02 3 4a ey a 9 10 11 12 13 14 [mse ae 14- OR 12-BIT DIGITAL OUTPUT WORD Funetional Diagram of the SDC/RDC1740/1741/1742 MODELS AVAILABLE The three synchro/resolver-to-digital converters described in this data sheet differ primarily in the areas of resolution, accuracy and dynamic performance as follows: Model SDC1740X YZ is a 14-bit converter with an overall accu- racy of +5.3 arc minutes and a resolution of 1.3 arc minutes. Model SDC1741 XYZ is a 12-bit converter with an overall accu- racy of +15.3 arc minutes and a resolution of 5.3 arc minutes. Model SDC1742XYZ is a 12-bit converter with an overall accu- racy of +8.5 arc minutes and a resolution of 5.3 arc minutes. Each model has two operating temperature range versions, those covering the industrial temperature range (0 to +70C) and the military temperature range (55C to + 125C). The XYZ code defines the option as follows: (X) signifies the operating temper- ature range, (Y) signifies the reference frequency, (Z) signifies the signal and reference voltage whether it will accept synchro or resolver format. To ensure a high level of reliability each con- verter receives stringent precap visual inspection, environmental screening and final electrical test. Military temperature range devices and those processed to high reliability screening standards (suffix B) receive further levels of testing and screening to ensure high levels of reliability. More information about the option codes is given under the heading Ordering Information. One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 Twx: 710/394-6577 Telex: 924491 Cables: ANALOG NORWOODMASSSPEC IFICATIONS (typical at 25C unless otherwise specified) Parameter SDC/RDC1740 SDC/RDC1741 | SDC/RDC1742 | Units Comments Notes CONVERTER PERFORMANCE Accuracy +5,.3 max +15.3 max +8.5 max arc min 1,3 Tracking Rate 27 min 18 min + rev/s 4 Resolution 14 12 xx Bits Output Coding Parallel (1 LSB=1.3 | (1 LSB=5.3 ** Natural Binary arc min) arc min) Signal & Reference Frequency 400 = = Hz Option X1Z 2.6 * * kHz Option X4Z Repeatability of Position Output | 1 * * LSB 4 Bandwidth 130 150 id Hz 4 SIGNAL INPUT IMPEDANCE 90V Signal 200 * kQ Resistive Tolerance +2% | 4 26V Signal Si = kQ 4 LL.8V Signal 26 kQ 4 REFERENCE INPUTS Reference Voltage 11.8, 26, 115 * * V rms See Ordering Reference Impedance Information 115V Ref 120 * kQ Resistive Tolerance +5% | 4 26V Ref 27 * | kQ 4 11.8V Ref 12.3 * kQ 4 ACCELERATION CONSTANT | 56000 80000 iad sec? Symbol K, 4 LARGE STEP RESPONSE 85 typ 60 typ ah ms 179 Step for Settling to | 1,3 100 max 75 max ae ms 1 LSB of Error POWER LINES +V5=+15V 28 typ 35 max * * mA Quiescent Condition 1,3 -V,=15V 28 typ 35 max * * mA Quiescent Condition 1,3 VL=+5V 35 typ 56 max ud * | mA Quiescent Condition 1,3 Power Dissipation 1.4 max * 7 Ww DIGITAL INPUTS (INHIBIT, ENABLE L, ENABLE M) V (Input High) 2 min * 7 V de VL=+5V 1,3 V (nput Low) 0.7 max * * V de VL=+5V 1,3 I (Input High) 20 max x x pA Vig=2.4V 1,3 I (Input Low) 400 max * * pA | Vy =0.4V 1,3 ENABLE AND DISABLE TIME | 80 max * * ns 2,4 INHIBIT Sense Logic Low to INHIBIT Time to Data Stable (after Negative-Going Edge of INHIBIT) 640 max ~ = ns 4 BUSY OUTPUT Sense Active Logic High when converter position output changing. Timing Positive going edge 50ns before change in position output. Width 400 typ = x ns 1,3 200 min * * ns 1, 3 600 max * * ns 13 Load 2 min * 7 TTL 4 DIGITAL OUTPUTS Voltage Levels Logic High 2.4 min * * V de V_=+5V, 1,3 Ion =240nA Logic Low 0.4 max * * V de VL=t+5V 1,3 Io. =9-6mA Load 6 max ia * TTLParameter SDC/RDC1740 SDC/RDCI1741 | SDC/RDC1742 | Units Comments Notes OPERATING TEMPERATURE RANGE Option 5YZ Oto + 70 = * C Option 4YZ 55 to +125 * * C DIMENSIONS 1.74% 1.14*0.28 * * Inch See Package 4 (44.2%28.9x7.1) | * mm Information WEIGHT 0.86 max = x Oz 4 ams 25 max * * | a NOTES Specified over the appropriate operating temperature range and for: (a) +10% signal and reference amplitude variation; (b) + 10% signal and reference harmonic distortion; (c) +5% power supply variation; (d) + 10% variation in reference frequency. ENABLE M enables most significant 8 bits. ENABLE L enables least significant 4 bits (or 6 bits for SDC/RDC1740). 3100% tested at nominal values of power supplies, input signal voltages and operating frequency. Guaranteed by design. *Specifications same as SDC/RDC1740. **Specifications same as SDC/RDC1741. Specifications subject to change without notice. SDC=Synchro-to-Digital Converter RDC=Resolver-to-Digital Converter 1740=14-Bit Resolution, +5.3 arc min Accuracy Y=1 1741=12-Bit Resolution, +15.3 arc min Accuracy Y=4 1742=12-Bit Resolution, +8.5 arc min Accuracy ABSOLUTE MAXIMUM RATINGS Ve) t0-GND So eicasies soe ee kektw re oe wre +17.25V de VetOiGND we sss cwsonc soy ae sekneeeacne ves sewer 17.25V de +V 2 toGND 2.2... eee +7V de Reference Input HItoGND................. +350V dc Reference Input LO toGND ................+350V de Common Mode Range ..........20000ueueae 175V rms S1, $2, $3, S4toGND ..................4.2350V de Any Logical InputtoGND .............. 0.4V to +V_,. Case toGND ....... cee ees +20V de Storage Temperature Range ............ 65C to + 150C CAUTION: 'Correct polarity voltages must be maintained on the +V, and Vsg pins. ?The +5V power supply must never go below GND potential. NOTE Absolute maximum ratings are those values beyond which damage to the device may occur. ORDERING INFORMATION For full definition, the converter part number should be suf- fixed by an option code. All the standard options and their option codes are shown below. For options not shown, please consult Analog Devices. SDC 1744 X Y ZB CL High-Rel Processing 1 Signal 11.8V Reference 26V Synchro 2 Signal 90V Reference 115V Synchro 3 Signal 11.8V Reference 11.8V_ Resolver 4 Signal 26V Reference 26V Resolver 8 4 2 Z Z Z Zz Zz Signal 11.8V Reference 26V_ Resolver 00Hz Reference Frequency -6kHz Reference Frequency X=4 SSC to +125C Operating Temperature Range X=5 0 to +70C Operating Temperature Range ig.PIN CONFIGURATION (sa) Bit 1 | (2) @ BIT2 @ ) BIT 3 BIT 4 @ BITS ) BIT6 @ BIT 7 @ ans joe oS BITS @) nas eae BIT 10 ) arn! @ @ BIT 12 @) SEE NOTE { am BIT 14 UP REFERENCE LO | (15) WP REFERENCE HI @) +V, -Vs ov GND +V5 INHIBIT BUSY ENABLE M ENABLE L NIC CASE Nic NIC $1 $2 83 SEE NOTE 1 NOTE 1. FOR THE RESOLVER OPTION PIN 1715 $4 FOR THE SYNCHRO OPTION PIN 17 IS NOT CONNECTED. NOTE 2. FOR THE 1741 AND 1742 PINS 13 AND 14 ARE NOT CONNECTED. Bit Number Weight in Degrees 1 (MSB) 180.0000 2 90.0000 3 45.0000 4 22.5000 5 11.2500 6 5.6250 7 2.8125 8 1.4063 9 0.7031 10 0.3516 ll 0.1758 12 (LSB for 1741/1742) 0.0879 13 0.0439 14 (LSB for 1740) 0.0220 Table |. Bit Weight Table PIN FUNCTION DESCRIPTION Pin) Mnemonic Description 1-14 Bit 1-14 (1740) Parallel output data bits. 1-12. Bit 1-12 (1741/1742) 15 REF LO Input pins for the reference signal. 16 REF HI 17 $4 OR N/C $4 signal input for Resolver option. N/C for Synchro option. 18 $3 19 $2 Synchro/Resolver input signals. 20 Sl 21 N/C No Connection. 22 N/C No Connection. 23 CASE Should be connected to OV GND. 24 N/C No Connection. 25 ENABLE L ENABLE L enables the 6 or 4 least significant bits. 26 ENABLE M ENABLE M enables the 8 most significant bits. Logic High sets the output data bits to a high impedance state; a Logic Low presents the data in the latches to the output pins. 27 BUSY Converter busy. A Logic High output indicates that the output latches are being updated and data should not be transferred. 28 INHIBIT Logic Low inhibits the data transfer from the counter to the output latches. 29 +V5 Main positive power supply. 30 OV GND Power supply ground. 31 -Vs Main negative power supply. 32 +V, Logic power supply.SDC/RDC 1740/1741/1742 WP REF HI SIN WP REF LO SCALING i R-To-D +V5 RESISTORS SUPPLIES $1 AND MATCH MICRO- |_|} CONTROL | = $2 TRANS- cos meso lvEn - Vs $3 FORMERS DIGITAL s4 CONVERTER oV GND (RESOLVER OPTION) REF +, 4/6 INHIBIT 8 ENABLE M CONTROL . F ENABLE L tos HIGH-BYTE LOW-BYTE nue 3-STATE BUFFER 3-STATE BUFFER 3 4 5 6 7 8 9 10 11 12 13 14 LSB 14- 4 OR 12-BIT DIGITAL OUTPUT WORD Figure 1. Functional Diagram of the SDC/RDC1740/1741/1742 THEORY OF OPERATION In the synchro-to-digital converter configuration, the 3-wire syn- chro output should be connected to $1, $2 and $3 on the unit and the Scott T transformer pair will convert these signals into resolver format, i.e., V.=K Eg sin wt cos 6 (SIN) (COS) where 6 is the angle of the synchro shaft. In the resolver-to-digital converter configuration, the 4-wire resolver output should be connected to $1, $2, $3 and $4 on the unit and the transformers will act purely as isolators. To understand the conversion process, then assume that the cur- rent word state of the up-down counter is . V, is multiplied by COS and V, is multiplied by SIN to give: K Eo sin wt sin 6 cos b and K Eo sin wt cos @ sin . These signals are subtracted by the error amplifier to give: K Eo sin wt (sin 8 cos @ cos 6 sin ) or K Eo sin ot sin (0-). A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null sin (@). The digital output (counter $), then represents the synchro/resolver shaft angle 6 within the specified accuracy of the converter. INHIBIT INPUT The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a busy pulse to refresh the output data. ENABLE INPUTS The ENABLE inputs determine the state of the output data. A Logic High maintains the output data pins in the high imped- ance condition, and application of a Logic Low presents the data in the latches to the output pins. ENABLE M enables the most significant 8 bits, while ENABLE L, enables the least sig- nificant 4 bits (6 bits in the SDC/RDC1740). The operation of the ENABLE inputs has no effect on the conversion process. DATA TRANSFER Data transfer can be accomplished using either the INHIBIT input or the trailing edge, positive to negative transition of the BUSY pulse output. The data will be valid 640ns after the application of a Logic Lo to the INHIBIT input. This is regardless of the time when the INHIBIT is applied and allows time for an active busy pulse to clear. By using the ENABLE M and ENABLE L inputs the two bytes of data can be transferred after which the INHIBIT should be returned to a Logic Hi state to enable the output latches to be updated. MAX DEPENDS ON 600ns MAX INPUT RATE 200ns MIN BUSY 200ns *| MAX 50ns MIN | DATA VALID p< VALID VALID Figure 2. Timing DiagramBUSY OUTPUT The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL levels. A BUSY is initiated each time the input moves by an analog equivalent of an LSB and the internal counter is incremented or decremented or the INHIBIT input is released. Typically the width of the BUSY pulse is 400ns during the posi- tion data output updates. The trailing edge, positive to negative transition, of the BUSY pulse indicates that the position data output has been updated and is ready for transfer (data valid). The maximum load on the BUSY output using the trailing edge of the BUSY pulse is 2 TTL loads. CONNECTING THE CONVERTER The power supply voltages connected to +V, and V, pins should be +15V and must not be reversed. The digital logic supply V,, is connected to +5V. It is suggested that a parallel combination of a 0.1.F ceramic and a 6.8yF electrolytic capacitor is placed from each of the three supply pins to GND. The pin marked CASE is connected electrically to the case and should be taken to a convenient zero volt potential in the system. The digital output is taken from Pin 1 through to Pin 12 for the SDC/RDC1741/1742 and Pin 1 through to Pin 14 for the SDC/RDC1740 where Pin 1 is the MSB. The reference connections are made to REF HI and REF LO. In the case of a synchro, the signals are connected to $1, $2 and $3 according to the following convention: Es).53= Epto-ru1 sin wt sin 6 Eg3.52= Epto-rui sin wt sin (6+120) Es>-51 = Erro-rut sin wt sin (6 + 240) For a resolver, the signals are connected to $1, 82, $3 and S4 according to the following convention: Es-53=Epto-ru1 sin wt sin 6 Es2.s4=Eputrio sin wt cos @ The BUSY, INHIBIT and ENABLE pins should be connected as described under the heading Data Transfer. RESISTIVE SCALING OF INPUTS A feature of these converters is that the signal and reference inputs can be resistively scaled to accommodate any change of input signal and reference voltages. This means that a standard converter can be used with a person- ality card in systems where a wide range of input and reference voltages are encountered. Note: The accuracy of the converter will be affected by the matching accuracies of resistors used for external scaling. To calculate the values of the external scaling resistors in the case of a synchro converter, add 1.11kQ per extra volt of signal in series with $1, $2 and $3 and 1kQ per extra volt of reference in series with RHI. In the case of a resolver-to-digital converter, add 2.22k0 in series with $1 and 2 per extra volt of signal and 1kQ per extra volt of reference in series with RHI. DYNAMIC PERFORMANCE The transfer function of the converter is given below. 1+ ST, Sour $? 1+ ST, Figure 3. Transfer Function of SDC/RDC1740/1741/1742 Open loop gain: Sour _ Ka _ 1+ST) On = ?_ssT+ST Closed loop gain: 8ouT 1+ ST, ON SST, 1+ STi + Rp + a Model SDC/RDC1740 Where K,=56,000 T1=0.01 T2=0.001525 The gain and phase diagrams are shown in Figures 4 and 5. Model SDC/RDC1741/1742 Where K,=80,000 T1=0.0087 T2=0.001569 The gain and phase diagrams are shown in Figures 6 and 7. ACCELERATION ERROR A tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant K, of the converter. K= Input Acceleration a~ Error in Output Angle The numerator and denominator have the same units. K, does not define maximum acceleration, only the error due to accelera- tion, maximum acceleration is in the region of 5 times the K, figure. The following is an example using the K, of the $DC1740. Acceleration of 50 revolutions sec? with K,=56000 5 Error in LSBs = aes = 14.62LSBsGAIN - dB Le , \ -4 125 25 50 100 200 FREQUENCY Hz Figure 4. SDC/RDC1740 Gain Plot 180 135 g 1 0 es -45 i ne -90 ~ 135 > Bie ae 180 125 25 50 100 200 FREQUENCY - Hz Figure 5. SDC/RDC1740 Phase Plot 160 wh Nl we i 25 40 55 70 85 100 125 TEMPERATURE - C Figure 8. SDC/RDC1740/41/42 MTBF Curve YEARS GAIN - dB 2 A \ pa \ | | | 4 \ \ \ \ 2 + | -4 12.5 25 50 100 200 FREQUENCY Hz Figure 6. SDC/RDC1741/1742 Gain Plot 180 135 -135 eS) -180 12.5 25 50 100 200 FREQUENCY Hz Figure 7. SDC/RDC1741/1742 Phase Plot RELIABILITY The reliability of these products is very high due to the exten- sive use of custom chip circuits that decrease the active compo- nent count. Calculations of the MTBF figure under various environmental conditions are available on request. As an example of the Mean Time Between Failures (MTBF) calculated according to MIL-HDBK-217E, Figure 8 shows the MTBF in years versus case temperature in naval sheltered con- ditions for SDC/RDC1740/41/42.OUTLINE DIMENSIONS Dimensions shown in inches and (mm). ANALOG DEVICES MEMORY DEVICES DIVN MADE IN ENGLAND SDC/RDC 1740 OPTION [7773 0.28+0.010 \_ (71 20.254) PIN 1 IDENTIFIER 0.2 20.010 (5.0 +0.254) az i | 0.025 tl a 010 (2.54) TYP }+ 0.8 (22.9) | (0.635) 1,50 (38.1) | * 1.74 (44,2) | eoeesececoseeece GLASS BEAD = PIN 1 BEAD STANDOFFS DIFFERENT 0.08 DIA. +0.010 COLOR | (2.03 DIA. +0.254) 0.600 (15.24) BOTTOM VIEW 1.14 (29.0) r-O TOLERANCES: +0.005 (=0.127) eeeeeeeeeoeeneee UNLESS OTHERWISE STATED 1.400 (35.56) STANDARD PROCESSING (5YZ OPTION) As part of the standard manufacturing procedure, all converters receive the following processing: Process Conditions 1. Preseal Burn In 64 hrs at +125C 2. Precap Visual Inspection In-house criteria 3. Seal Test, Fine and Gross In-house criteria 4. Final Electrical Test Performed at +25C Extended temperature range versions receive additional processing as follows: Final Electrical Test Performed at max and min operating temperatures OTHER PRODUCTS Many other hybrid products concerned with the conversion of synchro data are manufactured by Analog Devices, some of which are listed below. If you have any questions about our products or require advice about their use for a particular appli- cation, please contact our Applications Engineering Department. The SDC/RDC1767 and SDC/RDC1768 are hybrid synchro- to-digital converters with isolating microtransformers similar to the SDC/RDC1740/41/42 described on this data sheet with the additional features of analog velocity output and dc error output. The OSC1758 is a hybrid sine/cosine power oscillator which can provide a maximum power output of 1.5 watts, over a frequency range of 0 to 10kHz. The DRC1745 and DRC1746 are 14- and 16-bit natural binary latched output hybrid digital-to-resolver converters. The accura- cies available are +2 and +4 arc mins, and the outputs can sup- ply 2VA at 7V rms. PROCESSING FOR HIGH RELIABILITY Process Conditions 1. Preseal Burn In 64 hrs at +125C 2. Precap Visual Inspection 2017 3. Temperature Cycling 10 Cycles, 65C to +150C 4, Constant Acceleration 5000G, Y1 Plane 5. Interim Electrical Tests 6. Operating Burn In 96 hours @ +125C 7. Seal Test, Fine and Gross 1014 8. Final Electrical Testing Performed at T,.3,5 Tambient (Group A) and Tax 9. External Visual Inspection 2009 NOTE Test and screening data can be supplied. Further information on request. C811a206/89 PRINTED IN U.S.A