MC74ACT257D - ON Semiconductor - searchdatasheet.com

March, 2006 − Rev. 7

1Publication Order Number:

MC74AC257/D

MC74AC257, MC74ACT257

Quad 2−Input Multiplexer

with 3−State Outputs

The MC74AC257/74ACT257 is a quad 2−input multiplexer with

3−state outputs. Four bits of data from two sources can be selected

using a Common Data Select input. The four outputs present the

selected data in true (noninverted) form. The outputs may be switched

to a high impedance state by placing a logic HIGH on the common

Output Enable (OE) input, allowing the outputs to interface directly

with bus−oriented systems.

•Multiplexer Expansion by Tying Outputs Together

•Noninverting 3−State Outputs

•Outputs Source/Sink 24 mA

•′ACT257 Has TTL Compatible Inputs

wThese devices are available in Pb−free package(s). Specifications herein

apply to both standard and Pb−free devices. Please see our website at

www.onsemi.com for specific Pb−free orderable part numbers, or

contact your local ON Semiconductor sales office or representative.

1516 14 13 12 11 10

21 34567

VCC

OE I0c I1c ZcI0d I1d Zd

0a I1a ZaI0b I1b ZbGND

Figure 1. Pinout: 16−Lead Packages Conductors

(Top View)

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DIP−16

N SUFFIX

CASE 648

SO−16

D SUFFIX

CASE 751B

Device Package Shipping

ORDERING INFORMATION

MC74AC257N PDIP−16 25 Units/Rail

MC74AC257D SOIC−16 48 Units/Rail

MC74AC257DR2 2500 Tape & Reel

TSSOP−16

DT SUFFIX

CASE 948F

MC74AC257DT TSSOP−16 96 Units/Rail

MC74AC257DTR2 TSSOP−16

SOIC−16

2500 Tape & Reel

MC74ACT257N PDIP−16 25 Units/Rail

MC74ACT257D SOIC−16 48 Units/Rail

MC74ACT257DR2 2500 Tape & Reel

MC74ACT257DT TSSOP−16 96 Units/Rail

MC74ACT257DTR2 TSSOP−16

SOIC−16

2500 Tape & Reel

See general marking information in the device marking

section on page 8 of this data sheet.

DEVICE MARKING INFORMATION

EIAJ−16

M SUFFIX

CASE 966

MC74AC257MEL EIAJ−16 2000 Tape & Reel

MC74ACT257M EIAJ−16

MC74ACT257MEL EIAJ−16 2000 Tape & Reel

50 Units/Rail

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PIN NAME

PIN FUNCTION

SCommon Data Select Input

OE 3−State Output Enable Input

I0a−I0d Data Inputs from Source 0

I1a−I1d Data Inputs from Source 1

Za−Zd3−State Multiplexer Outputs

TRUTH TABLE

Output

Enable

Select

Input

Data

Inputs Outputs

OE S I0I1Z

H X X X Z

L H X LL

L H X HH

L L L XL

L L H X H

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Figure 2. Logic Symbol

OE I0a I1a I0b I1b

I0c I1c I0d I1d

ZaZcZd

FUNCTIONAL DESCRIPTION

The MC74AC257/74ACT257 is a quad 2−input

multiplexer with 3−state outputs. It selects four bits of data

from two sources under control of a Common Data Select

input. When the Select input is LOW, the I0x inputs are

selected and when Select is HIGH, the I1x inputs are

selected. The data on the selected inputs appears at the

outputs in true (noninverted) form. The device is the logic

implementation of a 4−pole, 2−position switch where the

position of the switch is determined by the logic levels

supplied to the Select input. The logic equations for the

outputs are shown below:

Za = OE•(I1a•S+I0a•S)

Zb = OE•(I1b•S+I0b•S)

Zc = OE•(I1c•S+I0c•S)

Zd = OE•(I1d•S+I0d•S)

When the Output Enable input (OE) is HIGH, the outputs

are forced to a high impedance state. If the outputs are tied

together, all but one device must be in the high impedance

state to avoid high currents that would exceed the maximum

ratings. Designers should ensure the Output Enable signals

to 3−state devices whose outputs are tied together are

designed so there is no overlap.

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NOTE: This diagram is provided only for the understanding of logic operations

and should not be used to estimate propagation delays.

OE I0a I1a I0b I1b I0c I1c I0d I1d S

ZaZbZcZd

Figure 3. Logic Diagram

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MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V

VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V

VOUT DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V

IIN DC Input Current, per Pin ±20 mA

IOUT DC Output Sink/Source Current, per Pin ±50 mA

ICC DC VCC or GND Current per Output Pin ±50 mA

Tstg Storage Temperature −65 to +150 °C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-

mended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage

′AC 2.0 5.0 6.0

′ACT 4.5 5.0 5.5

VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) 0−VCC V

tr, tfInput Rise and Fall Time (Note 1)

′AC Devices except Schmitt Inputs

VCC @ 3.0 V −150 −

VCC @ 4.5 V −40 −ns/V

VCC @ 5.5 V −25 −

tr, tfInput Rise and Fall Time (Note 2)

′ACT Devices except Schmitt Inputs

VCC @ 4.5 V −10 −

ns/V

VCC @ 5.5 V −8.0 −

TJJunction Temperature (PDIP) − − 140 °C

TAOperating Ambient Temperature Range −40 25 85 °C

IOH Output Current − High − − −24 mA

IOL Output Current − Low − − 24 mA

1. 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

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DC CHARACTERISTICS

Symbol Parameter VCC

(V)

74AC 74AC

Unit Conditions

TA = +25°C

TA =

−40°C to

+85°C

Typ Guaranteed Limits

VIH Minimum High Level

Input Voltage

3.0 1.5 2.1 2.1 VOUT = 0.1 V

4.5 2.25 3.15 3.15 V or VCC − 0.1 V

5.5 2.75 3.85 3.85

VIL Maximum Low Level

Input Voltage

3.0 1.5 0.9 0.9 VOUT = 0.1 V

4.5 2.25 1.35 1.35 V or VCC − 0.1 V

5.5 2.75 1.65 1.65

VOH Minimum High Level

Output Voltage

3.0 2.99 2.9 2.9 IOUT = −50 mA

4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

*VIN = VIL or VIH

3.0 −2.56 2.46 −12 mA

4.5 −3.86 3.76 IOH −24 mA

5.5 −4.86 4.76 −24 mA

VOL Maximum Low Level

Output Voltage

3.0 0.002 0.1 0.1 IOUT = 50 mA

4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

*VIN = VIL or VIH

3.0 −0.36 0.44 12 mA

4.5 −0.36 0.44 IOL 24 mA

5.5 −0.36 0.44 24 mA

IIN Maximum Input

Leakage Current 5.5 −±0.1 ±1.0 mAVI = VCC, GND

IOZ Maximum

3−State

Current

VI (OE) = VIL, VIH

5.5 −±0.5 ±5.0 mAVI = VCC, GND

VO = VCC, GND

IOLD †Minimum Dynamic

Output Current

5.5 − − 75 mA VOLD = 1.65 V Max

IOHD 5.5 − − −75 mA VOHD = 3.85 V Min

ICC Maximum Quiescent

Supply Current 5.5 −8.0 80 mAVIN = VCC or GND

*All outputs loaded; thresholds on input associated with output under test.

†Maximum test duration 2.0 ms, one output loaded at a time.

NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

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AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74AC 74AC

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

tPLH

Propagation Delay 3.3 1.5 5.0 8.5 1.0 9.0 ns 3−5

In to Zn5.0 1.5 4.0 6.0 1.0 7.0

tPHL

Propagation Delay 3.3 1.5 6.0 8.5 1.0 9.0 ns 3−5

In to Zn5.0 1.5 4.5 6.0 1.0 7.0

tPLH

Propagation Delay 3.3 1.5 7.0 10.5 1.5 11.5 ns 3−6

S to Zn5.0 1.5 5.0 7.5 1.0 8.5

tPHL

Propagation Delay 3.3 1.5 7.5 10.5 1.5 11.5 ns 3−6

S to Zn5.0 1.5 5.5 7.5 1.0 8.5

tPZH Output Enable Time 3.3 1.5 6.5 9.5 1.0 10.5 ns 3−7

5.0 1.5 5.0 7.5 1.0 8.5

tPZL Output Enable Time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3−8

5.0 1.5 5.0 8.5 1.0 9.5

tPHZ Output Disable Time 3.3 1.5 5.5 10.0 1.0 11.0 ns 3−7

5.0 1.5 5.0 9.0 1.0 10.0

tPLZ Output Disable Time 3.3 1.5 5.5 9.0 1.0 10.0 ns 3−8

5.0 1.5 5.0 8.0 1.0 9.0

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

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DC CHARACTERISTICS

Symbol Parameter VCC

(V)

74ACT 74ACT

Unit Conditions

TA = +25°C

TA =

−40°C to

+85°C

Typ Guaranteed Limits

VIH Minimum High Level

Input Voltage

4.5 1.5 2.0 2.0 VVOUT = 0.1 V

5.5 1.5 2.0 2.0 or VCC − 0.1 V

VIL Maximum Low Level

Input Voltage

4.5 1.5 0.8 0.8 VVOUT = 0.1 V

5.5 1.5 0.8 0.8 or VCC − 0.1 V

VOH Minimum High Level

Output Voltage

4.5 4.49 4.4 4.4 VIOUT = −50 mA

5.5 5.49 5.4 5.4

*VIN = VIL or VIH

4.5 −3.86 3.76 V IOH

−24 mA

5.5 −4.86 4.76 −24 mA

VOL Maximum Low Level

Output Voltage

4.5 0.001 0.1 0.1 VIOUT = 50 mA

5.5 0.001 0.1 0.1

*VIN = VIL or VIH

4.5 −0.36 0.44 V IOL

24 mA

5.5 −0.36 0.44 24 mA

IIN Maximum Input

Leakage Current 5.5 −±0.1 ±1.0 mAVI = VCC, GND

DICCT Additional Max. ICC/Input 5.5 0.6 −1.5 mA VI = VCC −2.1 V

IOZ Maximum

3−State

Current

VI (OE) = VIL, VIH

5.5 −±0.5 ±5.0 mAVI = VCC, GND

VO = VCC, GND

IOLD †Minimum Dynamic

Output Current

5.5 − − 75 mA VOLD = 1.65 V Max

IOHD 5.5 − − −75 mA VOHD = 3.85 V Min

ICC Maximum Quiescent

Supply Current 5.5 −8.0 80 mAVIN = VCC or GND

*All outputs loaded; thresholds on input associated with output under test.

†Maximum test duration 2.0 ms, one output loaded at a time.

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AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74ACT 74ACT

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

tPLH Propagation Delay

In to Zn

5.0 1.5 5.0 7.0 1.0 7.5 ns 3−6

tPHL Propagation Delay

In to Zn

5.0 2.0 6.0 7.5 1.5 8.5 ns 3−6

tPLH Propagation Delay

S to Zn

5.0 2.0 7.0 9.5 1.5 10.5 ns 3−6

tPHL Propagation Delay

S to Zn

5.0 2.5 7.0 10.5 2.0 11.5 ns 3−6

tPZH Output Enable Time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3−7

tPZL Output Enable Time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3−8

tPHZ Output Disable Time 5.0 2.5 6.5 9.0 1.5 10.0 ns 3−7

tPLZ Output Disable Time 5.0 2.0 6.0 7.5 1.5 8.5 ns 3−8

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

CAPACITANCE

Symbol Parameter Value

Typ Unit Test Conditions

CIN Input Capacitance 4.5 pF VCC = 5.0 V

CPD Power Dissipation Capacitance 50 pF VCC = 5.0 V

MARKING DIAGRAMS

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

AC257

AWLYWW

MC74AC257N

AWLYYWW AC

257

ALYW

ACT257

AWLYWW ACT

257

ALYW

MC74ACT257N

AWLYYWW

DIP−16 SO−16 TSSOP−16 EIAJ−16

74AC257

ALYW

74ACT257

ALYW

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

PDIP−16

N SUFFIX

16 PIN PLASTIC DIP PACKAGE

CASE 648−08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

SO−16

D SUFFIX

16 PIN PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

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PACKAGE DIMENSIONS

TSSOP−16

DT SUFFIX

16 PIN PLASTIC TSSOP PACKAGE

CASE948F−01

ISSUE O

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE −W−.

___ _

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉÉ

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

EIAJ−16

M SUFFIX

16 PIN PLASTIC EIAJ PACKAGE

CASE966−01

ISSUE O

DIM MIN MAX MIN MAX

INCHES

−−− 2.05 −−− 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

−−− 0.78 −−− 0.031

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005) 0.10 (0.004)

16 9

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Notes

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Notes

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MC74AC257/D

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