7. S1D15600/601/602 Series
Rev. 4.6
– i –
CONTENTS
1. DESCRIPTION ................................................................................................................................................7-1
2. FEATURES......................................................................................................................................................7-1
3. BLOCK DIAGRAM...........................................................................................................................................7-2
4. PAD .................................................................................................................................................................7-3
5. PIN DESCRIPTION .........................................................................................................................................7-5
6. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................7-9
7. FUNCTIONAL DESCRIPTION ......................................................................................................................7-21
8. COMMANDS .................................................................................................................................................7-40
9. COMMAND DISCRIPTION-INSTRUCTION SETUP EXAMPLES ................................................................7-49
Rev. 4.6
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–1
• On-chip 166 × 65-bit display RAM
• Direct relationship between RAM bits and display
pixels.
• High speed Interfaces to 6800- and 8080-series micro-
processors
• Selectable 8-bit parallel/serial interface
• Many command functions
• On-chip LCD power circuit including DC/DC
voltage converter, voltage regulator and voltage
followers.
• On-Chip Contrast control.
• Two types of VREG (Built-in power supply regulator
temperature gradient).
• Type1 (S1D1560*D00**, S1D1560*D10**)...–
0.2%/˚C
• Type2 (S1D15600D14**)...0.00%/˚C
• On-chip oscillator
• Ultra low power consumption
• Power Supply
VDD – VSS –2.4 V to –6.0 V
VDD – V5–3.5 V to –16.0 V
• Ta = –30 to 85°C
• CMOS process
• TCP, QTCP
• The system is not designed against the radio activity.
1. DESCRIPTION
The S1D15600/601/602 series is a single-chip LCD
driver for dot-matrix liquid crystal displays. It accepts
serial or 8-bit parallel display data directly from a micro-
processor and stores data in an on-chip 166 × 65-bit
RAM.
The S1D15600/601/602 series features 167 common and
segment outputs to drive either a 65 × 102-pixel
(S1D15600) display (4 rows × 6 columns with 16 × 16-
pixel characters) or a 33 × 134-pixel (S1D15601) display
(2 rows × 8 columns with 16 × 16-pixel characters) or a
17 × 150-pixel (S1D15602) display (1 row × 9 columns
with 16 × 16 characters). In addition, two S1D15600s
can be connected together to drive a 65 × 268-pixel
graphics display panel.
The S1D15600/601/602 series can read and write RAM
data with the minimum current consumption as it does
not require any external operation clock. Also, it has a
built-in LCD power supply featuring the very low current
consumption and, therefore, the display system of a high-
performance but handy instrument can be realized by use
of the minimum current consumption and LSI chip
configuration.
The S1D15600/601/602 Series has the S1D15600,
S1D15601 and S1D15602 available according to the
duty.
2. FEATURES
• Wide variety of duty and display areas
Single-chip
Model Duty LCD bias display area
1/65 65 × 102
S1D15600 1/64 1/9 64 × 102
1/49 1/7 49 × 102
1/48 48 × 102
1/33 33 × 134
S1D15601 1/32 1/7 32 × 134
1/25 1/5 25 × 134
1/24 24 × 134
S1D15602 1/17 1/5 17 × 150
1/16 16 × 150
Note: The LCD bias is obtained if the built-in power
supply is used.
S1D15600/601/602 Series
7–2 EPSON Rev. 4.6
3. BLOCK DIAGRAM
Common
and
segment
driver
Segment
driver
Common
and
segment
driver
Common
I
Shift
register Shift
register
O0 O31 toO32to O101 O102 O165 COMIto
SS
V
DD
V
V
1
V
2
V
3
V
4
V
5
CAP1+
CAP1–
CAP2+
CAP2–
R
V
T1, T2
Supply
voltage
generator1
Output
status
select
166–bit display data latch
I/O
buffer 166 x 65–bit display
data RAM Line
address
decoder
Line
counter
Display
initial line
register
166–bit column address decoder
8–bit column address counter
8–bit column address register
Page
address
register
Bus holder Command
decoder Status flag Oscillator
MPU interface I/O buffer
Display
timing
generator
Frame
control
V
1
V
2
V
3
V
4
V
5
DD
V
FR
SYNC
CL
CLO
DYO
M/S
OSC1
OSC2
D0D7 D1D2D4D6 D5 D3RESP/SSCLCS1 SIC86WRRDA0CS2
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–3
4. PAD
Pad layout
Chip size : 8.08 × 5.28 mm
Pad pitch : 100 µm (Min.)
Chip thickness : 625 µm
: 300 µm (Al-pad)
• Au-Bump Bump size A : 103 µm × 95 µm (Typ.) (Pad No. 1 ~ 6, 18, 36 ~ 42,
44 ~ 49)
Bump size B : 69 µm × 95 µm (Typ.) (other then the above)
Bump hight : 23 µm (Typ.)
• Al-pad Pad size A : 111 µm × 102 µm (Typ.) (Pad No. 1 ~ 6, 18, 36 ~ 42,
44 ~ 49)
Bump size B : 77 µm × 99 µm (Typ.) (Other then the above)
O0
O45
V5
V4
V3
V2
V1
V
V
V5
V
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
V
RD
WR
A0
C86
CS2
CS1
P/S
S1
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
DD
R
OUT
SS
O46
O120
O121
COM1
O165
D156*D0B
170
1
216
49
95
S1D15600/601/602 Series
7–4 EPSON Rev. 4.6
PAD PIN XY
No. Name
1V
53640 2487
2V
43489
3V
33339
4V
23188
5V
13037
6V
DD 2889
7 M/S 2755
8 RES 2604
9 SCL 2453
10 SI 2302
11 P/S 2151
12 CS1 2001
13 CS2 1850
14 C86 1699
15 A0 1548
16 WR 1397
17 RD 1247
18 VSS 1077
19 D0 945
20 D1 794
21 D2 643
22 D3 493
23 D4 342
24 D5 191
25 D6 40
26 D7 -111
27 DYO -261
28 CLO -412
29 SYNC -563
30 FR -714
31 CL -865
32 OSC2 -1015
33 OSC1 -1166
34 T2 -1317
35 T1 -1468
36 VSS -1638
37 CAP1+ -1789
38 CAP1- -1939
39 CAP2+ -2090
40 CAP2- -2241
41 VOUT -2392
42 V5-2543
43 VR-2674
44 VDD -2844
45 V1-2995
46 V2-3146
47 V3-3297
48 V4-3447
49 V5-3598
50 00 -3887 2294
51 01 2194
52 02 2094
53 03 1994
54 04 1894
PAD PIN XY
No. Name
55 05 -3887 1794
56 06 1694
57 07 1594
58 08 1494
59 09 1394
60 010 1294
61 011 1194
62 012 1094
63 013 994
64 014 894
65 015 794
66 016 694
67 017 594
68 018 494
69 019 394
70 020 294
71 021 194
72 022 94
73 023 -6
74 024 -106
75 025 -206
76 026 -306
77 027 -406
78 028 -506
79 029 -606
80 030 -706
81 031 -806
82 032 -906
83 033 -1006
84 034 -1106
85 035 -1206
86 036 -1306
87 037 -1406
88 038 -1506
89 039 -1606
90 040 -1706
91 041 -1806
92 042 -1906
93 043 -2006
94 044 -2106
95 045 -2206
96 046 -3711 -2487
97 047 -3611
98 048 -3511
99 049 -3411
100 050 -3311
101 051 -3211
102 052 -3111
103 053 -3011
104 054 -2911
105 055 -2811
106 056 -2711
107 057 -2611
108 058 -2511
PAD PIN XY
No. Name
109 059 -2411 -2487
110 060 -2311
111 061 -2211
112 062 -2111
113 063 -2011
114 064 -1911
115 065 -1811
116 066 -1711
117 067 -1611
118 068 -1511
119 069 -1411
120 070 -1311
121 071 -1211
122 072 -1111
123 073 -1011
124 074 -911
125 075 -811
126 076 -711
127 077 -611
128 078 -511
129 079 -411
130 080 -311
131 081 -211
132 082 -111
133 083 -11
134 084 89
135 085 189
136 086 289
137 087 389
138 088 489
139 089 589
140 090 689
141 091 789
142 092 889
143 093 989
144 094 1089
145 095 1189
146 096 1289
147 097 1389
148 098 1489
149 099 1589
150 0100 1689
151 0101 1789
152 0102 1889
153 0103 1989
154 0104 2089
155 0105 2189
156 0106 2289
157 0107 2389
158 0108 2489
159 0109 2589
160 0110 2689
161 0111 2789
162 0112 2889
PAD PIN XY
No. Name
163 0113 2989 -2487
164 0114 3089
165 0115 3189
166 0116 3289
167 0117 3389
168 0118 3489
169 0119 3589
170 0120 3689
171 0121 3887 -2206
172 0122 -2106
173 0123 -2006
174 0124 -1906
175 0125 -1806
176 0126 -1706
177 0127 -1606
178 0128 -1506
179 0129 -1406
180 0130 -1306
181 0131 -1206
182 0132 -1106
183 0133 -1006
184 0134 -906
185 0135 -806
186 0136 -706
187 0137 -606
188 0138 -506
189 0139 -406
190 0140 -306
191 0141 -206
192 0142 -106
193 0143 -6
194 0144 94
195 0145 194
196 0146 294
197 0147 394
198 0148 494
199 0149 594
200 0150 694
201 0151 794
202 0152 894
203 0153 994
204 0154 1094
205 0155 1194
206 0156 1294
207 0157 1394
208 0158 1494
209 0159 1594
210 0160 1694
211 0161 1794
212 0162 1894
213 0163 1994
214 0164 2094
215 0165 2194
216 COMI 2294
S1D15600/601/602 Series
PAD Center Coordinates Unit : µm
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–5
5. PIN DESCRIPTION
Power Supply
LCD Driver Supplies
Name I/O Description
Number of pins
VDD Supply 5V supply. Common to MPU power supply pin VCC.2
VSS Ground 2
V1 to V5Supply LCD driver supply voltages. The voltage determined by the 11
LCD cellis impedance-converted by a resistive divider or an
operational amplifier for application. Voltages should be
determined on a VDD- basis so as to satisfy the following
relationship. The voltages must satisfy the following relationship.
VDD ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5.
When master mode selects, these voltages are generated on-chip.
Name I/O Description
Number of pins
CAP1+ O DC/DC voltage converter capacitor 1 positive connection 1
CAP1– O DC/DC voltage converter capacitor 1 negative connection 1
CAP2+ O DC/DC voltage converter capacitor 2 positive connection 1
CAP2– O DC/DC voltage converter capacitor 2 negative connection 1
VOUT I/O DC/DC voltage converter output1 1
VRI Voltage adjustment pin. Applies voltage between VDD and V51
using a resistive divider.
T1, T2 I Liquid crystal power control terminals 2
Voltage
T1 T2 Boosting circuit regulation V/F circuit
circuit
LOW LOW Valid Valid Valid
LOW HIGH Valid Valid Valid
HIGH LOW Invalid Valid Valid
HIGH HIGH Invalid Invalid Valid
S1D15600D10B*S1D15601D10B*
S1D15600D00B*S1D15601D00B*S1D15602D00B*
V11/9 V51/7 V51/5 V5
V22/9 V52/7 V52/5 V5
V37/9 V55/7 V53/5 V5
V48/9 V56/7 V54/5 V5
S1D15600/601/602 Series
7–6 EPSON Rev. 4.6
Microprocessor Interface
Name I/O Description
Number of pins
D0 to D7 I/O Data inputs/outputs 8
A0 I Control/display data flag input. This is connected to the LSB 1
of the microprocessor address bus.
When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
RES I Reset input. System is reset and initialized when LOW. 1
CS1, CS2 I Chip select inputs. Data input/output is enabled when 2
CS1 is LOW and CS2 is HIGH.
RD (E) I Read enable input. See note. 1 1
WR (R/W) I Write enable input. See note. 2 1
C86 I Microprocessor interface select input. LOW when interfacing to 1
8080-series. HIGH when interfacing to 6800-series.
SI I Serial data input 1
SCL I Serial clock input. Data is read on the rising edge of SCL and
converted to 8-bit parallel data. 1
P/S I Parallel/serial data input select 1
In serial mode, data cannot be read from the RAM, and D0 to D7,
HZ, RD and WR must be HIGH or LOW. In parallel mode, SI
and SCL must be HIGH or LOW.
Note 1
When interfacing to 8080-series microprocessors, RD is active-LOW. When interfacing to 6800-series microproces-
sors, they are active-HIGH.
Note 2
When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microproces-
sors, It will be read mode when WR is high and It will be write mode when WR is LOW.
Data
Operating Data/co- Serial
P/S Chip select input/ Read/write
mode mmand clock
output
HIGH Parallel CS1, CS2 A0 D0 to D7 RD, WR —
LOW Serial CS1, CS2 A0 SI Write only SCL
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–7
Name I/O Description
Number of pins
OSCI I Connecting pins for feedback resistors of the built-in oscillator 2
When M/S = HIGH: Connect oscillator resistor Rf to the OSC1
and OSC2 pins. The OSC2 pin is used for output of the oscillator
amplifier.
OSC2 I/O When M/S = LOW: The OSC2 pin is used for input of oscillation 2
signal. The OSC1 pin should be left open. Fix the CL pin to theV
SS
level when using the internal oscillator circuit as the display clock.
CL I Display clock input. The line counter increments on the rising edge 1
of CL and the display pattern is output on the falling edge. When
use external display clock, OSC1 = HIGH, OSC2 = LOW and
reset this LSI by RES pin.
CLO O Display clock output. When using the master operation, the clock 1
signal is output on this pin. Connect CLO to YSCL on the
common driver.
M/S I Master/slave select input. Master makes some signals for display, 1
and slave gets them. This is for display syncronization.
Note
I = input mode
O = output mode
FR I/O LCD AC drive signal input/output. If the S1D15600/601/602 series 1
MPU’s are used in master and slave configuration, this pin must
be connected to each FR pin. Also when the S1D15600/601/602
series isused as the master MPU, this pin must be connected to
the FRpin of the common driver. Output is selected when M/S is
HIGH, and input is selected when M/S is LOW.
SYNC I/O Display sync input/output. If the S1D15600/601/602 series MPU’s 1
are used in master and slave configuration, this pin must be
connected to each SYNC pin. Output is selected when M/S is
HIGH, and Input is selected when M/S is LOW.
DYO O Start-up output for common driver. Connect to DIO of the 1
common driver.
Oscillator and Timing Control
Operating Internal Power
Device M/S FR SYNC OSC1 OSC2 DYO
mode oscillator supply
LOW Slave OFF OFF I I Open I O
156XDOB HIGH Master ON ON O O I O O
S1D15600/601/602 Series
7–8 EPSON Rev. 4.6
LCD Driver Outputs
Name I/O Description
Number of pins
O0 to O165 O LCD driver outputs. O0 to O31 and O102 to O165 are selectable 166
segment or common outputs, determined by a selection command.
O32 to O101 are segment outputs only.
For segment outputs, the ON voltage level is given as shown in
the following table.
For common outputs, the ON voltage is given as shown in the
following table.
COMI O
LCD driver common output. Common outputs when the “DUTY +1”
command is executed are as follows: 1
Common output special for the indicator.
LCD ON voltage
RAM data FR Normal display Inverse display
LOW V3V5
LOW HIGH V2VDD
LOW V5V3
HIGH HIGH VDD V2
Scan data FR LCD ON voltage
LOW V4
LOW HIGH V1
LOW VDD
HIGH HIGH V5
“DUTY + 1” ON “DUTY + 1” OFF
S1D15600 COM64, COM48 V1 or V4
S1D15601 COM32, COM24 V1 or V4
S1D15602 COM16 V1 or V4
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–9
6.ABSOLUTE MAXMUM RATINGS
Parameter Symbol Rating Unit
Supply voltage (1) –7.0 +0.03
Supply voltage range (2) VSS –6.0 to 0.3 V
(DC/DC When in use) (when triple boosting)
Driver supply voltage range (1) V5–18.0 to 0.3 V
Driver supply voltage range (2) V1, V2, V3, V4V5 to 0.3 V
Input voltage range VIN VSS –0.3 to 0.3 V
Output voltage range Vo VSS –0.3 to 0.3 V
Operating temperature range Topr –30 to 85 °C
Storage temperature range (TCP) Tstr –55 to 100 °C
Notes: 1. The voltages shown are based on VDD = 0 V.
2. Always keep the condition of VDD ≥ V1 ≥ V2 ≥ V3 ≥V4 ≥ V5 for voltages V1, V2, V3 and V4.
3. If LSIs are used over the absolute maximum rating, the LSIs may be destroyed permanently. It is
desirable to use them under the electrical characteristic conditions for general operation. Otherwise, a
malfunction of the LSI may be caused and LSI reliability may be affected.
4. A guarantee on operating temperature below –30°C may be studied individually.
V
CC
GND V
SS
V
DD
V
5
(S1D15600/601/602 series)(System)
V
DD
S1D15600/601/602 Series
7–10 EPSON Rev. 4.6
VDD = 0 V, VSS = –5 V ± 10%, Ta = –30 to +85°C unless otherwise noted.
Item Symbol Condition Min. Typ. Max. Unit Pin used
Power Recommend- VSS –5.5 –5.0 –4.5 V VSS
voltage (1) ed operation
Operational –6.0 –2.4 *1
Operating Operational V5–16.0 –4.0 V V5 *2
voltage (2) Operational V1, V20.4 × V5VDD VV1, V2
Operational V3, V4V50.6 × V5VV3, V4
High-level input voltage VIHC1 0.3 × VSS VDD V*3
VIHC2 0.15 × VSS VDD *4
VIHC1 VSS = –2.7 V 0.3 × VSS VDD *3
VIHC2 VSS = –2.7 V 0.2 × VSS VDD *4
Low-level input voltage VILC1 VSS 0.7 × VSS V*3
VILC2 VSS 0.85 × VSS *4
VILC1 VSS = –2.7 V VSS 0.7 × VSS *3
VILC2 VSS = –2.7 V VSS 0.8 × VSS *4
High-level output voltage VOHC1 IOH = –1 mA 0.2 × VSS VDD V*5
VOHC2 IOH = –120 µA 0.2 × VSS VDD OSC2
VOHC1 VSS = –2.7 V IOH = –0.5 mA 0.2 × VSS VDD V*5
VOHC2 VSS = –2.7 V IOH = –50 µA 0.2 × VSS VDD OSC2
Low-level output voltage VOLC1 IOL = 1 mA VSS 0.8 × VSS V*5
VOLC2 IOL = 120 µAVSS 0.8 × VSS OSC2
VOLC1 VSS = –2.7 V IOL = 0.5 mA VSS 0.8 × VSS V*5
VOLC2 VSS = –2.7 V IOL = 50 µAVSS 0.8 × VSS OSC2
Input leakage current ILI VIN = VDD or VSS –1.0 1.0 µA*6
Output leakage current ILO –3.0 3.0 µA*7
LCD driver ON resistance RON Ta = 25°CV5 = –14.0 V 2.0 3.0 kΩO0 to O166
V5 = –8.0 V 3.0 4.5 *8
Static power consumption ISSQ 0.00 5.0 µAVSS
I5Q V5 = –18.0V 0.01 15.0 µAV5
Input terminal capacity CIN Ta = 25°C f=1MHz 5.0 8.0 pF *3 *4
Oscillation frequency fOSC Rf=1 MΩVSS = –5V 15 18 22 kHz *9
±2% VSS = –2.7V 11 16 21
DC Characteristics
Reset time tR1.0 µs *10
Reset “L” pulse width tRW 1.0 µs *11
Input voltage VSS –6.0 –2.4 V *12
Amplified out- VOUT
when triple
–18.0 V VOUT
put voltage
boosting
Voltage regulator VOUT –16.0 –6.0 V VOUT
operation
voltage
Voltage regulutor V5
1
Supplied to S1D15600D00B*–16.0 –6.0 V *13
operation voltage V5
2
Supplied to S1D15601D00B*–16.0 –5.0 V
V5
3
Supplied to S1D15601D10B*–16.0 –4.0 V
V5
4
Supplied to S1D15602D00B*–16.0 –4.5 V
Reference voltage VREG Ta = 25°C –2.35 –2.5 –2.65 V
* See the 4-12 page for details.
Built-in power circuit
*VSS = –2.4V is on the same basis as VSS = –2.7V.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–11
When dynamic current consumption (I) is displaye; the built-in power circuit is on and T1 = T2 =
LOW. VDD = 0 V, VSS = –5 V ± 10%, Ta = –30 to +85°C unless otherwise noted.
Typical current consumption characteristics
- Dynamic current consumption (I), if an external clock and an external power supply are used.
- Dynamic current consumption (I), if the built-in oscillator and the external power supply are used.
Item Symbol Condition Min. Typ. Max. Unit Remarks
S1D15600 V5 = –12.5 V; 3 times amplified 169 340 µA
S1D15601 V5 = –8.0 V ; 3 times amplified 124 250 µA
S1D15602 IDD (1) V5 = –6.0 V ; 2 times amplified 53 110 µA *16
VSS = –2.7 V; 3 times amplified 66 130 µA
V5 = –6.0 V
Conditions: The built-in power supply is off but
the external one is used.
S1D15600 V5 – VDD = –12.5 V
S1D15601 V5 – VDD = –8.0 V
S1D15602 V5 – VDD = –6.0 V
External clock:
S1D15600 fCL = 4 kHz
S1D15601 fCL = 2 kHz
S1D15602 fCL = 1 kHz
Remarks: *14
Conditions: The built-in power supply is off but
the external one is used.
S1D15600 V5 – VDD = –12.5 V
S1D15601 V5 – VDD = –8.0 V
S1D15602 V5 – VDD = –6.0 V
Internal oscillation:
S1D15600 Rf = 1 MΩ
S1D15601 Rf = 1 MΩ
S1D15602 Rf = 1 MΩ
Remarks: *15
40
30
20
10
(A)
I (1)
(I + I5)
DD
SS
0 1234567
V
DD
(V)
S1D15600
S1D15601
S1D15602
S1D15600
S1D15601
S1D15602
80
60
40
20
(A)
I (1)
(I + I5)
DD
SS
0 1234567
V
DD
(V)
S1D15600
S1D15601
S1D15602
S1D15600
S1D15601
S1D15602
S1D15600/601/602 Series
7–12 EPSON Rev. 4.6
200
150
100
50
(A)
I (1)
DD
0 1234567
V
DD
(V)
S1D15600
S1D15601
S1D15602
S1D15600
S1D15601
S1D15602
Conditions: The built-in power supply is on and
T1 = T2 = Low.
S1D15600 V5 – VDD = –12.5 V; 3
times amplified
S1D15601 V5 – VDD = –8.0 V; 3
times amplified
S1D15602 V5 – VDD = –6.0 V; 2
times amplified
Internal oscillation:
S1D15600 Rf = 1 MΩ
S1D15601 Rf = 1 MΩ
S1D15602 Rf = 1 MΩ
Remarks: *16
- Dynamic current consumption (I), if the built-in power supply is used.
Notes: *1. Although the wide range of operating voltage is guaranteed, a spike voltage change during access to the
MPU is not guaranteed.
*2. The operating voltage range of the VSS and V5 systems (see Figure 11).
The operating voltage range is applied if an external power supply is used.
*3. Pins A0, D0 to D7, RD (E), WR (R/W), CS1, CS2, FR, SYNC, M/S, C86, SI, P/S, T1 and T2.
*4. Pins CL, SCL, and RES
*5. Pins D0 to D7, FR, SYNC, CL0, and DY0
*6. Pins A0, RD (E), WR (R/W), CS1, CS2, CL, M/S, RES, C86, SI, SCL, P/S, T1, and T2.
*7. Applied if pins D0 to D7, FR, and SYNC are high impedance.
*8. The resistance when the 0.1-volt voltage is applied between the “On” output terminal and each power
terminal (V1, V2, V3 or V4). It must be within the operating voltage (2).
R ON = 0.1 V/∆I
(∆I is the current that flows when 0.1 VDC is applied during power-on.)
*9. The relationship between the oscillation frequency, frame and Rf value (see Figure 10).
*10. “tr” (reset time) indicates the period between the time when the RES signal rises and when the internal
circuit has been reset. Therefore, the S1D1560* is usually operable after “tr” time.
*11. Specifies the minimum pulse width of RES” signal. The LOW pulse greater than “tRW” must be entered
for reset.
*12. If the voltage is amplified three times by the built-in power circuit, the primary power VSS must be used
within the input voltage range.
*13. The V5 voltage can be adjusted within the voltage follower operating range by the voltage regulator
circuit.
*14, 15, 16 Indicates the current consumed by the separate IC. The current consumption due to the LCD panel
capacity and wiring capacity is not included.
The current consumption is shown if the checker is used, the display is turned on, the output status of
Case 6 is selected, and the S1D15600D00B* is set to 1/64 duty, the S1D15601D00B* is set to 1/32
duty, and the S1D15602D00B* is set to 1/16 duty.
*14. Applied if an external clock is used and if not accessed by the MPU.
*15. Applied if the built-in oscillation circuit is used and if not accessed by the MPU.
*16. Applied if the built-in oscillation circuit and the built-in power circuit are used (T1 = T2 = Low) and if
not accessed by the MPU. Measuring conditions: C1 = 4.7 µF, C2 = 0.47 µF, Ra + Rb = 2 MΩ
This includes the current that flows through the voltage regulator resistor (Ra + Rb = 2 MΩ). If the
built-in power circuit is used, the current consumption is equal to the current of VSS power.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–13
Oscillator frequency vs. frame vs. Rf
[S1D1560*D00B*]
Figure 10 (a)
External clock (fCL) vs. frame
[S1D1560*D00B*]
Figure 10 (b)
The relationship between oscillator frequency fOSC
and LCD frame frequency fF is obtained from the
following expression.
Duty fF
S1D15600 1/64 focs/256
1/48 focs/192
S1D15601 1/32 focs/256
1/24 focs/192
S1D15602 1/16 focs/256
(fF indicates not fF signal cycle but cycle of LCD
AC.)
40
30
20
10
0 0.5 1.0 1.5 2.0 2.5
Ta = 25°C V = –5 V
SS
Rf [M ]
[KHz]
f
OSC
Ω
200
100
0 2468
[Hz]
[KHz]
duty 1/64 S1D15600
F
CL
duty 1/48
duty 1/32 S1D15601
duty 1/24
duty 1/16 S1D15602
f
f
S1D15600/601/602 Series
7–14 EPSON Rev. 4.6
2468
[V]
VSS [V]
–16
–13
2.4 3.0
–20
–10
0
–5
–15
V5–VDD
Operating voltage range for VSS and V5
Figure 11
Power consumption during access (IDD (2)) -
MPU access cycle
Figure 12
This graphic shows the current consumption when
the vertical patterns are written during “fcyc”. If not
accessed, IDD(1) is only shown.
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
Reset time tRSee note. 1.0 — — µs
Reset LOW-level pulsewidth
tRW 1.0 — — µs
Note
tR is measured from the rising edge of RES. The S1D15600 enters normal operating mode after a reset.
Reset
10
1
0.1
0.01
0 0.01 0.1 1 10
f c
y
c
[
MHz
]
[mA]
I
DD
(2)
5.0V
2.7V
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–15
Display control timing
Input timing
VSS = –4.5 to –2.7 V, Ta = –30 to 85 °C
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
CL LOW-level pulsewidth tWLCL 35 — — µs
CL HIGH-level pulsewidth tWHCL 35 — — µs
CL rise time tr—40—ns
CL fall time tf—40—ns
FR delay time tDFR –1.0 — 1.0 µs
SYNC delay time tDSNC –1.0 — 1.0 µs
Notes: 1. Effective only when the S1D15600D00B* is in the master mode.
2. The FR/SYNC delay time input timing is provided in the slave operation.
The FR/SYNC delay time output timing is provided in the master operation.
3. Each timing is based on 20% and 80% of VSS.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
VSS = –5.5 to –4.5 V, Ta = –30 to 85 °C
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
CL LOW-level pulsewidth tWLCL 35 — — µs
CL HIGH-level pulsewidth tWHCL 35 — — µs
CL rise time tr—30—ns
CL fall time tf—30—ns
FR delay time tDFR –1.0 — 1.0 µs
SYNC delay time tDSNC –1.0 — 1.0 µs
CL
SYNC
FR
DYO
CLO
WLCL WHCL
tf t
t
t
t
tr
t
t
tt
DFR
DSNC
DOL
CDL
DOH
CDH
S1D15600/601/602 Series
7–16 EPSON Rev. 4.6
Output timing
(1) System buses
VSS = –5.5 to –4.5 V, Ta = –30 to 85 °C
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
FR delay time tDFR CL = 50 pF — 60 150 ns
SYNC delay time tDSNC — 60 150 ns
DYO LOW-level delay time tDOL — 70 160 ns
DYO HIGH-level delay time tDOH — 70 160 ns
CLO to DYO LOW-level S1D15600D0*B* operating in
tCDL 10 40 100 ns
delay time master mode only
CLO to DYO HIGH-level S1D15600D0*B* operating in
tCDH 10 40 100 ns
delay time master mode only
VSS = –4.5 to –2.7 V, Ta = –30 to 85 °C
Rating
Parameter Symbol Condition Unit
Min. Typ. Max.
FR delay time tDFR CL = 50 pF — 120 240 ns
SYNC delay time tDSNC — 120 240 ns
DYO LOW-level delay time tDOL — 140 250 ns
DYO HIGH-level delay time tDOH — 140 250 ns
CLO to DYO LOW-level S1D15600D0*B* operating in
tCDL 10 100 200 ns
delay time master mode only
CLO to DYO HIGH-level S1D15600D0*B* operating in
tCDH 10 100 200 ns
delay time master mode only
Read/write characteristics I (80-series MPU)
WR, RD
(CS)
D0 ~ D7
(WRITE)
D0 ~ D7
(READ)
t
ACC8
t
CH8
t
DS8
t
DH8
tf
t
AW8
t
CCLR
tr
t
CYC8
t
CCLW
t
CCHR
t
CCHW
t
AH8
A0
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–17
VSS = –5.0 ±10%, Ta = –30 to 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Address hold time A0, CS tAH8 10 ns
Address setup time tAW8 10 ns
System cycle time tCYC8 200 ns
Control LOW pulse width (WR) WR tCCLW 22 ns
Control LOW pulse width (RD) RD tCCLR 77 ns
Control HIGH pulse width (WR) WR tCCHW 172 ns
Control HIGH pulse width (RD) RD tCCHR 117 ns
Data setup time tDS8 20 ns
Data hold time tDH8 10 ns
RD access time D0 to D7 tACC8 CL = 100pF 70 ns
Output disable time tCH8 10 50 ns
Input signal change time tr, tf15 ns
VSS = –2.7 to –4.5 V, Ta = –30 to 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Address hold time A0, CS tAH8 0ns
Address setup time tAW8 0ns
System cycle time tCYC8 450 ns
Control LOW pulse width (WR) WR tCCLW 44 ns
Control LOW pulse width (RD) RD tCCLR 194 ns
Control HIGH pulse width (WR) WR tCCHW 394 ns
Control HIGH pulse width (RD) RD tCCHR 244 ns
Data setup time tDS8 20 ns
Data hold time tDH8 10 ns
RD access time D0 to D7 tACC8 CL = 100pF 140 ns
Output disable time tCH8 10 100 ns
Input signal change time tr, tf15 ns
Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC8–tCCLW–
tCCHW) or tr + tf ≤ (tCYC8–tCCLR–tCCHR)
2. All signal timings are limited based on the 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the
LOW level.
If read/write operation is performed by the RD or WR signal while CS is active, it is determined by the
RD or WR signal timing.
If read/write operation is performed by CS while the RD or WR signal is in the low level, it is deter-
mined by the CS active timing.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
S1D15600/601/602 Series
7–18 EPSON Rev. 4.6
(2) System buses
Read/write characteristics II (68-series MPU)
VSS = –5.0 V ± 10%, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
System cycle time tCYC6 200 ns
Address setup time (A0) tAW6 10 ns
Address hold time R/W tAH6 10 ns
Data setup time tDS6 20 ns
Data hold time D0~D7 tDH6 10 n
Output disable time tOH6 CL = 100pF 10 50 ns
Access time tACC5 70 ns
Enable HIGH pulse READ EtEWHR 77 ns
width WRITE tEWHW 22 ns
Enable LOW pulse READ EtEWLR 117 ns
width WRITE tEWLW 172 ns
Input signal change time tr, tf15 ns
E
A0, R/W
D0 ~ D7
(WRITE)
D0 ~ D7
(READ)
t
CYC6
t
EWLR
t
EWLW
t
AW6
t
EWHR
t
EWHW
tf
t
AH6
t
DH6
t
DS6
t
ACC6
t
OH6
tr
t
AH6
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–19
CS
SCL
SI
A0
tf tSDS
tSLW tSCYC
tr tSHW
tSDH
tSAS tSAH
tCSS tCSH
VSS = –2.7 V ~ 4.5 V, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
System cycle time tCYC6 450 ns
Address setup time A0 tAW6 0ns
Address hold time R/W tAH6 0ns
Data setup time tDS6 20 ns
Data hold time D0 to D7 tDH6 10 ns
Output disable time tOH6 CL = 100pF 20 100 ns
Access time tACC5 140 ns
Enable HIGH pulse READ EtEWHR 194 ns
width WRITE tEWHW 44 ns
Enable LOW pulse READ EtEWLR 244 ns
width WRITE tEWLW 394 ns
Input signal change time tr, tf15 ns
Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC6-tEWLW-tEWHW)
or tr + tf ≤ (tCYC6-tEWLR-tEWHR).
2. All signal timings are limited based on the 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal
timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the
CS active timing.
4. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
(3) Serial interface
S1D15600/601/602 Series
7–20 EPSON Rev. 4.6
VSS = –5.0 V ±10%, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Serial clock cycle SCL tSCYC 250 ns
SCL HIGH pulse width tSHW 75 ns
SCL LOW pulse width tSLW 75 ns
Address setup time A0 tSAS 50 ns
Address hold time tSAH 200 ns
Data setup time SI tSDS 50 ns
Data hold time tSDH 30 ns
CS-SCL time cs tCSS 30 ns
tCSH 400
Input signal change time tr, tf50 ns
VSS = –2.7 V ~ –4.5 V, Ta = –30 ~ 85 °C
Item Signal Symbol Conditions Min. Max. Unit
Serial clock cycle SCL tSCYC 500 ns
SCL HIGH pulse width tSHW 150 ns
SCL LOW pulse width tSLW 150 ns
Address setup time A0 tSAS 100 ns
Address hold time tSAH 400 ns
Data setup time SI tSDS 100 ns
Data hold time tSDH 100 ns
CS-SCL time cs tCSS 60 ns
tCSH 800
Input signal change time tr, tf50 ns
*1. All signal timings are limited based on the 20% and 80% of VSS voltage.
*2. When usingin the range of VSS = –2.4 ~ –4.5V, raise the above ratings for –2.7 ~ –4.5V equally by 30%.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–21
Common
6800 series 8080 series Description
A0 R/W E
RD WR
1 1101Display data read out
1 0110Display data write
0 1101Status read
Write to internal reigister
0 0110
(command)
7. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Parallel/serial interface
Parallel data can be transferred in either direction be-
tween the controlling microprocessor and the S1D15600/
601/602 series through the 8-bit I/O buffer (D0 to D7).
Serial data can be sent from the microprocessor to the
S1D15600/601/602
series through the serial data input (SI), but not from the
S1D15600/601/602 series to the microprocessor. The
parallel or serial interface is selected by P/S as shown in
table 1.
Table 3. Parallel data transfer
For the parallel interface, the type of microprocessor is
selected by C86 as shown in table 2.
Table 2. Microprocessor selection for parallel
interface
Parallel interface
A0, WR (or R/W) and RD (or E) identify the type of
parallel data transfer to be made as shown in table 3.
Serial interface
The serial interface comprises an 8-bit shift register and
a 3-bit counter. These are reset when CS1 is HIGH and
CS2 is LOW. When these states are reversed, serial data
and clock pulses can be received from the microproces-
sor on SI and SCL, respectively.
Serial data is read on the rising edge of SCL and must be
input at SI in the sequence D7 to D0. On every eighth
clock pulse, the data is transferred from the shift register
and processed as 8-bit parallel data.
Input data is display data when A0 is HIGH and control
data when A0 is LOW. A0 is read on the rising edge of
every eighth clock signal.
The SLC signal is affected by the termination reflection
and external noise caused by the line length. The opera-
tion check on the actual machine is recommended.
MPU bus
C86 CS1 CS2 A0 RD WR D0 to D7
type
HIGH 6800-series CS1 CS2 A0 E R/W D0 to D7
LOW 8080-series CS1 CS2 A0 RD WR D0 to D7
Table 1. Parallel/serial interface selection
P/S Input type CS1 CS2 A0 RD WR C86 SI SCL D0 to D7
HIGH Parallel CS1 CS2 A0 RD WR C86 — — D0 to D7
LOW Serial CS1 CS2 A0 — — — SI SCL (Hz)
Note
“—” indicates fixed to either HIGH or to LOW
S1D15600/601/602 Series
7–22 EPSON Rev. 4.6
Figure 1. Serial interface timing
Chip select inputs
The S1D15600/601/602 series has two chip select pins:
CS1 and CS2, and data exchange between the microproc-
essor and the S1D15600/601/602 series is enabled when
CS1 is LOW and CS2 is HIGH. When these pins are set
to any other combination, D0 to D7 are high impedance.
The A0, RD, WR, SI and SCI inputs are disabled. If the
serial input interface has been selected, the shift register
and counter are reset. The Reset signal is entered
independent from the CS1 and CS2 status.
Data Transfer
To match the timing of the display data RAM and
registers to that of the controlling microprocessor, the
S1D15600/601/602 series uses an internal data bus and
bus buffer. A kind of pipeline processing takes place.
When the microprocessor reads the contents of RAM, the
data for the initial read cycle is first stored in the busbuffer
(dummy read cycle). On the next read cycle, the data is
read from the bus buffer onto the microprocessor bus. At
the same time, the next block of data is transferred from
RAM to the bus buffer. Likewise, when the microproc-
essor writes data to display data RAM, the data is first
stored in the bus buffer before being written to RAM at
the next write cycle.
When writing data from the microprocessor to RAM,
there is no delay since data is automatically transferred
from the bus buffer to the display data RAM. If the data
rate is required to slow down, the microprocessor can
insert an NOP instruction which has the same affect as
executing a wait procedure.
When a sequence of address sets is executed, a dummy
read cycle must be inserted between each pair of address
sets. This is necessary because the addressed data from
the RAM is delayed one cycle by the bus buffer, before
it is sent to the microprocessor. A dummy read cycle is
thus necessary after an address set and after a write cycle.
Figure 2. Write timing
N N+1 N+2 N+3
N N+1 N+2 N+3
WR
Bus
holder
DATA
MPU
WR
Internal
timing
12345678910
CS1
CS2
SI
SCL
A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–23
Figure 3. Read timing
Status Flag
The S1D15600/601/602 series has a single bit status flag,
D7. When D7 is HIGH, the device is busy and will only
accept a Status Read command. If cycle times are
monitored ed carefully, this flag does not have to be
checked before each command, and microprocessor ca-
pabilities can be fully utilized.
N n N+1 N+2
Nn
n+1
N+2
WR
Bus
holder
DATA
MPU
Internal
timing
Address set Dummy read Data read n Data read (n+1)
RD
WR
RD
Column
address N N+1
N
S1D15600/601/602 Series
7–24 EPSON Rev. 4.6
Figure 4. Display data RAM addressing
Note
For a 1/65 and 1/33 display duty cycles, page 8 is accessed following 1BH and 3BH, respectively.
Display Data RAM
The display data RAM stores pixel data for the LCD. It
is a 166-column × 65-row addressable array as shown in
figure 4.
Line
address
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
DATA
Page
address D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
0
Page 1
Page 0
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Common
address
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM I
1/64
Start
1/32
ADC
DO
=1 DO
=0
A5
A4
A3
A2
A1
A0
9F
9E
00
01
02
03
04
05
06
07
LCD
OUT
O0
O1
O2
O3
O4
O5
O6
O7
A2O3
O162
A3
A4
A5
O2
O1
O0
O163
O164
O165
000
0001
0010
0011
0100
0101
0110
0111
1000
to
to
to
Column address
(If the display start line is set to 1ch)
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–25
The 65 rows are divided into 8 pages of 8 lines and a ninth
page with a single line (D0 only). Data is read from or
written to the 8 lines of each page directly through D0 to
D7.
The time taken to transfer data is very short, because the
microprocessor inputs D0 to D7 correspond to the LCD
common lines as shown in figure 5. Large display
configurations can thus be created using multiple
S1D15600/601/602.
Figure 5. RAM-to-LCD data transfer
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller oper-
ates independently, data can be written to RAM at the
same time as data is being displayed, without causing the
LCD to flicker.
Column Address Counter
The column address counter is an 8-bit presettable coun-
ter that provides the column address to display data
RAM. See figure 4. It is incremented by 1 each time a
read or write command is received. The counter auto-
matically stops at the highest address, A6H. The con-
tents of the column address counter are changed by the
Column Address Set command. This counter is inde-
pendent of the page address register.
When the Select ADC command is used to select inverse
display operation, the column address decoder inverts
the relationship between the RAM column data and the
display segment outputs.
Page Address Register
The 4-bit page address register provides the page address
to display data RAM. The contents of the register are
changed by the Page Address Set command.
Page address 8 (D3 = HIGH, D2, D1, D0 = LOW) is a
special use RAM area for the indicator.
Initial Display Line Register
The initial display line register stores the address of the
RAM line that corresponds to the first (normally the top)
line (COM0) of the display. See figure 4. The contents
of this 6-bit register are changed by the Initial Display
Line command. At the start of each LCD frame, synchro-
nized with SYNC, the initial line is copied to the line
counter. The line counter is then incremented on the CL
clock signal once for every display line. This generates
the line addresses for the transfer of the 166 bits of RAM
data to the LCD drivers.
If a 1/65 or 1/33 display duty cycle is selected by the Duty
+ 1 command, the line address corresponding to the 65th
or 33rd SYNC signal is changed and the indicator spe-
cial-use line address is selected. If the Duty + 1 command
is not used, the indicator special-use line address is not
selected.
Output Selection Circuit
The number of common (COM) and segment (SEG)
driver outputs can be selected to fit different LCD panel
configurations by the output selection circuit.
There are 70 segment-only outputs (O32 to O101) and 96
common or segment dual outputs (O0 to O31 and O102
to O165). A command select the status of the dual
common/segment outputs. Figure 6 shows the six differ-
ent LCD driver arrangements.
Necessary LCD driver voltage is automatically allocated
to the COM/SEG dual outputs when their function is
determined by the output selection circuit.
The S1D15600 selects Case 1, 2 or 6 while the S1D15601
selects Case 3, 4, 5 or 6. As to the S1D15602, COM/SEG
output status cannot be selected, being fixed.
D0
D1
D2
D3
D4
1
0
1
0
0
COM0
COM1
COM2
COM3
COM4
S1D15600/601/602 Series
7–26 EPSON Rev. 4.6
Figure 6. Output configuration selection
the appropriate duty must be selected for each case.
Cases 1 to 6 are determined according to the three lowest
bits in the output status register in the output selection
circuit. The COM output scanning direction can be
selected by setting bit D3 in the output status register to
HIGH or LOW.
When COM outputs are assigned to the output drivers,
the unused RAM area is not available. However, all
RAM column addresses can still be accessed by the
microprocessor.
Since duty setting and output selection are independent,
Table 4
When the DUTY + 1 command is executed, pin COM1
becomes as shown in Figure 4 irrelevant to output selec-
tion:
Since master/slave operation and the output selection
circuit are completely independent in the S1D15600/
601/602 series, a chip either on the master or slave side
can be allocated to the COM output function in multi-
chip configuration.
The LCD driver outputs shown in Table 5 become
ineffective when the S1D15600 or S1D15601 is used
with 1/48 or 1/24 duty, respectively. In this case,
ineffective outputs are used in the open state.
S1D15600 S1D15601 S1D15602
Duty 1/64 1/48 1/32 1/24 1/16
COM I function COM64 COM48 COM32 COM24 COM16
Output status register Ineffective output
D3 D2 D1 D0
0101 O150 to O165
Case 1 1101 O102 to O117
S1D15600 0100 O150 to O165
Case 2 1100 O16toO31
0011 O0toO7
Case 3 1011 O23toO31
0010 O158 to O165
S1D15601 Case 4 1010 O134 to O141
0001 O158 to O165
Case 5 1001 O8toO15
Table 5
(D0) LOW 0
165 165
0
Column address
Display data RAM
102 segments
32 commons
32 commons
16 commons
102 segments
134 segments 32 commons
32 commons
64 commons
16 commons
134 segments
166 segments
134 segments
Case 1
Case 2
Case 3
Case 5
Case 4
Case 6 ↑
O0 ↑
O15 ↑
O31 ↑
O101 ↑
O133 ↑
O149 ↑
O165
→
←→
←
ADC HIGH
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–27
Status register
Case
3
4
D3
0
1
0
1
0
1
–
D2
0
0
0
0
0
0
0
D1
1
1
1
1
0
0
0
D0
1
1
0
0
1
1
0
1/32 duty
5
6
Status register
Case
3
4
D3
0
1
0
1
0
1
–
D2
0
0
0
0
0
0
0
D1
1
1
1
1
0
0
0
D0
1
1
0
0
1
1
0
1/24 duty
5
6
LCD driver output
O0 O15 O16 O31
COM31
COM0
COM0
COM31
O165149
O134 150
O133
SEG134
SEG134
COM0
COM31
COM31
COM0
COM16→31
O32
SEG134
SEG134
15←COM0
15←COM0
COM16→31
SEG134
SEG134
SEG166
LCD driver output
O0 O15 O16 O31
COM23
COM0
COM0
COM23
O165149
O134 150
O133
SEG134
SEG134
COM0
COM23
COM23
COM0
16→23
O32
SEG134
SEG134
15←COM0
15←COM0
16→23
SEG134
SEG134
SEG166
Status register
Case
1
2
6
D3
0
1
0
1
–
D2
1
1
1
1
0
D1
0
0
0
0
0
D0
1
1
0
0
0
1/64 duty
Status register
Case
1
2
6
D3
0
1
0
1
–
D2
1
1
1
1
0
D1
0
0
0
0
0
D0
1
1
0
0
0
1/48 duty
LCD driver output
O0 O31 O32 O101 O102 O133 O134 O165
COM0 COM63
COM63 COM0
COM63
COM0
COM32
COM31
SEG102
SEG102
SEG166
COM31
COM32
COM0
COM63
LCD driver output
O0 O31 O32 O101 O102 O133 O134 O165
COM0 COM47
COM47 COM0
COM0
COM32
COM31
SEG102
SEG102
SEG166
COM31 COM0 47
COM32 47
SEG102
SEG102
S1D15600 Output Status
The S1D15600 selects any output status from Cases 1, 2
and 6.
S1D15601 Output Status
The S1D15601 selects any output status from Cases 3, 4,
5 and 6.
(Display Area 24 × 134)
(Display Area 64 × 102)
(Display Area 48 × 102)
(Display Area 32 × 134)
S1D15600/601/602 Series
7–28 EPSON Rev. 4.6
S1D15602 Output Status
COM/SEG output status of the S1D15602 is fixed.
1/16 duty (16 × 150)
Display Timers
Line counter and display data latch
timing
The display clock, CL, provides the timing signals for the
line counter and the display data latch. The RAM line
address is generated synchronously using the display
clock. The display data latch synchronizes the 166-bit
display data with the display clock.
The timing of the LCD panel driver outputs is independ-
ent of the timing of the input data from the microproces-
sor.
FR and SYNC
The LCD AC signal, FR, and the synchronization signal,
SYNC, are generated from the display clock. The FR
controller generates the timing for the LCD panel driver
outputs. Normally, 2-frame wave patterns are generated,
but n-line inverse wave patterns can also be generated.
These produce a high-quality display if n is based on the
LCD panel being used.
SYNC synchronizes the timing of the line counter and
common timers. It is also needed to synchronize the
frame period and a 50% duty clock.
Table 6. Master and slave timing signal status
Part number Mode FR SYNC CLO DYO
CL
Master Output Output Output
output
SD1560
*
D
**
B
*
High
Slave Input Input Output
impedance
In a multiple-chip configuration, FR and SYNC are
inputs. The SYNC signal from the master synchronizes
the line counter and common timing of the slave.
Common timing signals
The internal common timing and the special-use com-
mon driver start signal, DYO, are generated from CL.
As shown in figures 7 and 8, DYO outputs a HIGH-level
pulse on the rising edge of the CL clock pulse that
precedes a change on SYNC. DYO is generated by both
the S1D15600D0B*, regardless of whether the device is
in master or slave mode. However, when operating in
slave mode, the device duty and the external SYNC
signal must be the same as that of the master. In a
multiple-chip configuration, FR and SYNC must be
supplied to the slave from the master.
LCD driver output
00 0149 150 0165
15 COM0
SEG150
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–29
SYNC
FR
DYO
RAM
data
CL 3132 1 2 3 4 5 6 272829303132 1 2 3 4 5
COM0 V
DD
V
1
V
4
V
5
COM1 V
DD
V
1
V
4
V
5
SEG n
V
DD
V
2
V
3
V
5
(S1D15601 1/32 duty)
2-frame AC driver waveform
Figure 7. Frame driver timing
S1D15600/601/602 Series
7–30 EPSON Rev. 4.6
SYNC
FR
DYO
RAM
data
CL 3132 1 2 3 4 5 6 272829303132 1 2 3 4 5
COM0 V
DD
V
1
V
4
V
5
COM1 V
DD
V
1
V
4
V
5
SEG n
V
DD
V
2
V
3
V
5
n line inverse driver waveform (n = 5, line inverse register 4)
Figure 8. Line inverse driver timing
Note
When n = 5, the line inversion register is set to 4.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–31
Figure 9. Example of segment and common timing
LCD Driver
The LCD driver converts RAM data into the 167 outputs
that drive the LCD panel. There are 70 segment outputs,
96 segment or common dual outputs, and a COM1 output
for the indicator display.
Two shift registers for the common/segment drivers are
used to ensure that the common outputs are output in the
correct sequence. The driver output voltages depend on
the display data, the common scanning signal and FR.
V
DD
V
SS
V
DD
V
1
V
2
V
3
V
4
V
5
V
DD
V
1
V
2
V
3
V
4
V
5
V
DD
V
1
V
2
V
3
V
4
V
5
V
DD
V
1
V
2
V
3
V
4
V
5
V
DD
V
1
V
2
V
3
V
4
V
5
V
5
V
4
V
3
V
2
V
1
V
DD
–V
1
–V
2
–V
3
–V
4
–V
5
V
5
V
4
V
3
V
2
V
1
V
DD
–V
1
–V
2
–V
3
–V
4
–V
5
FR
(SYNC)
COM0
COM1
COM2
SEG0
SEG1
COM0
to
SEG0
COM0
to
SEG1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM 1
COM12
COM13
COM14
COM15
SEG0 SEG1 SEG2 SEG3 SEG4
S1D15600/601/602 Series
7–32 EPSON Rev. 4.6
Display Data Latch Circuit
The display data latch circuit temporarily stores the
output display data from the display data RAM to the
LCD driver circuit in each common period. Since the
Normal/Inverse Display, Display ON/OFF and Display
All Points ON/OFF commands control the data in this
latch, the data in the display data RAM is remains
unchanged.
LCD Driver Circuit
This multiplexer generates 4-value levels for the LCD
driver, having 167 outputs of 70 SEG outputs, 96 SEG/
COM dual outputs and a COM output for the indicator
display. The SEG/COM dual outputs have a shift register
and sequentially transmits COM scanning signals. The
LCD driver voltage is output according to the combina-
tion of display data, COM scanning signal and FR signal.
Figure 9 shows a typical SEG/COM output waveform.
Oscillator Circuit
The low power consumption type CR oscillator adjusting
the oscillator frequency by use of only oscillator resistor
Rf is used as a display timing signal source or clock for
the voltage raising circuit of the LCD power supply.
The oscillator circuit is only available in the master
operation mode. When a signal from the oscillator circuit
is used for display clock, fix the CL pin to the VSS level.
When the oscillator circuit is not used, fix the OSC1 or
OSC2 pin to the VDD or VSS level, respectively.
The oscillator signal frequency is divided and output
from the CLO pin as display clock. The frequency is
divided to one-fourth, one-eighth or one-sixteenth in the
S1D15600, S1D15601 or S1D15602, respectively.
FR Control Circuit
The LCD driver voltage supplied to the LCD driver
outputs is selected using FR signal.
Power Supply Circuit
This is a power circuit to produce voltage needed to drive
liquid crystals at a low power consumption. This circuit
is valid only when the S1D1560*D**B* master is in
opera-tion. The power circuit consists of voltage tripler,
voltage regulator and the voltage follower.
The power circuit built into S1D1560*D**B* is set for
smaller scale liquid crystal panels and it is not too
suitable when the picture element is larger or to drive a
liquid crystal panel with lager indication capacity using
multiple chips. With liquid crystal panels with a larger
load capacity, the quality of display may become very
bad. Use an external power in such cases. (If an external
amp circuit is configured, we recommend to use the
S1F76600 and S1F76610.)
The power circuit can be controlled by the built-in power
ON/OFF command. When the built-in power is turned
off, all of the boosting circuit, voltage regulation circuit
and voltage follower circuit goes open. In this case, the
liquid crystal driving voltage V1, V2, V3, V4 and V5
should be supplied from outside and the terminals CAP1+,
CAP1-, CAP2+, CAP2-, Vout and VR should be kept
opened.
If the built-in power supply is turned on, you must always
enter this command after the wait time of the built-in
power supply turn-on completion command.
Various functions of the power circuit may be selected by
combinations of the setting of the T1 and T2. It is also
possible to make a combined use of the external power
Voltage Voltage voltage External Voltage
T1 T2 tripler regulator follower voltage tripler VR terminals
input terminals
LOW LOW ●●●●●●–
LOW HIGH ●●●●●●–
HIGH LOW ×●●●●VOUT OPEN
HIGH HIGH ××●●V5OPEN OPEN
supply and a portion of the functions of the built-in power
supply.
When (T1, T2) = (HIGH, LOW), the boosting circuit
does not work and open the boosting circuit terminals
(CAP1+, CAP1-, CAP2+ and CAP2-) and apply liquid
crystal driving voltage to the Vout terminals from outside.
When (T1, T2) = (HIGH, HIGH), the boosting circuit and
voltage regulation circuit do not work and open the
boosting circuit terminals and the VR terminals and
apply liquid crystal driving voltage connecting the V5
terminals.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–33
Voltage tripler
By connecting capacitors C1 between CAP1+ and
CAP1-, CAP2+ and CAP2- and VSS-Vout, the electric
potential between VDD-VSS is boosted to the triple
toward negative side and outputted from the Vout termi-
nal. When a double boosting is required, disconnect the
capacitor between CAP2+ and CAP2- and short-circuit
the CAP2- and Vout terminals to obtain output boosted
to the double out of the Vout (or CAP2-) terminal.
Signals from the oscillation circuit are used in the boost-
ing circuit and it then is necessary that the oscillation
circuit is in operation.
Electric potentials by the boosting functions are given
below.
Electric potentials of double boosting
Electric potentials of triple boosting
Voltage Regulator
The boosting voltage occurring at VOUT is sent to the
voltage regulator, and the V5 liquid crystal display (LCD)
driver voltage is output. This V5 voltage can be determined
by the following equation when resistors Ra and Rb (R1,
R2 and R3) are adjusted within the range of |V5| < |VOUT|.
VREG is the constant voltage source of the IC, and it is
constant and VREG –2.5 ± 0.15 V (if VDD is 0 V). To
adjust the V5 output voltage, insert a variable resistor
between VR, VDD and V5 as shown. A combination of R1
and R3 constant resistors and R2 variable resistor is
recommended for fine-adjustment of V5 voltage.
Setup example of resistors R1, R2 and R3: (In case of
Type 1)
When the Electronic Volume Control Function is OFF
(electronic volume control register values are
(D4,D3,D2,D1,D0)=(0,0,0,0,0)):
V5 = V
REG ....................... 1
(As IREF = 0 A)
• R1 + R2 + R3 = 5MΩ................................ 2
(Determined by the current passing between
VDD and V5)
• Variable voltage range by R2 V5 = –6 to –10 V
(Determined by the LCD characteristics)
∆R2 = OΩ, VREG = –2.55V
To obtain V5 = -10 V, from equation 1:
R2 + R3 = 2.92 × R1 ..................... 3
∆R2 = R2, VREG = –2.55V
To obtain V5 = -6 V, from equation
1
:
1.35 × (R1 + R2) = R3 .................. 4
From equations 2, 3 and 4:
R1=1.27MΩ
R2=0.85MΩ
R3=2.88MΩ
(VCC=+5V) VDD=0V
(GND) SS=–5VV
OUT=2VV SS=–10V
VDD
VSS
=0V
=–5V
OUT=3VV SS=–15V
V
DD
V
REG
R1
+
-
V
5
=(1+ ) V
REG
+I
REF
· Rb
Ra
R2
∆R2
VR I
REF
=(1+ ) V
REG
R1+∆R2
R3+R2-∆R2
+I
REF
· (R3+R2-∆R2)
Rb
V
5
R3
Ra
Rb
( 1 + R3 + R2 – ∆R2)
R1 + ∆R2
.
=
.
S1D15600/601/602 Series
7–34 EPSON Rev. 4.6
The voltage regulator has a temperature gradient of
approximately -0.2%/°C as the V REG voltage. To obtain
another temperature gradient, use the Electronic Volume
Control Function for software processing using the MPU.
As the VR pin has a high input impedance, the shielded
and short lines must be protected from a noise interference.
In case of Type 2, similarly preset R1, R2 and R3 on the
basis of VREG = VSS.
Voltage regulator using the Electronic Volume
Control Function
The Electronic Volume Control Function can adjust the
intensity (brightness level) of liquid crystal display (LCD)
screen by command control of V5 LCD driver voltage.
This function sets five-bit data in the electronic volume
control register, and the V5 LCD driver voltage can be
one of 32-state voltages.
To use the Electronic Volume Control Function, issue
the Set Power Control command to simultaneously operate
both the voltage regulator circuit and voltage follower
circuit.
Also, when the boosting circuit is off, the voltage must be
supplied from VOUT terminal.
When the Electronic Volume Control Function is used,
the V5 voltage can be expressed as follows:
V5 = (1 + ) VREG + Rb × ∆IREF ........................
5
Variable voltage range
The increased V5 voltage is controlled by use of IREF
current source of the IC. (For 32 voltage levels, ∆IREF =
IREF/31)
The minimum setup voltage of the V5 absolute value is
determined by the ratio of external Ra and Rb, and the
increased voltage by the Electronic Volume Control
Function is determined by resistor Rb. Therefore, the
resistors must be set as follows:
1) Determine Rb resistor depending on the V5 variable
voltage range by use of the Electronic Volume Control.
Rb = V5 variable voltage range
IREF
2) To obtain the minimum voltage of the V5 absolute
value, determine Ra using the Rb of Step 1) above.
Ra = Rb
V5–1 {V5 = (1 + Rb/Ra) × VREG}
VREG
The S1D15206 series have the built-in V REG reference
voltage and IREF current source which are constant
during voltage variation. However, they may change due
to the variation occurring in IC manufacturing and due to
the temperature change as shown below.
Consider such variation and temperature change, and set
the Ra and Rb appropriate to the LCD used.
VREG = –2.5V±0.15V } Type1
VREG = –0.2%/˚C
VREG = VSS }Type2
VREG = 0.00%/˚C
VREG = –0.2%/°C
IREF = –3.2µA±40% (For 16 levels)
IREF = 0.023µA/°C
–6.5µA±40% (For 32 levels)
0.052µA/°C
Ra is a variable resistor that is used to correct the V 5
voltage change due to VREG and IREF variation. Also, the
contrast adjustment is recommended for each IC chip.
Before adjusting the LCD screen contrast, set the
electronic volume control register values to
(D4,D3,D2,D1,D0)=(1,0,0,0,0) or (0,1,1,1,1) first.
When not using the Electronic Volume Control Function,
set the register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0)
by sending the RES signal or the Set Electronic Volume
Control Register command.
Setup example of constants when Electronic Volume
Control Function is used:
V5 maximum voltage: V5 = –6 V (Electronic
volume control register
values (D4,D3,D2,D1,D0)
= (0,0,0,0,0))
V5 minimum voltages: V5 = –10 V (Electronic
volume control register
values (D4,D3,D2,D1,D0)
= (1,1,1,1,1))
V5 variable voltage range: 4 V
Variable voltage levels: 32 levels
1) Determining the Rb:
R3 = V5 variable voltage range =4V
| IREF |6.5µA
Rb = 625KΩ
2) Determining the Ra:
Ra = Rb =625KΩ
V5max –1 –6V –1
VREG –2.55V
Ra = 462KΩ
Rb
Ra
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–35
Ta=–10°C
V5max = (1+Rb/Ra) × VREG (Ta=–10°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (–10°C–25°C)}
= –6.42V
V5min = V5max + Rb × IREF (Ta=–10°C)
= –6.42V + 625k
× {–6.5µA+(0.052µA/°C) ×
(–10°C–25°C)}
= –11.63V
Ta=–50°C
V5max = (1+Rb/Ra) × VREG (Ta=50°C)
= (1+625k/462k) × (–2.55V)
× {1+(–0.2%/°C) × (50°C–25°C)}
= –5.7V
V5min = V5max + Rb × IREF (Ta=50°C)
= –5.7V + 625k
× {–6.5µA+(0.052µA/°C) ×
(50°C–25°C)}
= –8.95V
The margin must also be determined in the same procedure
given above by considering the VREG and IREF variation.
This margin calculation results show that the V5 center
value is affected by the VREG and IREF variation. The
voltage setup width of the Electronic Volume Control
depends on the IREF variation. When the typical value of
0.2 V/step is set, for example, the maximum variation
range of 0.12 to 0.28 V must be considered.
In case of Type 2, it so becomes that VREG = VSS (VDD
basis) and there is no temperature gradient. However,
IREF carries the same temperature characteristics as with
Type 1.
According to the V5 voltage and temperature change,
equation 5 can be as follows (if VDD = 0 V reference):
Ta=25°C
V5max = (1+Rb/Ra) × VREG
= (1+625k/442k) × (–2.55V)
= –6.0V
V5min = V5 max + Rb × IREF
= –6V + 625k × (–6.5µA)
= –10.0V
S1D15600 Series V
5
[V]
-10V
-5V
-20 0 20 40 60
Ta [¡C]
V
5
variable voltage range
(32 levels)
V
5
(V
DD
) 0V
S1D15600/601/602 Series
7–36 EPSON Rev. 4.6
Example of V5 Voltage When Using S1D15600/601/602 Series Electronic Volume
Liquid Crystal Voltage Generating Circuit
A V5 potential is resistively divided within the IC to
cause V1, V2, V3 and V4 potentials needed for driving of
liquid crystals. The V1, V2, V3 and V4 potentials are
further converted in the impedance by the voltage fol-
lower before supplied to the liquid crystal driving circuit.
The liquid crystal driving voltage is fixed with each type.
As shown in Fig. 8, it needs to connect, externally voltage
stabilizing capacitors C2 to the liquid crystal power
terminals. When selecting such capacitor C2 make
actual liquid crystal displays matching to the display
capacity of the liquid crystal display panel, before deter-
mining on the capacitance as the constant value for
voltage stabilization.
types
Liquid crystal driving voltage
S1D15600D00B*1/9 bias voltage
S1D15600D10B*1/7 bias voltage
S1D15601D00B*1/7 bias voltage
S1D15601D10B*1/5 bias voltage
S1D15602D00B*1/5 bias voltage
S1D15600/601/602 Series V
5
(V)
V
5
Ta (°C)
–20 –10 0 10 20 30 40 50 60
–14
–12
–10
–8
–6
–4
–2
0
V
5
Min.
V
5
typ
V
5
Max.
➁➇
➄
➆
➂
➃
➅
➀
∗∗∗
∗
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–37
V
SS
osc1 osc2 M/S
V
SS
CAP1+
CAP1–
CAP2+
CAP2–
V
OUT
V
5
R3
R2
R1 V
DD
C1
C1
C1
C2
V
1
V
2
V
3
V
4
V
5
S1D1560
*
D
**
B
*
V
SS
CAP1+
CAP1–
CAP2+
CAP2–
V
5
V
DD
V
1
V
2
V
3
V
4
V
5
R
f
V
DD
V
DD
R
f
osc1 osc2 M/S
S1D1560
*
D
**
B
*
External
supply
voltage
V
R
V
OUT
V
R
V
SS
CL CL
*1
*2
V
SS
V
DD
V
DD
V
SS
When the built-in power circuit is not used
When the built-in power circuit is used
*1 Connect oscillator feedback resistor Rf as short
as possible and place it close to the IC for
preventing a malfunction.
*2 Use short wiring or shielded cables for the VR
pin due to high input impedance.
*3 Determine C1, C2 depending on the size of LCD
panel driven. You must set these values so that
the LCD driving voltage becomes stable. Set
(T1, T2)=(HIGH, LOW) and supply an external
voltage to V OUT. Display the LCD heavy load
pattern and determine C2 so that the LCD driving
voltages (V 1 to V5) become stable. Then, set
(T1, T2)=(LOW, LOW) and determine C1.
Set the same capacitance for C2.
*4 The “LCD SIZE” indicates the vertical and
horizontal length of the LCD panel display area.
Reference set values:
S1D15600 V5–11~ –13 V
S1D15601 V5–7~ –9 V
S1D15602 V5–5~ –7 V (Variable)
S1D15600 S1D15601 S1D15602
C1 4.7 µF 2.2 to 2.2 to
4.7 µF 4.7 µF
C2 0.1 to 0.1 to 0.1 µF
0.47 µF 0.47 µF
R1 1 MΩ700 kΩ500 kΩ
R2 200 kΩ200 kΩ200 kΩ
R3 4 MΩ1.6 MΩ700 kΩ
LCD 32×51 16×67 8×75
SIZE mm mm mm
DOT 64×102 32×134 16×150
.
=
.
.
=
.
.
=
.
S1D15600/601/602 Series
7–38 EPSON Rev. 4.6
* Precautions when installing the COG
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10 Ω. However, when installing the COG,
Exemplary connection diagram 1. Exemplary connection diagram 2.
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
2. Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V1. V2, V3 and V4) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause non-
conformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
VDD
VDD
V1
V2
V3
V4
V5
R4
R4
R4
R4
C2
C2
S1D15600/601/602 Series
C2
C2
C2
VDD
VDD
V1
V2
V3
V4
V5
R4
R4
C2
C2
S1D15600/601/602 Series
C2
C2
C2
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–39
Reset
When power is turned ON, the S1D15600/601/602 series
is initialized on the rising edge of RES. Initial settings are
as follows.
1. Display : OFF
2. Display mode : Normal
3. n-line inversion : OFF
4. Duty cycle : 1/64 (S1D15600)
1/32 (S1D15601)
5. ADC select : Normal (D0 = L)
6. Read/write modify : OFF
7. Internal power supply : OFF
8. Serial interface register data: Cleared
9. Display initial line register : Line 1
10. Column address counter : 0
11. Page address register : Page 0
12. Output selection circuit : Case 6
13. n-line inversion register : 16
14. Set the electronic control register to zero (0).
RES should be connected to the microprocessor reset
terminal so that both devices are reset at the same time.
RES must be LOW for at least 1 µs to correctly reset the
S1D15600/601/602 series. Normal operation starts 1 µs
after the rising edge on RES.
If the built-in LCD power circuit of the S1D1560*D**B*
is not used, the RES signal must be low when the external
LCD power supply is turned on. When the RES goes low,
each register is cleared to the above listed initial status.
However, the oscillation circuit and output pins (OSC2,
FR, SYNC, CLD, DYO, D0 to D7 pins) are not affected.
If the S1D15600 is not properly initialized when power
is turned ON, it can lock itself into a state that cannot be
cancelled.
Although S1D15600/601/602 Series devices maintain
the operation status under commands, when external
noise of excessive levels enters, their internal statys may
be changed. Consequently, it is necessary to provide
means to suppress noise occurring from package or the
system or orovide means to avoid influence of such
noise.
Also, to cope with sudden noise, we suggest you to set up
the software so the operation status can be periodically
refreshed.
When the Reset command is used, only initial settings 9
to 14 are active.
S1D15600/601/602 Series
7–40 EPSON Rev. 4.6
8. COMMANDS
The Command Set
A0, RD(E) and WR(R/W) identify the data bus com-
mands. Interpretation and execution of commands are
synchronized to the internal clock. Since a busy check is
normally not needed, commands can be processed at
high speed.
For the 80-series MPU interface, the command is acti-
vated when a low pulse is entered in the RD pin during
read or when a low pulse is entered in the WR pin during
write. While the 68-series MPU interface is set to the
read status when a high pulse is entered in the R/W pin,
Table 7. S1D15600/601/602 series command table
Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Turns the LCD display ON
01010101110and OFF
(1)Display ON/OFF 1 0 : OFF
1 : ON
(2)Display START Determines the RAM
0 1 0 0 1 Dispaly start address
Line set display line for COM 0
Sets the display RAM
(3)Page address set 0 1 0 1 0 1 1 Page address pages in the Page
Address register.
Sets the high order 4
(4)
Column address set;
High-order bits of the display RAM
0100001
high-order 4 bits column address column address in the
register.
Sets the low-order 4 bits
(4)
Column address set;
Low-order of the display RA
0100000
low-order 4 bits column address column address in the
register.
Reads the status
(5)Status read 0 0 1 Status 0000
information.
Writes data in the display
(6)Display data write 1 1 0 Write Data RAM.
Reads data from the
(7)Display data read 1 0 1 Read Data display RAM.
Outputs the display RAM
01010100000
(8)ADC select address for SEG.
10: Normal 1: Reversed
Displays the LCD image
01010100110
(9)Normal/reverse in normal or reverse
1
display mode.
0: Normal 1: Reversed
Lights all segments.
(10)Display all points 0 1 0 1 0 1 0 0100
0: Normal display
ON/OFF 1 1: All ON
01010101000Sets LCD drive duty (1).
(11)Duty select 1 0:1/24, 48 1:1/32, 64
01010101010Sets LCD drive duty (2).
(12)Duty +1 1 0: Normal 1: Duty+1
Sets the line reverse
(13)n-line reverse 0 1 0 0 0 1 1 No. of reversed driving and No. of
register set n-lines reverse lines in the line
reverse register.
(14)n-line reverse 0 1 0 0 0 1 0 0000Releases the line reverse
register release driving.
and it is set to the write status when a low pulse is entered
in this pin. The command is activated when a high pulse
is entered in the E pin. (For their timings, see Section 10
“Timing Characteristics.”) Therefore, the 68-series MPU
interface differs from the 80-series MPU interface in the
point where the RD (or E) signal is 1 (or high) during
status read and during display data read explained in the
command description and on the command table. The
following command description uses an 80-series MPU
interface example.
If the serial interface is selected, data is sequentially
entered from D7.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–41
Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Increments by 1 during
01011100000write of column address
(15)Read Modify write counter, and set to 0
during read.
01011101110Releases the Read
(16)End Modify write mode.
01011100010
(17)Reset Internal reset
(18)Output status 0 1 0 1 1 0 0 Sets the COM and SEG
Output status
register set status in registers.
(19)LCD Power 0 1 0 0 0 1 0 01000: Power OFF
supply ON/OFF 1 1: Power ON
Completes the turn-on
(20)Built-in power 0 1 0 1 1 1 0 1101
sequence of built-in
supply ON/OFF power supply.
Sets the V5 output
(21)Electronic volume 0 1 0 1 0 0 Electronic control voltage in the electronic
control register set value control register.
A complex command to
(22)Power save turn off the display and
light all indictors.
S1D15600/601/602 Series
7–42 EPSON Rev. 4.6
(1) Display ON/OFF
Alternatively turns the display ON and OFF.
Note
D = 0 Display OFF
D = 1 Display ON
(2) Display Start Line Set
Loads the RAM line address of the initial display line,
COM0, into the initial display line register. The RAM
display data becomes the top line of the LCD screen. It
is followed by the higher number lines in ascending
order, corresponding to the duty cycle. The screen can be
scrolled using this command by incrementing the line
address.
A3 A2 A1 A0 Page
00000
00011
00102
00113
01004
01015
01106
01117
10008
(3) Page Address Set
Loads the RAM page address from the microprocessor
into the page address register. A page address, along with
a column address, defines a RAM location for writing or
reading display data. When the page address is changed,
the display status is not affected.
Page address 8 is a special use RAM area for the indica-
tor. Only D0 is available for data exchange.
(5) Status read
Indicates to the microprocessor the four S1D15600 status
conditions.
(4) Column Address Set
Loads the RAM column address from the microproces-
sor into the column address register. The column address
is divided into two parts-4 high-order bits and 4 low-
order bits.
When the microprocessor reads or writes display data to
or from RAM, column addresses are automatically
incremented, starting with the address stored in the
column address register and ending with address 166.
The page address is not incremented automatically.
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010111D
A5 A4 A3 A2 A1 A0 Line address
000000 0
000001 1
000010 2
↓↓
111110 62
111111 63
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0 1 0 0 1 A5A4A3A2A1A0
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101011A3A2A1A0 E R/W
A0D7D6D5D4D3D2D1D0
RD WR
ON/ RES-
0 0 1 Busy ADC 0 0 0 0
OFF ET
A7 A6 A5 A4 A3 A2 A1 A0
Column address
00000000 0
00000001 1
↓↓
10100101 165
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0 1 0 0 0 0 0 A3A2A1A0
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0 1 0 0 0 0 1 A7A6A5A4
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–43
BUSY Indicates whether or not the S1D15600 will
accept a command. If BUSY is 1, the device
is currently executing a command or is reset-
ting, and no new commands can be accepted.
If BUSY is 0, a new command can be ac-
cepted. It is not necessary for the microproc-
essor to check the status of this bit if enough
time is allowed for the last cycle to be com-
pleted.
ADC Indicates the relationship between RAM col-
umn addresses and the segment drivers. If
ADC is 1, the relationship is normal and
column address n corresponds to segment
driver n. If ADC is 0, the relationship is
inverted and column address (165 – n) corre-
sponds to segment driver n.
ON/OFF Indicates whether the display is ON or OFF.
If ON/OFF is 1, the display is OFF. If ON/
OFF is 0, the display is ON. Note that this is
the opposite of the Display ON/OFF com-
mand.
RESET Indicates when initialization is in process as
the result of RES or the Reset command.
(6) Display Data Write
Writes bytes of display data from the microprocessor to
the RAM location specified by the column address and
page address registers. The column address is incremented
automatically so that the microprocessor can continu-
ously write data to the addressed page.
(7) Display Data Read
Sends bytes of display data to the microprocessor from
the RAM location specified by the column address and
page address registers. The column address is incremented
automatically so that the microprocessor can continously
read data from the addressed page. A dummy read is
required after loading an address into the column address
register.
Display data cannot be read through the serial interface.
(8) ADC Select
Selects the relationship between the RAM column ad-
dresses and the segment drivers. When reading or
writing display data, the column address is incremented
as shown in figure 4.
The output pin relationship can also be changed by the
microprocessor. There are very few restrictions on pin
assignments when constructing an LCD module.
(9) Normal/Reverse Display
Determines whether the data in RAM is displayed nor-
mally or inverted.
(10) Display All Points ON/OFF
Turns all LCD points ON independently of the display
data in RAM. The RAM contents are not changed.
This command has priority over the normal/inverse
display command.
If this command is received when the display status is
OFF, the Power Save command is executed.
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
1 1 0 Write data
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
1 0 1 Read data
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010011D
Note
D = 0 LCD segment is ON when RAM data is 1
(normal).
D = 1 LCD segment is ON when RAM data is 0
(inverse).
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010010D
Note
D = 0 Normal display status
D = 1 All display segments ON
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010000D
Note
D = 0 Rotate right (normal direction)
D = 1 Rotate left (reverse direction)
S1D15600/601/602 Series
7–44 EPSON Rev. 4.6
(11) Duty Select
Selects the LCD driver duty.
Since this is independent from contents of the output
status register, the duty must be selected according to the
LCD output status.
In multi-chip configuration, the master and slave devices
must have the same duty.
(12) Duty + 1
Increases the duty by 1. If 1/48 or 1/64 duty is selected
in the S1D15600 for example, 1/49 or 1/65 is set, respec-
tively and COM1 functions as either the COM48 or
COM64 output. The display line always accesses the
RAM area corresponding to page address 8, D0. (Refer
to Figure 4.)
In multi-chip configuration, the Duty + 1 command must
be executed to both the master and slave sides.
(13)
n
-line Reverse Register Set
Selects the number of inverse lines for the LCD AC
controller. The value of n is set between 2 to 16 and is
stored in the n-line inversion register.
Do not use this command when using the votage follower
of the built-in power supply, the characteristics of the
built-in power supply cannot then be guaranteed to stay
within the specification.
(14)
n
-line Reverse Register Release
Cancels n-line inversion and restores the normal 2-frame
AC control. The contents of the n-line inversion register
are not changed.
Model D Duty
0 1/48 or 1/64
S1D15600 1 1/49 or 1/65
0 1/24 or 1/32
S1D15601 1 1/25 or 1/33
0 1/16
S1D15602 1 1/17
Model D Duty
0 1/48
S1D15600 1 1/64
0 1/24
S1D15601 1 1/32
0 1/16
S1D15602 1 1/16
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010100D
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101010101D
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0 1 0 0 0 1 1 A3 A2 A1 A0
Number of inverted
A3 A2 A1 A0 lines
0000 –
0001 2
0010 3
↓↓
1110 15
1111 16
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
01 000 100000
(15) Read Modify Write
Following this command, the column address is no
longer incremented automatically by a Read Display
Data command. The column address is still incremented
by the Write Display Data command. This mode is
cancelled by the End command. The column address is
then returned to its value prior to the Modify Read
command. This command makes it easy to manage the
duplication of data from a particular display area for
features such as cursor blinking.
Note that the Column Address Set command cannot be
used in modify-read mode.
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
01 011 100000
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–45
(16) End
Cancels the modify read mode. The column address
prior to the Modify Read command is restored.
(17) Reset
Resets the initial display line, column address, page
address, and n-line inversion registers to their initial
values. This command does not affect the display data in
RAM.
The reset command does not initialize the LCD power
supply. Only RES can be used to initialize the supplies.
(18) Output Status Register Set
Available only in the S1D15600 and S1D15601.
This command selects the role of the COM/SEG dual
pins and determines the LCD driver output status.
The COM output scanning direction can be selected by
setting A3 to HIGH or LOW. For details, refer to the
Output Status Circuit in each function description.
Figure 13. Command sequence for
cursor blinking
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
01011101110
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
01011100010
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0101100A3A2A1A0
A3: Selection of the COM output scanning direction
Page address set.
Column address set.
Read–modify–write cycle.
Dummy read.
Data read.
Data write.
Changes
finished?
END
Yes
No
Column
address N N+1 N+2 N+3 N+m N
Read–modify–write mode set End
Return
S1D15600/601/602 Series
7–46 EPSON Rev. 4.6
Number of
Output
A
2
A
1
A
0
COM/SEG Remarks
Status Output pins
Applies to the
0 0 0 Case 6 SEG 166 SED1560/61
0 0 1 Case 5 SEG 134, COM 32 Applies to the
0 1 0 Case 4 SEG 134, COM 32 SED1561
0 1 1 Case 3 SEG 134, COM 32
1 0 0 Case 2 SEG 102, COM 64 Applies to the
SED1560
1 0 1 Case 1 SEG 102, COM 64
1 1 0 Case 6 SEG 166 Applies to the
SED1560/61
1 1 1 Case 6 SEG 166
(19) LCD Power Supply ON/OFF
Turns the S1D1560*D**B* internal LCD power supply
ON or OFF. When the power supply is ON, the voltage
converter, the voltage regulator circuit and the voltage
followers are operating. For the converter to function,
the oscillator must also be operating.
Sequence in the Built-in Power supply
ON/OFF Status
To turn on built-in power supply, execute the above built-
in power supply ON sequence. To turn off internal power
supply execute the power save sequence as shown in the
following power supply OFF status. Accordingly, to turn
on built-in power supply again after turn it off (power
save), execute the “Power Save Clear Sequence” that
will be described afterwards.
*1: Regarding the S1D15602, it is not necessary to
execute a command to decide an output status.
*2: When the COMI pin is not used, it is not necessary
to enter the DUTY+1 and DUTY+1 Clear com-
mands.
*3: When the built-in power supply startup end com-
mand is not executed, current is consumed
stationarily.
Built-in power supply startup end command must
always be used in a pair with built-in power supply
ON command.
*4: The waiting time depends on the externally-in-
stalled capacitance C2 (refer to 7-37). After the
waiting time shown in Graph 1, the power supply
can be started surely.
Built-in power supply ON status
Reset by RES signal
*1 Output Status Select command A*(H)
*2 *DUTY+1 command AB(H)
Electronic Volume Control setup **(H)
Internal Power Supply ON command 25(H)
*4,5 (Waiting time)
*3 Power Supply Startup End command ED(H)
Built-in power supply OFF status
Display OFF command AE(H)
Output Status case 6 command CF(H)
*2 *DUTY+1 Clear command AA(H)
Display All ON command A5(H)
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0100010010D
Note
D = 0 Supply OFF
D = 1 Supply ON
When an external power supply is used with the
S1D15600D**B*, the internal supply must be OFF.
If the S1D15600D**B* is used in a multiple-chip
configu-ration, an external power supply that meets the
specifications of the LCD panel must be used. An
S1D15600 operating as a slave must have its internal
power supply turned OFF.
(20) Built-in Power Supply ON/OFF
This command turns on the built-in power supply.
The S1D15600 series has the built-in, low-power LCD
driving voltage generator circuit which can cut almost all
currents except those required for LCD display. This is
the primary advantage of the S1D15600 series product.
However, it has the LOW power and you need perform
the following power-on sequence when turning on the
built-in power supply:
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
01011101101
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–47
120
100
80
60
40
20
0 0.5 1.0
Capacitance C2
Graph 1 (µF)
Waiting
time
(ms)
V5 voltage conditions
1/9 bias V5 = –6.0 to –16.0 V
1/7 bias V5 = –5.0 to –12.0 V
1/5 bias V5 = –4.5 to –8.0 V
1/9 bias
1/7 bias
1/5 bias
*5: Within the waiting time in built-in power supply ON status, any command other than built-in power supply control
commands such as Power Save, and display ON/OFF command, display normal rotation/reverse command, display
all ON command, output status select command and DUTY+1 clear command can accept another command without
any problem. RAM read and write operations can be freely performed.
(21) Electronic Volume Control Register Set
Through these commands, the liquid crystal driving
voltage V5 being outputted from the voltage regulation
circuit of the built-in liquid crystal power supply, in order
to adjust the contrast of the liquid crystal display.
By setting data to the 4 bit register, one of the 16 voltage
status may be selected for the liquid crystal driving
voltage V5. External resistors are used for setting the
voltage regulation range of the V5. For details refer to the
paragraph of the voltage regulation circuit in the Clause
for the explanation of functions.
When not using the electronic volume control function,
set to (0, 0, 0, 0, 0).
(22) Power Save (Complex Command)
If the Display All Points ON command is specified in the
display OFF state, the system enters the power save
status, reducing the power consumption to approximate
the static power consumption value. The internal state in
the power save status is as follows:
(a) The oscillator and power supply circuits are stopped.
A4 A3 A2 A1 A0 | V5 |
0000
0 Small (as the absolute value)
:
:
11111
Large (as the absolute value)
(b) The LCD driver is stopped and segment and com-
mon driver outputs output the VDD level.
(c) An input of an external clock is inhibited and OSC2
enters the high-impedance state.
(d) The display data and operation mode before execu-
tion of the power save command are held.
(e) All LCD driver voltages are fixed to the VDD level.
The power save mode is cancelled by entering either the
Display ON command or the Display All Points OFF
command (display operation state). When external volt-
age driver resistors are used to supply the LCD driver
voltage level, the current through them must be cut off by
the power save signal.
If an external power supply is used, it must be turned OFF
using the power save signal in the same manner and
voltage levels must be fixed to the floating or VDD level.
Sequence in the Power Save Status
Power Save and Power Save Clear must be executed
according to the following sequence.
To give a liquid crystal driving voltage level by the
externally-installed resistance dividing circuit, the cur-
rent flowing in this resistance must be cut before or
concurrently with putting the S1D15600/601/602 series
into the power save status so that it may be fixed to the
floating or VDD level.
When using an external power supply, likewise, its
function must be stopped before or concurrently with
putting the S1D15600/601/602 series ino the power save
status so that it may be fixed to the floating or VDD level.
In a configurationinwhich an exclusive common driver
such as S1D16700 is combined with the S1D15600/601/
602 series, it is necessary to stop the external power
supply function after putting all the common output into
non-selection level.
E R/W
A0D7D6D5D4D3D2D1D0
RD WR
0 1 0 1 0 0 A4A3A2A1A0
S1D15600/601/602 Series
7–48 EPSON Rev. 4.6
Power save sequence
Display OFF command AE(H)
*3 Output Status case 6 command CF(H)
*2 *DUTY+1 Clear command AA(H)
*1 Display All ON command A5(H)
Power save clear sequence
Reset by RES signal
*3 Output Status Select command C*(H)
*2 *DUTY+1 command AB(H)
Internal Power Supply ON command 25(H)
*1 Display All ON Status OFF
*6 (Waiting time)
*5 Power Supply Startup End command ED(H)
*1: In the power save sequence, the power save status is
provided after the display all ON command. In the
power save clear sequence, the power save status is
cleared after the display all ON status OFF com-
mand.
*2 When the COMI pin is not used, it is not necessary to
eneter the DUTY+1 command and DUTY+1 clear
command.
*3 In the S1D15602, it is not necessary to execute a
command to decide an output status.
*4 The display ON command can be executed any-
where if it is later than the display all ON status OFF
command.
*5 When internal power supply startup end command is
not executed, current is consumed stationarily. In-
ternal power supply startup end command must
always be used in a pair with internal power supply
ON command.
*6 The waiting time depends on the Externally-installed
capacitance C2 (refer to 7-46). After the waiting
time shown in the above Graph 1, the power supply
can be started surely.
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–49
9. COMMAND DESCRIPTION – INSTRUCTION SETUP EXAMPLES
Instruction Setup Examples
Initial setup
Note: As power is turned on, this IC outputs non-LCD-drive potentials V2 – V3 from SEG terminal (generates output
for driving the LCD) and V 1 –V4 from COM terminal (also used for generating the LCD drive output). If charge
remains on the smoothing capacitor being inserted between the above LCD driving terminals, the display screen
can be blacked out momentarily. In order to avoid this trouble, it is recommended to employ the following
powering on procedure.
• When the built-in power is used immediately after the main power is turned on:
Turn on V
DD
and V
SS
power while maintaining
RES terminal at LOW.
Wait until the power supply is stabilized.
Turn on the initial setup mode (Default). *1
Initial setup is complete
Function select through the commands (user setup).
ADC select *2
Output state register set *3
Duty select *4
Duty + 1 *5
Electronic volume *6
n-line inversion register set *7
Function select through the command (user setup).
Built-in power supply ON *8
Waiting time *9
Function select through the command (user setup)
Powering on is complete *10
Cancel the reset mode (RES terminal = HIGH).
Operations ranging from powering on
through the power control set must be
completed within 5 ms.
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned.
Check them on the actual system.
Notes: *1: Refer to the “Reset Circuit” in the Function Description.
*2: Refer to the “ADC Select” in the Command Selection (8).
*3: Refer to the “Output State Register Set” in the Command Description (18).
*4: Refer to the “Duty Select” in the Command Description (11).
*5: Refer to the “Duty + 1” in the Command Description.
*6: Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in
the Command Description (21).
*7: Refer to the “n-line Inversion Register Set” in the Command Description (13).
*8: Refer to the “Built-in Power Supply ON/OFF” in the Command Description (21).
*9: Refer to the “Built-in Power Supply ON/OFF Sequence” in the Command Description.
*10:Refer to the “Built-in Power Supply ON Complete” in the Command Description (20).
S1D15600/601/602 Series
7–50 EPSON Rev. 4.6
• When the built-in power supply is not used immediately after the main power is turned on:
Turn V
DD
and V
SS
power on with RES terminal being set to LOW.
Wait until the power supply is stabilized.
Turn on the initial setup mode (Default) *1
Initial setup is complete
Function select through the commands (user setup)
ADC select *2
Output state register set *3
Duty select *4
Electronic volume *6
n-line inversion register set *7
Implement the power save sequence (multiple commands) *11
Implement the power save cancel sequence *12
Cancel the reset mode (RES terminal = HIGH) The power save mode
must be turned on within
5 ms from powering on.
* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. Check
them on the actual system.
Notes: *1: Refer to the “Reset Circuit” in the Function Description.
*2: Refer to the “ADC Select” in the Command Description (8).
*3: Refer to the “Output State Register Set” in the Command Description (18)
*4: Refer to the “Duty Select” in the Command Description (11).
*6: Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in
the Command Description (21).
*7: Refer to the “n-line Inversion Register Set” in the Command Description (13).
*8: Refer to the “Built-in Power Supply ON/OFF” in the Command Description (19).
*11,12: You can select either the sleep mode or standby mode for the power save mode. Refer to the “Power
Save (Multiple Commands)” in the Command Description (22).
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–51
• Data Display
Data display is complete
Initial setup is complete
Function select through the commands (user setup)
Display start line set *13
Page address set *14
Column address set *15
Function select through the command (user setup)
Display ON/OFF *17
Function select through the command (user setup)
Display data write *16
Notes: *13:Refer to the “Display Line Set” in the Command Description (2).
*14:Refer to the “Page Address Set” in the Command Description (3).
*15:Refer to the “Column Address Set” in the Command Description (4).
*16:Refer to the “Display Data Write” in the Command Description (6).
*17:Refer to the “Display ON/OFF” in the Command Description (1).
It is recommended to avoid the all-white-display of the display start data.
• Powering Off *18
Turn V
DD
and V
SS
power
Any state
Function select through the command (user setup)
Power save sequence *19
The time spent for the operations ranging from power
save through powering off (V
DD
– V
SS
= 2.4V) (
t
L
)
must be longer than the time required for V
5
to V
1
go
under the LCD panel threshold voltage (normally 1V).
*
t
H
is determined by time constant of the external
resisters Ra and Rb (for adjusting voltages V
5
to V
1
)
and the smoothing capacitor C2.
* It is recommended to cut
t
L
shorter by connecting a
resistor between V
DD
and V
5
.
Notes: *18:This IC functions as the logic circuit of the power supplies VDD – VSS, and used for controlling the
driver of LCD power supplies VDD – V5. Thus, if power supplies VDD – VSS are turned off while
voltage is still present on LCD power supplies VDD – V5, drivers (COM and SEG) may output
uncontrolled voltage. Therefore, you are required to observe the following powering off procedure:
Turn the built-in power supply off, then turn off the IC power supplies (VDD – VSS) only after making
sure that potential of V5 – V1 is below the LCD panel threshold voltage level. Refer to the “Supply
Circuit” in the Function Description.
*19:When the power save command is entered, you must not implement reset from RES terminal until VDD –
VSS power are turned off. Refer to the “Power Save” in the Command Description.
• Refresh
It is recommended that the operating modes and display contens be refreshed periodically,to prevent the effect of
unexpected noise. This sequence, however, must not be turned on as long as the initial setup, data display or powering
off sequence is taking place.
Refresh sequence
Refresh the DDRAM.
Set every command according to the state being selected
(including setup of the default state).
S1D15600/601/602 Series
7–52 EPSON Rev. 4.6
S1D1560*D**B*–S1D1560*D**B*
(when oscillator circuit is used)
S1D1560*D**B*–S1D1560*D**B* (External clock)
V
DD
V
SS
V
SS
V
DD
External clock
FR
SYNC
OSC1 OSC2 CLO DYOCL
S1D1560
*
D00
*
(Slave) M/S V
SS
FR
SYNC
OSC1 OSC2 CLO DYOCL
S1D1560
*
D
**
B
*
(Master)
M/S
V
SS
V
SS
V
SS
V
SS
Rf
FR
SYNC
OSC1 OSC2 CLO DYOCL
V
DD
S1D1560
*
D
**
B
*
(Master)
M/S FR
SYNC
OSC1 OSC2 CLO DYOCL
S1D1560
*
D
**
B
*
(Slave) M/S V
SS
Rf
V
DD
FR
SYNC
OSC1 OSC2 CLO DYOCL
S1D1560
*
D00
*
(Slave) M/S
FR
SYNC
OSC1 OSC2 CLO DYOCL
S1D1560
*
D00
*
(Master)
M/S
V
DD
Connection between LCD drivers
The LCD display area can be increased by using the
S1D15600/601/602 series in a multiple-chip configuration
or with the S1D15600/601/602 series special common
driver (S1D16300).
Application with external Driver
S1D1560*D**B*–S1D16300
S1D16300
DIO
FR
YSCL
Rf
FR
SYNC
OSC1 OSC2 CLO DYOCL
V
DD
S1D1560
*
D
**
B
*
(Master) M/S
V
SS
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–53
V
CC
A0
A0 to A15
VMA
D0 to D7
E
R/W
RES
GND
MPU Decoder
RESET
V
DD
A0
CS1
CS2
D0 to D7
E
R/W
RES V
SS
P/S
C86
S1D15600
V
CC
A0
A0 to A7
PORT1
PORT2
RES
GND
MPU Decoder
RESET
V
DD
A0
CS1
CS2
SI
SCL
RES V
SS
P/S
C86
S1D15600 V
DD
or
GND
Microprocessor Interface
The S1D15600/601/602 series interfaces to either 8080-
or 6800-series microprocessors. The number of
connections to the microprocessor can be minimized by
V
CC
A0
A1 to A7
IORQ
D0 to D7
RD
WR
RES
GND
MPU Decoder
RESET
V
DD
A0
CS1
CS2
D0 to D7
RD
WR
RES V
SS
P/S
C86
S1D15600
8080-series microprocessors
6800-series microprocessors
Serial interface
using a serial interface. When used in a multiple-chip
configuration, the S1D15600 is controlled by the chip
select signals from the microprocessor.
S1D15600/601/602 Series
7–54 EPSON Rev. 4.6
LCD Panel Interface Examples
Single-chip configurations
Multiple-chip configurations
Segments
Segments
65 x 102
S1D15600
(Master)
Case 1
Commons
S1D15601
(Master)
Case 4
33 x 134
Commons
Segments
S1D15602
17 x 150
Commons
SegmentsSegments
Segments
S1D15600
(Master)
Case 1
Commons
S1D15601
(Master)
Case 4
Commons
S1D15600
(Slave)
Case 6
65 x 268
33 x 300
S1D15601
(Slave)
Case 6
Segments
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–55
Special Common Driver Configurations
* If an external amp circuit is configured,
we recommend to use the S1F76600
and S1F76610.
Segments
S1D15600
(Master)
Case 6
65 x 166
S1D
16702 Commons
S1D15600/601/602 Series
7–56 EPSON Rev. 4.6
SED1560T TCP Pin Layout
This drawing is not for specifying the TCP outline shape.
O0
O165
COMI
V5
V4
V3
V2
V1
V
V
V5
V
CAP2–
CAP2+
CAP1–
CAP1+
V
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
V
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
V
V1
V2
V3
V4
V5
S1D15600
TOP
VIEW
DD
R
OUT
SS
SS
DD
S1D15600/601/602 Series
Rev. 4.6 EPSON 7–57
TCP DIMENSIONS (2 ways)
(Punching hole
for good product)
(Mold, marking area)
(Mold, marking area)
SR batten
PI batten
Output terminal pattern shape
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 111P (52.25mm)
• Solder resist positional tolerance: ±0.3
S1D15600/601/602 Series
7–58 EPSON Rev. 4.6
TCP DIMENSIONS (4 ways)
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 25µm
• Sn plating: 0.80±0.05µm
• Product pitch: 71P (33.25mm)
• Solder resist positional tolerance: ±0.3
Sealing plastic (epoxide plastic or equivalent)
HOKURIKU TORYO
Output terminal pattern shape
Resist
(PI coating)
(Mold, marking area)
(Mold, marking area)
