NVMFD5C650NL MOSFET - Power, Dual N-Channel 60 V, 4.2 mW, 111 A Features * * * * * * Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFD5C650NLWF - Wettable Flank Option for Enhanced Optical Inspection AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX 4.2 m @ 10 V 60 V Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RJC (Notes 1, 2, 3) TC = 25C Power Dissipation RJC (Notes 1, 2) Continuous Drain Current RJA (Notes 1, 2, 3) Steady State Dual N-Channel TC = 25C Pulsed Drain Current Value Unit VDSS 60 V VGS 20 V ID 111 A PD Steady State ID PD 1.8 502 A TJ, Tstg -55 to + 175 C IS 91 A Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, IL(pk) = 6 A) EAS 186 mJ Lead Temperature for Soldering Purposes (1/8 from case for 10 s) TL 260 C Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit C/W Junction-to-Case - Steady State RJC 1.37 Junction-to-Ambient - Steady State (Note 2) RJA 46.9 D1 D1 W 3.5 IDM Operating Junction and Storage Temperature MARKING DIAGRAM A 21 15 TA = 100C TA = 25C, tp = 10 s S2 S1 62 TA = 100C TA = 25C G2 G1 W 125 D2 D1 88 TC = 100C TA = 25C Power Dissipation RJA (Notes 1 & 2) Symbol TC = 100C 111 A 5.8 m @ 4.5 V MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter ID MAX 1 DFN8 5x6 (SO8FL) CASE 506BT A Y W ZZ S1 G1 S2 G2 XXXXXX AYWZZ D1 D1 D2 D2 D2 D2 = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface-mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. (c) Semiconductor Components Industries, LLC, 2015 July, 2019 - Rev. P3 1 Publication Order Number: NVMFD5C650NL/D NVMFD5C650NL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified) Parameter Symbol Test Condition Min Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 A 60 Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate-to-Source Leakage Current V 27.1 VGS = 0 V, VDS = 60 V mV/C TJ = 25 C 10 TJ = 125C 100 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 98 A 100 A nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain-to-Source On Resistance Forward Transconductance RDS(on) 1.2 2.2 -5.0 VGS = 10 V ID = 20 A 3.5 4.2 VGS = 4.5 V ID = 20 A 4.6 5.8 gFS VDS = 15 V, ID = 50 A V mV/C 120 m S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 2546 VGS = 0 V, f = 1 MHz, VDS = 25 V 1258 pF 17 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V; ID = 50 A 16 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 50 A 37 Threshold Gate Charge QG(TH) Gate-to-Source Charge QGS Gate-to-Drain Charge QGD Plateau Voltage VGP 3.3 td(ON) 13 4.3 VGS = 4.5 V, VDS = 48 V; ID = 50 A nC 8.3 3.1 V SWITCHING CHARACTERISTICS (Note 5) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 48 V, ID = 5 A, RG = 1.0 tf 24 ns 37 13 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 20 A TJ = 25C 0.9 TJ = 125C 0.8 tRR ta tb 1.2 V 44 VGS = 0 V, dIS/dt = 50 A/s, IS = 50 A QRR 22 ns 22 35 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 s, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFD5C650NL TYPICAL CHARACTERISTICS 140 10 to 4.5 V 3.6 V ID, DRAIN CURRENT (A) 120 3.4 V 100 80 3.2 V 60 3.0 V 40 2.8 V 0 0.5 1.0 2.0 1.5 60 40 TJ = 25C 2.5 0 1.0 0.5 2.0 1.5 TJ = -55C 2.5 3.0 3.5 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (m) VGS, GATE-TO-SOURCE VOLTAGE (V) ID = 20 A TJ = 25C 8 7 6 5 3 TJ = 125C VDS, DRAIN-TO-SOURCE VOLTAGE (V) 9 4 5 6 7 8 9 10 4.0 8 TJ = 25C 7 VGS = 4.5 V 6 5 VGS = 10 V 4 3 2 10 20 30 50 40 60 70 80 100 90 VGS, GATE-TO-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 2.0 1.8 80 0 100K TJ = 175C ID = 20 A VGS = 10 V TJ = 150C 10K IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (m) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) VGS = 2.6 V 10 4 100 20 20 0 VDS = 10 V 120 ID, DRAIN CURRENT (A) 140 1.6 1.4 1.2 1.0 TJ = 125C 1K TJ = 85C 100 TJ = 25C 10 0.8 0.6 -50 -25 0 25 50 75 100 125 150 1 175 5 15 25 35 45 55 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage www.onsemi.com 3 NVMFD5C650NL TYPICAL CHARACTERISTICS VGS, GATE-TO-SOURCE VOLTAGE (V) 10K C, CAPACITANCE (pF) Ciss 1K Coss 100 10 1 Crss TJ = 25C VGS = 0 V f = 1 MHz 0 10 20 30 40 60 50 10 9 8 7 6 5 Qgd Qgs 4 3 VDS = 48 V ID = 50 A TJ = 25C 2 1 0 0 5 10 15 20 25 30 35 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-to-Source vs. Total Charge 40 1K td(off) t, TIME (ns) 100 IS, SOURCE CURRENT (A) VGS = 0 V VGS = 4.5 V VDS = 48 V ID = 50 A tf tr td(on) 10 1 1 10 1 0.1 100 TJ = 125C 0.3 0.4 TJ = 25C 0.5 TJ = -55C 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 100 TJ(initial) = 25C 10 TC = 25C VGS 10 V Single Pulse 1 10 s RDS(on) Limit Thermal Limit Package Limit 0.1 1 IPEAK (A) 10 0.1 0.6 RG, GATE RESISTANCE () 1000 ID, DRAIN CURRENT (A) 10 10 TJ(initial) = 100C 1 0.5 ms 1 ms 10 ms 100 1000 0.1 0.00001 0.0001 0.001 0.01 VDS, DRAIN-TO-SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Drain Current vs. Time in Avalanche www.onsemi.com 4 NVMFD5C650NL TYPICAL CHARACTERISTICS 100 R(t) (C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% 0.1 0.01 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Response DEVICE ORDERING INFORMATION Marking Package Shipping NVMFD5C650NLT1G 5C650L DFN8 (Pb-Free) 1500 / Tape & Reel NVMFD5C650NLWFT1G 650LWF DFN8 (Pb-Free, Wettable Flanks) 1500 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL-Dual) CASE 506BT ISSUE E DATE 26 FEB 2013 1 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 0.20 C D A B D1 8 7 6 EE EE PIN ONE IDENTIFIER NOTE 7 1 2 2X 0.20 C 5 E1 E 4X c 3 GENERIC MARKING DIAGRAM* h A1 4 1 XXXXXX AYWZZ TOP VIEW 0.10 C DETAIL A A 0.10 C NOTE 4 C SIDE VIEW DETAIL A D2 D3 4X e 1 L K 4 DETAIL B 4X b1 N 4X G *This information is generic. Please refer to device data sheet for actual part marking. MILLIMETERS MAX MIN MAX --- 0.90 1.10 --- --- 0.05 0.33 0.42 0.51 0.33 0.42 0.51 0.20 --- 0.33 5.15 BSC 4.70 4.90 5.10 3.90 4.10 4.30 1.50 1.70 1.90 6.15 BSC 5.70 5.90 6.10 3.90 4.15 4.40 1.27 BSC 0.45 0.55 0.65 --- --- 12 _ 0.51 --- --- 0.56 --- --- 0.48 0.61 0.71 3.25 3.50 3.75 1.80 2.00 2.20 ALTERNATE CONSTRUCTION DETAIL B M XXXXXX= Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability SEATING PLANE NOTE 6 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N 8 5 8X SOLDERING FOOTPRINT* E2 4.56 0.75 b K1 BOTTOM VIEW 2X 0.10 C A B 0.05 C 2X 2.08 8X 0.56 NOTE 3 4.84 4X 1.40 2.30 6.59 3.70 0.70 4X 1.00 1.27 PITCH 5.55 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON50417E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. DFN8 5X6, 1.27P DUAL FLAG (SO8FL-DUAL) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 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