MC74HCT374ADWR2 - ON Semiconductor

May, 2011 − Rev. 11

1Publication Order Number:

MC74HCT374A/D

MC74HCT374A

Octal 3-State Noninverting

D Flip-Flop with

LSTTL-Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT374A may be used as a level converter for

interfacing TTL or NMOS outputs to High−Speed CMOS inputs.

The HCT374A is identical in pinout to the LS374.

Data meeting the setup and hold time is clocked to the outputs with

the rising edge of Clock. The Output Enable does not affect the state of

the flip−flops, but when Output Enable is high, the outputs are forced

to the high−impedance state. Thus, data may be stored even when the

outputs are not enabled.

The HCT374A is identical in function to the HCT574A, which has

the input pins on the opposite side of the package from the output pins.

This device is similar in function to the HCT534A, which has

inverting outputs.

Features

•Output Drive Capability: 15 LSTTL Loads

•TTL/NMOS−Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 mA

•In Compliance With the JEDEC Standard No. 7.0 A Requirements

•Chip Complexity: 276 FETs or 69 Equivalent Gates

•Improvements over HCT374

— Improved Propagation Delays

— 50% Lower Quiescent Power

— Improved Input Noise and Latchup Immunity

•These Devices are Pb−Free and are RoHS Compliant

http://onsemi.com

MARKING

DIAGRAMS

HCT

374A

ALYWG

G

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

20

1

HCT374A

AWLYYWWG

PDIP−20

N SUFFIX

CASE 738 1

20

1

20 MC74HCT374AN

AWLYYWWG

20

1

74HCT374A

AWLYYWWG

20

1

SOEIAJ−20

F SUFFIX

CASE 967

SOIC−20

DW SUFFIX

CASE 751D

TSSOP−20

DT SUFFIX

CASE 948E

1

20

1

20

1

20

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HCT374A

http://onsemi.com

2

LOGIC DIAGRAM

DATA

INPUTS

D0

11

CLOCK

D1

D2

D3

D4

D5

D6

D7 18

17

14

13

8

7

4

3

1

OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2

PIN 20 = VCC

PIN 10 = GND

NONINVERTING

OUTPUTS

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Output

Enable Clock D Q

LHH

LLL

L L,H, X No Change

HXXZ

X = don’t care

Z = high impedance

Q2

D1

D0

Q0

OUTPUT

ENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CLOCK

Q4

D4

D5

Q5

ÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*

ÎÎÎÎ

69

ÎÎÎ

ea.

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎÎ

1.5

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎÎ

5.0

ÎÎÎ

mW

ÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎÎ

.0075

ÎÎÎ

pJ

*Equivalent to a two−input NAND gate.

ORDERING INFORMATION

Device Package Shipping†

MC74HCT374ANG PDIP−20

(Pb−Free)

1440 Units / Box

MC74HCT374ADWG SOIC−20

(Pb−Free)

38 Units / Rail

MC74HCT374ADWR2G SOIC−20

(Pb−Free)

1000 Units / Reel

MC74HCT374ADTR2G TSSOP−20* 2500 Units / Reel

MC74HCT374AFELG SOEIAJ−20

(Pb−Free)

2000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HCT374A

http://onsemi.com

3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±35

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ÎÎÎÎÎ

260

ÎÎÎ

_C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

4.5

ÎÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

0

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time (Figure 1)

ÎÎÎ

0

ÎÎÎ

500

ÎÎÎ

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎ

– 55 to

25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎ

4.5

5.5

ÎÎÎÎ

2.0

ÎÎÎÎ

2.0

ÎÎÎÎ

2.0

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎ

4.5

5.5

ÎÎÎÎ

0.8

ÎÎÎÎ

0.8

ÎÎÎÎ

0.8

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

4.5

5.5

ÎÎÎÎ

4.4

5.4

ÎÎÎÎ

4.4

5.4

ÎÎÎÎ

4.4

5.4

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 6.0 mA

ÎÎÎ

4.5

ÎÎÎÎ

3.98

ÎÎÎÎ

3.84

ÎÎÎÎ

3.7

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

4.5

5.5

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 6.0 mA

ÎÎÎ

4.5

ÎÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.4

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎÎ

Maximum Three−State Leakage

Current

ÎÎÎÎÎÎÎÎÎ

Output in High−Impedance State

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

±0.5

ÎÎÎÎ

±5.0

ÎÎÎÎ

±10

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply Current

(per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎ

5.5

ÎÎÎÎ

4.0

ÎÎÎÎ

40

ÎÎÎÎ

160

ÎÎ

mA

ÎÎÎÎ

DICC

ÎÎÎÎÎÎÎÎÎÎ

Additional Quiescent Supply Current

ÎÎÎÎÎÎÎÎÎ

Vin = 2.4 V, Any One Input

Vin = VCC or GND, Other Inputs

lout = 0 mA

ÎÎÎ

5.5

ÎÎÎÎÎ

≥ −55_C

ÎÎÎÎÎÎ

25_C to 125_C

ÎÎ

mA

ÎÎÎÎÎ

2.9

ÎÎÎÎÎÎ

2.4

1. Total Supply Current = ICC + ΣDICC.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HCT374A

http://onsemi.com

4

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎÎÎÎ

30

ÎÎÎÎ

24

ÎÎÎÎÎ

20

ÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ÎÎÎÎÎ

31

ÎÎÎÎ

39

ÎÎÎÎÎ

47

ÎÎ

ns

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

ÎÎÎÎÎ

30

ÎÎÎÎ

38

ÎÎÎÎÎ

45

ÎÎ

ns

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

ÎÎÎÎÎ

30

ÎÎÎÎ

38

ÎÎÎÎÎ

45

ÎÎ

ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎÎÎÎ

12

ÎÎÎÎ

15

ÎÎÎÎÎ

18

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three−State Output Capacitance

(Output in High−Impedance State)

ÎÎÎÎÎ

15

ÎÎÎÎ

15

ÎÎÎÎÎ

15

ÎÎ

pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip−Flop)* 65 pF

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock

(Figure 3)

ÎÎÎÎÎ

12

ÎÎÎÎ

15

ÎÎÎÎÎ

18

ÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data

(Figure 3)

ÎÎÎÎÎ

5.0

ÎÎÎÎ

5.0

ÎÎÎÎÎ

5.0

ÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

(Figure 1)

ÎÎÎÎÎ

12

ÎÎÎÎ

15

ÎÎÎÎÎ

18

ÎÎ

ns

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎÎÎ

500

ÎÎÎÎ

500

ÎÎÎÎÎ

500

ÎÎ

ns

MC74HCT374A

http://onsemi.com

5

SWITCHING WAVEFORMS

Figure 1.

trtf

VCC

GND

tTHL

tTLH

90%

1.3 V

10%

2.7 V

1.3 V

0.3 V

CLOCK

tPLH tPHL

Q

tw

1/fmax

1.3 V

OUTPUT

ENABLE

Q

tPZL tPLZ

tPZH tPHZ

10%

90%

3 V

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

1.3 V

DATA

CLOCK

3 V

GND

VALID

th

tsu

1.3 V

Figure 2.

Figure 3.

Q

TEST CIRCUITS

Figure 4.

EXPANDED LOGIC DIAGRAM

C

D0 D1 D2 D3 D4 D5 D6 D7

347813141718

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

256912151619

DQ

CLOCK

OUTPUT

ENABLE

11

1

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH

1 kW

Figure 5.

C

DQ

C

DQ

C

DQ

C

DQ

C

DQ

C

DQ

C

DQ

MC74HCT374A

http://onsemi.com

6

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

CASE 738−03

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

M

L

J20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A25.66 27.171.010 1.070

B6.10 6.600.240 0.260

C3.81 4.570.150 0.180

D0.39 0.550.015 0.022

G2.54 BSC0.100 BSC

J0.21 0.380.008 0.015

K2.80 3.550.110 0.140

L7.62 BSC0.300 BSC

M0 15 0 15

N0.51 1.010.020 0.040

____

E

1.27 1.770.050 0.070

1

11

10

20

−A−

SEATING

PLANE

K

N

FG

D20 PL

−T−

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

eT

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

MC74HCT374A

http://onsemi.com

7

PACKAGE DIMENSIONS

TSSOP−20

DT SUFFIX

CASE 948E−02

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E 6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74HCT374A

http://onsemi.com

8

PACKAGE DIMENSIONS

SOEIAJ−20

F SUFFIX

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.81 --- 0.032

A1

HE

Q1

LE

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

HE

A1

LE

Q1

_

c

A

Z

D

E

20

110

11

b

M

0.13 (0.005)

e

0.10 (0.004)

VIEW P

DETAIL P

M

L

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC74HCT374A/D

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative