KM416C256D, KM416V256D CMOS DRAM
This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and
package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is
fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
¡Ü Part Identification
- KM416C256D/DL (5V, 512K Ref.)
- KM416V256D/DL (3.3V, 512K Ref.)
¡Ü Fast Page Mode operation
¡Ü 2 CAS Byte/Wrod Read/Write operation
¡Ü CAS-before-RAS refresh capability
¡Ü RAS-only and Hidden refresh capability
¡Ü Self-refresh capability (L-ver only)
¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
¡Ü Early Write or output enable controlled write
¡Ü JEDEC Standard pinout
¡Ü Available in 40-pin SOJ 400mil and44(40)-pin
TSOP(II) 400mil packages
¡Ü Triple +5V¡¾10% power supply(5V product)
¡Ü Triple +3.3V¡¾0.3V power supply(3.3V product)
Control
Clocks VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0
.
.
A8
Memory Array
262,144 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
¡Ü Refresh Cycles
Part
NO. VCC Refresh
cycle Refresh period
Normal L-ver
C256D 5V 512K 8ms 128ms
V256D 3.3V
¡Ü Performance Range:
Speed tRAC tCAC tRC tPC Remark
-5 50ns 15ns 90ns 35ns 5V only
-6 60ns 15ns 10ns 40ns 5V/3.3V
-7 70ns 20ns 130ns 45ns 5V/3.3V
¡Ü Active Power Dissipation
Speed 3.3V(512 Ref.) 5V(512 Ref.)
-5 -605
-6 325 495
-7 290 440
Unit : mW
Sense Amps & I/O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
KM416C256D, KM416V256D CMOS DRAM
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
N.C
A0
A1
A2
A3
VCC
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIN CONFIGURATION (Top Views)
¡Ü KM416C/V256DT
Pin Name Pin Function
A0 - A8 Address Inputs
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
WRead/Write Input
OE Data Output Enable
VCC Power(+5V)
Power(+3.3V)
N.C No Connection
¡Û
¡Û
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
N.C
A0
A1
A2
A3
VCC
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
¡Ü KM416C/V256DJ
¡Û
¡Û
(SOJ) (TSOP-II)
KM416C256D, KM416V256D CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex
tended peri-
ods may affect device reliability.
Parameter Symbol Rating Units
3.3V 5V
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 -55 to +150 ¡É
Power Dissipation PD1 1 W
Short Circuit Output Current IOS 50 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70¡É)
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
Parameter Symbol 3.3V 5V Units
Min Typ Max Min Typ Max
Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V
Ground VSS 0 0 0 0 0 0 V
Input High Voltage VIH 2.0 -VCC+0.3 2.4 -VCC+1.0 V
Input Low Voltage VIL -0.3 -0.8 -1.0 -0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Symbol Min Max Units
3.3V
Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.3V,
all other input pins not under test=0 Volt) II(L) -5 5uA
Output Leakage Current
(Data out is disabled, 0V¡ÂVOUT¡ÂVCC)IO(L) -5 5uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 -V
Output Low Voltage Level(IOL=2mA) VOL -0.4 V
5V
Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.5V,
all other input pins not under test=0 Volt) II(L) -5 5uA
Output Leakage Current
(Data out is disabled, 0V¡ÂVOUT¡ÂVCC)IO(L) -5 5uA
Output High Voltage Level(IOH=-5mA) VOH 2.4 -V
Output Low Voltage Level(IOL=4.2mA) VOL -0.4 V
*2
*1
*2
*1
KM416C256D, KM416V256D CMOS DRAM
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In
ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,
Din=Don't care, TRC=125us, TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
Symbol Power Speed Max Units
KM416V254D KM416C254D
ICC1 Don't care -5
-6
-7
-
90
80
110
90
80
mA
mA
mA
ICC2 Don't care Don't care 1 2 mA
ICC3 Don't care -5
-6
-7
-
90
80
110
90
80
mA
mA
mA
ICC4 Don't care -5
-6
-7
-
60
55
70
60
55
mA
mA
mA
ICC5 Normal
LDon't care 0.5
100 1
150 mA
uA
ICC6 Don't care -5
-6
-7
-
90
80
110
90
80
mA
mA
mA
ICC7 LDon't care 200 300 uA
ICCS LDon't care 100 200 uA
KM416C256D, KM416V256D CMOS DRAM
CAPACITANCE (TA=25¡É, VCC=5V or 3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A8] CIN1 -5pF
Input capacitance [RAS, UCAS, LCAS, W, OE]CIN2 -7pF
Output capacitance [DQ0 - DQ15] CDQ -7pF
Test condition (5V device) : VCC=5.0V¡¾10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter Symbol -5 -6 -7 Units Notes
Min Max Min Max Min Max
Random read or write cycle time tRC 90 110 130 ns
Read-modify-write cycle time tRWC 132 152 177 ns
Access time from RAS tRAC 50 60 70 ns 3,4,10
Access time from CAS tCAC 15 15 20 ns 3,4,5
Access time from column address tAA 25 30 35 ns 3,10
CAS to output in Low-Z tCLZ 0 0 0 ns 3
Output buffer turn-off delay tOFF 012 0 12 0 17 ns 6
Transition time (rise and fall) tT350 3 50 3 50 ns 2
RAS precharge time tRP 30 40 50 ns
RAS pulse width tRAS 50 10K 60 10K 70 10K ns
RAS hold time tRSH 15 15 20 ns
CAS hold time tCSH 50 60 70 ns
CAS pulse width tCAS 15 10K 15 10K 20 10K ns
RAS to CAS delay time tRCD 20 35 20 45 20 50 ns 4
RAS to column address delay time tRAD 15 25 15 30 15 35 ns 10
CAS to RAS precharge time tCRP 5 5 5 ns
Row address set-up time tASR 0 0 0 ns
Row address hold time tRAH 10 10 10 ns
Column address set-up time tASC 0 0 0 ns 12
Column address hold time tCAH 10 10 15 ns 12
Column address to RAS lead time tRAL 25 30 35 ns
Read command set-up time tRCS 0 0 0 ns
Read command hold time referenced to CAS tRCH 0 0 0 ns 8
Read command hold time referenced to RAS tRRH 0 0 0 ns 8
Write command set-up time tWCS 0 0 0 ns 7
Write command hold time tWCH 10 10 15 ns
Write command pulse width tWP 10 10 15 ns
Write command to RAS lead time tRWL 15 15 15 ns
Write command to CAS lead time tCWL 13 15 15 ns 15
AC CHARACTERISTICS (0¡É¡ÂTA¡Â70¡É, See note 1,2)
Test condition (3.3V device) : VCC=3.3V¡¾0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
*1
Note) *1 : 5V only
KM416C256D, KM416V256D CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter Symbol -5 -6 -7 Units Notes
Min Max Min Max Min Max
Data set-up time tDS 000ns 9,19
Data hold time tDH 10 10 15 ns 9,19
Refresh period (Normal) tREF 8 8 8 ms
Refresh period (L-ver) tREF 128 128 128 ms
CAS to W delay time tCWD 37 37 47 ns 7,14
RAS to W delay time tRWD 72 82 97 ns 7
Column address to W delay time tAWD 47 52 62 ns 7
CAS precharge to W delay time tCPWD 52 57 67 ns 7
CAS set-up time (CAS -before-RAS refresh) tCSR 10 10 10 ns 17
CAS hlod time (CAS -before-RAS refresh) tCHR 10 10 10 ns 18
RAS to CAS precharge time tRPC 555ns
CAS precharge time (CBR counter test cycle) tCPT 20 20 25 ns
Access time from CAS precharge tCPA 30 35 40 ns 3
Fast Page mode cycle time tPC 35 40 45 ns
Fast Page read-modify-write cycle time tPRWC 77 82 97 ns
CAS precharge time (Fast Page cycle) tCP 10 10 10 ns 13
RAS pulse width (Fast Page cycle) tRASP 50 100K 60 100K 70 100K ns
RAS hold time from CAS precharge tRHCP 30 35 40 ns
OE access time tOEA 15 15 20 ns
OE to data delay tOED 12 12 17 ns
Output buffer turn off delay time from OE tOEZ 0 12 0 12 0 17 ns 6
OE command hold time tOEH 15 15 20 ns
RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 11
RAS precharge time (C-B-R self refresh) tRPS 90 110 130 ns 11
CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 11
*1
Note) *1 : 5V only
KM416C256D, KM416V256D CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 50pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD¡ÃtRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS¡ÃtWCS(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWD¡ÃtCWD(min), tRWD¡ÃtRWD(min), tAWD¡ÃtAWD(min) and tCPWD¡ÃtCPWD(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in ealy write cycles and to the W FALLing edge in OE controlled
write cycle and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
KM416C/V256D/DL Truth Table
RAS LCAS UCAS WOE DQ0 - DQ7 DQ8-DQ15 STATE
HHHHH Hi-Z Hi-Z Standby
LHHHH Hi-Z Hi-Z Refresh
L L H H LDQ-OUT Hi-Z Byte Read
LHLHLHi-Z DQ-OUT Byte Read
LLLHLDQ-OUT DQ-OUT Word Read
L L HLHDQ-IN -Byte Write
LHL L H-DQ-IN Byte Write
LLLLHDQ-IN DQ-IN Word Write
LLLH H Hi-Z Hi-Z -
7.
6.
5.
10.
9.
8.
3.
2.
1.
4.
KM416C256D, KM416V256D CMOS DRAM
512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L-
version).
tASC, tCAH are referenced to the earlier CAS rising edge.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge.
tCSR is referenced to earlier CAS falling low before RAS transition low.
tCHR is referenced to the later CAS rising high after RAS transition low.
tCSR tCHR
RAS
LCAS
UCAS
tDS tDH
LCAS
DQ0 ~ DQ15 Din
20.
16.
15.
14.
11.
13.
12.
17.
tDS, tDH are specified for earlier CAS falling low.
UCAS
w