LG1600FXH1200 - Agere Systems, Inc.

Data Sheet

August 1999

LG1600FXH Clock and Data Regenerator

Figure 1. LG1600FXH Open View

Features

■Integrated clock recovery and data retiming

■Surface-mount package

■Single ECL supply

■Robust FPLL design

■Operation up to BER = 1e–3

■SONET/SDH compatible loss of signal alarm

■High effective Q allows long run lengths

■Jitter tolerance exceeding ITU-T/Bellcore

■Low clock jitter generation: typical <0.005 UI

■Standard and custom data rates

0.50 Gbits/s—5.5 Gbits/s

■Complementary 50 Ω I/Os

Applications

■SONET/SDH receiver terminals and regenerators

OC-12 through OC-96/STM-4 through STM-32

■SONET/SDH test equipment

■Pro prietary bit rate systems

■Digital video transmission

■Clock doublers and quadruplers

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

2Lucent Technologies Inc.

Functional Description

The LG1600FXH Clock and Data Regenerator (CDR)

is a compact, single device solution to clock recovery

and data retiming in high-speed communication sys-

tems such as fiber-opti c data links and long-span fiber-

optic regenerators and terminals. Using frequency and

phase-lock loop (FPLL) techniques, the device regen-

erates clean clock and error-free data signals from a

nonreturn-to-zero (NRZ) data input, corrupted by jitter

and intersymbol interference. The LG1600FXH

exceeds ITU-T/Bellcore jitter tolerance requirements

for SONET/SDH systems.

The device houses two integrated circuits on an alu-

mina substrate inside a hermetically sealed 3 cm ×

3cm (1.2in. × 1.2 in.) surf ace-mount package: a GaAs

IC that contains the high-speed part of an FPLL as well

as a highly sensitive decision circuit; and a silicon bipo-

lar IC that contains a loop filter, acquisition, and signal

detect circuitry.

The two ac-coupled complementary data inputs can be

driven differentially as well as single ended. A dc feed-

back voltage V–FB maintains a data input threshold

V–TH (decision level) that is optimum for a wide range

of 50% duty cycle input levels (connect to V–TH). If

needed, the user can supply an external threshold to

compensate for different mark densities or distorted

input signals (see Figure 10).

Regenerated clock and data are a v ailable from comple-

mentary outputs that can either be ac coupled, to pro-

vide 50 Ω output match, or dc coupled with 50 Ω to

ground at the receiving end.

The second-order PLL filter bandwidth is set by the

user with an external resistor between pin 11 and

ground (required). An internal capacitor provides suffi-

cient PLL damping for most applications. In critical

applications, PLL damping can be increased using an

external capacitor between pins 9 and 11.

The device is powered by a single –5.2 V ECL compat-

ible supply and typically consumes 1.5 W.

The LG1600FXH comes in standard bit rates, but can

be factory tuned for any rate between 500 Mbits/s and

5500 Mbits/s.

A test fixture (TF1004A) with SMA connectors is avail-

able to allow quick e valuation of the LG1600FXH.

Theory of Operation

A digital regenerator has the task of retransmitting a bit

stream that is received from a remote source with the

same fidelity at which it was originally transmitted.

Two basic properties of the digital signal need to be

restored: the timing of the transitions between the bits

and the value of each bit.

12-3225(F)r.6

Figure 2. LG1600FXH Block Diagram

VCO

V + CLKO

V – CLKO

FREQ. & 90°

LOOP CONTROL &

1197

VREF CEXT REXT LOS

V–TH

V–FB

V–IN

V+IN

V+FB

0.047 µF

1 kΩ50 Ω

25 kΩ

50 Ω

25 kΩ

1 kΩ

43 38

V + OUT V – OUT VSS

0.047 µF

SIGNAL DETECT

PHASE

DETECT.

0°

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

3Lucent Technologies Inc.

Theory of Operation (continued)

Consequently, the timing inf ormation that is present in

the data needs to be extracted and a decision as to the

v alue of each bit must be made. Both timing instant and

decision le vels are critical, since the economics of data

transmission dictate the largest distance possible

between transmitter and receiver. A practically closed

data ey e can therefore be expected at the output of the

receiver, allowing only a small decision window.

An added complication in nonreturn-to-zero (NRZ) sys-

tems is the absence of clock component in the data

signal itself. Practical clock recovery circuits have used

a combination of nonlinear processing to extract a

spectral component at the clock frequency and narrow-

band filtering using a SAW filter or dielectric resonator.

The relative bandwidth of such a filter must be on the

order of a few tenths of a percent to minimize the data

pattern dependence of the resulting clock. Temperature

behavior of the passband characteristics, such as

group delay, m ust be tightly matched to that of the data

path. These extreme requirements make such a dis-

crete design very difficult to manufacture at Gbits/s

data rates.

The LG1600FXH cl ock and data regenerato r relies on

phase-lock loop techniques, rather than passive filter-

ing. The filter properties of a PLL are determined at low

frequencies where parasitic elements play only a minor

roll and stability is easily maintained. Furthermore, the

reference frequency is determined by the data rate

itself, rather than by the physical properties of a band-

pass filter.

Although PLLs can eliminate some of the shortcomings

of passive bandpass filters used in clock recovery cir-

cuits, care was taken in the design of the LG1600FXH

to preserve desired properties such as linearity of the

jitter characteristics. A linear jitter transfer mak es it a lot

easier for the system designer to predict the overall

performance of a link.

As a result, the architecture chosen for the device is not

basically different from the conventional clock recovery

circuit. A transition detector extracts a pulse train from

the incoming data sign al which is used as a reference

signal for a PLL. The transition pulse train can be seen

as a clock signal that is modulated with the instanta-

neous transition density of the data signal. The PLL

locks onto the frequency and phase of this pulse train

and freewheels during times when transitions are

absent. The LG1600FXH features dual phase detec-

tors; one driven by an in-phase clock which is also driv-

ing the decision circuit flip-flop, the other is driven by a

quadrature clock. The phase detectors produce a zero

output when their respective clocks are centered with

respect to the transition pulses.

12-3226(F)r.3

Figure 3. Frequency and Phase Detector

For a transition pulse of half the width of the bit period,

the timing diagram of Figure 4 shows how the in-phase

clock ends up in the center of the data eye when the

quadrature-phase detector output is forced to zero by

the loop. The (patented) transition detector is com-

prised of an (active) circulator, a shorted stub, and an

exclusive-OR gate. The circulator/stub combination

produces a delayed version of the data. A transition at

the input of the circuit results in an output pulse from

the exclusive-OR gate whose width equals the return

delay of the stub. The stub is tuned for a given bit rate

and can be adjusted so that the in-phase clock is

exactly centered in the error-free phase range of the

retiming flip-flop.

12-3227(F)r.2

Figure 4. Timing Diagram

PDQ

PDI

LOGIC

TO FLIP-FLOP

FROM

VCO

90°

0°

TRANSITION

PULSE

DATA

CIRCULATOR

DELAYED

DATA

STUB

FPD OUT

TRANSITION

DELAYED

DATA

1/2 T

1/4 T

DATA

PULSE

CLOCK

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

4Lucent Technologies Inc.

Theory of Operation (continued)

12-3228(F)r.4

Figure 5. Frequency and Phase Detector

Characteristics

The frequency detector is not a separate function but

an integral part of the phase-lock loop . Any transition

between frequency and phase acquisition is completely

avoided. Figure 5 shows the output characteristics of

the FPD, which is essentially an e xtended range phase

detector. The two quadrature clock phases are used to

produce hysteresis, which e xtends the phase detector

range to ±270°. The extended range gives the phase

detector a static frequency sensitivity as demonstrated

in Figure 6. F or clock frequencies lower than the bit rate

(the phase is increasing), the top trajectory of the dia-

gram in Figure 6 is followed. When the VCO frequency

exceeds the bit rate, the lower trajectory applies. Since

the linear part of the phase detector produces a net-

zero output, in the first instance, positive pulses are f ed

into the loop filter increasing the VCO frequency, while

in the latter case, the FPD produces negative pulses.

The wide, 540° range of the phase detector is also

responsible for the high jitter tolerance of the

LG1600FXH and an associated immunity to cycle slip

under high jitter conditions. The clock can be momen-

tarily misaligned as much as 270° but still return to its

original position. This property is extremely important

in synchronous systems, since a cycle slip would cause

misalignment of the demultiplexer following the circuit

resulting in a loss of frame condition. The LG1600FXH

can handle bit error rates up to 1e–3 as a result of low-

frequenc y ji tter.

12-3229(F)r.4

Figure 6. Frequency Detector Operation

PLL Dimens ioning

The LG1600FXH CDR employs a heavily damped

second order phase-lock loop. A linear model of this

PLL is depicted in Figure 7. The conventional second-

order equation describing the jitter transfer of the PLL

is shown below:

where ϕi and ϕo denote the input and output phase,

respectively, ς is the PLL damping ratio and ωn is the

natural frequency. For most clock recov ery applications

a very high damping is required, that renders the PLL

essentially as a first-order system with a slight peaking

that is generally undesirable. The second-order equa-

tion above does not provide much insight into the peak-

ing and bandwidth parameters.

12-3230(F)r.5

Figure 7. Phase-Lock Loop Linear Model

–360

–180

180

360

FPD OUT

PHASE

FPD

OUT

FPD

OUT

TIME

A. < f

B. > f

() ϕo

ϕi

------s

() 2ςωnsωn

s22ςωnsωn

------------------------------------------

ϕiϕo

VCO

PHAS E DETECTOR

SUM OF INTERNAL

AND EXTERNAL

LOOP FILTER

CAPACITANCE

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

5Lucent Technologies Inc.

Theory of Operation (continued)

A more useful expression of the PLL characteristics is

the following*:

The jitter transfer is now directly expressed in the phys-

ical loop gain pole product, ωb, and the loop filter time

constant, τ. Damping ratio , ς, and natural frequency, ωn

simply relate to these two parameters as follows:

and

* Wolaver, D.H.,

Phase-Locked Loop Circuit Design

, Prentice Hall,

1991.

() ωb11

sτ

-----





sωb11

sτ

-----





--------------------------------------

ςω

bτ

0.5

ωnωnτ⁄

For moderate damping ς > 2.5 (ωbτ < 0.1), the –3 dB

bandwidth of the PLL can be approximated by the loop

gain pole product:

JBW ≈ ωb = KdRxKo

while the jitter peaking can be expressed in terms of

the product of PLL bandwidth and loop filter time con-

stant:

As the last two expressions make clear, the PLL band-

width is controlled by the value of the external resistor

(see Figure 8), while the peaking depends both on the

resistor value (quadratically) and total loop filter capac-

itance.

()

max 11

ωbτ

---------

+≈11

2CKdKo

--------------------------

12-3231(F)r.4—12-3232(F)r.4

Figure 8. Jitter Bandwidth vs. External Resistor Value

0 50 100 200 250

0.0

0.2

0.6

0.8

1.0

1.2

Rx (

Ω

)

0.4

150

A. LG1600FXH0622 (Cx = 0.15

(MHz)

0 50 100 200 250

0.0

0.6

1.8

2.4

3.0

3.6

Rx (

Ω

)

1.2

150

B. LG1600FXH2488 (Cx = 0)

JBW (MHz)

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

6Lucent Technologies Inc.

Pin Information

The pinout for the LG1600FXH is shown in Figure 9.

12-3233(F)r.1

Figure 9. Pin Diagram

DNC

VREF

CEXT

REXT

LOS

DNC

GND

18 26 31 34

V–CLKO

V+CLKO

NIC

GND

V–TH

V–FB

V+OUT

V–OUT

VSS

GND

68 65

NIC

V+FB

V+IN

V–IN

GND

60 55 52

19 20 21 22 23 24 25 27 28 29 30 32 33

53545657585967 66 64 63 62 61

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

7Lucent Technologies Inc.

Pin Information (continued)

The pin descriptions for the LG1600FXH are given in Tab le 1.

Table 1. Pin Descriptions

Pin Symbol Name/Description

1, 4, 17 DNC Do Not Connect. Internal test point or reserved for future use.

REF Reference Voltage. Nominally –3.2 V. Can be used to bias LG1605DXB

(see data sheet ). Load ≥10 kΩ.

EXT Terminal for optional external capacitor to increase PLL damping (normally

not connected).

11 REXT Terminal for external resistor to set PLL bandwidth (Required).

14 LOS Loss of Signal Indicator. Provides approximately 1 mA sink current with

data signal present, can interface to CMOS, TTL when connected to logic

VDD through a 10 kΩ resistor. Normally grounded when not used.

26 V–CLKO Recovered Clock Out. ac couple or terminate into 50 Ω to GND.

31 V+CLKO Recovered Clock Out. ac couple or terminate into 50 Ω to GND.

35 VSS Supply Voltage. –5.2 Vdc nominal.

Warning: Connecting a positive voltage to this pin will permanently

damage the device.

38 V–OUT Regenerated Data Out. ac couple or terminate into 50 Ω to GND.

43 V+OUT Regenerated Data Out. ac couple or terminate into 50 Ω to GND.

48 V–FB dc Feedback Voltage. Connect to V–TH.

51 V–TH Input Threshold Voltage. Connect to V–FB.

55 V–IN Negative Data Input. Internally ac coupled.

60 V+IN Positive Data Input. Internally ac coupled.

65 V+FB dc Feedback Voltage. Internally connected; not normally used.

18, 68 NIC No Internal Connection. May be grounded.

2, 3, 5, 6,

8, 10, 12,

13, 15 , 16,

19, 20 , 21,

22, 23 , 24,

25, 27 , 28,

29, 30 , 32,

33, 34 , 36,

37, 39 , 40,

41, 42 , 44,

45, 46 , 47,

49, 50 , 52,

53, 54 , 56,

57, 58 , 59,

61, 62 , 63,

64, 66, 67

GND Ground. Connect to top ground plane of coplanar/microstrip circuit board.

Body GND Ground. Does not need to be connected. GND pins provide all necessary

ground connections.

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

8Lucent Technologies Inc.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These

are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in

excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for

extended periods can adversely affect device reliability.

Table 2. Absolute Maximum Ratings

Recommended Operating Conditions

Table 3. Recommended Operating Conditions

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-

sure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group

employs a human-body model (HBM) for ESD-susceptibility testing and protection design evaluation. The HBM

(resistance = 1500 Ω, capacitance = 100 pF) is used. The HBM ESD threshold presented in Table 4 was obtained

by using these circuit parameters.

Table 4. ESD Threshold

Mounting and Connections

Certain precautions must be taken when using solder. For installation using a constant temperature solder, temper-

atures of under 300 °C may be employed for periods of time up to 5 seconds, maximum. For installation with a sol-

dering iron (battery operated or nonswitching only), the soldering tip temperature should not be greater than

300 °C and the soldering time for each lead must not exceed 5 seconds.

Parameter Min Max Unit

Supply Voltage Range (VSS)–70.5V

Loss of Signal Bias Voltage (VDD)—7V

Power Dissipation — 2 W

Voltage (all pins) VSS 0.5 V

Transient Voltage to ac Couple Pins (V±IN, REXT)—±3V

Storage Temperature Range –40 125 °C

Operating Temperature Range –40 100 °C

Parameter Symbol Min Max Unit

Case Temperature tCASE 070°C

Power Supply VSS –4.7 –5.7 V

HBM ESD Threshold

Device Voltage

LG1600FXH ≥200 V

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

9Lucent Technologies Inc.

Electrical Characteristics

tCASE = 0 °C to 70 °C, VSS = –4.7 V to –5.7 V, VDD = 5 V, bit rate = fB Gbits/s ±0.05% NRZ and data pattern =

223 – 1 PRBS, 200 mV ≤ V±IN ≤ 800 mV, BER < 1e–9, unless otherwise indicated.

Note: Minimum and maximum v alues are testing requirements. Typical values are characteristics of the de vice and

are the result of engineering e v aluations. Typical values are f or inf ormation purposes only and are not part of

the testing requirements.

Parameter Symbol Conditions Min Typ Max Unit

Data Input Voltage V–IN Single ended on either input 200 — 800 mVp-p

Data Input Voltage V+IN – V–IN Differential 200 — 1600 mVp-p

Data Output Voltage V±OUT ac coupled 625 750 900 mVp-p

Data Output Voltage V±OUT dc coupled 650 800 900 mVp-p

Clock Output Voltage V±CLKO dc coupled 650 750 900 mVp-p

Clock Output Voltage V±CLKO ac coupled; fB ≤ 3 Gbits/s 625 750 900 mVp-p

Clock Output Voltage V±CLKO ac coupled; fB > 3 Gbits/s 500 600 900 mVp-p

Output Pulse Width Rela-

tive to Bit Period T = 1/fBPW% tCASE = 40 °C 90 100 110 %

Clock Output Duty Cycle DCCLKO tCASE = 40 °C 40 — 60 %

Clock/Data Output Transi-

tion Time tr, tf20% to 80% — 80 100 ps

Maximum Bit Error Rate BERMAX Jitter modulation @ fB × 40 kHz,

tCASE = 40 °C 1e–3 ———

LOS Output Voltage, Low VLOSL RL = 10 kΩ–1 –0.8 0.5 V

LOS Output Voltage, High VLOSH RL = 10 kΩ, V–IN = 0 V VDD –

0.5 VDD VDD V

Loss of Signal Delay τLOS Measured from last data transi-

tion, tCASE = 40 °C 10 30 100 µs

Jitter Generation JGEN ——0.0050.01UI

Jitter Transfer Bandwidth JBW User adjustable with RX as sug-

gested by Figure 8, tCASE = 25 °C —f

B—MHz

Output Ref erence Voltage VREF Load to ground ≥ 20 kΩ–3.4 –3.15 –2.9 V

Jitter Tolerance JTOL fmod ≤ fB x 40 kHz, tCASE = 40 °C

fB x 40 kHz ≤ fmod ≤ fB × 400 kHz,

tCASE = 40 °C

fmod ≥ fB × 400 kHz,

tCASE = 40 °C

1.5

0.6 fB/

fmod

0.15

2 fB/fmod

0.5

—

Acquisition/Recovery

Time τACQ Measured from first data

transition*, tCASE = 40 °C

* P arameter guaranteed by design or characterization and not production tested.

— 600 800 µs

Supply Current ISS –5.7 V ≤ VSS ≤ –4.7 V — 290 320 mA

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

10 Lucent Technologies Inc.

Test Circuit

12-3234(F)r.6

Notes:

Resistor RX determines the PLL bandwidth and is required for normal operation. The LG1600FXH differs in this respect from the LG1600AXD

CDR, which has an internal resistor that sets a minimum bandwidth. The recommended v alue is 140 Ω for optimal jitter transfer performance.

Capacitor CX is optional and can be used to increase the damping of the PLL in critical applications.

The outputs may be either ac coupled, as indicated, or dc terminated into 50 Ω. In the first case, good output return loss can be obtained. The

latter configuration provides a 0 mV to –800 mV output swing for easy interface to dc-coupled circuits.

Figure 10. LG1600FXH Typical Test Circuit

500 k

Ω

VCO

CLKO

–

CLKO

FREQ. &

PHASE

DETECT.

0°

90°

LOOP CONTROL &

SIGNAL DETECT

11 1497

REF

EXT

LOS

–TH

51 V

–FB

–IN

+IN

+FB

0.047

1 k

Ω

25 k

Ω

25 k

Ω

1 k

Ω

43 38

+OUT

–OUT

0.047

Ω

DATA

GENERATOR

OPTIONAL

THRESHOLD

CONTROL

ALTERNATIVE

Ω

OPTIONAL

> 0.1

F/f

5.2 V

OPTIONAL

> 100 pF/f

Ω

OPTIONAL

(SEE TEXT)

= 140

Ω

REQUIRED

0.047

10 k

Ω

5 V

LOS

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

11Lucent Technologies Inc.

Typical Performance Characteristics

Figure 11. LG1600FXH Ty pical Eye Patterns

LG1600FXH0553

LG1600FXH2488

LG1600FXH4977

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

12 Lucent Technologies Inc.

Typical Performance Characteristics (continued)

12-3235(F)r.2

Figure 12. Data Clock Output Timing Diagram

0 500 1500 2000

–100

100

200

300

500

BIT PERIOD ( p s)

1000

400

OUTPUT TIMING (ps)

OUTPUT TIMING

y = 1/4x – 65

V±OUT

V+CLKO

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

13Lucent Technologies Inc.

Typical Performance Characteristics (continued)

12-3236(F)r.3

Figure 13. Error Recovery Timing Diagram

0 200 400 800

100

300

400

500

700

INPUT BLANKING (µs)

200

600

RECOVERY TIME (µs)

BLANKING

INPUT

OUTPUT

ERROR

ERROR RECOVERY

1000

PULSE

DATA

SIGNAL

TIME

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

14 Lucent Technologies Inc.

Typical Performance Characteristics (continued)

12-3237(F)r.4

Figure 14. Error Recovery Test Circuit

ERROR DETECTOR

TRIG

OUT

PULSE

GENERATOR

CH3 CH2 CH1

OSCILLOSCOPE

CLK

DATA

CLK

BLNK

PATTERN

GENERATOR DATA

IN DATA

OUT

CLK OUT

CH1

CH2

CH3

DIGITIZING

OSCILLOSCOPE

MIXER

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

15Lucent Technologies Inc.

Outline Diagram

68-Pin Surface-Mou nt Package

Dimensions are in inches.

12-3350(F).ar.1

0.015 TYP

0.050 TYP

1.370 ± 0.10

0.010

DETAIL A

0.158

0.010

–0.002

0.030

0—5

R0.020

DETAIL A

+0.005

18 34

5268

1.180

0.590

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

16 Lucent Technologies Inc.

Ordering Information

Device Code Package Temperature Comcode

LG1600FXHXXXX Surface-Mount Package 0 °C to 70 °C 107236143

LG1600FXH0500 Surface-Mount Package 0 °C to 70 °C 107914038

LG1600FXH0553 Surface-Mount Package 0 °C to 70 °C 107236101

LG1600FXH0622 Surface-Mount Package 0 °C to 70 °C 107339244

LG1600FXH1200 Surface-Mount Package 0 °C to 70 °C 107841447

LG1600FXH1244 Surface-Mount Package 0 °C to 70 °C 107386179

LG1600FXH1298 Surface-Mount Package 0 °C to 70 °C 107236127

LG1600FXH1555 Surface-Mount Package 0 °C to 70 °C 107914046

LG1600FXH2380 Surface-Mount Package 0 °C to 70 °C 107236135

LG1600FXH2433 Surface-Mount Package 0 °C to 70 °C 107645939

LG1600FXH2488 Surface-Mount Package 0 °C to 70 °C 107081879

LG1600FXH2666 Surface-Mount Package 0 °C to 70 °C 107386187

LG1600FXH2949 Surface-Mount Package 0 °C to 70 °C 107385650

LG1600FXH3111 Surface-Mount Package 0 °C to 70 °C 107394132

LG1600FXH3840 Surface-Mount Package 0 °C to 70 °C 107840423

LG1600FXH4977 Surface-Mount Package 0 °C to 70 °C 107081887

LG1600FXH5332 Surface-Mount Package 0 °C to 70 °C 107081895

TF1004A Test Fixture — 106497621

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

17Lucent Technologies Inc.

Appendix

The test fixture mentioned in the data sheet is sold separately and is described in detail below.

5-7831(F)

Figure 15. TF1004A Test Fixture

TF1004A Test Fixture Featu res

■SMA co nnectors

■Easy package placement

■Good RF performance

Test Fixture Functional Descrip tion

The TF1004A test fixture is used to characterize 68-pin surf ace-mount packages f or high-speed fiber-optic commu-

nications. The fixture consists of a metallized substrate (PTFE filled material) fastened to a brass base with RF

connectors and mounting hardware for the package. The package leads make contact to the circuit traces on the

fixture through use of a pressure ring and four finger nuts.

The TF1004A is preassembled and fully tested prior to shipment.

Before Use of Test Fixture

■Due to possible stress during shipment, SMA connectors may be misaligned.

■Check each SMA for continuity.

■If necessary, realign and retighten with a 5/64 in. hex key wrench.

Data Sheet

LG1600FXH Clock and Data Regenerator August 1999

18 Lucent Technologies Inc.

Appendix (continued)

Instructions for Use of Test Fixture

A pair of flat-tip tweezers can be used to insert or remov e a package from the test fixture. Alwa ys wear a grounding

strap to prevent ESD.

1. To insert a package, remove the four finger nuts and gently lift the pressure ring off of the test fixture.

2. Place the pressure ring, cavity side up, on a flat ESD safe surface.

3. Connect the metal tube to any general-purpose vacuum source with flexible tubing. The vacuum source should

be off.

4. Place the package, lid down, on a flat ESD safe surface. Locate pin 1 on the package.

5. Insert the package into the pressure ring (lid down) with pin 1 located next to the orientation mark and turn on

the vacuum. The vacuum will retain the package in the pressure ring during the following steps.

6. Align the vertically conductive material on the circuit board.

7. Place the pressure ring down over the alignment pins and gently tighten the finger nuts.

8. Remove vacuum, if desired. The vacuum source tubing can be removed for convenience.

5-7832(F)r.1

Figure 16. TF1004A Connector Assignment

V+CLK

V–CLK

NIC

DNC

LOS

V–FB V+OUT V–OUT VSS

V–TH

DNC

V–IN

V+IN

V+FB

(48) (43) (38) (35)

(51)

(55)

(60)

(1)

(4)

(7) (11)(9)

(14)

(17)

(18)

(26)

(31)

VREF CEXT REXT

(65)

PIN #1

NIC = NO INTERNAL CONNECTION

DNC = DO NOT CONNECT

(##) = PACKAGE PIN NUMBER

Data Sheet

August 1999 LG1600FXH Clock and Data Regenerator

19Lucent Technologies Inc.

Notes

LG1600FXH Clock and Data Regenerator Preliminary Data Sheet

Interactive Terminal Transmission Convergence August 1999

For additional information, contact your Microelectronics Group Account Manager or the following:

INTERNET: http://www.lucent.com/micro

E-MAIL: docmaster@micro.lucent.com

N. AMERICA: Microelectronics Gro up, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-1 5P-BA, Allentown, PA 1 81 03

1-800-372-2447, FAX 610-712-4106 ( In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Microelectronics Group, Lucent Technologie s Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHIN A: Micr o electronics G r ou p, Lucent Technolo gi es ( C hina) C o., Ltd., A - F 2, 23/F, Zao Fong Uni ver s e B uildin g, 1800 Zhon g S han Xi Ro ad , S hanghai

200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652

JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Technical Inquiries: GERMANY:

(49) 89 95086 0

(Munich), UNITED KINGDOM:

(44) 1344 865 900

(Ascot),

FRANCE:

(33) 1 40 83 68 00

(Paris ), SWED EN:

(46) 8 594 607 00

(Stockholm), FINLAND:

(358) 9 4354 2800

(Helsinki),

ITALY:

(39) 02 6608131

(Milan ), SPAIN:

(34) 1 807 1441

(Madrid)

Lucent Technologies Inc. reser ves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

Printed in U.S.A.

August 1999

DS99-186HSPL (Replaces DS96-237FCE)