| FAIRCHILD sapeospaapeysnnpaenranesetenssasvepsesanened SEMICONDUCTOR CD4016BC Quad Bilateral Switch General Description The CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. Itis pin-for-pin compatible with CD4066BC. Features lf Wide supply voltage range: 3V to 15V Mf Wide range of digital and analog switching: +7.5 Vpeax Bf ON resistance for 15V operation: 400Q. (typ.) Mf Matched ON resistance over 15V signal input: ARon = 102 (typ.) Bi High degree of linearity: 0.4% distortion (typ.) @ fig =1 KHZ, Vig=5 Vop, Vpp-Vss = 10V, R, = 10 kQ @ Extremely low OFF switch leakage: 0.1 nA (typ.) @ Vpp Vsg = 10V Ta = 25C November 1983 Revised January 1999 @ Extremely high control input impedance: 10'20, (typ.) lf Low crosstalk between switches: 50 cB (typ.) @ fig = 0.9 MHz, RL=1 kQ li Frequency response, switch ON: 40 MHz (typ.) Applications + Analog signal switching/multiplexing Signal gating Squelch control Chopper Modulator/Demodulator Commutating switch + Digital signal switching/multiplexing * CMOS logic implementation + Analog-to-digital/digital-to-analog conversion * Digital control of frequency, impedance, phase, and ana- log-signal gain Ordering Code: Order Number | Package Number Package Description CD4016BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow CD4016BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the letter suffix X to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC 1 in/out 4 [ swa | vo 2 1 OUT/IN 3 CONTROLA 3 12 OUT/IN Eq P CONTROL D 4 11 IN/OUT rm IN/OUT 5 CONTROL B [swe | O UTIN 6 CONTROL C 3 OUT/IN 7 8 Vss IN/OUT Schematic Diagram CONTROL ofp | 1999 Fairchild Semiconductor Corporation DS00566 1.prf www.fairchildsemi.com YOUMS |e19}e/1g PEND DA9LOVADCD4016BC Absolute Maximum Ratingsinote 1) (Note 2) Vpp Supply Voltage Vin Input Voltage Tg Storage Temperature Range Power Dissipation (Pp) Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) 0.5V to +18V -0.5V to Vop +0.5V -65C to + 150C 700 mW 500 mW 260C. DC Electrical Characteristics (Note 2) Recommended Operating Conditions ote 2) Vpp Supply Voltage Vin Input Voltage Ta Operating Temperature Range 3V to 15V OV to Vop 40C to +85C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of Recom- mended Operating Conditions and Electrical Characteristics provide con- ditions for actual device operation. Note 2: Vgc = OV unless otherwise specified. Symbol Parameter Conditions - re - ase - sere Units Min Max | Min Typ | Max | Min Max lbp Quiescent Device Vpp=5V, Vin= Vpp oF Vsg 1.0 0.01 1.0 7.5 pA Current Vpp= 10V, Vin=Vpp oF Vgg 2.0 0.01 2.0 15 pA Vpp= 15V, Vin = Vpp oF Vsg 4.0 0.01 4.0 30 pA Signal Inputs and Outputs Ron ON Resistance R._= 10kQ to (Vpp Vgg)/2 Vo=Vpp: Vis= Vs oF Vpp Vpp= 10V 610 275 | 660 840 Q Vpp= 15V 370 200 400 520 Q Ri = 10k to (Vpp Vgg)/2 Vc=Vpp Vpp= 10V, Vig=4.75 to 5.25V 1900 850 | 2000 2380 | Q Vpp= 15, Vig= 7.25 to 7.75V 790 400 | 850 1080 | Q ARon AON Resistance Ri = 10kQ to (Vpp Vgg)/2 Between any 2 of Vo=Vpp. Vis= Vsg to Vpp 4 Switches Vpp= 10V 15 Q (In Same Package) Vpp= 15V 10 Q lis Input or Output Vo=0, Vpp = 15V +50 +0.1 +50 +200 nA Leakage Vig = OV or 15, Switch OFF Vog = 15V or OV Control Inputs Vite LOW Level Input Vig =Vgs and Vpp Voltage Vos =Vpp and Vgg lig =+10 pA Vpp=5V 0.9 0.7 0.4 Vv Vpp= 10V 0.9 0.7 0.4 v Vpp= 15V 0.9 0.7 0.4 Vv Vic HIGH Level Input Vpp=5V 3.5 3.5 3.5 Vv Voltage Vpp= 10V 7.0 7.0 7.0 Vv Vpp= 15V 11.0 11.0 11.0 Vv (Note 3) and Figure 8 lI Input Current Voo- Vgg = 15V +0.3 +10 | +0.3 +1.0 HA Vpp2 Vis2 Vss Vpp2 Vc2 Vss Note 3: If the switch input is held at Vpp, Vic is the control input level that will cause the switch output to meet the standard B series Voy, and Iq}, output levels. If the analog switch input is connected to Vgg, Viy is the control input level which allows the switch to sink standard B series |Iq4|, high level cur- rent, and still maintain a Vo, < B series. These currents are shown in Figure 8. www.fairchildsemi.comAC Electrical Characteristics (ote 4) Ta = 25C, t,=t}= 20 ns and Vgg = OV unless otherwise specified Symbol Parameter Conditions Min Typ Max Units tpyL tpLy Propagation Delay Time Vo=Vpp, C_=50 pF (Figure 1) Signal Input to Signal Output Rr, = 200k Vpp = 5V 58 100 ns Vpp= 10V 27 50 ns Vpp = 15V 20 40 ns tpzy; tpz Propagation Delay Time R._= 1.0 kQ, C, =50 pF, (Figure 2, Figure 3) Control Input to Signal Vpp = 5V 20 50 ns Output HIGH Impedance to Vpp = 10V 18 40 ns Logical Level Vpp = 15V 17 35 ns tpyz: tpiz Propagation Delay Time R_ = 1.0 kQ, C, =50 pF, (Figure 2, Figure 3) Control Input to Signal Vpp = 5V 15 40 ns Output Logical Level to Vpp = 10V 11 25 ns HIGH Impedance Vpp = 15V 10 22 ns Sine Wave Distortion Vo=Vpp=5V, Vgg =-5 0.4 % RL = 10 kQ, Vig=5 Vp-p, f= 1 kHz, (Figure 4) Frequency Response Switch Vo=Vpp=5V, Vgg =-5V, 40 MHz ON (Frequency at 3 dB) R_=1kQ, Vig=5 Vp-p, 20 Logig Vog/Vog (1 kHz) dB, (Figure 4) Feedthrough Switch OFF Vpp = 5V, Vo= Veg =-5V, 1.25 MHz (Frequency at 50 dB) R_=1kQ, Vig=5 Vp p, 20 Logig (Vog/Vig) = 50 4B, (Figure 4) Crosstalk Between Any Two Von = Vora) = 5Vs Vgg = Vevay = -5. 0.9 MHz Switches (Frequency at 50 dB) RL = 1 kQVigiay = 5 Vp-p, 20 Logi (VogiayVogay) = -50 4B, (Figure 5) Crosstalk; Control Input to Vpp = 10V, RL = 10 kQ 150 mVp.p Signal Output Rin= 1k, Voc = 10V Square Wave, C,_=50 pF (Figure 6) Maximum Control Input R_=1 kQ, CL =50 pF, (Figure 7) Vosi = % Vog(1 kHz) Vpp = BY 6.5 MHz Vpp = 10V 8.0 MHz Vpp = 15V 9.0 MHz Cig Signal Input Capacitance 4 pF Cos Signal Output Capacitance Vpp = 10V 4 pF Clos Feedthrough Capacitance Vo=0V 0.2 pF Cin Control Input Capacitance 5 75 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: These devices should not be connected to circuits with the power ON. Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in C, wherever it is speci- fied. Note 7: Vig is the voltage at the in/out pin and Vgg is the voltage at the out/in pin. Vg is the voltage at the control input. www.fairchildsemi.com 949-0709CD4016BC AC Test Circuits and Switching Time Waveforms Yoo ve= oo CONTROL Vpg 10F4 | is IN/OUT sui teyes OUT/AN Vss I Yoo tpzH vo | von Yoo CONTROL = Vpn 50% 1084 ov Vig = f 13 = Yop WWOUT itcues OUT/IN Vos | wan ss ey aL Vou 50 pF 1K 10% av FIGURE 2. tpzy, tpyz Propagation Delay Time Control to Signal Output tPZL tpLz v Yoo Ypo c tPZL tpLz RL CONTROL =~ Vpp tk : 10F4 Vig = OV IN is= 9 VOUT sircues OUT/N Vos Vg l T shor | FIGURE 3. tpzy, tpyz Propagation Delay Time Control to Signal Output 5V 2.5V CONTROL = Vpp / 10F4 Vis OV _ Viot Is IN/OUT giitcHes OUTAN Vos Vss ~2.5V poo NG BL | 14 +| -5V Vo= Vpp for distortion and frequency response tests Vo= Vsg for feedthrough test FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough www.fairchildsemi.com 4AC Test Circuits and Switching Time Waveforms (Continued) VclA)= Voo | CONTROL Vpp SV VigfA]) Jinour _ | OF 4 's F007 suarcHes CUTN Vasia) Vss R | 1k -5V = 25vy , I~ Visi) ov VctB) = Vgg BV | | -2.5 }______ 1 -_ CONTROL = Vgq VisiB) = OV 1OF4 Is IN/OUT oitcHes OUT/AN Vosiel Vv ss AL | 1k = BV = FIGURE 5. Crosstalk Between Any Two Switches Ve 10V CONTROL Vpp Ve 10F4 Vv IN/OUT ts HOUT cwiteues QUTAN Vos mY T "h t TT" Gen | Vos _- CROSSTALK FIGURE 6. Crosstalk Control to Input Signal Output v Ve DoD CONTROL Vp 10F4 switcHes OUT/IN Vos Vss Cy RL 50 pF 1k 4 Vos @ 1 kHz = Vos 20 = = = | FIGURE 7. Maximum Control Input Frequency Vis = Vpp IN/OUT 5 www.fairchildsemi.com 949-0709CD4016BC AC Test Circuits and Switching Time Waveforms (Continued) Temperature Switch Input Switch Output Range Vpp Vis lig (mA) Vos(V) 40C 25C +85C Min Max 5 0 0.2 0.16 0.12 0.4 5 5 0.2 0.16 0.12 46 COMMERCIAL 10 0 0.5 0.4 0.3 0.5 10 10 -0.5 0.4 0.3 9.5 15 0 1.4 1.2 1.0 1.5 15 15 -1.4 -1.2 -1.0 13.5 FIGURE 8. CD4016B Switch Test Conditions for Vinic Typical Performance Characteristics ON Resistance vs. Signal ON Resistance Temperature Voltage T, = 25C Variation for Vpp Vgg = 10V 900 800 700 600 500 400 300 200 100 900 800 700 600 500 400 300 200 100 Von Vss = 10V Vpo Vss = 15V CHANNEL ON RESISTANCE (Ron}(2) CHANNEL ON RESISTANCE (Ron)() -B8-6 -4 -2 0 2 4 6 B 8-6-4 -2 0 2 4 6 8B SIGNAL INPUT (is)() SIGNAL INPUT (Vjs)(} ON Resistance Temperature Variation for Vpp Vgsg = 15V 500 @ +125C @ +85 400 +25 300 200 40 100 55 CHANNEL ON RESISTANCE (Ron)(2) -8 6-4-2 0 2 4 6 8 SIGNAL INPUT (Vis){) www.fairchildsemi.com 6Typical Applications CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 INPUT f 1 OF 4 Special Considerations 4 Input Multiplexer 10F4 SWITCHES ~ 10F 4 SWITCHES I COMMON >_ 10F4 SWITCHES ~ Co 1 OF 4 SWITCHES ~TS 432 1 CONTROL Sample/Hold Amplifier b OUTPUT SWITCHES |. anal S/H LF356 The CD4016B is composed of 4, two-transistor analog non-linear. It is recommended that at 5V, voltages on the in/ switches. These switches do not have any linearization or out pins be maintained within about 1V of either Vpp or compensation circuitry for Roy as do the CD4066B's. Vga; and that at 3V the voltages on the in/out pins should Because of this, the special operating considerations for be at Vpp or Vgg for reliable operation. the CD4066B do not apply to the CD4016B, but at low sup- ply voltages, <5V, the CD4016B's on resistance becomes 7 www.fairchildsemi.com 949-0709CD4016BC 0.1500.157 0.010 0.020 {0.254-0.508) 4 \ 1s 0.0080.010 (0.2030.254) TYP ALL LEADS 0.004 (0.102) ALL LEAD TIPS (810-3988) & MAX TYP ALL LEADS == t 0.016 ~0.050 (0.406 1.270} TYP ALL LEADS Physical DimeNnsSiONS inches (millimeters) unless otherwise noted 0.3350.344 (8.509 8.738) 140613 12 19 10 G 8 HAA AAS 0.228 0,244 we 791~6.198) | ~. (5.791 6-998) fms TPS _ rN LEAD NO. 1 a? IDENT < 1 2 3.04 5 6 #7 0.010 wax (0.254) 0.053 - 0.069. (1.346 1.753) 0.0040.070 ; (0.102 0.254) SEATING y+. et ed id Ed PLANE 4 A | A 0.014 0.050 0.014 -0.020 0.356} | ~<_ | ____ TvP (0.366) (1.270) (0.356 0.508) TYP 0.008 (0.203) /P tea ine sy 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.comPhysical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) 0.740 0.770 [~~ {1a.80 19.58) SOS 0.090 (2.286) fa] fra) [x2] [5] fio] [3] [ie] INDEX AREA ~ CO 0.250 +0.010 O LT (6.350 0.254) PINNG. 1 --"% c__} PINNO.1 IDENT DAE Ghd IDENT 0.092 D.030 MAX (2.337) (0.762) DEPTH OPTION 1 OPTION 02 0-138 50.006, 0.300 -0.320 a1as_0 200 (3.429 0.127) 1 os rane wm ee ~> je = re eg 4 TYP - (3.683 5.080) | (1.524) ~\ ee OPTIONAL (1.651) A 7 a az ryt | A ashe 0.008 0.016 0.020 Y _ 90 +4 TYP Pe _ {0-2030.405) (0 3 ae] | MIN 0.1250.150 Lt j (3.175 3.810) > 0.075 0.015. 0.280 | (1.905 10.381) aah | 0.0140,023 > P(7. (0.3360.584) 0.100 +0.010 MIN , : > wosp. 001. (@3E 0-254) ; - t _- 0.000 0.010 +0.040 (1270 0.254) 0.325 on3 , +1015) 8.25 ( 5 0.381 NI4A (REV F} 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no drcuit pater licenses are implied ard Fairchild reserves the right al any time without notice to change said circuitry ard specifications. YOUMS |e19}e/1g PEND DA9LOVAD