General Description
The MAX6443–MAX6452 low-current microprocessor
reset circuits feature single or dual manual reset inputs
with an extended 6.72s setup period. Because of the
extended setup period, short switch closures (nuisance
resets) are ignored.
On all devices, the reset output asserts when any of the
monitored supply voltages drops below its specified
threshold. The reset output remains asserted for the
reset timeout period (210ms typ) after all monitored
supplies exceed their reset thresholds. The reset output
is one-shot pulse asserted for the reset timeout period
(140ms min) when selected manual reset input(s) are
held low for an extended setup timeout period of 6.72s.
These devices ignore manual reset transitions of less
than 6.72s (typ).
The MAX6443–MAX6448 are single fixed-voltage µP
supervisors. The MAX6443/MAX6444 have a single
extended manual reset input. The MAX6445/MAX6446
have two extended manual reset inputs. The MAX6447/
MAX6448 have one extended and one immediate manual
reset input.
The MAX6449–MAX6452 have one fixed-threshold µP
supervisor and one adjustable-threshold µP supervisor.
The MAX6449/MAX6450 have two delayed manual
reset inputs. The MAX6451/MAX6452 have one delayed
and one immediate manual reset input.
The MAX6443–MAX6452 have an active-low RESET
with push-pull or open-drain output logic options. These
devices, offered in small SOT packages, are fully guar-
anteed over the extended temperature range (-40°C to
+85°C).
Applications
Set-Top Boxes
Consumer Electronics
DVD Players
Modems
MP3 Players
Industrial Equipment
Automotive
Medical Devices
Features
♦Single- or Dual-Supply Voltage Monitors
♦Precision Factory-Set Reset Thresholds from
1.6V to 4.6V
♦Adjustable Threshold to Monitor Voltages Down
to 0.63V (MAX6449–MAX6452)
♦Single or Dual Manual Reset Inputs with Extended
6.72s Setup Period
♦Optional Short Setup Time Manual Reset Input
(MAX6447/MAX6448 and MAX6451/MAX6452)
♦Immune to Short Voltage Transients
♦Low 6µA Supply Current
♦Guaranteed Valid Reset Down to VCC = 1.0V
♦Active-Low RESET (Push-Pull or Open-Drain)
Outputs
♦140ms (min) Reset Timeout Period
♦Small SOT143 and SOT23 Packages
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
________________________________________________________________ Maxim Integrated Products 1
VCC
MR1
RESET
GND
MAX6443
MAX6444
SOT143
TOP VIEW
4
3
1
2
Pin Configurations
Ordering Information
19-2656; Rev 2; 12/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX6443 US_ _L -T -40°C to +85°C 4 SOT143-4
MAX6444 US_ _L -T -40°C to +85°C 4 SOT143-4
Note: The “_ _ ” is a placeholder for the threshold voltage level
of the devices. A desired threshold level is set by the two-num-
ber suffix found in Table 1. All devices are available in tape-
and-reel only. There is a 2500-piece minimum order increment
for standard versions (Table 2). Sample stock is typically held
on standard versions only. Nonstandard versions require a
minimum order increment of 10,000 pieces. Contact factory for
availability.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Pin Configurations continued at end of data sheet.
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
All Voltages Referenced to GND
VCC ..........................................................................-0.3V to +6V
Open-Drain RESET ..................................................-0.3V to +6V
Push-Pull RESET ........................................-0.3V to (VCC + 0.3V)
MR1, MR2, MR2, RSTIN ..........................................-0.3V to +6V
Input Current, All Pins.......................................................±20mA
Continuous Power Dissipation (TA= +70°C)
4-Pin SOT143-4 (derate 4.0mW/°C above +70°C) .....320mW
5-Pin SOT23-5 (derate 7.1mW/°C above +70°C) .......571mW
6-Pin SOT23-6 (derate 8.7mW/°C above +70°C) .......696mW
Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VCC = 1.0V to 5.5V, TA= -40°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range VCC 1.0 5.5 V
VCC = 5.5V, no load 7 20
VCC Supply Current ICC VCC = 3.6V, no load 6 16 µA
46 4.50 4.63 4.75
44 4.25 4.38 4.50
31 3.00 3.08 3.15
29 2.85 2.93 3.00
26 2.55 2.63 2.70
23 2.25 2.32 2.38
22 2.12 2.19 2.25
17 1.62 1.67 1.71
VCC Reset Threshold VTH
16 1.52 1.58 1.62
V
Reset Threshold Tempco 60 ppm/°C
Reset Threshold Hysteresis 2 × VTH mV
TA = 0°C to +85°C 0.615 0.630 0.645
RSTIN Threshold VTH-RSTIN MAX6449–MAX6452 TA = -40°C to +85°C 0.610 0.650 V
RSTIN Threshold Hysteresis VHYST MAX6449–MAX6452 2.5 mV
RSTIN Input Current IRSTIN MAX6449–MAX6452 -25 +25 nA
RSTIN to Reset Output Delay MAX6449–MAX6452, VRSTIN falling at
1mV/µs 15 µs
Reset Timeout Period tRP 140 210 280 ms
VCC to RESET Output Delay tRD VCC falling at 1mV/µs 20 µs
MR1 Minimum Setup Period
Pulse Width tMR 4.48 6.72 8.96 s
MR1 + MR2 Minimum Setup
Period Pulse Width MAX6445/MAX6446/MAX6449/MAX6450 4.48 6.72 8.96 s
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MR2 Minimum Setup Period
Pulse Width MAX6447/MAX6448/MAX6451/MAX6452 1 µs
MR2 Glitch Rejection MAX6447/MAX6448/MAX6451/MAX6452 100 ns
MR2 to RESET Delay MAX6447/MAX6448/MAX6451/MAX6452 200 ns
Manual Reset Timeout Period tMRP 140 210 280 ms
MR1 to VCC Pullup Impedance 25 50 75 kΩ
MR2 to VCC Pullup Impedance MAX6445/MAX6446/MAX6449/MAX6450 25 50 75 kΩ
VCC ≥ 1.00V, ISINK = 50µA, RESET asserted 0.3
VCC ≥ 1.20V, ISINK = 100µA, RESET
asserted 0.3
VCC ≥ 2.55V, ISINK = 1.2mA, RESET
asserted 0.3
RESET Output Low
(Open Drain or Push-Pull) VOL
VCC ≥ 4.25V, ISINK = 3.2mA, RESET
asserted 0.4
V
VCC ≥ 1.80V, ISOURCE = 200µA, RESET
deasserted 0.8 × VCC
VCC ≥ 3.15V, ISOURCE = 500µA, RESET
deasserted 0.8 × VCC
RESET Output High
(Push-Pull) VOH
VCC ≥ 4.75V, ISOURCE = 800µA, RESET
deasserted 0.8 × VCC
V
RESET Open-Drain Leakage
Current ILKG RESET deasserted 1 µA
MR1, MR2, MR2
Input Low Voltage VIL 0.3 × VCC V
MR1, MR2, MR2
Input High Voltage VIH 0.7 × VCC V
Note 1: Devices production tested at +25°C. Overtemperature limits are guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.0V to 5.5V, TA= -40°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 1)
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6443/52 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.04.53.5 4.02.0 2.5 3.01.5
1
2
3
4
5
6
7
8
9
0
1.0 5.5
TA = +25°C
TA = -40°C
TA = +85°C
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX6443/52 toc02
TEMPERATURE (°C)
NORMALIZED TIMEOUT PERIOD
603510-15
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
0.95
-40 85
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
MAX6443/52 toc03
RESET THRESHOLD OVERDRIVE (mV)
TRANSIENT DURATION (µs)
800600400200
50
100
150
200
250
0
0 1000
VTH = 4.4V
RESET OCCURS
ABOVE THE CURVE
NORMALIZED VCC RESET THRESHOLD
vs. TEMPERATURE
MAX6443/52 toc04
TEMPERATURE (°C)
NORMALIZED VCC RESET THRESHOLD
603510-15
0.98
0.99
1.00
1.01
1.02
1.03
0.97
-40 85
VCC TO RESET DELAY
vs. TEMPERATURE
MAX6443/52 toc05
TEMPERATURE (°C)
VCC TO RESET DELAY (µs)
603510-15
20.4
20.8
21.2
21.6
22.0
22.4
22.8
23.2
23.6
24.0
20.0
-40 85
VCC = FALLING AT 1mV/µs
RSTIN TO RESET DELAY
vs. TEMPERATURE (RSTIN FALLING)
MAX6443/52 toc06
TEMPERATURE (°C)
RSTIN TO RESET DELAY (µs)
603510-15
20.4
20.8
21.2
21.6
22.0
22.4
22.8
23.2
23.6
24.0
20.0
-40 85
RSTIN FALLING AT 1mV/µs
MANUAL RESET TO RESET DELAY
(MAX6445/MAX6446/MAX6449/MAX6450)
MAX6443/52 toc07
TIME (1s/div)
MR1
(5V/div)
MR2
(5V/div)
RESET
(5V/div)
VCC = 5V
VCC TO RESET DELAY
MAX6443/52 toc08
TIME (100µs/div)
VCC (100mV/div)
RESET
(2V/div)
VCC = 4.5V
VCC = 4.3V
VTH = 4.392V
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________ 5
Detailed Description
Reset Output
The reset output is typically connected to the reset
input of a microprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6443–
MAX6452 µP supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down and brownout conditions (see the
Typical Operating Circuit).
RESET changes from high to low whenever the moni-
tored voltages (RSTIN or VCC) drop below the reset
threshold voltages. Once VRSTIN and VCC exceed their
respective reset threshold voltages, RESET remains low
for the reset timeout period and then goes high. RESET
is one-shot pulsed whenever selected manual reset
inputs are asserted. RESET stays asserted for the nor-
mal reset timeout period (140ms min).
RESET is guaranteed to be in the proper output logic
state for VCC inputs ≥1V. For applications requiring valid
reset logic when VCC is less than 1V, see the Ensuring a
Valid
RESET
Output Down to VCC = 0V section.
Pin Description
PIN
MAX6443
MAX6444
MAX6445
MAX6446
MAX6447
MAX6448
MAX6449
MAX6450
MAX6451
MAX6452
NAME FUNCTION
1 2 2 2 2 GND Ground
21111RESET
Acti ve- Low P ush- P ul l or Op en- D r ai n Outp ut. RES ET
chang es fr om hi g h to l ow w hen V
C C
or RS TIN d r op s b el ow
i ts sel ected r eset thr eshol d and r em ai ns l ow for the 210m s
r eset ti m eout p er i od after al l m oni tor ed p ow er - sup p l y i np uts
exceed thei r sel ected r eset thr eshol d s. RES ET i s one- shot
p ul sed l ow for the r eset ti m eout p er i od ( 140m s m i n) after
sel ected m anual r eset i np uts ar e asser ted l ong er than the
sp eci fi ed
setup p er i od . For the op en- d r ai n outp ut, use a
m i ni m um 20kΩ p ul l up r esi stor to V
C C .
3—3—3
Manual Reset Input, Active Low. Internal 50kΩ pullup to
VCC. Pull MR1 low for the typical input pulse width
(6.72s) to one-shot pulse RESET for the reset timeout
period.
—3—3—
MR1
Manual Reset Input, Active Low. Pull both MR1 and
MR2 low for the typical input pulse width (6.72s) to one-
shot pulse RESET for the reset timeout period.
44444V
CC VCC Voltage Input. Power supply and input for the
primary microprocessor voltage reset monitor.
—5—6—MR2
Manual Reset Input, Active Low. Internal 50kΩ pullup to
VCC. Pull both MR1 and MR2 low for the typical input
pulse width (6.72s) to one-shot pulse RESET for the
reset timeout period.
—— 5 — 6MR2
Manual Reset Input. Pull the MR2 high to immediately
one-shot pulse RESET for the reset timeout period.
— — — 5 5 RSTIN
Reset Input. High-impedance input to the adjustable
reset comparator. Connect RSTIN to the center point of
an external resistor-divider to set the threshold of the
externally monitored voltage.
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
6 _______________________________________________________________________________________
Manual Reset Input Options
Unlike typical manual reset functions associated with
supervisors, each device in the MAX6443–MAX6452
family includes at least one manual reset input, which
must be held logic-low for an extended setup period
(6.72s typ) before the RESET output asserts. When
valid manual reset input conditions/setup periods are
met, the RESET output is one-shot pulse asserted low
for a fixed reset timeout period (140ms min). Existing
front-panel pushbutton switches (i.e., power on/off,
channel up/down, or mode select) can be used to drive
the manual reset inputs. The extended manual reset
setup period prevents nuisance system resets during
normal front-panel usage or resulting from inadvertent
short-term pushbutton closure.
The MAX6443/MAX6444, MAX6447/MAX6448, and
MAX6451/MAX6452 include a single manual reset input
with extended setup period (MR1). The MAX6445/
MAX6446 and MAX6449/MAX6450 include two manual
reset inputs (MR1 and MR2) with extended setup peri-
ods. For dual MR1, MR2 devices, both inputs must be
held low simultaneously for the extended setup period
(6.72s typ) before the reset output is pulse asserted.
The dual extended setup provides greater protection
from nuisance resets. (For example, the user or service
technician is informed to simultaneously push both the
on/off button and the channel-select button for 6.72s to
reset the system.)
The MAX6443–MAX6452 RESET output is pulse asserted
once for the reset timeout period after each valid manual
reset input condition. At least one manual reset input
must be released (go high) and then be driven low for the
extended setup period before RESET asserts again.
Internal timing circuitry debounces low-to-high manual
reset logic transitions, so no external circuitry is required.
Figure 1 illustrates the single manual reset function of the
MAX6443/MAX6444 single-voltage monitors, and Figure
2 represents the dual manual reset function of the
MAX6445/MAX6446 and MAX6449/MAX6450.
The MAX6447/MAX6448 and MAX6451/MAX6452
include both an extended setup period and immediate
setup period manual reset inputs. A low-to-high MR2
rising edge transition immediately pulse asserts the
RESET output for the reset timeout period (140ms min).
If the MAX6447/MAX6448 and MAX6451/MAX6452
MR2 input senses another rising edge before the end
of the 140ms timeout period (Figure 3), the internal
timer clears and begins counting again. If no rising
edges are detected within the 210ms timeout period,
RESET deasserts. The high-to-low transition on MR2
input is internally debounced for 210ms to ensure that
there are no false RESET assertions when MR2 is dri-
ven from high to low (Figure 4). The MR2 input can be
used for system test purposes or smart-card-detect
applications (see the Applications Information section).
Adjustable Input Voltage (RSTIN)
The MAX6449–MAX6452 monitor the voltage on RSTIN
using an adjustable reset threshold set with an external
resistor voltage-divider (Figure 5). Use the following for-
mula to calculate the externally monitored voltage
(VMON-TH):
VMON-TH = VTH-RSTIN ✕(R1+ R2) / R2
where VMON-TH is the desired reset threshold voltage
and VTH-RSTIN is the reset input threshold (0.63V).
Resistors R1 and R2 can have very high values to mini-
mize current consumption because of low leakage cur-
rents. Set R2 to some conveniently high value (250kΩ,
for example), and calculate R1 based on the desired
reset threshold voltage, using the following formula:
R1 = R2 ✕(VMON-TH / VTH-RSTIN - 1) Ω
RESET TIMEOUT PERIOD
210ms
MR1 SETUP PERIOD
6.72s
MR1
RESET
Figure 1. MAX6443/MAX6444 Manual Reset Timing Diagram
MR2
RESET
MR1
6.72s
210ms
Figure 2. MAX6445/MAX6446/MAX6449/MAX64450 Manual
Reset Timing Diagram
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________ 7
Applications Information
Interrupt Before Reset
To minimize data loss and speed system recovery,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6443–
MAX6452 manual reset inputs allows the same push-
button (connected to both the processor interrupt and
the extended MR1 input, as shown in Figure 6) to con-
trol both the interrupt and hard reset functions. If the
pushbutton is closed for less than 6.72s, the processor
is only interrupted. If the system still does not respond
properly, the pushbutton (or two buttons for the dual
manual reset) can be closed for the full extended setup
period to hard reset the processor. If desired, connect
an LED to the RESET output to blink off (or on) for the
reset timeout period to signify when the pushbutton is
closed long enough for a hard reset (the same LED
might be used as the front-panel power-on display).
Smart Card Insertion/Removal
The MAX6447/MAX6448/MAX6451/MAX6452 dual manu-
al resets are useful in applications in which both an
extended and immediate setup periods are needed.
Figure 7 illustrates the insertion and removal of a smart
card. MR1 monitors a front-panel pushbutton. When
closed for 6.72s, RESET one-shot pulses low for 140ms
min. Because MR1 is internally pulled to VCC through a
50kΩresistor, the front-panel switch can be connected to
MR2
RESET
t = 210ms
t < 210ms
COUNTER RESET
Figure 3. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Assertion DebouncingTiming Diagram
MR2
RESET
210ms
DEBOUNCING PERIOD
210ms
TIMEOUT PERIOD
POSITIVE EDGE
NO RESET
OUTPUT
ASSERTED
Figure 4. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Deassertion Debouncing Timing Diagram
MAX6449
MAX6451
RSTIN VCC
R1
R2
RESET
GND
VMON_TH = 0.63 x (R1 + R2) / R2
VMON_TH VCC
Figure 5. Calculating the Monitored Threshold Voltages
MAX6443 µP
VCC RESET
VCC
+3.3V
NMI
LED
RESET
MR1
GND
PUSHBUTTON SWITCH:
CLOSE FOR < 4.48s
FOR SYSTEM INTERRUPT;
CLOSE FOR > 6.72s FOR
SYSTEM RESET
Figure 6. Interrupt Before Reset Application Circuit
MAX6443–MAX6452
a microprocessor for general-purpose I/O control. MR2
monitors a switch to detect when a smart card is inserted.
When the switch is closed high (card inserted), RESET
one-shot pulses low for 140ms. MR2 is internally
debounced for 210ms to prevent false resets when the
smart card is removed.
Interfacing to Other Voltages
for Logic Compatibility
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 8, the
open-drain output can be connected to voltages from 0
to 6V.
Generally, the pullup resistor connected to the RESET
connects to the supply voltage that is being monitored
at the IC’s VCC pin. However, some systems may use
the open-drain output to level-shift from the monitored
supply to reset circuitry powered by some other supply
(Figure 8). Keep in mind that as the supervisor’s VCC
decreases toward 1V, so does the IC’s ability to sink
current at RESET. RESET is pulled high as VCC decays
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
Ensuring a Valid
RESET
Down to
VCC = 0V (Push-Pull
RESET
)
When VCC falls below 1V, RESET current-sinking capa-
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to
undetermined voltages. This presents no problems in
most applications, because most µPs and other circuitry
do not operate with VCC below 1V.
In applications in which RESET must be valid down to
0V, add a pulldown resistor between RESET and GND
for the push-pull outputs. The resistor sinks any stray
leakage currents, holding RESET low (Figure 9). The
value of the pulldown resistor is not critical; 100kΩis
large enough not to load RESET and small enough to
pull RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
Transient Immunity
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively immune to short-duration falling tran-
sients (glitches). The graph Maximum Transient Duration
vs. Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
µP Reset Circuits with Long Manual Reset
Setup Period
8 _______________________________________________________________________________________
MAX6451 µP
VCC
RSTIN
RESET
DIGITAL INPUT
I/O SUPPLY
CORE SUPPLY
+3.3V
+1.5V
RESET
MR1
MR2
GND
FRONT-PANEL SWITCH
STANDARD µP INPUT
AND 6.72s MANUAL
RESET DELAY
SMART CARD DETECT:
IMMEDIATE ONE-SHOT
WHEN MANUAL
RESET CLOSES
Figure 7. MAX6451/MAX6452 Application Circuit
MAX6444
MAX6446
MAX6448
MAX6450
MAX6452
µP
RESET
RESET
GND
VCC
5V 3.3V
100kΩ
N
Figure 8. Interfacing to Other Voltage Levels
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a falling pulse
applied to VCC, starting above the actual reset thresh-
old (VTH) and ending below it by the magnitude indicat-
ed (reset threshold overdrive). As the magnitude of the
transient increases (VCC goes further below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a VCC transient that goes 100mV
below the reset threshold and lasts 20µs or less does
not cause a reset pulse to be asserted.
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________ 9
MAX6443
MAX6445
MAX6447
MAX6449
MAX6451
RESET
VCC
VCC
GND
100kΩ
Figure 9. Ensuring
RESET
Valid to VCC = 0
PART NO. SUFFIX
( _ _ )
VCC NOMINAL
VOLTAGE
THRESHOLD (V)
46 4.625
44 4.375
31 3.075
29 2.925
26 2.625
23 2.313
22 2.188
17 1.665
16 1.575
Table 1. Reset Voltage Threshold
PART TOP
MARK PART TOP
MARK
MAX6443US16L KAFW MAX6448UK16L AEER
MAX6443US23L KAFX MAX6448UK23L AEES
MAX6443US26L KAFY MAX6448UK26L AEET
MAX6443US29L KAFK MAX6448UK29L AEEU
MAX6443US46L KAFZ MAX6448UK46L AEEV
MAX6444US16L KAGA MAX6449UT16L ABEL
MAX6444US23L KAGB MAX6449UT23L ABNP
MAX6444US26L KAGC MAX6449UT26L ABNQ
MAX6444US29L KAGD MAX6449UT29L ABNR
MAX6444US46L KAFL MAX6449UT46L ABNS
MAX6445UK16L AEEF MAX6450UT16L ABEM
MAX6445UK23L AEEG MAX6450UT23L ABNX
MAX6445UK26L AEEH MAX6450UT26L ABNY
MAX6445UK29L AEEI MAX6450UT29L ABNZ
MAX6445UK46L AEAO MAX6450UT46L ABOA
MAX6446UK16L AEEN MAX6451UT16L ABNT
MAX6446UK23L AEEO MAX6451UT23L ABEN
MAX6446UK26L AEEP MAX6451UT26L ABNU
MAX6446UK29L AEAP MAX6451UT29L ABNV
MAX6446UK46L AEEQ MAX6451UT46L ABNW
MAX6447UK16L AEEJ MAX6452UT16L ABOB
MAX6447UK23L AEEK MAX6452UT23L ABOC
MAX6447UK26L AEAQ MAX6452UT26L ABOD
MAX6447UK29L AEEL MAX6452UT29L ABOE
MAX6447UK46L AEEM MAX6452UT46L ABOF
Table 2. Standard Versions Table
Chip Information
TRANSISTOR COUNT: 1384
PROCESS: BiCMOS
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
10 ______________________________________________________________________________________
Ordering Information (continued)
PART TEMP RANGE PIN-PACKAGE
MAX6445 UK_ _L -T -40°C to +85°C 5 SOT23-5
MAX6446 UK_ _L -T -40°C to +85°C 5 SOT23-5
MAX6447 UK_ _L -T -40°C to +85°C 5 SOT23-5
MAX6448 UK_ _L -T -40°C to +85°C 5 SOT23-5
MAX6449 UT_ _L -T -40°C to +85°C 6 SOT23-6
MAX6450 UT_ _L -T -40°C to +85°C 6 SOT23-6
MAX6451 UT_ _L -T -40°C to +85°C 6 SOT23-6
MAX6452 UT_ _L -T -40°C to +85°C 6 SOT23-6
Note: The “_ _ ” is a placeholder for the threshold voltage level
of the devices. A desired threshold level is set by the two-num-
ber suffix found in Table 1. All devices are available in tape-
and-reel only. There is a 2500-piece minimum order increment
for standard versions (Table 2). Sample stock is typically held
on standard versions only. Nonstandard versions require a
minimum order increment of 10,000 pieces. Contact factory for
availability.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
MAX6444 µP
VCC VCC
RESETMR1
+3.3V
RESET
GND GND
RESET TIMEOUT PERIOD
210ms
MR1 SETUP PERIOD
6.72s
MR1
RESET
Typical Operating Circuit
TOP VIEW
GND
VCC
MR1
15MR2RESET
MAX6445
MAX6446
SOT23-5
2
34
GND
VCC
MR1
15MR2RESET
MAX6447
MAX6448
SOT23-5
2
34
GND
VCC
MR1
16MR2
5RSTIN
RESET
MAX6449
MAX6450
SOT23-6
2
34
GND
VCC
MR1
16MR2
5RSTIN
RESET
MAX6451
MAX6452
SOT23-6
2
34
Pin Configurations (continued)
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
______________________________________________________________________________________ 11
*Other timing options may be available. Contact factory for availability.
PART MR1
SETUP
MR2
(NO SETUP)
MR2
SETUP RSTIN PUSH-PULL RESET OPEN-DRAIN RESET
MAX6443 6.72s — — — ✔—
MAX6444 6.72s — — — — ✔
MAX6445 6.72s — 6.72s — ✔—
MAX6446 6.72s — 6.72s — — ✔
MAX6447 6.72s ✔—— ✔—
MAX6448 6.72s ✔—— — ✔
MAX6449 6.72s — 6.72s ✔✔ —
MAX6450 6.72s — 6.72s ✔—✔
MAX6451 6.72s ✔—✔✔ —
MAX6452 6.72s ✔—✔—✔
Selector Guide
MAX6443–
MAX6452
MAX6449–
MAX6452
MAX6447
MAX6448
MAX6451
MAX6452
MAX6445
MAX6446
MAX6449
MAX6450
RSTIN
VCC
RESET
TIMEOUT PERIOD
(210ms typ)
MR2 ONE-SHOT
DEBOUNCE
CIRCUIT
MANUAL RESET
SETUP PERIOD
(6.72s typ)
0.63V
1.23V
MR1
GND
VCC
VCC VCC
RESET
MR2
MR2
Functional Diagram
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
12 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SOT-143 4L.EPS
E1
1
21-0052
PACKAGE OUTLINE, SOT-143, 4L
SOT-23 5L .EPS
E
1
1
21-0057
PACKAGE OUTLINE, SOT-23, 5L
MAX6443–MAX6452
µP Reset Circuits with Long Manual Reset
Setup Period
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
6LSOT.EPS
PACKAGE OUTLINE, SOT 6L BODY
21-0058
1
1
G
